URL
https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk
Subversion Repositories sdhc-sc-core
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 124 to Rev 125
- ↔ Reverse comparison
Rev 124 → Rev 125
/sdhc-sc-core/trunk/src/grpSd/unitSdCardModel/src/SdData.sv
33,6 → 33,43
data.push_back(crc[i]); |
endfunction |
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task automatic recv(virtual ISdCard.Card ICard, ref logic rddata[$]); |
aCrc16 crc[4]; |
ICard.cbcard.Data <= 'bzzzz; |
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if (mode == wide) begin |
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// startbits |
wait(ICard.cbcard.Data == 'b0000); |
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$display("Startbits: %t", $time); |
for (int j = 0; j < 512*2; j++) begin |
@ICard.cbcard; |
for(int i = 0; i < 4; i++) begin |
rddata.push_back(ICard.cbcard.Data[i]); |
end |
end |
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// crc |
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for (int j = 0; j < 16; j++) begin |
@ICard.cbcard; |
for(int i = 0; i < 4; i++) begin |
crc[i] = ICard.cbcard.Data[i]; |
end |
end |
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// end bits |
@ICard.cbcard; |
$display("Endbits: %t", $time); |
assert(ICard.cbcard.Data == 'b1111); |
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$display("%b", ICard.cbcard.Data); |
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end |
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endtask |
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task automatic send(virtual ISdCard.Card ICmd, logic data[$]); |
aCrc16 crc = 0; |
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/sdhc-sc-core/trunk/src/grpSd/unitSdCardModel/src/SdCardModel.sv
24,12 → 24,17
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local event CmdReceived, InitDone; |
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local rand int datasize; // ram addresses = 2^datasize - 1; 512 byte blocks |
constraint cdatasize {datasize > 1; datasize <= 32;} |
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local logic[0:512*8-1] ram[]; |
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function new(virtual ISdCard CardInterface, event CmdReceived, event InitDone); |
ICard = CardInterface; |
state = new(); |
this.CmdReceived = CmdReceived; |
this.InitDone = InitDone; |
this.CCS = 0; |
this.CCS = 1; |
rca = 0; |
mode = standard; |
ICard.cbcard.Data <= 'z; |
89,6 → 94,9
SDCommandR6 rcaresponse; |
logic data[$]; |
SdData sddata; |
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// create ram |
ram = new[2^(datasize-1)]; |
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// expect CMD0 so that state is clear |
recv(); |
253,21 → 261,39
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task write(); |
SDCommandR1 response; |
SdData sddata = new(this.mode, widewidth); |
logic rddata[$]; |
logic[31:0] addr; |
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// expect Write |
recv(); |
assert(recvcmd.id == cSdCmdWriteSingleBlock); |
// recvcmd.arg = address |
addr = recvcmd.arg; |
assert(addr < ram.size()); |
response = new(cSdCmdWriteSingleBlock, state); |
response.send(ICard); |
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// TODO: receive data |
// recv data |
sddata.recv(ICard, rddata); |
$display("rddata: %p", rddata); |
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$display("datasize: %h", datasize); |
$display("Address: %h", addr); |
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// write into ram |
for (int i = 0; i < 512; i++) begin |
for (int j = 7; j >= 0; j--) begin |
ram[addr][i * 8 + j] = rddata.pop_front(); |
end |
end |
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$display("Ram at write address: %h", ram[addr]); |
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endtask |
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task recvCMD55(RCA_t rca); |
SDCommandR1 response; |
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// expect CMD55 |
recv(); |
assert(recvcmd.id == cSdCmdNextIsACMD); |
/sdhc-sc-core/trunk/src/grpSd/unitSdClockMaster/src/SdClockMaster-Rtl-a.vhdl
29,6 → 29,7
else |
if (iDisable = cActivated) then |
SdClk <= cActivated; |
Counter <= 0; |
else |
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if (iHighSpeed = cActivated) then |
67,7 → 68,7
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if (iDisable = cActivated) then |
oSdCardClk <= cInactivated; |
oSdStrobe <= cInactivated; |
oSdStrobe <= cInactivated; |
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else |
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/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src/SdVerificationTestbench.sv
31,6 → 31,7
SDCommandToken recvCmd, sendCmd; |
int c = 0; |
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assert(card.randomize()); |
ICmd.nResetAsync <= 0; |
BusInterface.RST_I <= 1; |
#10; |
61,7 → 62,7
begin // driver for wishbone interface |
@$root.Testbed.InitDone; |
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Bus.Write('b100, 'h01010101); |
Bus.Write('b100, 'h04030201); |
Bus.Write('b100, 'h02020202); |
Bus.Write('b100, 'h03030303); |
Bus.Write('b100, 'h04040404); |
73,7 → 74,8
Bus.Write('b000, 'h00000010); |
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#10000; |
Bus.Write('b100, 'h09090909); |
for (int i = 0; i < 512; i++) |
Bus.Write('b100, 'h09090909); |
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end |
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/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/wave.do
1,75 → 1,6
onerror {resume} |
quietly WaveActivateNextPane {} 0 |
add wave -noupdate -format Event /Testbed/CmdReceived |
add wave -noupdate -format Event /Testbed/InitDone |
add wave -noupdate -divider CardInterface |
add wave -noupdate -format Logic /Testbed/CardInterface/Clk |
add wave -noupdate -format Logic /Testbed/CardInterface/nResetAsync |
add wave -noupdate -format Logic /Testbed/CardInterface/Cmd |
add wave -noupdate -format Logic /Testbed/CardInterface/SClk |
add wave -noupdate -format Literal -radix hexadecimal /Testbed/CardInterface/Data |
add wave -noupdate -divider Wishbone |
add wave -noupdate -format Logic /Testbed/BusInterface/ERR_I |
add wave -noupdate -format Logic /Testbed/BusInterface/RTY_I |
add wave -noupdate -format Logic /Testbed/BusInterface/CLK_I |
add wave -noupdate -format Logic /Testbed/BusInterface/RST_I |
add wave -noupdate -format Logic /Testbed/BusInterface/ACK_I |
add wave -noupdate -format Literal /Testbed/BusInterface/DAT_I |
add wave -noupdate -format Logic /Testbed/BusInterface/CYC_O |
add wave -noupdate -format Literal /Testbed/BusInterface/ADR_O |
add wave -noupdate -format Literal /Testbed/BusInterface/DAT_O |
add wave -noupdate -format Logic /Testbed/BusInterface/SEL_O |
add wave -noupdate -format Logic /Testbed/BusInterface/STB_O |
add wave -noupdate -format Literal /Testbed/BusInterface/TGA_O |
add wave -noupdate -format Literal /Testbed/BusInterface/TGC_O |
add wave -noupdate -format Logic /Testbed/BusInterface/TGD_O |
add wave -noupdate -format Logic /Testbed/BusInterface/WE_O |
add wave -noupdate -format Logic /Testbed/BusInterface/LOCK_O |
add wave -noupdate -format Literal /Testbed/BusInterface/CTI_O |
add wave -noupdate -format Literal /Testbed/BusInterface/BTE_O |
add wave -noupdate -divider Controller |
add wave -noupdate -format Logic /Testbed/top/sdcontroller_inst/iclk |
add wave -noupdate -format Logic /Testbed/top/sdcontroller_inst/inresetasync |
add wave -noupdate -format Logic /Testbed/top/sdcontroller_inst/ohighspeed |
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/isdcmd |
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/osdcmd |
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/isddata |
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/osddata |
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/idataram |
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/odataram |
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/isdwbslave |
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/osdwbslave |
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/oledbank |
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/r |
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/nextr |
add wave -noupdate -divider data |
add wave -noupdate -format Logic /Testbed/top/sddata_inst/iclk |
add wave -noupdate -format Logic /Testbed/top/sddata_inst/inresetasync |
add wave -noupdate -format Logic /Testbed/top/sddata_inst/istrobe |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/isddatafromcontroller |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/osddatatocontroller |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/isddatafromram |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/osddatatoram |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/idata |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/odata |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/ireadfifo |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/oreadfifo |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/crcin |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/crcout |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/crcdatain |
add wave -noupdate -format Literal -expand /Testbed/top/sddata_inst/r |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/nextr |
add wave -noupdate -divider fifo |
add wave -noupdate -format Literal -radix unsigned /Testbed/top/writedatafifo_inst/data |
add wave -noupdate -format Logic /Testbed/top/writedatafifo_inst/rdclk |
add wave -noupdate -format Logic /Testbed/top/writedatafifo_inst/rdreq |
add wave -noupdate -format Logic /Testbed/top/writedatafifo_inst/wrclk |
add wave -noupdate -format Logic /Testbed/top/writedatafifo_inst/wrreq |
add wave -noupdate -format Literal -radix hexadecimal /Testbed/top/writedatafifo_inst/q |
add wave -noupdate -format Logic /Testbed/top/writedatafifo_inst/rdempty |
add wave -noupdate -format Logic /Testbed/top/writedatafifo_inst/wrfull |
TreeUpdate [SetDefaultTree] |
WaveRestoreCursors {{Cursor 1} {7675026 ns} 0} {{Cursor 2} {10084945 ns} 0} {{Cursor 3} {10085095 ns} 0} |
WaveRestoreCursors {{Cursor 1} {1092925 ns} 0} {{Cursor 2} {10084945 ns} 0} {{Cursor 3} {10085095 ns} 0} |
configure wave -namecolwidth 150 |
configure wave -valuecolwidth 100 |
configure wave -justifyvalue left |
84,4 → 15,4
configure wave -timeline 0 |
configure wave -timelineunits ns |
update |
WaveRestoreZoom {10084910 ns} {10085169 ns} |
WaveRestoreZoom {1113124 ns} {1113362 ns} |
/sdhc-sc-core/trunk/src/grpSd/unitSdController/src/SdController-e.vhdl
21,7 → 21,7
generic ( |
gClkFrequency : natural := 25E6; |
gHighSpeedMode : boolean := true; |
gStartupTimeout : time := 10 ms; |
gStartupTimeout : time := 1 ms; |
gReadTimeout : time := 100 ms |
); |
port ( |