URL
https://opencores.org/ocsvn/rise/rise/trunk
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- This comparison shows the changes necessary to convert path
/
- from Rev 124 to Rev 125
- ↔ Reverse comparison
Rev 124 → Rev 125
/trunk/vhdl/dmem.vhd
9,7 → 9,7
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library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use IEEE.STD_LOGIC_ARITH.all; |
use ieee.numeric_std.all; |
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use WORK.RISE_PACK.all; |
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19,7 → 19,6
port ( |
clk : in std_logic; |
reset : in std_logic; |
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wr_enable : in std_logic; |
addr : in MEM_ADDR_T; |
data_in : in MEM_DATA_T; |
40,6 → 39,7
sinit : in std_logic; |
we : in std_logic); |
end component; |
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component sc_uart is |
generic (ADDR_BITS : integer; |
CLK_FREQ : integer; |
54,7 → 54,7
WR_DATA : in std_logic_vector(15 downto 0); |
RD, WR : in std_logic; |
RD_DATA : out std_logic_vector(15 downto 0); |
RDY_CNT : out IEEE.NUMERIC_STD.unsigned(1 downto 0); |
RDY_CNT : out unsigned(1 downto 0); |
TXD : out std_logic; |
RXD : in std_logic; |
NCTS : in std_logic; |
62,19 → 62,21
end component; |
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signal uart_address(1 downto 0): std_logic_vector(1 downto 0); |
signal uart_wr_data :std_logic_vector(15 downto 0); |
signal uart_rd : std_logic; |
signal uart_wr : std_logic; |
signal uart_rd_data: std_logic_vector(15 downto 0); |
signal uart_address : std_logic_vector(1 downto 0); |
signal uart_wr_data :std_logic_vector(15 downto 0); |
signal uart_rd : std_logic; |
signal uart_wr : std_logic; |
signal uart_rd_data : std_logic_vector(15 downto 0); |
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signal uart_txd_sig : std_logic; |
signal uart_rxd_sig : std_logic; |
signal uart_txd_sig : std_logic; |
signal uart_rxd_sig : std_logic; |
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signal mem_addr : std_logic_vector (11 downto 0); |
signal mem_data_in :MEM_DATA_T; |
signal mem_data_out :MEM_DATA_T; |
signal mem_wr_enable: std_logic; |
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signal rdy_cnt_sig : IEEE.NUMERIC_STD.unsigned(1 downto 0); |
begin -- dmem_rtl |
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-- Uart modul einbinden |
95,7 → 97,7
RD => uart_rd, |
WR => uart_wr, |
RD_DATA => uart_rd_data, |
RDY_CNT => open, |
RDY_CNT => rdy_cnt_sig, |
TXD => uart_txd_sig, |
RXD => uart_rxd_sig, |
NCTS => '0', |
112,8 → 114,8
we => mem_wr_enable); |
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uart_txd <= uart_txd_sig; |
uart_rxd <= uart_rxd_sig; |
uart_txd <= uart_txd_sig; |
uart_rxd_sig <= uart_rxd; |
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process (wr_enable, addr, data_in, uart_rd_data, mem_data_out) |
begin |
139,7 → 141,7
mem_wr_enable <= wr_enable; |
end if; |
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end process |
end process; |
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end dmem_rtl; |
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