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/trunk/bench/vhdl/tb_prod-c.vhd
0,0 → 1,34
-------------------------------------------------------------------------------
--
-- Testbench for the production test.
--
-- $Id: tb_prod-c.vhd,v 1.1 2006-06-10 18:50:51 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
 
configuration tb_prod_behav_c0 of tb_prod is
 
for behav
 
for t420_b: t420
use configuration work.t420_struct_c0;
end for;
 
for tb_elems_b: tb_elems
use configuration work.tb_elems_behav_c0;
end for;
 
end for;
 
end tb_prod_behav_c0;
 
 
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
/trunk/bench/vhdl/tb_prod.vhd
0,0 → 1,451
-------------------------------------------------------------------------------
--
-- Testbench for the production test as proposed by
-- "Testing of COP400 Familiy Devices"
-- National Semiconductor
-- COP Note 7
-- April 1991
--
-- $Id: tb_prod.vhd,v 1.1 2006-06-10 18:50:51 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
 
entity tb_prod is
 
end tb_prod;
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.t400_system_comp_pack.t420;
use work.tb_pack.all;
use work.t400_opt_pack.all;
 
architecture behav of tb_prod is
 
-- 5 MHz clock
constant period_c : time := 200 ns;
signal ck_s : std_logic;
signal en_ck_s : std_logic := '0';
 
signal reset_n_s : std_logic;
 
signal io_l_s : std_logic_vector(7 downto 0);
signal io_d_s,
d_s : std_logic_vector(3 downto 0);
signal exp_d_s : std_logic_vector(3 downto 0) := "0000";
signal io_g_s,
g_s : std_logic_vector(3 downto 0);
signal exp_g_s : std_logic_vector(3 downto 0) := "0000";
signal io_in_s : std_logic_vector(3 downto 0);
 
signal si_s,
so_s,
sk_s : std_logic;
 
signal cs_n_s,
rd_n_s,
wr_n_s : std_logic;
 
signal tb_io_l_s : std_logic_vector(7 downto 0);
signal disable_s : boolean := true;
signal pass_s : std_logic := 'L';
signal fail_s : std_logic := 'L';
 
signal vdd4_s : std_logic_vector(3 downto 0);
 
begin
 
vdd4_s <= (others => '1');
reset_n_s <= '1';
 
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
t420_b : t420
generic map (
opt_ck_div_g => t400_opt_ck_div_4_c
)
port map (
ck_i => ck_s,
ck_en_i => en_ck_s,
reset_n_i => reset_n_s,
cko_i => io_in_s(2),
si_i => si_s,
so_o => so_s,
sk_o => sk_s,
io_l_b => io_l_s,
io_d_o => io_d_s,
io_g_b => io_g_s,
io_in_i => io_in_s
);
 
io_l_s <= (others => 'H');
io_d_s <= (others => 'L');
io_g_s <= (others => 'L');
io_in_s <= (others => 'H');
 
io_in_s <= io_g_s; -- feedthrough for production test
 
d_s <= to_X01(io_d_s);
g_s <= to_X01(io_g_s);
 
 
-----------------------------------------------------------------------------
-- Testbench elements
-----------------------------------------------------------------------------
tb_elems_b : tb_elems
generic map (
period_g => period_c,
d_width_g => 4,
g_width_g => 4
)
port map (
io_l_i => tb_io_l_s,
io_d_i => vdd4_s,
io_g_i => vdd4_s,
io_in_o => open,
so_i => so_s,
si_o => si_s,
sk_i => sk_s,
ck_o => ck_s
);
 
 
-----------------------------------------------------------------------------
-- Process ck_div
--
-- Purpose:
-- Generates the en_ck_s signal from the high frequency clock.
--
ck_div: process (ck_s)
variable cnt_v : natural := 0;
begin
if ck_s'event and ck_s = '1' then
en_ck_s <= '0';
 
if cnt_v = 25 then
cnt_v := 0;
en_ck_s <= '1';
else
cnt_v := cnt_v + 1;
end if;
end if;
end process ck_div;
--
-----------------------------------------------------------------------------
 
 
-----------------------------------------------------------------------------
-- Process exp
--
-- Purpose:
-- Sets the expected values for D and G ports.
--
exp: process
procedure w_p(signal sig : in std_logic_vector) is
begin
wait until sig'event;
end;
 
procedure exp_d_p(exp : in natural) is
begin
w_p(d_s);
exp_d_s <= std_logic_vector(to_unsigned(exp, 4));
end;
 
procedure exp_g_p(exp : in natural) is
begin
w_p(g_s);
exp_g_s <= std_logic_vector(to_unsigned(exp, 4));
end;
 
begin
-- default settings
pass_s <= 'L';
exp_d_s <= (others => '0');
exp_g_s <= (others => '0');
 
wait for 1 us;
disable_s <= false;
 
-- G(0 > 9)
exp_g_p(9);
 
-- G(9 > 6)
exp_g_p(6);
 
-- D(0 > 13)
exp_d_p(13);
 
-- D(13 > 3)
exp_d_p(3);
 
-- D(3 > 2)
exp_d_p(2);
 
-- D(2 > 3)
exp_d_p(3);
 
-- G(6 > 7)
exp_g_p(7);
 
-- G(7 > 8)
exp_g_p(8);
 
-- G(8 > 9)
exp_g_p(9);
 
-- G(9 > 11)
exp_g_p(11);
 
-- G(11 > 7)
exp_g_p(7);
 
-- G(7 > 1)
exp_g_p(1);
 
-- D(2 > 0)
exp_d_p(0);
 
-- G(1 > 5)
exp_g_p(5);
 
-- D(0 > 15)
exp_d_p(15);
 
-- G(5 > 9)
exp_g_p(9);
 
-- D(15 > 0)
exp_d_p(0);
 
-- G(9 > 10)
exp_g_p(10);
 
-- G(10 > 9)
exp_g_p(9);
 
-- G(9 > 1)
exp_g_p(1);
 
-- G(1 > 4)
exp_g_p(4);
 
-- G(4 > 14)
exp_g_p(14);
 
-- G(14 > 3)
exp_g_p(3);
 
-- G(3 > 14)
exp_g_p(14);
 
-- G(14 > 7)
exp_g_p(7);
 
-- G(7 > 9)
exp_g_p(9);
 
-- G(9 > 10)
exp_g_p(10);
 
-- G (10 > 7)
exp_g_p(7);
 
-- G(7 > 10)
exp_g_p(10);
 
-- G(10 > 7)
exp_g_p(7);
 
-- G(7 > 10)
exp_g_p(10);
 
-- G(10 > 0)
exp_g_p(0);
 
-- G(0 > 10)
exp_g_p(10);
 
-- G(10 > 7)
exp_g_p(7);
 
-- G(7 > 10)
exp_g_p(10);
 
-- D was at 15 before
-- -- D(15 > 0)
-- exp_d_p(0);
 
-- G(10 > 1)
exp_g_p(1);
 
-- G(1 > 0)
exp_g_p(0);
 
-- D(0 > 11)
exp_d_p(11);
 
-- G(10 > 9)
exp_g_p(9);
 
---------------------------------------------------------------------------
-- RAM tests
--
for reg in 0 to 3 loop
exp_g_p(7);
exp_g_p(14);
exp_g_p(5);
exp_g_p(12);
exp_g_p(3);
exp_g_p(10);
exp_g_p(1);
exp_g_p(8);
exp_g_p(15);
exp_g_p(6);
exp_g_p(13);
exp_g_p(4);
exp_g_p(11);
exp_g_p(2);
exp_g_p(9);
exp_g_p(0);
end loop;
 
wait for 1 us;
if fail_s /= '1' then
pass_s <= '1';
end if;
wait;
end process exp;
--
-----------------------------------------------------------------------------
 
 
-----------------------------------------------------------------------------
-- Process exp_d
--
-- Purpose:
-- Checks the expected value for the D port.
--
exp_d: process (ck_s)
begin
if disable_s then
fail_s <= 'L';
elsif ck_s'event and ck_s = '0' then
if d_s /= exp_d_s then
fail_s <= '1';
end if;
end if;
end process exp_d;
--
-----------------------------------------------------------------------------
 
 
-----------------------------------------------------------------------------
-- Process exp_g
--
-- Purpose:
-- Checks the expected value for the G port.
--
exp_g: process (ck_s)
begin
if disable_s then
fail_s <= 'L';
elsif ck_s'event and ck_s = '0' then
if g_s /= exp_g_s then
fail_s <= '1';
end if;
end if;
end process exp_g;
--
-----------------------------------------------------------------------------
 
 
-----------------------------------------------------------------------------
-- Process pass_fail
--
-- Purpose:
-- Collects the pass/fail signal and generates the respective sequence
-- on tb_io_l_s.
--
pass_fail: process
procedure tb_pass_fail(pass : in boolean) is
begin
tb_io_l_s <= "00000000";
wait for 1 us;
tb_io_l_s <= "10100000";
wait for 1 us;
tb_io_l_s <= "01010000";
wait for 1 us;
 
if pass then
tb_io_l_s <= "00000000";
else
tb_io_l_s <= "11110000";
end if;
wait for 1 us;
end;
 
begin
tb_io_l_s <= (others => '0');
 
loop
wait until pass_s'event or fail_s'event;
if fail_s = '1' then
tb_pass_fail(pass => false);
elsif pass_s = '1' then
tb_pass_fail(pass => true);
end if;
end loop;
end process pass_fail;
--
-----------------------------------------------------------------------------
 
end behav;
 
 
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
/trunk/sw/verif/system/production_test/prod --- trunk/sw/verif/system/production_test/test.asm (nonexistent) +++ trunk/sw/verif/system/production_test/test.asm (revision 125) @@ -0,0 +1,504 @@ + ;; ******************************************************************* + ;; $Id: test.asm,v 1.1 2006-06-10 18:49:47 arniml Exp $ + ;; + ;; Production test as proposed by + ;; "Testing of COP400 Familiy Devices" + ;; National Semiconductor + ;; COP Note 7 + ;; April 1991 + ;; + + ;; the cpu type is defined on asl's command line + + org 0x00 + +; INSTRUCTION RESULT COMMENTS + + NOP ; NO CHANGE CHECK NOP & ALLOW TRANSIENT + ; CYCLE FOR MODE + OGI 9 ; G(0 > 9) NOT FOR 410L/411L + OGI 6 ; G(9 > 6) REVERSE ALL G STATES + STII 8 ; SET UP 0,0 FOR FUTURE + LBI 3, 13 ; B TO NEW POSITION (3, 13) + OBD ; D(0 > 13) CHECK D + CLRA ; MAKE SURE A = 0 + XABR ; 3 > A;0 > Br + CAB ; MOVE 3 to Bd + OBD ; D(13 > 3) CHECK XABR CAB & D CHANGE + CLRA ; ! + AISC 2 ; !FORCE A > 2 + CAB ; 2 > Bd + OBD ; D(3 > 2) VERIFY 2 FROM A > Bd + STII 7 ; 7 > 0,2 & Bd > 3 + OBD ; D(2 > 3) STII INCREMENTS Bd + CAB ; SEE THAT A STILL THE SAME + OMG ; G(6 > 7) OMB & RAM CHECK + CLRA + CAB ; B(0,0) + OMG ; G(7 > 8) TIE IN RAM, A & G OPERATION + SMB 0 ; SMB INST. CHECK + OMG ; G(8 > 9) : + SMB 1 ; : + OMG ; G(9 > 11) : + RMB 0 ; : + RMB 3 ; : + LD 0 ; :2 > A (modified AL) + CAB ; A = 2 > B + OMG ; G(11 > 7) OUTPUT M(0,2) + LD 1 ; M(0,2) > A; B > 1,2 + XAD 0,0 ; A(7) < => M(0,0) 2 + AISC 15 ; AISC CHECK; A = 1 + LDD 0,0 ; CHECK SKIP OF 2 BYTE INST. + X 0 ; STORE 1 + OMG ; G(7 > 1) VERIFY + LD 0 ; COPY1,2 BACK TO A + ADT ; ADD TEN + XDS 0 ; LEAVE 11 IN 1,2;GO 1, 1 WITH 1 + XDS 0 ; LEAVE 1 IN 1,1;GO 1,0 W ? + OBD ; D(2 > 0) CHECK Bd MOVEMENT + STII 5 ; 5 > 1,0;Bd TO 1,1 + CBA ; CHECK B > A + AISC 3 ; AISC CHECK 4 >A + +; INSTRUCTION RESULT COMMENTS + + XDS 0 ; 1 > A; 4 > 1,1 + OMG ; G(1 > 5) FROM 1,0 + XDS 0 ; 5 > A; 1 > 1,0; Bd < 15 SKIP + LDD 0,0 ; SKIPPED ! + OBD ; D(0 > 15) + AISC 4 ; 9 > A + X 0 ; 9 > 15 + OMG ; G(5 > 9) + CLRA + COMP ; ONES TO A + XOR ; FLIP MEMORY + XIS 0 ; 6 > 1,15; 9 > A; Bd > 1,0 + LDD 0,0 ; SKIP + AISC 8 ; A > 1 (added AL) + LDD 0,0 ; SKIP (added AL) + SKE + LBI 1,2 ; SKIP 2 WORD LBI (NOT IN 410) + OBD ; D(15 > 0) VERIFY WORD + SKE ; 11 NOT = 9 + LBI 1,0 ; BACK TO 1,0 + SMB 2 ; : + SKE ; : + RMB 2 ; : + SKE ; :CHECK BIT + SMB 3 ; :MANIPULATIONS + SKE ; : + LDD 0,0 ; : + X 3 ; Bd > 2,0 + XAD 1,1 ; 9 > 1,1; 4 > A + XIS 1 ; 4 > 2,0; Bd > 3,1 + ING ; INPUT G PORT + X 0 ; STORE + +; INSTRUCTION RESULT COMMENTS + + CLRA + ASC ; CHECK ADD WITH CARRY + SC ; CHECK SET CARRY + SKC ; CHECK SKIP ON CARRY + LDD 0,0 + X 0 ; STORE A + OMG ; G = 9 NO CHANGE + CLRA + ASC + X 0 + OMG ; G(9 > 10) CARRY ADDS ONE TO MEMORY + CAMQ ; STORE A & M IN Q; 10,9 + XDS 0 ; 9 > 3,1; 10 > A; Bd > 3,0 + CQMA ; STORE 9 IN 3,0 (added AL) + OMG ; G(10 > 9) + LD 2 ; 9 > A; Bd > 1,0 + +; INSTRUCTION RESULT COMMENTS + + OMG ; G(9 > 1) + LD 3 ; 1 > A; Bd > 2,0 + OMG ; G(1 > 4) (result corrected AL) + ADD ; ADD WITHOUT CARRY + X 0 ; STORE 3 IN 2,0 + SC + LDD 0,0 ; 7 > A + CASC ; CHECK CASC + SKC + X 0 ; STORE 12 + OMG ; G(4 > 14) (prev and current result corrected AL) + CLRA ; : + AISC 3 ; : + X 0 ; : + SC ; :CHECK + SKC ; :SKC/SC + X 0 ; : + OMG ; G(14 > 3) (prev result corrected AL) + RC ; : + SKC ; :CHECK + X 0 ; :RC + OMG ; G(3 > 14) : + LBI 0,0 ; :CHECK + LBI 1,15 ; ;SEQUENTIAL LBI'S + LBI 2,7 ; ALSO SKIPPED (LBI 2,7 NOT IN 410) + OMG ; G(14 > 7) + CQMA ; LOAD CONSTANTS FROM Q + OMG ; G(7 > 9) CHECK + X 0 ; : + OMG ; G(9 > 10) : + LEI 1 + XAS ; STORE A - > S (9) + CLRA + AISC 7 ; : + SKGBZ 0 ; : + X 0 ; :CHECK + OMG ; : + SKGBZ 1 ; : + X 0 ; ;G BIT + OMG ; G (10 > 7) : + SKGBZ 2 ; : + X 0 ; : + OMG ; G(7 > 10) :TESTS + SKGBZ 3 ; : + X 0 ; : + OMG ; G(10 > 7) : + +; INSTRUCTION RESULT COMMENTS + + SKGZ + X 0 ; :CHECK + OMG ; G(7 > 10) : + OGI 0 ; G(10 > 0) :G TEST + SKGZ ; : + X 0 ; : + OMG ; G(0 > 10) : + SKMBZ 0 + X 0 ; CHECK MEMORY BIT TESTS + OMG ; NO CHANGE + SKMBZ 1 + +; INSTRUCTION RESULT COMMENTS + + X 0 + OMG ; G(10 > 7) NO SKIP + SKMBZ 2 + X 0 ; WON'T SKIP + OMG ; G(7 > 10) + INIL ; SEE THAT L LATCHES RESET + ININ ; ASSUME G - > I + SKE + X 1 ; Br > 1 + OMG ; SHOULD BE EQUAL + INIL ; : + X 0 ; : + SKMBZ 3 ; : + OBD ; D(15 > 0) :INIL TEST + OGI 1 ; G(10 > 1) :(result added AL) + LBI 3,11 ; : + OGI 0 ; G(1 > 0) :(result added AL) + NOP ; (NOP added AL) + INIL ; : + X 0 ; : + SKMBZ 0 ; : + OBD ; D(0 > 11) : + NOP + XAS ; : + X 0 ; :XAS TEST + OMG ; G(10 > 9) : + +; INSTRUCTION RESULT COMMENTS + + LBI 0,0 ; LOAD RAM WITH + STII 7 ; CONSTANTS USING + STII 14 ; STII + STII 5 + STII 12 + STII 3 + STII 10 + STII 1 + STII 8 + STII 15 + STII 6 + STII 13 + STII 4 + STII 11 + STII 2 + STII 9 + STII 0 + LBI 1,0 + STII 7 + STII 14 + STII 5 + STII 12 + STII 3 + STII 10 + STII 1 + STII 8 + STII 15 + STII 6 + STII 13 + STII 4 + STII 11 + STII 2 + STII 9 + STII 0 + LBI 2,0 + STII 7 + STII 14 + STII 5 + STII 12 + STII 3 + STII 10 + STII 1 + STII 8 + STII 15 + STII 6 + STII 13 + +; INSTRUCTION RESULT COMMENTS + + STII 4 + STII 11 + +; INSTRUCTION RESULT COMMENTS + + STII 2 + STII 9 + STII 0 + LBI 3,0 + STII 7 + STII 14 + STII 5 + STII 12 + STII 3 + STII 10 + STII 1 + STII 8 + STII 15 + STII 6 + STII 13 + STII 4 + STII 11 + STII 2 + STII 9 + STII 0 + +; INSTRUCTION RESULT COMMENTS + + LBI 0,0 ; CHECK FOR RAM DATA + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + NOP + +; INSTRUCTION RESULT COMMENTS + + LBI 1,0 ; CHECK FOR RAM DATA + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + +; INSTRUCTION RESULT COMMENTS + + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + NOP + +; INSTRUCTION RESULT COMMENTS + + LBI 2,0 ; CHECK FOR RAM DATA + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + +; INSTRUCTION RESULT COMMENTS + + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + NOP + +; INSTRUCTION RESULT COMMENTS + + LBI 3,0 ; CHECK FOR RAM DATA + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + OMG ; OUTPUT DATA + LD 0 ; : + XIS 0 ; :MOVE TO NEXT DIGIT + NOP + + jmp .

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