OpenCores
URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 125 to Rev 126
    ↔ Reverse comparison
  •

Rev 125 → Rev 126

/sdhc-sc-core/trunk/src/grpSd/unitSdCardModel/src/SdData.sv
61,7 → 61,7
 
// end bits
@ICard.cbcard;
$display("Endbits: %t", $time);
$display("Endbits: %h, %t", ICard.cbcard.Data, $time);
assert(ICard.cbcard.Data == 'b1111);
 
$display("%b", ICard.cbcard.Data);
/sdhc-sc-core/trunk/src/grpSd/unitSdCardModel/src/SdCardModel.sv
27,7 → 27,7
local rand int datasize; // ram addresses = 2^datasize - 1; 512 byte blocks
constraint cdatasize {datasize > 1; datasize <= 32;}
 
local logic[0:512*8-1] ram[];
local logic[512*8-1:0] ram[];
 
function new(virtual ISdCard CardInterface, event CmdReceived, event InitDone);
ICard = CardInterface;
208,7 → 208,7
for (int i = 0; i < 512; i++)
data.push_back(0);
 
data[511-400] = 1;
data[511-401] = 1;
data[511-376] = 1;
sddata.send(ICard, data);
 
224,7 → 224,7
for (int i = 0; i < 512; i++)
data.push_back(0);
 
data[511-400] = 1;
data[511-401] = 1;
data[511-376] = 1;
sddata.send(ICard, data);
 
243,18 → 243,23
task read();
SDCommandR1 response;
logic data[$];
logic[31:0] addr;
SdData sddata = new(mode, usual);
 
// expect Read
recv();
assert(recvcmd.id == cSdCmdReadSingleBlock);
// recvcmd.arg = address
addr = recvcmd.arg;
assert(addr < ram.size());
response = new(cSdCmdReadSingleBlock, state);
response.send(ICard);
 
data = {};
for(int i = 0; i < (512 * 8); i++)
data.push_back(1);
for (int i = 0; i < 512; i++) begin
for (int j = 7; j >= 0; j--) begin
data.push_back(ram[addr][i*8 + j]);
end
end
 
sddata.send(ICard, data);
endtask
/sdhc-sc-core/trunk/src/grpSd/unitSdTop/src/SdTop-Rtl-ea.vhdl
15,7 → 15,7
 
entity SdTop is
generic (
gUseSameClocks : boolean := true;
gUseSameClocks : boolean := false;
gClkFrequency : natural := 100E6;
gHighSpeedMode : boolean := true
);
77,10 → 77,15
signal iWbDat : aSdWbSlaveDataInput;
signal oWbDat : aSdWbSlaveDataOutput;
signal SdWbSlaveToWriteFifo : aoWriteFifo;
signal SdWbSlaveToReadFifo : aoReadFifo;
signal WriteFifoToSdWbSlave : aiWriteFifo;
signal iReadFifo : aiReadFifo;
signal oReadFifo : aoReadFifo;
signal SdWbSlaveFromReadFifo : aiReadFifo;
signal iReadWriteFifo : aiReadFifo;
signal oReadWriteFifo : aoReadFifo;
signal iWriteReadFifo : aiWriteFifo;
signal oWriteReadFifo : aoWriteFifo;
signal ReadFifoQTemp : std_logic_vector(31 downto 0);
signal WriteFifoQTemp : std_logic_vector(31 downto 0);
signal DisableSdClk : std_ulogic;
 
begin
142,7 → 147,11
 
-- To write fifo
oWriteFifo => SdWbSlaveToWriteFifo,
iWriteFifo => WriteFifoToSdWbSlave
iWriteFifo => WriteFifoToSdWbSlave,
 
-- To read fifo
oReadFifo => SdWbSlaveToReadFifo,
iReadFifo => SdWbSlaveFromReadFifo
);
 
SdController_inst: entity work.SdController(Rtl)
158,8 → 167,6
oSdCmd => SdCmdFromController,
iSdData => SdDataToController,
oSdData => SdDataFromController,
iDataRam => SdControllerFromDataRam,
oDataRam => SdControllerToDataRam,
oSdWbSlave => iSdControllerSync,
iSdWbSlave => oSdControllerSync,
oLedBank => oLedBank
183,30 → 190,15
iStrobe => SdStrobe,
iSdDataFromController => SdDataFromController,
oSdDataToController => SdDataToController,
iSdDataFromRam => SdDataFromRam,
oSdDataToRam => SdDataToRam,
iData => iData,
oData => oData,
oReadFifo => oReadFifo,
iReadFifo => iReadFifo,
oReadWriteFifo => oReadWriteFifo,
iReadWriteFifo => iReadWriteFifo,
oWriteReadFifo => oWriteReadFifo,
iWriteReadFifo => iWriteReadFifo,
oDisableSdClk => DisableSdClk
);
 
DataRam_inst: entity work.SimpleDualPortedRam
generic map (
gDataWidth => 32,
gAddrWidth => 7
)
port map (
iClk => iSdClk,
iAddrRW => SdDataToRam.Addr,
iDataRW => SdDataToRam.Data,
iWeRW => SdDataToRam.We,
oDataRW => SdDataFromRam.Data,
iAddrR => SdControllerToDataRam.Addr,
oDataR => SdControllerFromDataRam.Data
);
 
SdClockMaster_inst: entity work.SdClockMaster
generic map (
gClkFrequency => gClkFrequency
236,15 → 228,29
port map (
data => std_logic_vector(SdWbSlaveToWriteFifo.data),
rdclk => iSdClk,
rdreq => oReadFifo.rdreq,
rdreq => oReadWriteFifo.rdreq,
wrclk => iWbClk,
wrreq => SdWbSlaveToWriteFifo.wrreq,
q => ReadFifoQTemp,
rdempty => iReadFifo.rdempty,
rdempty => iReadWriteFifo.rdempty,
wrfull => WriteFifoToSdWbSlave.wrfull
);
 
iReadFifo.q <= std_ulogic_vector(ReadFifoQTemp);
iReadWriteFifo.q <= std_ulogic_vector(ReadFifoQTemp);
 
ReadDataFifo_inst: entity work.WriteDataFifo
port map (
data => std_logic_vector(oWriteReadFifo.data),
rdclk => iWbClk,
rdreq => SdWbSlaveToReadFifo.rdreq,
wrclk => iSdClk,
wrreq => oWriteReadFifo.wrreq,
q => WriteFifoQTemp,
rdempty => SdWbSlaveFromReadFifo.rdempty,
wrfull => iWriteReadFifo.wrfull
);
 
SdWbSlaveFromReadFifo.q <= std_ulogic_vector(WriteFifoQTemp);
 
end architecture Rtl;
 
/sdhc-sc-core/trunk/src/grpSd/unitSdTop/syn/SdTopsyn.tcl
18,7 → 18,7
package require ::quartus::project
package require ::quartus::flow
 
project_new TbdSdsyn -revision TbdSdSyn -overwrite
project_new SdTopsyn -revision SdTopSyn -overwrite
 
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C35F484C8
/sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/src/SdWbSlave-Rtl-a.vhdl
11,30 → 11,37
 
type aWbState is (idle, ClassicWrite, ClassicRead);
type aSdIntState is (idle, newOperation);
type aReadBufferState is (invalid, readreq, latchdata, valid);
 
type aRegs is record
 
WbState : aWbState; -- state of the wb interface
SdIntState : aSdIntState; -- state of the sd controller interface
OperationBlock : aOperationBlock; -- Operation for the SdController
ReqOperation : std_ulogic; -- Register for catching edges on the SdController ReqOperationEdge line
-- Register outputs
oWbDat : aSdWbSlaveDataOutput;
oWbCtrl : aWbSlaveCtrlOutput;
oController : aSdWbSlaveToSdController;
oWriteFifo : aoWriteFifo;
WbState : aWbState; -- state of the wb interface
SdIntState : aSdIntState; -- state of the sd controller interface
OperationBlock : aOperationBlock; -- Operation for the SdController
ReqOperation : std_ulogic; -- Register for catching edges on the SdController ReqOperationEdge line
ReadBuffer : aData;
ReadBufferState : aReadBufferState;
-- Register outputs
oWbDat : aSdWbSlaveDataOutput;
oWbCtrl : aWbSlaveCtrlOutput;
oController : aSdWbSlaveToSdController;
oWriteFifo : aoWriteFifo;
oReadFifo : aoReadFifo;
 
end record aRegs;
 
constant cDefaultRegs : aRegs := (
WbState => idle,
SdIntState => idle,
OperationBlock => cDefaultOperationBlock,
ReqOperation => cInactivated,
oWbDat => (Dat => (others => '0')),
oWbCtrl => cDefaultWbSlaveCtrlOutput,
oController => cDefaultSdWbSlaveToSdController,
oWriteFifo => cDefaultoWriteFifo);
WbState => idle,
SdIntState => idle,
OperationBlock => cDefaultOperationBlock,
ReqOperation => cInactivated,
oWbDat => (Dat => (others => '0')),
oWbCtrl => cDefaultWbSlaveCtrlOutput,
oController => cDefaultSdWbSlaveToSdController,
oWriteFifo => cDefaultoWriteFifo,
oReadFifo => cDefaultoReadFifo,
ReadBuffer => (others => '0'),
ReadBufferState => invalid);
 
signal R, NxR : aRegs;
 
43,6 → 50,7
oWbCtrl <= R.oWbCtrl;
oController <= R.oController;
oWriteFifo <= R.oWriteFifo;
oReadFifo <= R.oReadFifo;
 
WbStateReg : process (iClk, iRstSync)
begin
55,7 → 63,7
end if;
end process WbStateReg ;
 
WbStateAndOutputs : process (iWbCtrl, iWbDat, iController, iWriteFifo, R)
WbStateAndOutputs : process (iWbCtrl, iWbDat, iController, iWriteFifo, iReadFifo, R)
begin
-- Default Assignments
 
64,6 → 72,32
NxR.oWbCtrl <= cDefaultWbSlaveCtrlOutput;
NxR.oWriteFifo <= cDefaultoWriteFifo;
 
case R.ReadBufferState is
when invalid =>
-- is new data available?
if (iReadFifo.rdempty = cInactivated) then
NxR.oReadFifo.rdreq <= cActivated;
NxR.ReadBufferState <= readreq;
end if;
 
when readreq =>
-- readreq was sent, data is available next cylce
NxR.oReadFifo.rdreq <= cInactivated;
NxR.ReadBufferState <= latchdata;
 
when latchdata =>
NxR.ReadBuffer <= iReadFifo.q;
NxR.ReadBufferState <= valid;
 
when valid =>
-- do nothing, wishbone statemachine sets the state to invalid when it used it
null;
 
when others =>
report "Error: Invalid ReadBufferState" severity error;
end case;
 
-- Determine next state
case R.WbState is
when idle =>
90,8 → 124,32
NxR.oWbDat.Dat <= R.OperationBlock.EndAddr;
 
when cReadDataAddr =>
-- read data from fifo
-- check if data is available
case R.ReadBufferState is
when valid =>
-- use buffered data
NxR.oWbDat.Dat <= R.ReadBuffer;
NxR.ReadBufferState <= invalid;
 
when latchdata =>
-- use input directly
NxR.oWbDat.Dat <= iReadFifo.q;
NxR.ReadBufferState <= invalid;
 
when readreq =>
-- no data available, insert a waitstate
NxR.oWbCtrl.Ack <= cInactivated;
NxR.WbState <= idle;
 
when invalid =>
-- no data available, insert a waitstate
NxR.oWbCtrl.Ack <= cInactivated;
NxR.WbState <= idle;
 
when others =>
report "Invalid ReadBufferState" severity error;
end case;
 
when others =>
report "Read to an invalid address" severity warning;
NxR.oWbCtrl.Err <= cActivated;
/sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/src/SdWbSlave-e.vhdl
31,7 → 31,11
 
-- To write fifo
oWriteFifo : out aoWriteFifo;
iWriteFifo : in aiWriteFifo
iWriteFifo : in aiWriteFifo;
-- To read fifo
oReadFifo : out aoReadFifo;
iReadFifo : in aiReadFifo
);
end entity;
 
/sdhc-sc-core/trunk/src/grpSd/unitSdClockMaster/src/SdClockMaster-Rtl-a.vhdl
13,6 → 13,7
signal Counter : natural range 0 to 3;
signal SdStrobe25MHz : std_ulogic;
signal SdStrobe50MHz : std_ulogic;
signal Disable : std_ulogic;
 
begin
 
27,29 → 28,33
Counter <= 0;
SdClk <= cInactivated;
else
if (iDisable = cActivated) then
SdClk <= cActivated;
Counter <= 0;
if (iDisable = cActivated and SdClk = cInactivated) then
Disable <= cActivated;
else
 
if (iHighSpeed = cActivated) then
if (Counter = 0 or Counter = 2) then
SdClk <= cActivated;
else
SdClk <= cInactivated;
end if;
if (Disable = cActivated and iDisable = cInactivated) then
Disable <= cInactivated;
else
if (Counter = 0 or Counter = 1) then
SdClk <= cActivated;
 
if (iHighSpeed = cActivated) then
if (Counter = 0 or Counter = 2) then
SdClk <= cActivated;
else
SdClk <= cInactivated;
end if;
else
SdClk <= cInactivated;
if (Counter = 0 or Counter = 1) then
SdClk <= cActivated;
else
SdClk <= cInactivated;
end if;
end if;
end if;
 
if (Counter < 3) then
Counter <= Counter + 1;
else
Counter <= 0;
if (Counter < 3) then
Counter <= Counter + 1;
else
Counter <= 0;
end if;
end if;
end if;
end if;
71,7 → 76,7
oSdStrobe <= cInactivated;
 
else
 
oSdCardClk <= not SdClk;
 
if (iHighSpeed = cInactivated) then
/sdhc-sc-core/trunk/src/grpSd/unitSdData/src/SdData-Rtl-a.vhdl
18,35 → 18,35
subtype aByteCounter is unsigned(LogDualis(8)-1 downto 0);
 
type aReg is record
State : aState;
Region : aRegion;
BlockCounter : aBlockCounter;
ByteCounter : aByteCounter;
WordCounter : aWordCounter;
FirstSend : std_ulogic;
Data : aoSdData;
Controller : aSdDataToController;
Ram : aSdDataToRam;
ReadFifo : aoReadFifo;
Mode : aSdDataBusMode;
Word : aWord;
DisableSdClk : std_ulogic;
State : aState;
Region : aRegion;
BlockCounter : aBlockCounter;
ByteCounter : aByteCounter;
WordCounter : aWordCounter;
FirstSend : std_ulogic;
Data : aoSdData;
Controller : aSdDataToController;
ReadWriteFifo : aoReadFifo;
WriteReadFifo : aoWriteFifo;
Mode : aSdDataBusMode;
Word : aWord;
DisableSdClk : std_ulogic;
end record aReg;
 
constant cDefaultReg : aReg := (
State => idle,
Region => startbit,
BlockCounter => to_unsigned(0, aBlockCounter'length),
WordCounter => to_unsigned(0, aWordCounter'length),
ByteCounter => to_unsigned(7, aByteCounter'length),
FirstSend => cInactivated,
Data => (Data => "0000", En => "0000"),
Controller => cDefaultSdDataToController,
Ram => cDefaultSdDataToRam,
ReadFifo => cDefaultoReadFifo,
Mode => standard,
Word => (others => '0'),
DisableSdClk => cInactivated);
State => idle,
Region => startbit,
BlockCounter => to_unsigned(0, aBlockCounter'length),
WordCounter => to_unsigned(0, aWordCounter'length),
ByteCounter => to_unsigned(7, aByteCounter'length),
FirstSend => cInactivated,
Data => (Data => "0000", En => "0000"),
Controller => cDefaultSdDataToController,
ReadWriteFifo => cDefaultoReadFifo,
WriteReadFifo => cDefaultoWriteFifo,
Mode => standard,
Word => (others => '0'),
DisableSdClk => cInactivated);
 
type aCrcOut is record
Clear : std_ulogic;
80,8 → 80,8
"000" & CrcOut.DataIn;
 
oSdDataToController <= R.Controller;
oSdDataToRam <= R.Ram;
oReadFifo <= R.ReadFifo;
oReadWriteFifo <= R.ReadWriteFifo;
oWriteReadFifo <= R.WriteReadFifo;
oDisableSdClk <= R.DisableSdClk;
 
Regs : process (iClk, inResetAsync)
92,12 → 92,13
if (iStrobe = cActivated) then
R <= NextR;
end if;
R.ReadFifo.rdreq <= NextR.ReadFifo.rdreq and iStrobe;
R.ReadWriteFifo.rdreq <= NextR.ReadWriteFifo.rdreq and iStrobe;
R.WriteReadFifo.wrreq <= NextR.WriteReadFifo.wrreq and iStrobe;
R.DisableSdClk <= NextR.DisableSdClk;
end if;
end process Regs;
 
Comb : process (iData.Data, iSdDataFromController, CrcIn, iReadFifo, R)
Comb : process (iData.Data, iSdDataFromController, CrcIn, iReadWriteFifo, iWriteReadFifo, R)
 
procedure ShiftIntoCrc (constant data : in std_ulogic_vector(3 downto 0)) is
begin
124,11 → 125,9
 
if (R.WordCounter = 0) then
NextR.WordCounter <= to_unsigned(3, aWordCounter'length);
NextR.FirstSend <= cInactivated;
 
-- save word to ram
NextR.Ram.We <= cActivated;
NextR.Ram.En <= cActivated;
-- NextR.WriteReadFifo.wrreq <= cActivated;
 
if (R.BlockCounter = 0) then
NextR.Region <= crc;
136,10 → 135,6
NextR.BlockCounter <= R.BlockCounter - 1;
end if;
else
if (R.WordCounter = 3 and R.FirstSend = cInactivated) then
NextR.Ram.Addr <= R.Ram.Addr + 1;
end if;
 
NextR.WordCounter <= R.WordCounter - 1;
end if;
else
147,9 → 142,14
end if;
 
end procedure NextCounterAndSaveToRamWide;
 
procedure NextCounterAndSaveToRamUsual(constant byteend : natural; constant bytedec : natural) is
begin
if (R.WordCounter = 0 and R.ByteCounter = 7 and R.FirstSend = cInactivated) then
-- save word to ram
NextR.WriteReadFifo.wrreq <= cActivated;
NextR.WriteReadFifo.data <= R.Word;
end if;
 
if (R.ByteCounter = byteend) then
NextR.ByteCounter <= to_unsigned(7, aByteCounter'length);
156,12 → 156,8
 
if (R.WordCounter = 3) then
NextR.WordCounter <= to_unsigned(0, aWordCounter'length);
NextR.FirstSend <= cInactivated;
 
-- save word to ram
NextR.Ram.We <= cActivated;
NextR.Ram.En <= cActivated;
 
NextR.FirstSend <= cInactivated;
if (R.BlockCounter = 127) then
NextR.BlockCounter <= to_unsigned(0, aBlockCounter'length);
NextR.Region <= crc;
169,10 → 165,6
NextR.BlockCounter <= R.BlockCounter + 1;
end if;
else
if (R.WordCounter = 0 and R.FirstSend = cInactivated) then
NextR.Ram.Addr <= R.Ram.Addr + 1;
end if;
 
NextR.WordCounter <= R.WordCounter + 1;
end if;
else
184,14 → 176,19
variable temp : std_ulogic_vector(3 downto 0) := "0000";
 
begin
NextR <= R;
NextR.Data.En <= (others => cInactivated);
NextR.Controller <= cDefaultSdDataToController;
NextR.Ram.We <= cInactivated;
NextR.Ram.En <= cInactivated;
NextR.ReadFifo <= cDefaultoReadFifo;
CrcOut <= cDefaultCrcOut;
 
-- default assignments
 
NextR <= R;
NextR.Data.En <= (others => cInactivated);
NextR.Controller <= cDefaultSdDataToController;
NextR.Controller.WideMode <= R.Controller.WideMode;
NextR.Controller.SpeedBits.HighSpeedSupported <= R.Controller.SpeedBits.HighSpeedSupported;
NextR.Controller.SpeedBits.SwitchFunctionOK <= R.Controller.SpeedBits.SwitchFunctionOK;
NextR.ReadWriteFifo <= cDefaultoReadFifo;
NextR.WriteReadFifo <= cDefaultoWriteFifo;
CrcOut <= cDefaultCrcOut;
 
case R.State is
when idle =>
if (iSdDataFromController.CheckBusy = cActivated and iData.Data(0) = cInactivated) then
202,7 → 199,6
NextR.Region <= data;
NextR.State <= receive;
NextR.ByteCounter <= to_unsigned(7,aByteCounter'length);
NextR.Ram.Addr <= iSdDataFromController.StartAddr;
NextR.FirstSend <= cActivated;
 
if (iSdDataFromController.DataMode = widewidth) then
220,7 → 216,7
end if;
 
elsif (iSdDataFromController.Valid = cActivated) then
case iReadFifo.rdempty is
case iReadWriteFifo.rdempty is
when cActivated =>
report "Fifo empty, waiting for data" severity note;
NextR.DisableSdClk <= cActivated;
228,7 → 224,7
when cInactivated =>
NextR.State <= send;
NextR.Region <= startbit;
NextR.ReadFifo.rdreq <= cActivated;
NextR.ReadWriteFifo.rdreq <= cActivated;
NextR.DisableSdClk <= cInactivated;
NextR.WordCounter <= to_unsigned(0, aWordCounter'length);
 
257,7 → 253,7
NextR.Region <= data;
 
-- save data from fifo
NextR.Word <= iReadFifo.q;
NextR.Word <= iReadWriteFifo.q;
 
when data =>
case R.Mode is
281,7 → 277,7
NextR.BlockCounter <= R.BlockCounter + 1;
 
-- save data
NextR.Word <= iReadFifo.q;
NextR.Word <= iReadWriteFifo.q;
end if;
 
else
294,7 → 290,7
 
if ((R.ByteCounter = 7 and R.WordCounter = 3 and R.BlockCounter < 127)) then
-- handle rdempty
if (iReadFifo.rdempty = cActivated) then
if (iReadWriteFifo.rdempty = cActivated) then
report "No data available, fifo empty, waiting for new data" severity note;
NextR.DisableSdClk <= cActivated;
NextR.ByteCounter <= R.ByteCounter;
302,7 → 298,7
else
-- request new data from fifo
NextR.DisableSdClk <= cInactivated;
NextR.ReadFifo.rdreq <= cActivated;
NextR.ReadWriteFifo.rdreq <= cActivated;
end if;
end if;
 
312,13 → 308,15
SendBitAndShiftIntoCrc(temp);
 
if (R.ByteCounter = 1 and R.WordCounter = 3 and R.BlockCounter < 127) then
-- TODO: handle rdempty
if (iReadFifo.rdempty = cActivated) then
-- handle rdempty
if (iReadWriteFifo.rdempty = cActivated) then
report "No data available, fifo empty, waiting for new data" severity note;
NextR.DisableSdClk <= cActivated;
NextR.ByteCounter <= R.ByteCounter;
 
else
-- request new data from fifo
NextR.ReadFifo.rdreq <= cActivated;
NextR.ReadWriteFifo.rdreq <= cActivated;
end if;
end if;
 
336,7 → 334,7
NextR.BlockCounter <= R.BlockCounter + 1;
 
-- save data
NextR.Word <= iReadFifo.q;
NextR.Word <= iReadWriteFifo.q;
end if;
 
else
378,13 → 376,13
when usual =>
case R.Mode is
when standard =>
NextR.Ram.Data(CalcBitAddrInWord(R.WordCounter, R.ByteCounter)) <= iData.Data(0);
NextR.Word(CalcBitAddrInWord(R.WordCounter, R.ByteCounter)) <= iData.Data(0);
ShiftIntoCrc("000" & iData.Data(0));
NextCounterAndSaveToRamUsual(0,1);
 
when wide =>
for idx in 0 to 3 loop
NextR.Ram.Data(CalcBitAddrInWord(R.WordCounter, R.ByteCounter - idx)) <= iData.Data(3 - idx);
NextR.Word(CalcBitAddrInWord(R.WordCounter, R.ByteCounter - idx)) <= iData.Data(3 - idx);
end loop;
 
ShiftIntoCrc(std_ulogic_vector(iData.Data));
397,14 → 395,28
when widewidth =>
case R.Mode is
when standard =>
NextR.Ram.Data(CalcBitAddrInWord(R.WordCounter, R.ByteCounter)) <= iData.Data(0);
if (iSdDataFromController.ExpectBits = ScrBits) then
if (R.BlockCounter = 1 and R.WordCounter = 2 and R.ByteCounter = 2) then
NextR.Controller.WideMode <= iData.Data(0);
end if;
end if;
 
--NextR.WriteReadFifo.data(CalcBitAddrInWord(R.WordCounter, R.ByteCounter)) <= iData.Data(0);
ShiftIntoCrc("000" & iData.Data(0));
NextCounterAndSaveToRamWide(0, 1);
 
when wide =>
for idx in 0 to 3 loop
NextR.Ram.Data(CalcBitAddrInWord(R.WordCounter, R.ByteCounter - idx)) <= iData.Data(3 - idx);
end loop;
if (iSdDataFromController.ExpectBits = SwitchFunctionBits) then
if (R.BlockCounter = 12 and R.WordCounter = 2 and R.ByteCounter = 3) then
NextR.Controller.SpeedBits.HighSpeedSupported <= iData.Data(1);
elsif (R.BlockCounter = 11 and R.WordCounter = 3 and R.ByteCounter = 3) then
NextR.Controller.SpeedBits.SwitchFunctionOK <= iData.Data;
end if;
end if;
 
-- for idx in 0 to 3 loop
-- NextR.WriteReadFifo.data(CalcBitAddrInWord(R.WordCounter, R.ByteCounter - idx)) <= iData.Data(3 - idx);
-- end loop;
ShiftIntoCrc(std_ulogic_vector(iData.Data));
NextCounterAndSaveToRamWide(3, 4);
 
417,6 → 429,13
end case;
 
when crc =>
if iSdDataFromController.DataMode = usual then
-- save last word to ram
NextR.WriteReadFifo.wrreq <= cActivated;
NextR.WriteReadFifo.data <= R.Word;
end if;
 
-- shift received crc into crc
case R.Mode is
when standard =>
ShiftIntoCrc("000" & iData.Data(0));
428,7 → 447,7
report "Unhandled mode" severity error;
end case;
 
 
-- crc is 16 bit long
if (R.BlockCounter = 15) then
NextR.Region <= endbit;
else
/sdhc-sc-core/trunk/src/grpSd/unitSdData/src/SdData-e.vhdl
13,6 → 13,7
use ieee.numeric_std.all;
use work.Global.all;
use work.Sd.all;
use work.SdWb.all;
use work.CRCs.all;
 
entity SdData is
25,17 → 26,15
iSdDataFromController : in aSdDataFromController;
oSdDataToController : out aSdDataToController;
 
-- Ram
iSdDataFromRam : in aSdDataFromRam;
oSdDataToRam : out aSdDataToRam;
 
-- Card
iData : in aiSdData;
oData : out aoSdData;
-- ReadFifo
iReadFifo : in aiReadFifo;
oReadFifo : out aoReadFifo;
-- Fifos
iReadWriteFifo : in aiReadFifo;
oReadWriteFifo : out aoReadFifo;
iWriteReadFifo : in aiWriteFifo;
oWriteReadFifo : out aoWriteFifo;
 
oDisableSdClk : out std_ulogic
);
/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/Files.tcl
12,8 → 12,7
StrobesClocks Counter {Rtl}
Sd SdController {Rtl}
Sd SdData {Rtl}
Memory SimpleDualPortedRam {Rtl}
Memory SinglePortedRam {Rtl}
Cyclone2 WriteDataFifo {Syn}
StrobesClocks StrobeGen {Rtl}
Sd SdWbSlave {Rtl}
Sd SdClockMaster {Rtl}
/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/syn/TbdSdsyn.tcl
33,7 → 33,8
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name FMAX_REQUIREMENT "100 MHz" -section_id Clock
set_global_assignment -name FMAX_REQUIREMENT "100 MHz" -section_id SdClock
set_global_assignment -name FMAX_REQUIREMENT "100 MHz" -section_id WbClock
set_global_assignment -name ENABLE_DRC_SETTINGS OFF
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
44,7 → 45,8
 
source ../Pins.tcl
 
set_instance_assignment -name CLOCK_SETTINGS Clock -to iClk
set_instance_assignment -name CLOCK_SETTINGS SdClock -to iSdClk
set_instance_assignment -name CLOCK_SETTINGS WbClock -to iWbClk
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 
# Commit assignments
/sdhc-sc-core/trunk/src/grpSd/pkgSdWb/src/SdWb-p.vhdl
108,6 → 108,17
wrfull : std_ulogic; -- write full
 
end record aiWriteFifo;
type aoReadFifo is record
rdreq : std_ulogic; -- read request
end record aoReadFifo;
 
constant cDefaultoReadFifo : aoReadFifo := (rdreq => '0');
 
type aiReadFifo is record
q : std_ulogic_vector(31 downto 0); -- read data (1 cycle after rdreq)
rdempty : std_ulogic; -- no data available
end record aiReadFifo;
 
end package SdWb;
 
/sdhc-sc-core/trunk/src/grpSd/pkgSd/src/Sd-p.vhdl
160,7 → 160,6
Mode : aSdDataBusMode; -- select 1 bit or 4 bit mode
DataMode : aSdDataMode; -- select usual or wide width data
ExpectBits : aSdDataBits; -- how many bits are expected in wide with data mode
StartAddr : aAddr;
Valid : std_ulogic; -- valid, when the datablock is valid and has to be sent
CheckBusy : std_ulogic; -- check for busy signaling
end record aSdDataFromController;
169,10 → 168,18
Mode => standard,
DataMode => usual,
ExpectBits => ScrBits,
StartAddr => 0,
Valid => cInactivated,
CheckBusy => cInactivated);
 
type aSpeedBits is record
HighSpeedSupported : std_ulogic;
SwitchFunctionOK : std_ulogic_vector(3 downto 0); -- 0x01 when ok
end record aSpeedBits;
 
constant cDefaultSpeedBits : aSpeedBits := (
HighSpeedSupported => '0',
SwitchFunctionOK => (others => '0'));
 
type aSdDataToController is record
Ack : std_ulogic; -- gets asserted when a datablock was sent to the card
Receiving : std_ulogic; -- gets asserted when a datablock is currently received
179,6 → 186,8
Valid : std_ulogic; -- gets asserted when DataBlock is valid and therefore it was received correctly
Busy : std_ulogic; -- gets asserted when the card returns busy
Err : std_ulogic; -- gets asserted when an error occurred during receiving a data block (CRC)
SpeedBits : aSpeedBits; -- gets set, when data for check or switch function cmd is received (DataMode = widewidth and ExpectBits = SwitchFunctionBits
WideMode : std_ulogic; -- gets set, when scr is read (datamode = widewidth and ExpectBits = ScrBits)
end record aSdDataToController;
 
constant cDefaultSdDataToController : aSdDataToController := (
186,7 → 195,9
Receiving => cInactivated,
Valid => cInactivated,
Busy => cInactivated,
Err => cInactivated);
Err => cInactivated,
SpeedBits => cDefaultSpeedBits,
WideMode => cInactivated);
 
-- SdData to Ram
type aSdDataToRam is record
285,7 → 296,7
-- 3:0 group 1 for access mode
constant cSdCmdCheckSpeedSupport : aSdCmdArg := X"00FFFFF1";
constant cSdCmdSwitchSpeed : aSdCmdArg := X"80FFFFF1";
constant cSdHighSpeedFunctionSupportBit : natural := 400;
constant cSdHighSpeedFunctionSupportBit : natural := 401;
constant cSdHighSpeedFunctionGroupLow : natural := 376;
 
type aiSdCmd is record
305,18 → 316,7
Data : std_ulogic_vector(3 downto 0);
En : std_ulogic_vector(3 downto 0);
end record aoSdData;
 
type aoReadFifo is record
rdreq : std_ulogic; -- read request
end record aoReadFifo;
 
constant cDefaultoReadFifo : aoReadFifo := (rdreq => '0');
 
type aiReadFifo is record
q : std_ulogic_vector(31 downto 0); -- read data (1 cycle after rdreq)
rdempty : std_ulogic; -- no data available
end record aiReadFifo;
 
end package Sd;
 
package body Sd is
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src/SdVerificationTestbench.sv
26,6 → 26,7
 
program Test(ISdCard ICmd, WishboneInterface BusInterface);
initial begin
logic[31:0] rd;
Wishbone Bus = new(BusInterface.Master);
SDCard card = new(ICmd, $root.Testbed.CmdReceived, $root.Testbed.InitDone);
SDCommandToken recvCmd, sendCmd;
50,6 → 51,7
begin // driver for SdCardModel
card.init();
card.write();
card.read();
 
/*for (int i = 0; i < `cCmdCount; i++) begin
@$root.Testbed.CardRecv;
63,6 → 65,10
@$root.Testbed.InitDone;
 
Bus.Write('b100, 'h04030201);
Bus.Write('b001, 'h00000001);
Bus.Write('b000, 'h00000010);
 
#10000;
Bus.Write('b100, 'h02020202);
Bus.Write('b100, 'h03030303);
Bus.Write('b100, 'h04040404);
70,13 → 76,17
Bus.Write('b100, 'h06060606);
Bus.Write('b100, 'h07070707);
Bus.Write('b100, 'h08080808);
Bus.Write('b001, 'h00000001);
Bus.Write('b000, 'h00000010);
 
#10000;
for (int i = 0; i < 512; i++)
Bus.Write('b100, 'h09090909);
 
Bus.Write('b000, 'h00000001);
 
for (int i = 0; i < 128; i++) begin
Bus.Read('b011, rd);
$display("Read: %h", rd);
end
 
end
 
begin // checker
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/wave.do
1,6 → 1,92
onerror {resume}
quietly WaveActivateNextPane {} 0
WaveRestoreCursors {{Cursor 1} {1092925 ns} 0} {{Cursor 2} {10084945 ns} 0} {{Cursor 3} {10085095 ns} 0}
add wave -noupdate -format Logic /Testbed/BusInterface/ERR_I
add wave -noupdate -format Logic /Testbed/BusInterface/RTY_I
add wave -noupdate -format Logic /Testbed/BusInterface/CLK_I
add wave -noupdate -format Logic /Testbed/BusInterface/RST_I
add wave -noupdate -format Logic /Testbed/BusInterface/ACK_I
add wave -noupdate -format Literal /Testbed/BusInterface/DAT_I
add wave -noupdate -format Logic /Testbed/BusInterface/CYC_O
add wave -noupdate -format Literal /Testbed/BusInterface/ADR_O
add wave -noupdate -format Literal /Testbed/BusInterface/DAT_O
add wave -noupdate -format Logic /Testbed/BusInterface/SEL_O
add wave -noupdate -format Logic /Testbed/BusInterface/STB_O
add wave -noupdate -format Literal /Testbed/BusInterface/TGA_O
add wave -noupdate -format Literal /Testbed/BusInterface/TGC_O
add wave -noupdate -format Logic /Testbed/BusInterface/TGD_O
add wave -noupdate -format Logic /Testbed/BusInterface/WE_O
add wave -noupdate -format Logic /Testbed/BusInterface/LOCK_O
add wave -noupdate -format Literal /Testbed/BusInterface/CTI_O
add wave -noupdate -format Literal /Testbed/BusInterface/BTE_O
add wave -noupdate -divider SdWbSlave
add wave -noupdate -format Logic /Testbed/top/sdwbslave_inst/iclk
add wave -noupdate -format Logic /Testbed/top/sdwbslave_inst/irstsync
add wave -noupdate -format Literal /Testbed/top/sdwbslave_inst/iwbctrl
add wave -noupdate -format Literal /Testbed/top/sdwbslave_inst/owbctrl
add wave -noupdate -format Literal /Testbed/top/sdwbslave_inst/iwbdat
add wave -noupdate -format Literal /Testbed/top/sdwbslave_inst/owbdat
add wave -noupdate -format Literal /Testbed/top/sdwbslave_inst/icontroller
add wave -noupdate -format Literal /Testbed/top/sdwbslave_inst/ocontroller
add wave -noupdate -format Literal /Testbed/top/sdwbslave_inst/owritefifo
add wave -noupdate -format Literal /Testbed/top/sdwbslave_inst/iwritefifo
add wave -noupdate -format Literal /Testbed/top/sdwbslave_inst/oreadfifo
add wave -noupdate -format Literal /Testbed/top/sdwbslave_inst/ireadfifo
add wave -noupdate -format Literal /Testbed/top/sdwbslave_inst/r
add wave -noupdate -format Literal /Testbed/top/sdwbslave_inst/nxr
add wave -noupdate -divider sdcard
add wave -noupdate -format Logic /Testbed/CardInterface/Clk
add wave -noupdate -format Logic /Testbed/CardInterface/nResetAsync
add wave -noupdate -format Logic /Testbed/CardInterface/Cmd
add wave -noupdate -format Logic /Testbed/CardInterface/SClk
add wave -noupdate -format Literal -radix hexadecimal /Testbed/CardInterface/Data
add wave -noupdate -divider clockmaster
add wave -noupdate -format Logic /Testbed/top/sdclockmaster_inst/iclk
add wave -noupdate -format Logic /Testbed/top/sdclockmaster_inst/irstsync
add wave -noupdate -format Logic /Testbed/top/sdclockmaster_inst/ihighspeed
add wave -noupdate -format Logic /Testbed/top/sdclockmaster_inst/idisable
add wave -noupdate -format Logic /Testbed/top/sdclockmaster_inst/osdstrobe
add wave -noupdate -format Logic /Testbed/top/sdclockmaster_inst/osdcardclk
add wave -noupdate -format Logic /Testbed/top/sdclockmaster_inst/sdclk
add wave -noupdate -format Literal /Testbed/top/sdclockmaster_inst/counter
add wave -noupdate -format Logic /Testbed/top/sdclockmaster_inst/sdstrobe25mhz
add wave -noupdate -format Logic /Testbed/top/sdclockmaster_inst/sdstrobe50mhz
add wave -noupdate -divider sddata
add wave -noupdate -format Logic /Testbed/top/sddata_inst/iclk
add wave -noupdate -format Logic /Testbed/top/sddata_inst/inresetasync
add wave -noupdate -format Logic /Testbed/top/sddata_inst/istrobe
add wave -noupdate -format Literal /Testbed/top/sddata_inst/isddatafromcontroller
add wave -noupdate -format Literal /Testbed/top/sddata_inst/osddatatocontroller
add wave -noupdate -format Literal /Testbed/top/sddata_inst/idata
add wave -noupdate -format Literal /Testbed/top/sddata_inst/odata
add wave -noupdate -format Literal /Testbed/top/sddata_inst/ireadwritefifo
add wave -noupdate -format Literal /Testbed/top/sddata_inst/oreadwritefifo
add wave -noupdate -format Literal /Testbed/top/sddata_inst/iwritereadfifo
add wave -noupdate -format Literal /Testbed/top/sddata_inst/owritereadfifo
add wave -noupdate -format Logic /Testbed/top/sddata_inst/odisablesdclk
add wave -noupdate -format Literal /Testbed/top/sddata_inst/crcin
add wave -noupdate -format Literal /Testbed/top/sddata_inst/crcout
add wave -noupdate -format Literal /Testbed/top/sddata_inst/crcdatain
add wave -noupdate -format Literal /Testbed/top/sddata_inst/r
add wave -noupdate -format Literal /Testbed/top/sddata_inst/nextr
add wave -noupdate -divider sdcontroller
add wave -noupdate -format Logic /Testbed/top/sdcontroller_inst/iclk
add wave -noupdate -format Logic /Testbed/top/sdcontroller_inst/inresetasync
add wave -noupdate -format Logic /Testbed/top/sdcontroller_inst/ohighspeed
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/isdcmd
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/osdcmd
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/isddata
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/osddata
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/isdwbslave
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/osdwbslave
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/oledbank
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/r
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/nextr
add wave -noupdate -format Logic /Testbed/top/sdcontroller_inst/timeoutenable
add wave -noupdate -format Logic /Testbed/top/sdcontroller_inst/timeoutdisable
add wave -noupdate -format Logic /Testbed/top/sdcontroller_inst/timeout
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/timeoutmax
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1150621 ns} 0} {{Cursor 2} {10084945 ns} 0} {{Cursor 3} {10085095 ns} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
15,4 → 101,4
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {1113124 ns} {1113362 ns}
WaveRestoreZoom {1149954 ns} {1155829 ns}
/sdhc-sc-core/trunk/src/grpSd/unitSdController/src/SdController-Rtl-a.vhdl
84,7 → 84,6
 
oSdCmd <= R.ToSdCmd;
oSdData <= R.ToSdData;
oDataRam <= R.ToDataRam;
oSdWbSlave <= R.ToSdWbSlave;
oHighSpeed <= R.HighSpeed;
 
97,7 → 96,7
end if;
end process Regs;
 
Comb : process (iSdCmd, iSdData, iDataRam, iSdWbSlave, Timeout, R)
Comb : process (iSdCmd, iSdData, iSdWbSlave, Timeout, R)
variable ocr : aSdRegOCR;
variable arg : aSdCmdArg;
variable NextRegion : aRegion;
115,21 → 114,6
end if;
end procedure EnableNcrTimeout;
 
procedure CheckSpeedResponse is
begin
if (R.ToDataRam.Addr = R.ToSdData.StartAddr + (511-400)/32) then
if (iDataRam.Data(16) = cActivated) then
NextR.ToDataRam.Addr <= R.ToSdData.StartAddr + (511 - 376)/32;
else
NextState := requestnewoperation;
end if;
elsif (R.ToDataRam.Addr = R.ToSdData.StartAddr + (511 - 376)/32) then
if (iDataRam.Data(27 downto 24) /= X"1") then
NextState := requestnewoperation;
end if;
end if;
end procedure CheckSpeedResponse;
 
begin
-- default assignments
NextR <= R;
394,10 → 378,9
 
when waitstatedata =>
NextRegion := send;
NextR.ToDataRam.Addr <= R.ToSdData.StartAddr;
 
if (Timeout = cActivated) then
if (iDataRam.Data(cSdWideModeBit) = cActivated) then
if (iSdData.WideMode = cActivated) then
NextCmdRegion := SetBusWidth;
NextR.SendCMD55 <= cActivated;
 
406,7 → 389,6
end if;
end if;
 
 
when others =>
report "Unhandled region" severity error;
end case;
476,14 → 458,19
end if;
 
when receivedata =>
NextR.ToDataRam.Addr <= R.ToSdData.StartAddr + (511-400)/32;
null;
 
when waitstatedata =>
CheckSpeedResponse;
 
if (Timeout = cActivated) then
NextRegion := send;
NextCmdRegion := ChangeSpeed;
-- check if high speed mode is supported
if (iSdData.SpeedBits.HighSpeedSupported = cActivated and
iSdData.SpeedBits.SwitchFunctionOK = X"1") then
NextRegion := send;
NextCmdRegion := ChangeSpeed;
else
NextRegion := idle;
NextState := requestnewoperation;
end if;
end if;
 
when others =>
511,15 → 498,19
end if;
 
when receivedata =>
NextR.ToDataRam.Addr <= R.ToSdData.StartAddr + (511-400)/32;
 
when waitstatedata =>
CheckSpeedResponse;
 
if (Timeout = cActivated) then
NextR.HighSpeed <= cActivated;
NextCmdRegion := GetStatus;
NextRegion := idle;
-- check if switching was successful
if (iSdData.SpeedBits.HighSpeedSupported = cActivated and
iSdData.SpeedBits.SwitchFunctionOK = X"1") then
NextR.HighSpeed <= cActivated;
NextRegion := send;
NextCmdRegion := GetStatus;
else
NextRegion := idle;
NextState := requestnewoperation;
end if;
end if;
 
when others =>
651,8 → 642,8
NextRegion := waitstatedata;
 
when waitstatedata =>
NextR.Region <= idle;
NextR.State <= requestnewoperation;
NextRegion := idle;
NextState := requestnewoperation;
 
when others =>
report "Unhandled region";
/sdhc-sc-core/trunk/src/grpSd/unitSdController/src/SdController-e.vhdl
37,10 → 37,6
iSdData : in aSdDataToController;
oSdData : out aSdDataFromController;
 
-- DataRam
iDataRam : in aSdControllerFromRam;
oDataRam : out aSdControllerToRam;
 
-- SdWbSlave
iSdWbSlave : in aSdWbSlaveToSdController;
oSdWbSlave : out aSdControllerToSdWbSlave;
/sdhc-sc-core/trunk/src/grpSynchronization/unitSynchronizer/src/Synchronizer-Rtl-ea.vhdl
38,7 → 38,7
SyncReg : process (iToClk, inResetAsync)
begin
-- asynchronous reset
if (inResetAsync = cActivated) then
if (inResetAsync = cnActivated) then
Sync <= (others => '0');
 
elsif (rising_edge(iToClk)) then

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.