URL
https://opencores.org/ocsvn/can/can/trunk
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- This comparison shows the changes necessary to convert path
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- from Rev 126 to Rev 127
- ↔ Reverse comparison
Rev 126 → Rev 127
/trunk/bench/verilog/can_testbench_defines.v
50,6 → 50,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.8 2003/02/18 00:17:44 mohor |
// Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted. |
// |
// Revision 1.7 2003/02/09 02:24:11 mohor |
// Bosch license warning added. Error counters finished. Overload frames |
// still need to be fixed. |
80,7 → 83,7
`define CAN_MODE_RESET 1'h1 /* Reset mode */ |
|
/* Bit Timing 0 register value */ |
`define CAN_TIMING0_BRP 6'h1 /* Baud rate prescaler (2*(value+1)) */ |
`define CAN_TIMING0_BRP 6'h0 /* Baud rate prescaler (2*(value+1)) */ |
`define CAN_TIMING0_SJW 2'h2 /* SJW (value+1) */ |
|
/* Bit Timing 1 register value */ |
/trunk/bench/verilog/can_testbench.v
50,6 → 50,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.36 2003/08/20 10:03:20 mohor |
// Artisan RAMs added. |
// |
// Revision 1.35 2003/06/17 15:14:48 mohor |
// cs_can_i is used only when WISHBONE interface is not used. |
// |
287,11 → 290,11
`endif |
|
|
// Generate clock signal 24 MHz |
// Generate clock signal 25 MHz |
initial |
begin |
clk=0; |
forever #21 clk = ~clk; |
forever #20 clk = ~clk; |
end |
|
|
391,13 → 394,12
// After exiting the reset mode sending bus free |
repeat (11) send_bit(1); |
|
// test_synchronization; // test currently switched off |
test_synchronization; // test currently switched off |
// test_empty_fifo_ext; // test currently switched off |
// test_full_fifo_ext; // test currently switched off |
// send_frame_ext; // test currently switched off |
// test_empty_fifo; // test currently switched off |
test_full_fifo; // test currently switched on |
// send_frame; // test currently switched off |
// test_full_fifo; // test currently switched on |
// bus_off_test; // test currently switched off |
// forced_bus_off; // test currently switched off |
// send_frame_basic; // test currently switched off |
1021,11 → 1023,12
fork |
|
begin |
#1500; |
#1100; |
$display("\n\nStart receiving data from CAN bus"); |
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc |
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc |
receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h0, 15'h6cea); // mode, rtr, id, length, crc |
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc |
receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h1, 15'h00c5); // mode, rtr, id, length, crc |
receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h2, 15'h7b4a); // mode, rtr, id, length, crc |
end |
1035,11 → 1038,23
end |
|
begin |
// Transmitting acknowledge |
wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack); |
wait (can_testbench.i_can_top.i_can_bsp.go_tx) // waiting for tx to start |
wait (~can_testbench.i_can_top.i_can_bsp.need_to_tx) // waiting for tx to finish |
tx_request_command; // start another tx |
end |
|
begin |
// Transmitting acknowledge (for first packet) |
wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack & can_testbench.i_can_top.i_can_bsp.tx_point); |
#1 rx = 0; |
wait (can_testbench.i_can_top.i_can_bsp.rx_ack_lim); |
wait (can_testbench.i_can_top.i_can_bsp.rx_ack_lim & can_testbench.i_can_top.i_can_bsp.tx_point); |
#1 rx = 1; |
|
// Transmitting acknowledge (for second packet) |
wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack & can_testbench.i_can_top.i_can_bsp.tx_point); |
#1 rx = 0; |
wait (can_testbench.i_can_top.i_can_bsp.rx_ack_lim & can_testbench.i_can_top.i_can_bsp.tx_point); |
#1 rx = 1; |
end |
|
|
1051,10 → 1066,6
read_receive_buffer; |
release_rx_buffer_command; |
read_receive_buffer; |
release_rx_buffer_command; |
read_receive_buffer; |
release_rx_buffer_command; |
read_receive_buffer; |
|
#200000; |
|
1161,9 → 1172,9
|
begin |
// Transmitting acknowledge |
wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack); |
wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack & can_testbench.i_can_top.i_can_bsp.tx_point); |
#1 rx = 0; |
wait (can_testbench.i_can_top.i_can_bsp.rx_ack_lim); |
wait (can_testbench.i_can_top.i_can_bsp.rx_ack_lim & can_testbench.i_can_top.i_can_bsp.tx_point); |
#1 rx = 1; |
end |
|
1833,7 → 1844,15
#1 rx=0; |
repeat (10*BRP) @ (posedge clk); |
#1 rx=1; |
// Resynchronization early |
repeat (11*BRP) @ (posedge clk); // one frames too late |
#1 rx=0; |
repeat (10*BRP) @ (posedge clk); |
#1 rx=1; |
|
repeat (10*BRP) @ (posedge clk); |
#1 rx=0; |
repeat (10*BRP) @ (posedge clk); |
end |
endtask |
|
/trunk/sim/rtl_sim/run/wave.do
116,8 → 116,8
define variable nofullpathfilenames |
include bookmark with filenames |
include scope history without filenames |
define waveform window listpane 4.96 |
define waveform window namepane 10.99 |
define waveform window listpane 7.94 |
define waveform window namepane 11.94 |
define multivalueindication |
define pattern curpos dot |
define pattern cursor1 dot |
148,50 → 148,72
define web browser command netscape |
define zoom outfull on initial add off |
add group \ |
testbench \ |
can_testbench.receive_frame.arbitration_lost \ |
can_testbench.rx \ |
can_testbench.rx_and_tx \ |
can_testbench.i_can_top.i_can_bsp.sample_point \ |
|
add group \ |
can_top \ |
can_testbench.i_can_top.wb_clk_i \ |
can_testbench.i_can_top.i_can_btl.clk \ |
can_testbench.i_can_top.wb_cyc_i \ |
can_testbench.i_can_top.wb_adr_i[7:0]'h \ |
can_testbench.i_can_top.wb_cyc_i \ |
can_testbench.i_can_top.wb_stb_i \ |
can_testbench.i_can_top.wb_we_i \ |
can_testbench.i_can_top.wb_dat_i[7:0]'h \ |
can_testbench.i_can_top.wb_dat_o[7:0]'h \ |
can_testbench.i_can_top.wb_ack_o \ |
can_testbench.i_can_top.cs \ |
can_testbench.i_can_top.cs_sync1 \ |
can_testbench.i_can_top.cs_sync2 \ |
can_testbench.i_can_top.cs_sync3 \ |
can_testbench.i_can_top.tx \ |
can_testbench.i_can_top.rx \ |
can_testbench.i_can_top.i_can_bsp.arbitration_lost \ |
can_testbench.i_can_top.i_can_btl.transmitting \ |
can_testbench.i_can_top.i_can_bsp.tx_state \ |
can_testbench.i_can_top.i_can_bsp.transmitter \ |
can_testbench.i_can_top.ale_i \ |
can_testbench.i_can_top.clk_i \ |
can_testbench.i_can_top.cs_can_i \ |
can_testbench.i_can_top.irq_on \ |
can_testbench.i_can_top.port_0_io[7:0]'h \ |
can_testbench.i_can_top.rd_i \ |
can_testbench.i_can_top.rst_i \ |
can_testbench.i_can_top.rx_i \ |
can_testbench.i_can_top.tx_o \ |
can_testbench.i_can_top.tx_oen_o \ |
can_testbench.i_can_top.wr_i \ |
can_testbench.i_can_top.rx_i \ |
can_testbench.i_can_top.rx_sync \ |
can_testbench.i_can_top.i_can_bsp.hard_sync \ |
can_testbench.i_can_top.i_can_btl.resync \ |
can_testbench.i_can_top.i_can_bsp.rx_ack \ |
can_testbench.i_can_top.i_can_bsp.rx_ack_lim \ |
can_testbench.i_can_top.i_can_bsp.send_ack \ |
can_testbench.i_can_top.i_can_btl.sampled_bit \ |
can_testbench.i_can_top.i_can_bsp.rx_inter \ |
can_testbench.i_can_top.i_can_bsp.rx_idle \ |
|
add group \ |
can_btl \ |
can_testbench.i_can_top.rx_i \ |
can_testbench.i_can_top.i_can_btl.rx \ |
can_testbench.i_can_top.i_can_btl.sync \ |
can_testbench.i_can_top.i_can_btl.seg1 \ |
can_testbench.i_can_top.i_can_btl.seg2 \ |
can_testbench.i_can_top.i_can_btl.sample_point \ |
can_testbench.i_can_top.i_can_btl.quant_cnt[3:0]'h \ |
can_testbench.i_can_top.i_can_btl.baud_r_presc[5:0]'h \ |
can_testbench.i_can_top.i_can_btl.clk \ |
can_testbench.i_can_top.i_can_btl.clk_cnt[8:0]'h \ |
can_testbench.i_can_top.i_can_btl.clk_cnt[6:0]'h \ |
can_testbench.i_can_top.i_can_btl.clk_en \ |
can_testbench.i_can_top.i_can_btl.delay[3:0]'h \ |
can_testbench.i_can_top.i_can_btl.go_seg1 \ |
can_testbench.i_can_top.i_can_btl.go_seg2 \ |
can_testbench.i_can_top.i_can_btl.go_sync \ |
can_testbench.i_can_top.i_can_btl.transmitting \ |
can_testbench.i_can_top.i_can_btl.hard_sync \ |
can_testbench.i_can_top.i_can_btl.preset_cnt[8:0]'h \ |
can_testbench.i_can_top.i_can_btl.quant_cnt[7:0]'h \ |
can_testbench.i_can_top.i_can_btl.reset_mode \ |
can_testbench.i_can_top.i_can_btl.hard_sync_blocked \ |
can_testbench.i_can_top.i_can_btl.preset_cnt[7:0]'h \ |
can_testbench.i_can_top.i_can_btl.quant_cnt[3:0]'h \ |
can_testbench.i_can_top.i_can_btl.resync \ |
can_testbench.i_can_top.i_can_btl.resync_latched \ |
can_testbench.i_can_top.i_can_btl.rst \ |
can_testbench.i_can_top.i_can_btl.rx_idle \ |
can_testbench.i_can_top.i_can_btl.sample[1:0]'h \ |
can_testbench.i_can_top.i_can_btl.sample_point \ |
can_testbench.i_can_top.i_can_btl.sampled_bit \ |
can_testbench.i_can_top.i_can_btl.sampled_bit_q \ |
can_testbench.i_can_top.i_can_btl.sync \ |
can_testbench.i_can_top.i_can_btl.seg1 \ |
can_testbench.i_can_top.i_can_btl.seg2 \ |
can_testbench.i_can_top.i_can_btl.sync \ |
can_testbench.i_can_top.i_can_btl.sync_blocked \ |
can_testbench.i_can_top.i_can_btl.sync_jump_width[1:0]'h \ |
can_testbench.i_can_top.i_can_btl.sync_window \ |
202,46 → 224,10
can_testbench.i_can_top.i_can_btl.tx_point \ |
|
add group \ |
can_acf \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_code_0[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_code_1[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_code_2[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_code_3[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_filter_mode \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_mask_0[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_mask_1[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_mask_2[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_mask_3[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.clk \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.data0[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.data1[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.extended_mode \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.go_rx_crc_lim \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.id[28:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.id_ok \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.ide \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.match \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.match_df_ext \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.match_df_std \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.match_sf_ext \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.match_sf_std \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.reset_mode \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.rst \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.rtr1 \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.rtr2 \ |
|
add group \ |
testbench \ |
can_testbench.receive_frame.arbitration_lost \ |
can_testbench.receive_frame.tmp \ |
can_testbench.receive_frame.cnt's \ |
can_testbench.receive_frame.mode \ |
can_testbench.receive_frame.pointer's \ |
can_testbench.receive_frame.total_bits's \ |
can_testbench.rx \ |
|
add group \ |
can_bsp \ |
can_testbench.i_can_top.i_can_bsp.arbitration_lost \ |
can_testbench.i_can_top.i_can_bsp.go_early_tx \ |
can_testbench.i_can_top.i_can_bsp.go_early_tx_latched \ |
can_testbench.i_can_top.i_can_bsp.ack_err_latched \ |
can_testbench.i_can_top.i_can_bsp.bit_err_latched \ |
can_testbench.i_can_top.i_can_bsp.form_err_latched \ |
261,8 → 247,6
can_testbench.i_can_top.sampled_bit_q \ |
can_testbench.i_can_top.i_can_bsp.transmitting \ |
can_testbench.rx \ |
can_testbench.i_can_top.rx \ |
can_testbench.i_can_top.tx \ |
can_testbench.i_can_top.i_can_bsp.sample_point \ |
can_testbench.i_can_top.i_can_bsp.tx_point \ |
can_testbench.i_can_top.i_can_bsp.tx_point_q \ |
273,7 → 257,6
can_testbench.i_can_top.i_can_bsp.basic_chain_data[63:0]'h \ |
can_testbench.i_can_top.i_can_bsp.extended_chain_std[18:0]'h \ |
can_testbench.i_can_top.i_can_bsp.extended_chain_ext[38:0]'h \ |
can_testbench.i_can_top.i_can_bsp.extended_chain_data[63:0]'h \ |
can_testbench.i_can_top.i_can_bsp.extended_mode \ |
can_testbench.i_can_top.i_can_bsp.rst_tx_pointer \ |
can_testbench.i_can_top.i_can_bsp.addr[7:0]'h \ |
304,7 → 287,6
can_testbench.i_can_top.i_can_bsp.overload_cnt1[2:0]'h \ |
can_testbench.i_can_top.i_can_bsp.overload_cnt2[2:0]'h \ |
can_testbench.i_can_top.i_can_bsp.enable_overload_cnt2 \ |
can_testbench.i_can_top.i_can_bsp.priority_lost \ |
can_testbench.i_can_top.i_can_bsp.transmitter \ |
can_testbench.i_can_top.i_can_bsp.suspend \ |
can_testbench.i_can_top.i_can_bsp.enable_error_cnt2 \ |
334,7 → 316,6
can_testbench.i_can_top.i_can_bsp.node_bus_off \ |
can_testbench.i_can_top.i_can_bsp.rtr1 \ |
can_testbench.i_can_top.i_can_bsp.rtr2 \ |
can_testbench.i_can_top.i_can_bsp.priority_lost \ |
can_testbench.i_can_top.i_can_bsp.bit_de_stuff_tx \ |
can_testbench.i_can_top.i_can_bsp.bit_stuff_cnt_tx[2:0]'h \ |
can_testbench.i_can_top.i_can_bsp.bit_stuff_cnt_en \ |
342,11 → 323,8
can_testbench.i_can_top.i_can_bsp.bit_de_stuff_reset \ |
can_testbench.i_can_top.i_can_btl.hard_sync \ |
can_testbench.i_can_top.i_can_btl.resync \ |
can_testbench.i_can_top.rx \ |
can_testbench.i_can_top.i_can_bsp.tx_pointer[5:0]'h \ |
can_testbench.i_can_top.tx \ |
can_testbench.rx \ |
can_testbench.i_can_top.rx \ |
can_testbench.i_can_top.i_can_bsp.sample_point \ |
can_testbench.i_can_top.i_can_bsp.tx_point \ |
can_testbench.i_can_top.i_can_bsp.rx_ack \ |
378,7 → 356,6
can_testbench.i_can_top.i_can_bsp.clk \ |
can_testbench.i_can_top.i_can_bsp.tx_state \ |
can_testbench.i_can_top.i_can_bsp.transmitting \ |
can_testbench.i_can_top.i_can_bsp.priority_lost \ |
can_testbench.i_can_top.i_can_bsp.go_crc_enable \ |
can_testbench.i_can_top.i_can_bsp.go_error_frame \ |
can_testbench.i_can_top.i_can_bsp.go_rx_ack \ |
441,8 → 418,36
can_testbench.i_can_top.i_can_bsp.wr_fifo \ |
|
add group \ |
can_acf \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_code_0[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_code_1[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_code_2[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_code_3[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_filter_mode \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_mask_0[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_mask_1[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_mask_2[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_mask_3[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.clk \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.data0[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.data1[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.extended_mode \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.go_rx_crc_lim \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.id[28:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.id_ok \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.ide \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.match \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.match_df_ext \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.match_df_std \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.match_sf_ext \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.match_sf_std \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.reset_mode \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.rst \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.rtr1 \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.rtr2 \ |
|
add group \ |
can_fifo \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.addr[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.clk \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.data_in[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.data_out[7:0]'h \ |
493,22 → 498,6
|
add group \ |
tmp \ |
can_testbench.i_can_top.wb_clk_i \ |
can_testbench.i_can_top.clk \ |
can_testbench.i_can_top.wb_adr_i[7:0]'h \ |
can_testbench.i_can_top.wb_dat_i[7:0]'h \ |
can_testbench.i_can_top.wb_dat_o[7:0]'h \ |
can_testbench.i_can_top.wb_we_i \ |
can_testbench.i_can_top.wb_cyc_i \ |
can_testbench.i_can_top.wb_ack_o \ |
can_testbench.i_can_top.cs_sync1 \ |
can_testbench.i_can_top.cs_sync2 \ |
can_testbench.i_can_top.cs_sync3 \ |
can_testbench.i_can_top.cs_ack1 \ |
can_testbench.i_can_top.cs_ack2 \ |
can_testbench.i_can_top.cs_ack3 \ |
can_testbench.i_can_top.cs_sync_rst1 \ |
can_testbench.i_can_top.cs_sync_rst2 \ |
can_testbench.i_can_top.cs \ |
|
|
517,5 → 506,5
fontsize 12 \ |
|
|
open window waveform 1 geometry 10 59 1592 1140 |
zoom at 59216.62ns 0.00797244 0.00000000 |
open window waveform 1 geometry 10 60 1592 1139 |
zoom at 56539.58(0)ns 0.00581205 0.00000000 |
/trunk/sim/rtl_sim/bin/memory_file_list
1,7 → 1,3
apa.v |
actel_ram_64x8_sync.v |
actel_ram_64x4_sync.v |
actel_ram_64x1_sync.v |
art_hstp_64x4_bist.v |
art_hstp_64x8_bist.v |
art_hsdp_64x8/art_hsdp_64x8.v |
/trunk/syn/synplicity/can.prj
1,61 → 1,100
#-- Synplicity, Inc. |
#-- Version 7.2 |
#-- Project file /projects/zoidberg/igorm/can/syn/synplicity/can.prj |
#-- Written on Sat Mar 1 21:07:14 2003 |
|
|
#add_file options |
add_file -verilog "$LIB/proasic/proasicplus.v" |
add_file -verilog "../../../memory/actel/ram_64x8_sync/actel_ram_64x8_sync.v" |
add_file -verilog "../../../memory/actel/ram_64x4_sync/actel_ram_64x4_sync.v" |
add_file -verilog "../../../memory/actel/ram_64x1_sync/actel_ram_64x1_sync.v" |
add_file -verilog "../../rtl/verilog/can_registers.v" |
add_file -verilog "../../rtl/verilog/can_bsp.v" |
add_file -verilog "../../rtl/verilog/can_btl.v" |
add_file -verilog "../../rtl/verilog/can_defines.v" |
add_file -verilog "../../rtl/verilog/can_register.v" |
add_file -verilog "../../rtl/verilog/can_register_asyn.v" |
add_file -verilog "../../rtl/verilog/can_register_asyn_syn.v" |
add_file -verilog "../../rtl/verilog/can_register_syn.v" |
add_file -verilog "../../rtl/verilog/can_top.v" |
add_file -verilog "../../rtl/verilog/can_fifo.v" |
add_file -verilog "../../rtl/verilog/can_acf.v" |
add_file -verilog "../../rtl/verilog/can_crc.v" |
add_file -verilog "../../rtl/verilog/can_ibo.v" |
|
|
#implementation: "rev_1" |
impl -add rev_1 |
|
#device options |
set_option -technology PA |
set_option -part APA150 |
set_option -speed_grade Std |
|
#compilation/mapping options |
set_option -default_enum_encoding default |
set_option -symbolic_fsm_compiler 1 |
set_option -resource_sharing 1 |
set_option -top_module "can_top" |
|
#map options |
set_option -frequency 50.000 |
set_option -fanout_limit 12 |
set_option -maxfan_hard 0 |
set_option -disable_io_insertion 0 |
set_option -report_path 4000 |
|
#simulation options |
set_option -write_verilog 0 |
set_option -write_vhdl 0 |
|
#automatic place and route (vendor) options |
set_option -write_apr_constraint 1 |
|
#set result format/file last |
project -result_file "rev_1/can_top.edn" |
|
#implementation attributes |
set_option -compiler_compatible 0 |
set_option -include_path "../../rtl/verilog/;../../bench/verilog/" |
impl -active "rev_1" |
#-- Synplicity, Inc. |
#-- Version 7.2.2 |
#-- Project file X:\zoidberg_soc\zoidberg_soc\can\syn\synplicity\can.prj |
#-- Written on Tue Sep 23 14:15:42 2003 |
|
|
#add_file options |
add_file -verilog "$LIB/proasic/proasicplus.v" |
add_file -verilog "../../../memory/actel/ram_64x8_sync/actel_ram_64x8_sync.v" |
add_file -verilog "../../../memory/actel/ram_64x4_sync/actel_ram_64x4_sync.v" |
add_file -verilog "../../../memory/actel/ram_64x1_sync/actel_ram_64x1_sync.v" |
add_file -verilog "../../rtl/verilog/can_registers.v" |
add_file -verilog "../../rtl/verilog/can_bsp.v" |
add_file -verilog "../../rtl/verilog/can_btl.v" |
add_file -verilog "../../rtl/verilog/can_defines.v" |
add_file -verilog "../../rtl/verilog/can_register.v" |
add_file -verilog "../../rtl/verilog/can_register_asyn.v" |
add_file -verilog "../../rtl/verilog/can_register_asyn_syn.v" |
add_file -verilog "../../rtl/verilog/can_register_syn.v" |
add_file -verilog "../../rtl/verilog/can_top.v" |
add_file -verilog "../../rtl/verilog/can_fifo.v" |
add_file -verilog "../../rtl/verilog/can_acf.v" |
add_file -verilog "../../rtl/verilog/can_crc.v" |
add_file -verilog "../../rtl/verilog/can_ibo.v" |
|
|
#implementation: "rev_1" |
impl -add rev_1 |
|
#device options |
set_option -technology PA |
set_option -part APA150 |
set_option -speed_grade Std |
|
#compilation/mapping options |
set_option -default_enum_encoding default |
set_option -symbolic_fsm_compiler 1 |
set_option -resource_sharing 1 |
set_option -top_module "can_top" |
|
#map options |
set_option -frequency 50.000 |
set_option -fanout_limit 12 |
set_option -maxfan_hard 0 |
set_option -disable_io_insertion 0 |
set_option -report_path 4000 |
|
#simulation options |
set_option -write_verilog 0 |
set_option -write_vhdl 0 |
|
#automatic place and route (vendor) options |
set_option -write_apr_constraint 1 |
|
#set result format/file last |
project -result_file "rev_1/can_top.edn" |
|
#implementation attributes |
set_option -compiler_compatible 0 |
set_option -include_path "../../rtl/verilog/;../../bench/verilog/" |
|
|
#implementation: "rev_2" |
impl -add rev_2 |
|
#device options |
set_option -technology PA |
set_option -part APA600 |
set_option -speed_grade Std |
|
#compilation/mapping options |
set_option -default_enum_encoding default |
set_option -symbolic_fsm_compiler 1 |
set_option -resource_sharing 0 |
set_option -top_module "can_top" |
|
#map options |
set_option -frequency 50.000 |
set_option -fanout_limit 12 |
set_option -maxfan_hard 0 |
set_option -disable_io_insertion 0 |
set_option -report_path 4000 |
|
#simulation options |
set_option -write_verilog 1 |
set_option -write_vhdl 0 |
|
#automatic place and route (vendor) options |
set_option -write_apr_constraint 1 |
|
#set result format/file last |
project -result_file "rev_2/can_top.edn" |
|
#implementation attributes |
set_option -vlog_std v95 |
set_option -compiler_compatible 0 |
set_option -num_critical_paths "" |
set_option -num_startend_points "" |
set_option -include_path "../../rtl/verilog/;../../bench/verilog/" |
impl -active "rev_2" |