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URL https://opencores.org/ocsvn/or1k/or1k/trunk

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    from Rev 1260 to Rev 1261
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Rev 1260 → Rev 1261

/trunk/uclinux/uClinux-2.0.x/include/asm-or32/board.h
3,7 → 3,7
#define _ASM_OR32_BOARH_H
 
/* System clock frequecy */
#define SYS_CLK 25000000
#define SYS_CLK 100000000
 
/* Memory organization */
#define SRAM_BASE_ADD 0x00000000
18,12 → 18,12
#define KBD_BASE_ADD 0x94000000
 
/* Define this if you want to use I and/or D cache */
#define ICACHE 0
#define DCACHE 0
#define ICACHE 1
#define DCACHE 1
 
#define IC_SIZE 4096
#define IC_SIZE 8192
#define IC_LINE 16
#define DC_SIZE 4096
#define DC_SIZE 8192
#define DC_LINE 16
 
/* Define this if you want to use I and/or D MMU */
39,16 → 39,34
#define IMMU_PAGE_ADD_MASK 0x3fff /* 0x3fff for 8k, 0x1fff for 4k page size */
#define IMMU_SET_ADD_MASK 0x3f /* 0x3f for, 64 0x7f for 128 nuber of sets */
 
/* Uart definitions */
#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
 
/* You have to set console baud rate manually in drivers/char/console.c line 350 (function rs_init()) */
#define OR32_CONSOLE_BAUD 115200
#define UART_DEVISOR SYS_CLK/(16*OR32_CONSOLE_BAUD)
 
#define CONFIG_OETH_UNKNOWN_TX_NEXT 1
/* Define this if you are using MC */
#define MC_INIT 1
 
/* Memory controller initialize values */
#if 0
// 25MHz
#define MC_CSR_VAL 0x0B000300
#define MC_MASK_VAL 0x000003f0
#define FLASH_TMS_VAL 0x00000103
#define SDRAM_BASE_ADD 0x00000000
#define SDRAM_TMS_VAL 0x19220057
#else
// 100MHz
#define MC_CSR_VAL 0x0B000300
#define MC_MASK_VAL 0x000003f0
#define FLASH_TMS_VAL 0x0000010c
#define SDRAM_BASE_ADD 0x00000000
#define SDRAM_TMS_VAL 0x2a5a0300
#endif
 
/* Define ethernet MAC address */
#define MACADDR0 0x00

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