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Rev 127 → Rev 128

/trunk/bench/verilog/dbg_tb.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.37 2004/01/25 14:10:25 mohor
// Display for VATS added.
//
// Revision 1.36 2004/01/22 13:58:51 mohor
// Port signals are all set to zero after reset.
//
193,8 → 196,10
wire mbist_select_o;
wire debug_select_o;
 
reg rst_i;
 
`ifdef WISHBONE_SUPPORTED
// WISHBONE common signals
reg wb_rst_i;
reg wb_clk_i;
// WISHBONE master interface
210,7 → 215,9
wire wb_err_i;
wire [2:0] wb_cti_o;
wire [1:0] wb_bte_o;
`endif
 
`ifdef CPU_SUPPORTED
// CPU signals
wire cpu_clk_i;
wire [31:0] cpu_addr_o;
224,6 → 231,7
wire cpu_we_o;
wire cpu_ack_i;
wire cpu_rst_o;
`endif
 
// Text used for easier debugging
reg [199:0] test_text;
292,6 → 300,7
.tck_i (tck_pad_i),
.tdi_i (tdo_o),
.tdo_o (debug_tdi_i),
.rst_i (rst_i),
// TAP states
.shift_dr_i (shift_dr_o),
299,10 → 308,11
.update_dr_i (update_dr_o),
// Instructions
.debug_select_i (debug_select_o),
.debug_select_i (debug_select_o)
 
`ifdef WISHBONE_SUPPORTED
// WISHBONE common signals
.wb_rst_i (wb_rst_i),
,
.wb_clk_i (wb_clk_i),
// WISHBONE master interface
317,9 → 327,12
.wb_cab_o (wb_cab_o),
.wb_err_i (wb_err_i),
.wb_cti_o (wb_cti_o),
.wb_bte_o (wb_bte_o),
.wb_bte_o (wb_bte_o)
`endif
 
`ifdef CPU_SUPPORTED
// CPU signals
,
.cpu_clk_i (cpu_clk_i),
.cpu_addr_o (cpu_addr_o),
.cpu_data_i (cpu_data_i),
332,18 → 345,18
.cpu_we_o (cpu_we_o),
.cpu_ack_i (cpu_ack_i),
.cpu_rst_o (cpu_rst_o)
`endif
 
 
 
 
);
 
 
 
`ifdef WISHBONE_SUPPORTED
wb_slave_behavioral wb_slave
(
.CLK_I (wb_clk_i),
.RST_I (wb_rst_i),
.RST_I (rst_i),
.ACK_O (wb_ack_i),
.ADR_I (wb_adr_o),
.CYC_I (wb_cyc_o),
356,13 → 369,14
.WE_I (wb_we_o),
.CAB_I (1'b0)
);
`endif
 
 
 
`ifdef CPU_SUPPORTED
cpu_behavioral i_cpu_behavioral
(
// CPU signals
.cpu_rst_i (wb_rst_i),
.cpu_rst_i (rst_i),
.cpu_clk_o (cpu_clk_i),
.cpu_addr_i (cpu_addr_o),
.cpu_data_o (cpu_data_i),
376,10 → 390,10
.cpu_ack_o (cpu_ack_i),
.cpu_rst_o (cpu_rst_o)
);
`endif
 
 
 
 
// Initial values
initial
begin
397,22 → 411,26
initial
begin
test_enabled = 1'b0;
wb_rst_i = 1'b0;
rst_i = 1'b0;
#1000;
wb_rst_i = 1'b1;
rst_i = 1'b1;
#1000;
wb_rst_i = 1'b0;
rst_i = 1'b0;
 
// Initial values for wishbone slave model
`ifdef WISHBONE_SUPPORTED
wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
`endif
#1 test_enabled<=#1 1'b1;
end
 
`ifdef WISHBONE_SUPPORTED
initial
begin
wb_clk_i = 1'b0;
forever #5 wb_clk_i = ~wb_clk_i;
end
`endif
 
always @ (posedge test_enabled)
begin
432,8 → 450,10
#500;
goto_run_test_idle;
 
`ifdef CPU_SUPPORTED
// Test stall signal
stall_test;
`endif
 
// Testing read and write to internal registers
#10000;
447,11 → 467,9
set_instruction(`DEBUG);
#10000;
 
`ifdef WISHBONE_SUPPORTED
chain_select(`WISHBONE_DEBUG_CHAIN, 1'b0); // {chain, gen_crc_err}
 
// #10000;
// xxx(4'b1001, 32'he579b242);
 
#10000;
 
// debug_wishbone(`WB_READ8, 1'b0, 32'h12345678, 16'h4, 1'b0, "abc 1"); // {command, ready, addr, length, gen_crc_err, text}
466,7 → 484,6
// debug_wishbone(`WB_READ16, 1'b0, 32'h12345679, 16'h4, 1'b0, "abc 6"); // {command, ready, addr, length, gen_crc_err, text}
 
#10000;
// xxx(4'b1001, 32'he579b242);
 
debug_wishbone(`WB_READ32, 1'b1, 32'h12345678, 16'h4, 1'b0, "read32 2"); // {command, ready, addr, length, gen_crc_err, text}
 
514,7 → 531,9
 
#10000;
debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, "go 2"); // {command, ready, addr, length, gen_crc_err, text}
`endif // WISHBONE_SUPPORTED
 
`ifdef CPU_SUPPORTED
#10000;
chain_select(`CPU_DEBUG_CHAIN, 1'b0); // {chain, gen_crc_err}
 
569,6 → 588,7
 
#10000;
debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
`endif
 
 
 
578,7 → 598,6
 
 
 
 
#5000 gen_clk(1); // One extra TCLK for debugging purposes
$display("STATUS: passed");
$display("\n\nSimulation end.");
587,6 → 606,7
end
 
 
`ifdef CPU_SUPPORTED
task stall_test;
integer i;
 
596,10 → 616,10
 
// Set bp_i active for 1 clock cycle and check is stall is set or not
check_stall(0); // Should not be set at the beginning
@ (posedge wb_clk_i);
@ (posedge cpu_clk_i);
#1 dbg_tb.i_cpu_behavioral.cpu_bp_o = 1'b1;
#1 check_stall(1); // set?
@ (posedge wb_clk_i);
@ (posedge cpu_clk_i);
#1 dbg_tb.i_cpu_behavioral.cpu_bp_o = 1'b0;
#1 check_stall(1); // set?
 
647,6 → 667,7
end
end
endtask // check_stall
`endif
 
 
task initialize_memory;
658,7 → 679,9
for (i=0; i<length; i=i+4) // This data will be return from wb slave
begin
addr = start_addr + i;
`ifdef WISHBONE_SUPPORTED
wb_slave.wr_mem(addr, {addr[7:0], addr[7:0]+2'd1, addr[7:0]+2'd2, addr[7:0]+2'd3}, 4'hf); // adr, data, sel
`endif
end
for (i=0; i<4096; i=i+1) // This data will be written to wb slave
begin
842,6 → 865,7
 
 
 
`ifdef WISHBONE_SUPPORTED
task debug_wishbone;
input [2:0] command;
input ready;
1192,8 → 1216,10
endtask // debug_wishbone_go
 
 
`endif // WISHBONE_SUPPORTED
 
 
`ifdef CPU_SUPPORTED
task debug_cpu;
input [2:0] command;
input [31:0] addr;
1443,6 → 1469,7
gen_clk(1); // to run_test_idle
end
endtask // debug_cpu_go
`endif // CPU_SUPPORTED
 
 
 
1576,7 → 1603,17
 
 
// Detecting CRC error
always @ (posedge dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_end or posedge dbg_tb.i_dbg_top.chain_latch_en or posedge dbg_tb.i_dbg_top.i_dbg_cpu.crc_cnt_end)
always @ (
posedge dbg_tb.i_dbg_top.chain_latch_en
`ifdef WISHBONE_SUPPORTED
or posedge dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_end
`endif
`ifdef CPU_SUPPORTED
or posedge dbg_tb.i_dbg_top.i_dbg_cpu.crc_cnt_end
`endif
)
 
 
begin
#2;
if (~dbg_tb.i_dbg_top.crc_match)
1588,46 → 1625,6
 
 
 
// Detecting errors in counters
always @ (dbg_tb.i_dbg_top.i_dbg_wb.cmd_cnt or
dbg_tb.i_dbg_top.i_dbg_wb.cmd_cnt_end or
dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt or
dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt_end or
dbg_tb.i_dbg_top.i_dbg_wb.data_cnt or
dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_end or
dbg_tb.i_dbg_top.i_dbg_wb.cmd_cnt_en or
dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt_en or
dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_en or
dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_en or
dbg_tb.i_dbg_top.i_dbg_wb.status_cnt1
//dbg_tb.i_dbg_top.i_dbg_wb.status_cnt2 or
//dbg_tb.i_dbg_top.i_dbg_wb.status_cnt3 or
//dbg_tb.i_dbg_top.i_dbg_wb.status_cnt4
// dbg_tb.i_dbg_top.i_dbg_wb. or
)
begin
if ((~dbg_tb.i_dbg_top.i_dbg_wb.cmd_cnt_end) & (
dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt_en |
dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_en |
dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_en |
dbg_tb.i_dbg_top.i_dbg_wb.status_cnt1
)
)
begin
$display("\n\n\t\t(%0t) ERROR in counters !!!", $time);
#10000;
$stop;
end
 
 
 
end
 
 
 
 
 
 
endmodule // dbg_tb
 
 
/trunk/rtl/verilog/dbg_top.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.41 2004/01/25 14:04:18 mohor
// All flipflops are reset.
//
// Revision 1.40 2004/01/20 14:23:47 mohor
// Define name changed.
//
195,6 → 198,7
tck_i,
tdi_i,
tdo_o,
rst_i,
 
// TAP states
shift_dr_i,
202,10 → 206,12
update_dr_i,
 
// Instructions
debug_select_i,
debug_select_i
 
 
`ifdef WISHBONE_SUPPORTED
// WISHBONE common signals
wb_rst_i,
,
wb_clk_i,
// WISHBONE master interface
220,9 → 226,12
wb_cab_o,
wb_err_i,
wb_cti_o,
wb_bte_o,
wb_bte_o
`endif
 
`ifdef CPU_SUPPORTED
// CPU signals
,
cpu_clk_i,
cpu_addr_o,
cpu_data_i,
235,6 → 244,7
cpu_we_o,
cpu_ack_i,
cpu_rst_o
`endif
);
 
 
242,6 → 252,7
input tck_i;
input tdi_i;
output tdo_o;
input rst_i;
 
// TAP states
input shift_dr_i;
251,11 → 262,8
// Instructions
input debug_select_i;
 
// WISHBONE common signals
input wb_rst_i; // WISHBONE reset
input wb_clk_i; // WISHBONE clock
// WISHBONE master interface
`ifdef WISHBONE_SUPPORTED
input wb_clk_i;
output [31:0] wb_adr_o;
output [31:0] wb_dat_o;
input [31:0] wb_dat_i;
269,6 → 277,18
output [2:0] wb_cti_o;
output [1:0] wb_bte_o;
 
reg wishbone_scan_chain;
reg wishbone_ce;
wire tdi_wb;
wire tdo_wb;
wire crc_en_wb;
wire shift_crc_wb;
`else
wire crc_en_wb = 1'b0;
wire shift_crc_wb = 1'b0;
`endif
 
`ifdef CPU_SUPPORTED
// CPU signals
input cpu_clk_i;
output [31:0] cpu_addr_o;
283,9 → 303,18
input cpu_ack_i;
output cpu_rst_o;
 
reg cpu_debug_scan_chain;
reg wishbone_scan_chain;
reg cpu_debug_scan_chain;
reg cpu_ce;
wire tdi_cpu;
wire tdo_cpu;
wire crc_en_cpu;
wire shift_crc_cpu;
`else
wire crc_en_cpu = 1'b0;
wire shift_crc_cpu = 1'b0;
`endif
 
 
reg [`DATA_CNT -1:0] data_cnt;
reg [`CRC_CNT -1:0] crc_cnt;
reg [`STATUS_CNT -1:0] status_cnt;
301,30 → 330,21
reg chain_select_error;
wire crc_out;
wire crc_match;
wire crc_en_wb;
wire crc_en_cpu;
wire shift_crc_wb;
wire shift_crc_cpu;
 
wire data_shift_en;
wire selecting_command;
 
reg tdo_o;
reg wishbone_ce;
reg cpu_ce;
 
wire tdi_wb;
wire tdi_cpu;
 
wire tdo_wb;
wire tdo_cpu;
 
 
wire shift_crc;
 
// data counter
always @ (posedge tck_i or posedge wb_rst_i)
always @ (posedge tck_i or posedge rst_i)
begin
if (wb_rst_i)
if (rst_i)
data_cnt <= #1 {`DATA_CNT{1'b0}};
else if(shift_dr_i & (~data_cnt_end))
data_cnt <= #1 data_cnt + 1'b1;
337,9 → 357,9
 
 
// crc counter
always @ (posedge tck_i or posedge wb_rst_i)
always @ (posedge tck_i or posedge rst_i)
begin
if (wb_rst_i)
if (rst_i)
crc_cnt <= #1 {`CRC_CNT{1'b0}};
else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & chain_select)
crc_cnt <= #1 crc_cnt + 1'b1;
350,9 → 370,9
assign crc_cnt_end = crc_cnt == `CRC_LEN;
 
 
always @ (posedge tck_i or posedge wb_rst_i)
always @ (posedge tck_i or posedge rst_i)
begin
if (wb_rst_i)
if (rst_i)
crc_cnt_end_q <= #1 1'b0;
else
crc_cnt_end_q <= #1 crc_cnt_end;
360,9 → 380,9
 
 
// status counter
always @ (posedge tck_i or posedge wb_rst_i)
always @ (posedge tck_i or posedge rst_i)
begin
if (wb_rst_i)
if (rst_i)
status_cnt <= #1 {`STATUS_CNT{1'b0}};
else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
status_cnt <= #1 status_cnt + 1'b1;
376,9 → 396,9
assign selecting_command = shift_dr_i & (data_cnt == `DATA_CNT'h0) & debug_select_i;
 
 
always @ (posedge tck_i or posedge wb_rst_i)
always @ (posedge tck_i or posedge rst_i)
begin
if (wb_rst_i)
if (rst_i)
chain_select <= #1 1'b0;
else if(selecting_command & tdi_i) // Chain select
chain_select <= #1 1'b1;
389,14 → 409,22
 
always @ (chain)
begin
`ifdef CPU_SUPPORTED
cpu_debug_scan_chain <= #1 1'b0;
`endif
`ifdef WISHBONE_SUPPORTED
wishbone_scan_chain <= #1 1'b0;
`endif
chain_select_error <= #1 1'b0;
case (chain) /* synthesis parallel_case */
`CPU_DEBUG_CHAIN : cpu_debug_scan_chain <= #1 1'b1;
`WISHBONE_DEBUG_CHAIN : wishbone_scan_chain <= #1 1'b1;
default : chain_select_error <= #1 1'b1;
`ifdef CPU_SUPPORTED
`CPU_DEBUG_CHAIN : cpu_debug_scan_chain <= #1 1'b1;
`endif
`ifdef WISHBONE_SUPPORTED
`WISHBONE_DEBUG_CHAIN : wishbone_scan_chain <= #1 1'b1;
`endif
default : chain_select_error <= #1 1'b1;
endcase
end
 
404,9 → 432,9
assign chain_latch_en = chain_select & crc_cnt_end & (~crc_cnt_end_q);
 
 
always @ (posedge tck_i or posedge wb_rst_i)
always @ (posedge tck_i or posedge rst_i)
begin
if (wb_rst_i)
if (rst_i)
chain <= `CHAIN_ID_LENGTH'b111;
else if(chain_latch_en & crc_match)
chain <= #1 chain_dr[`CHAIN_DATA_LEN -1:1];
416,9 → 444,9
assign data_shift_en = shift_dr_i & (~data_cnt_end);
 
 
always @ (posedge tck_i or posedge wb_rst_i)
always @ (posedge tck_i or posedge rst_i)
begin
if (wb_rst_i)
if (rst_i)
chain_dr <= #1 `CHAIN_DATA_LEN'h0;
else if (data_shift_en)
chain_dr[`CHAIN_DATA_LEN -1:0] <= #1 {tdi_i, chain_dr[`CHAIN_DATA_LEN -1:1]};
431,7 → 459,7
.data (tdi_i),
.enable (shift_dr_i),
.shift (1'b0),
.rst (wb_rst_i),
.rst (rst_i),
.sync_rst (update_dr_i),
.crc_out (),
.clk (tck_i),
443,12 → 471,14
wire crc_en;
wire crc_en_dbg;
reg crc_started;
 
assign crc_en = crc_en_dbg | crc_en_wb | crc_en_cpu;
 
assign crc_en_dbg = shift_dr_i & crc_cnt_end & (~status_cnt_end);
 
always @ (posedge tck_i or posedge wb_rst_i)
always @ (posedge tck_i or posedge rst_i)
begin
if (wb_rst_i)
if (rst_i)
crc_started <= #1 1'b0;
else if (crc_en)
crc_started <= #1 1'b1;
467,7 → 497,7
.enable (crc_en), // enable has priority
// .shift (1'b0),
.shift (shift_dr_i & crc_started & (~crc_en)),
.rst (wb_rst_i),
.rst (rst_i),
.sync_rst (update_dr_i),
.crc_out (crc_out),
.clk (tck_i),
514,14 → 544,25
 
assign shift_crc = shift_crc_wb | shift_crc_cpu;
 
always @ (shift_crc or crc_out or wishbone_ce or tdo_wb or tdo_cpu or tdo_chain_select or cpu_ce)
always @ (shift_crc or crc_out or tdo_chain_select
`ifdef WISHBONE_SUPPORTED
or wishbone_ce or tdo_wb
`endif
`ifdef CPU_SUPPORTED
or cpu_ce or tdo_cpu
`endif
)
begin
if (shift_crc) // shifting crc
tdo_tmp = crc_out;
`ifdef WISHBONE_SUPPORTED
else if (wishbone_ce) // shifting data from wb
tdo_tmp = tdo_wb;
`endif
`ifdef CPU_SUPPORTED
else if (cpu_ce) // shifting data from cpu
tdo_tmp = tdo_cpu;
`endif
else
tdo_tmp = tdo_chain_select;
end
538,32 → 579,50
// Signals for WISHBONE module
 
 
always @ (posedge tck_i or posedge wb_rst_i)
always @ (posedge tck_i or posedge rst_i)
begin
if (wb_rst_i)
if (rst_i)
begin
`ifdef WISHBONE_SUPPORTED
wishbone_ce <= #1 1'b0;
`endif
`ifdef CPU_SUPPORTED
cpu_ce <= #1 1'b0;
`endif
end
else if(selecting_command & (~tdi_i))
begin
`ifdef WISHBONE_SUPPORTED
if (wishbone_scan_chain) // wishbone CE
wishbone_ce <= #1 1'b1;
`endif
`ifdef CPU_SUPPORTED
if (cpu_debug_scan_chain) // CPU CE
cpu_ce <= #1 1'b1;
`endif
end
else if (update_dr_i) // igor !!! This needs to be changed?
begin
`ifdef WISHBONE_SUPPORTED
wishbone_ce <= #1 1'b0;
`endif
`ifdef CPU_SUPPORTED
cpu_ce <= #1 1'b0;
`endif
end
end
 
 
`ifdef WISHBONE_SUPPORTED
assign tdi_wb = wishbone_ce & tdi_i;
`endif
 
`ifdef CPU_SUPPORTED
assign tdi_cpu = cpu_ce & tdi_i;
`endif
 
 
`ifdef WISHBONE_SUPPORTED
// Connecting wishbone module
dbg_wb i_dbg_wb (
// JTAG signals
580,7 → 639,7
.crc_match_i (crc_match),
.crc_en_o (crc_en_wb),
.shift_crc_o (shift_crc_wb),
.rst_i (wb_rst_i),
.rst_i (rst_i),
 
// WISHBONE common signals
.wb_clk_i (wb_clk_i),
599,8 → 658,10
.wb_cti_o (wb_cti_o),
.wb_bte_o (wb_bte_o)
);
`endif
 
 
`ifdef CPU_SUPPORTED
// Connecting cpu module
dbg_cpu i_dbg_cpu (
// JTAG signals
617,7 → 678,7
.crc_match_i (crc_match),
.crc_en_o (crc_en_cpu),
.shift_crc_o (shift_crc_cpu),
.rst_i (wb_rst_i),
.rst_i (rst_i),
 
// CPU signals
.cpu_clk_i (cpu_clk_i),
632,9 → 693,9
.cpu_we_o (cpu_we_o),
.cpu_ack_i (cpu_ack_i),
.cpu_rst_o (cpu_rst_o)
);
`endif // CPU_SUPPORTED
 
 
);
 
 
endmodule
/trunk/rtl/verilog/dbg_defines.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.16 2004/01/20 14:23:45 mohor
// Define name changed.
//
// Revision 1.15 2003/12/23 15:07:34 mohor
// New directory structure. New version of the debug interface.
// Files that are not needed removed.
122,3 → 125,9
`define CPU_DEBUG_CHAIN 3'b000
`define WISHBONE_DEBUG_CHAIN 3'b001
 
// If WISHBONE debugging is supported uncomment the folowing line
`define WISHBONE_SUPPORTED
 
// If CPU_DEBUG is supported uncomment the folowing line
`define CPU_SUPPORTED
 
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