OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /
    from Rev 1270 to Rev 1271
    Reverse comparison

Rev 1270 → Rev 1271

/trunk/orp/orp_soc/sim/src/flash.in
404,8 → 404,8
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a3
00
d7
e2
27
f0
24
d4
0c
28
24
84
62
ff
ec
9c
83
00
01
d7
e2
27
ec
03
ff
ff
d9
15
00
00
00
84
62
ff
f8
84
82
ff
f4
e0
63
28
d4
0c
20
00
28
84
82
ff
f0
e0
63
20
00
9d
63
2c
00
00
00
0d
d4
0c
18
2c
9c
a0
00
06
84
6c
00
02
15
08
04
00
00
00
52
d4
0a
28
0c
84
41
8e
00
00
44
9c
aa
00
48
0c
84
84
00
9c
21
00
18
9c
21
ff
e4
d4
01
10
0a
20
00
9c
41
00
1c
d7
e2
1f
fc
84
62
ff
fc
18
a0
10
20
a8
a5
30
40
e0
83
28
05
d7
e2
27
fc
9c
60
6a
00
0c
04
00
d7
e2
1f
e8
84
62
ff
e8
00
79
9c
80
00
09
e5
a3
20
0a
85
21
00
10
00
85
41
00
04
15
85
81
00
08
85
c1
00
0c
44
00
48
00
9c
21
00
10
84
83
00
1f
15
00
a8
c3
00
00
8c
a2
ff
ff
db
e2
2f
fb
8c
62
ff
ff
db
e2
1f
fa
94
a2
ff
fe
df
e2
2f
f8
94
62
ff
fe
df
e2
1f
f6
84
a2
ff
fc
d7
e2
2f
f0
84
62
ff
fc
d7
e2
1f
ec
8c
62
ff
fb
90
82
ff
fa
e0
63
20
9c
e4
00
94
82
ff
f8
e0
63
20
09
18
60
00
98
82
ff
f6
e0
63
20
00
84
82
ff
f0
e0
a8
63
20
00
84
82
ff
ec
e0
63
20
00
d7
e2
1f
fc
84
62
ff
e8
50
9c
83
80
00
01
d7
e2
27
e8
03
ff
ff
de
15
41
90
a3
00
00
e4
25
20
00
84
62
ff
fc
9d
63
10
00
00
07
15
00
00
00
02
15
18
80
00
00
00
a8
84
41
21
2c
84
64
00
00
e0
67
18
02
d4
06
18
00
44
00
48
00
9c
21
15
00
1c
54
68
69
73
20
74
65
73
74
20
73
74
72
69
6e
67
20
4d
55
53
54
20
4e
4f
54
20
62
65
20
6d
6f
64
69
66
69
65
64
2e
2e
2e
00
00
00
00
9c
21
ff
64
fc
d4
01
10
04
9c
41
00
9c
d4
01
48
00
d7
e2
1f
fc
9c
62
ff
d0
18
80
04
00
a8
84
08
18
9c
62
ff
d0
9c
a0
00
29
04
00
01
99
15
a8
a5
21
2c
19
00
00
00
9c
6b
a9
08
20
48
84
85
00
00
90
82
ff
d5
9c
64
a8
e3
00
00
04
84
c8
00
01
83
15
00
00
00
9c
62
ff
6c
9c
82
ff
d0
9c
a0
00
00
e4
06
28
04
00
01
8f
15
10
00
00
00
90
82
ff
d5
05
9c
64
60
00
0a
84
c6
00
04
00
01
7a
15
d4
07
30
00
84
c8
00
00
90
82
ff
71
9c
64
00
00
04
00
01
76
15
00
50
9c
a6
00
0c
85
21
00
84
62
ff
fc
04
00
01
73
15
44
00
48
00
9c
21
00
90
62
ff
6c
90
82
ff
6d
e0
63
20
04
19
00
90
82
ff
6e
e0
63
20
00
90
82
ff
6f
e0
63
20
00
90
82
ff
70
e0
63
20
a9
08
21
30
18
60
00
90
82
ff
71
e0
63
20
00
90
82
ff
72
e0
a8
63
20
50
84
c8
00
90
82
ff
73
e0
63
20
00
90
82
ff
74
e0
63
20
9c
80
00
41
90
82
ff
75
e0
63
20
a3
00
90
82
ff
76
e0
63
20
00
90
82
ff
77
e0
63
e4
25
20
00
90
82
ff
78
e0
63
20
10
00
90
82
ff
79
e0
63
20
00
90
82
ff
7a
03
9c
e0
63
20
00
90
82
ff
7b
e0
63
20
00
90
82
ff
7c
9c
e0
63
20
00
90
82
ff
7d
01
e0
63
20
87
30
04
18
60
00
90
82
ff
7e
e0
63
20
00
90
82
ff
7f
e0
a8
63
20
21
28
9c
a0
00
90
82
ff
80
e0
63
42
d4
08
20
00
90
82
ff
81
e0
63
20
d8
03
28
00
90
82
ff
82
e0
63
20
44
00
90
82
ff
83
e0
63
20
48
00
90
82
ff
84
e0
63
20
15
00
90
82
ff
85
e0
63
20
00
90
82
ff
86
e0
63
20
00
90
82
ff
87
e0
63
20
18
60
00
90
82
ff
88
e0
63
20
00
90
82
ff
89
e0
a8
63
20
50
9c
80
00
90
82
ff
8a
e0
63
41
d8
03
20
00
90
82
ff
8b
e0
63
20
00
90
82
ff
8c
e0
63
20
00
90
82
ff
8d
e0
63
20
00
90
82
ff
8e
e0
63
20
00
90
82
ff
8f
e0
63
20
00
90
82
ff
90
e0
63
20
00
90
82
ff
91
e0
63
20
00
90
82
ff
92
e0
63
20
00
90
82
ff
93
e0
63
20
00
84
82
ff
fc
e0
64
18
80
00
d7
e2
1f
fc
84
62
ff
fc
04
00
01
1e
15
00
00
00
a8
84
62
ff
fc
9d
63
00
00
00
00
00
02
15
00
00
00
85
21
30
9c
60
00
00
84
41
d4
04
18
00
04
44
00
48
00
9c
21
15
00
9c
52
45
53
55
4c
54
3a
20
25
2e
38
6c
78
0a
00
00
9c
21
ff
e4
f4
d4
01
10
0c
9c
41
48
00
1c
d4
01
48
08
50
04
00
d4
01
10
15
60
08
a9
84
00
00
a9
43
00
9c
60
00
04
00
d7
e2
1f
fc
9c
a0
00
9f
d4
0c
18
00
d7
e2
2f
f8
9c
60
00
00
d7
e2
1f
f4
9c
60
e4
2b
18
00
01
07
ff
fe
1c
15
10
00
00
05
9c
60
00
04
9c
6b
60
00
03
d4
0c
18
00
d7
e2
1f
fc
9c
60
ff
ff
07
ff
fe
17
15
00
04
e4
4a
18
00
10
00
9c
6b
00
19
b8
6a
00
d7
e2
1f
f8
02
18
80
04
00
a8
84
62
ff
fc
84
82
ff
f8
11
9c
e0
63
20
00
84
82
ff
f4
e0
64
18
02
d7
e2
1f
f4
84
62
ff
f8
04
83
00
00
f3
44
00
20
00
15
00
00
2761,591 → 2409,615
9c
60
00
01
07
ff
fe
7b
15
00
00
00
9c
6b
00
10
d4
0c
18
00
d7
e2
1f
fc
9c
18
60
ff
ff
07
ff
fe
76
15
00
00
00
a8
63
21
2c
9c
6b
80
00
64
84
a3
00
d7
e2
1f
f8
84
62
ff
fc
84
82
ff
f8
e0
63
00
e5
a5
20
00
84
82
13
ff
f4
e0
64
18
02
d7
e2
1f
f4
84
62
ff
f8
04
f9
9c
60
00
03
9c
80
00
e0
15
00
00
00
00
06
d4
0c
20
00
03
ff
ff
fe
9c
60
80
00
01
07
03
ff
fe
94
15
ff
f2
9c
60
00
02
85
21
00
00
9c
6b
85
41
00
04
85
81
00
d7
e2
1f
fc
9c
60
ff
ff
07
ff
fe
8f
15
08
44
00
48
00
9c
21
00
0c
9c
6b
63
00
00
d7
e2
1f
f8
84
62
ff
fc
84
82
ff
f8
02
e0
63
20
00
84
82
ff
f4
e0
64
18
02
d7
e2
1f
f4
84
62
ff
f8
04
00
d4
05
20
00
cd
44
00
48
00
15
00
00
00
9c
60
00
21
ff
fc
d4
01
07
ff
fe
b7
15
48
00
9c
e5
00
05
a9
23
00
9c
6b
00
00
d7
e2
1f
fc
9c
60
ff
ff
b9
07
ff
fe
b2
15
00
02
a9
64
00
00
9c
6b
a5
00
00
d7
e2
1f
f8
84
62
ff
fc
84
82
ff
f8
06
e0
63
20
68
18
00
84
82
ff
f4
e0
64
18
02
d7
e2
1f
f4
84
62
ff
f8
a8
87
00
00
d4
03
30
04
d4
03
38
78
e5
a7
28
00
0c
00
ba
15
00
0a
d4
03
30
00
00
9c
60
00
01
07
ff
fe
e4
15
cc
e0
67
1b
06
e0
63
58
00
d4
03
38
00
00
9c
6b
84
00
01
e5
a4
28
00
d7
e2
1f
fc
9c
60
13
ff
ff
07
ff
fe
df
15
fd
9c
63
00
00
00
04
9c
6b
80
00
cc
e0
c8
48
00
d7
e2
1f
f8
e0
87
23
06
e0
84
62
58
00
9c
a4
ff
fc
84
82
ff
f8
e0
65
00
00
9c
63
20
00
84
82
ff
f4
e0
64
01
d4
05
18
02
d7
e2
1f
f4
00
84
62
ff
f8
04
c6
00
00
a7
15
18
60
00
00
00
a8
63
21
2c
d4
24
37
a0
9c
60
80
00
01
07
ff
ff
12
15
05
d4
03
20
00
85
21
00
00
9c
6b
44
00
48
00
d7
e2
1f
fc
9c
60
ff
ff
07
ff
ff
0d
15
21
00
04
b8
a3
00
18
b8
a5
00
9c
6b
00
00
d7
e2
1f
f8
98
b8
84
62
ff
fc
84
82
ff
f8
e0
63
20
00
84
82
ff
f4
e0
64
18
02
d7
e2
1f
f4
b8
84
62
ff
f8
04
00
98
e4
05
20
00
94
15
0c
00
00
06
9d
60
00
00
18
a0
04
60
00
00
a8
a5
0a
3c
d4
63
20
50
9d
60
00
01
d8
03
28
00
84
62
44
00
48
00
15
00
00
00
9c
21
ff
f4
18
a0
93
22
a8
a5
b8
63
e0
83
28
d4
01
48
00
d4
01
20
50
04
04
d4
01
60
08
d4
01
70
0c
d4
01
80
10
d4
01
90
14
d4
01
a0
18
d4
01
b0
1c
9d
80
00
02
aa
c4
00
83
15
00
a9
c3
00
00
84
62
ff
f4
18
a0
93
22
a8
a5
bf
e2
e0
83
28
9e
80
00
9c
64
00
9e
40
00
04
00
aa
0c
00
83
15
00
9d
44
00
03
e0
ae
60
00
84
62
90
8a
00
00
07
ff
f4
18
a0
93
22
a8
a5
bf
e2
e0
83
28
ff
e1
90
65
00
9c
64
00
e4
2b
90
00
04
10
00
00
6f
05
15
00
00
00
85
21
9e
80
00
08
84
41
9d
4a
00
0c
44
01
9d
8c
00
48
01
e5
ac
80
00
13
ff
ff
f6
e0
ae
60
00
9c
21
74
ff
a9
9c
80
00
1c
04
02
a4
63
00
00
ff
e4
43
15
20
00
10
00
00
03
9c
60
00
52
9d
40
80
00
07
e4
34
18
00
0c
00
00
0f
9d
60
00
01
a8
6e
00
00
07
ff
fd
a3
a8
96
00
00
9c
60
00
00
e5
ab
18
00
10
00
00
07
9d
80
8c
00
07
18
60
00
00
a8
63
21
2c
9d
60
20
00
01
00
00
00
03
d4
03
60
00
9d
80
20
60
00
e4
ac
58
00
85
21
00
00
85
41
00
04
85
81
00
08
85
c1
00
0c
86
01
00
10
86
41
00
14
86
81
00
03
15
18
86
c1
00
1c
44
00
48
00
e1
60
60
9c
21
00
c0
20
9c
80
50
00
02
c0
60
50
03
e4
2a
58
23
20
00
13
ff
ff
fd
9d
4a
0c
00
10
00
03
9d
40
60
00
01
a9
4a
9d
60
00
10
a9
4a
00
08
c0
44
00
50
11
48
00
15
00
00
00
15
e0
63
20
00
a9
63
00
00
44
00
48
00
15
00
00
00
15
04
00
00
00
2c
15
00
00
3373,7 → 3045,7
a8
63
11
70
b0
18
80
00
3452,8 → 3124,8
00
a8
a5
21
34
20
38
e4
64
28
3500,8 → 3172,8
00
a8
21
31
34
59
50
18
40
04
3508,8 → 3180,8
00
a8
42
0e
34
0c
ec
44
00
10
3537,7 → 3209,7
b8
a5
00
85
86
a8
a5
00
3552,12 → 3224,12
14
18
a0
00
10
19
22
a8
a5
21
02
00
57
d4
04
28
3568,8 → 3240,8
08
9c
a0
00
e0
03
ff
d4
04
28
3596,12 → 3268,12
1c
18
a0
07
24
00
00
a8
a5
82
30
01
03
d4
04
28
3617,7 → 3289,7
b8
a5
00
85
86
a8
a5
04
3644,8 → 3316,8
00
07
ff
ff
04
fd
5d
15
00
00
3654,7 → 3326,7
00
00
05
9c
a8
6b
00
00
3694,20 → 3366,20
00
00
00
9c
84
81
00
04
84
00
9c
61
00
00
04
9c
63
64
00
00
9c
84
83
00
00
15
3778,10 → 3450,14
00
00
00
b5
b4
63
00
00
a9
63
00
00
44
00
48
3790,50 → 3466,58
00
00
00
9d
63
9c
a5
ff
ff
9c
c0
ff
ff
e4
25
30
00
0c
00
00
0a
a9
63
00
00
07
9c
65
00
00
8c
64
e4
00
00
9c
a5
ff
ff
d8
0b
18
03
38
00
9c
65
00
00
9c
84
00
01
9d
6b
00
01
e4
23
25
30
00
00
13
ff
ff
fa
fb
9c
a5
ff
ff
63
00
01
a9
63
00
00
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0d
c8
/trunk/orp/orp_soc/sim/bin/tests
0,0 → 1,18
basic-nocache
cbasic-nocache-O2
dhry-nocache-O2
except-nocache
mmu-nocache
mul-nocache-O2
syscall-nocache
tick-nocache
uart-nocache
basic-icdc
cbasic-icdc-O2
dhry-icdc-O2
except-icdc
mmu-icdc
mul-icdc-O2
syscall-icdc
tick-icdc
uart-icdc
trunk/orp/orp_soc/sim/bin/tests Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/orp/orp_soc/sim/bin/tests.other =================================================================== --- trunk/orp/orp_soc/sim/bin/tests.other (nonexistent) +++ trunk/orp/orp_soc/sim/bin/tests.other (revision 1271) @@ -0,0 +1,18 @@ +basic-icdc +basic-nocache +mul-nocache-O2 +mul-icdc-O2 +except-nocache +except-icdc +dhry-nocache-O2 +dhry-icdc-O2 +cbasic-nocache-O2 +cbasic-icdc-O0 +tick-nocache +tick-icdc +syscall-nocache +syscall-icdc +uart-nocache +uart-icdc +mmu-nocache +mmu-icdc
trunk/orp/orp_soc/sim/bin/tests.other Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/orp/orp_soc/sim/bin/run_rtl_regression =================================================================== --- trunk/orp/orp_soc/sim/bin/run_rtl_regression (revision 1270) +++ trunk/orp/orp_soc/sim/bin/run_rtl_regression (revision 1271) @@ -6,9 +6,12 @@ # List all test cases #set simpletests=(buserr-nocache immu-nocache dmmu-nocache basic-nocache mul-nocache-O2 syscall-nocache cbasic-nocache-O2 ints1-nocache ints2-nocache \ # buserr-icdc immu-icdc dmmu-icdc basic-icdc mul-icdc-O2 syscall-icdc cbasic-icdc-O2 ints1-icdc ints2-icdc) -#set simpletests=(except_test basic-nocache mul-nocache-O2 cbasic-nocache-O2 ints1-nocache ints2-nocache \ + +#set simpletests=(basic-nocache mul-nocache-O2 cbasic-nocache-O2 ints1-nocache ints2-nocache \ # basic-icdc mul-icdc-O2 cbasic-icdc-O2 ints1-icdc ints2-icdc) -set simpletests=(dhry-nocache-O2 dhry-icdc-O2 mmu-nocache mmu-icdc basic-icdc basic-nocache mul-nocache-O2 mul-icdc-O2) + +#set simpletests=(icm-icdc icm-nocache dhry-nocache-O2 dhry-icdc-O2 mmu-nocache mmu-icdc basic-icdc basic-nocache mul-nocache-O2 mul-icdc-O2 basic-ic basic-dc) +#set simpletests=(crc32-icdc-O0 minimad dhry-nocache-O2 dhry-icdc-O2 mmu-nocache mmu-icdc basic-icdc basic-nocache mul-nocache-O2 mul-icdc-O2 basic-ic basic-dc) #set complextests=(buserr-ic immu-ic dmmu-ic basic-ic mul-ic-O2 syscall-ic cbasic-ic-O2 ints1-ic ints2-ic \ # buserr-dc immu-dc dmmu-dc basic-dc mul-dc-O2 syscall-dc cbasic-dc-O2 ints1-dc ints2-dc \ # mul-nocache-O0 cbasic-nocache-O0 \ @@ -15,27 +18,29 @@ # mul-icdc-O0 cbasic-icdc-O0 \ # mul-ic-O0 cbasic-ic-O0 \ # mul-dc-O0 cbasic-dc-O0) -set complextests=(except-nocache except-icdc cbasic-nocache-O2 cbasic-icdc-O0) -set simpletimes=(250 100 100 400 40 40 40 40 60 \ - 40 40 40 40 40 40 40 40 40) -set complextimes=(40 40 40 40 40 40 40 40 40 \ - 40 40 40 40 40 40 40 40 100 \ - 40 40 \ - 40 40 \ - 40 40 \ - 40 40) + +#set complextests=(except-nocache except-icdc cbasic-nocache-O2 cbasic-icdc-O0 tick-nocache tick-icdc \ +# syscall-nocache syscall-icdc uart-nocache uart-icdc debug-nocache debug-dc ) + +set simpletests=`cat ../bin/tests` +set complextests=() + +set simpletimes=(500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 ) +set complextimes=(40 40 \ + 400 140 \ + 100 40 \ + 40 40 \ + 40 40 ) set iterations=( \ - "OR1200_REGISTERED_OUTPUTS+FLASH_GENERIC+FLASH_GENERIC_REGISTERED+SRAM_GENERIC_REGISTERED" \ - "OR1200_REGISTERED_OUTPUTS+FLASH_GENERIC+OR1200_CLMODE_1TO2" \ - "OR1200_REGISTERED_OUTPUTS" \ - "" \ - "OR1200_REGISTERED_OUTPUTS+FLASH_GENERIC+FLASH_GENERIC_REGISTERED+OR1200_REGISTERED_INPUTS" \ - "OR1200_REGISTERED_OUTPUTS+FLASH_GENERIC+FLASH_GENERIC_REGISTERED+OR1200_CLMODE_1TO2" \ - "OR1200_REGISTERED_OUTPUTS+OR1200_REGISTERED_INPUTS" \ - "OR1200_REGISTERED_OUTPUTS+OR1200_REGISTERED_INPUTS+OR1200_CLMODE_1TO2" \ - "OR1200_REGISTERED_OUTPUTS+OR1200_CLMODE_1TO2" \ - "" \ - "OR1200_REGISTERED_OUTPUTS+OR1200_REGISTERED_INPUTS+FLASH_GENERIC_REGISTERED" \ + "DBG_IF_MODEL+SRAM_GENERIC_REGISTERED+OR1200_CLMODE_1TO2" \ + "DBG_IF_MODEL+OR1200_CLMODE_1TO2" \ + "DBG_IF_MODEL+FLASH_GENERIC" \ + "DBG_IF_MODEL" \ + "DBG_IF_MODEL+FLASH_GENERIC+FLASH_GENERIC_REGISTERED" \ + "DBG_IF_MODEL+FLASH_GENERIC+FLASH_GENERIC_REGISTERED+SRAM_GENERIC_REGISTERED" \ + "DBG_IF_MODEL+FLASH_GENERIC+FLASH_GENERIC_REGISTERED+OR1200_CLMODE_1TO2" \ + "DBG_IF_MODEL+FLASH_GENERIC+FLASH_GENERIC_REGISTERED+SRAM_GENERIC_REGISTERED+OR1200_CLMODE_1TO2" \ + "DBG_IF_MODEL+SRAM_GENERIC_REGISTERED" \ "") # Process arguments @@ -67,26 +72,26 @@ set i = 0; foreach test ($tests) @ i += 1; - echo -n " Test ${i}: ${test}, $maxtimes[$i] ms\t" + /bin/echo -n -e " Test ${i}: ${test}, $maxtimes[$i] ms\t" if ((${i} % 2) == 0) then - echo "" + /bin/echo -e "" endif end -echo "" +/bin/echo -e "" set i = 1; while ($iterations[$i] != "") - echo " Iteration ${i}: ${iterations[$i]}\t" + /bin/echo -e " Iteration ${i}: ${iterations[$i]}\t" @ i += 1; end # Prepare all .args files iteration: -echo "" -echo "<<<" -echo "<<< Iteration ${iter}: ${iterations[$iter]}" -echo "<<<" +/bin/echo -e "" +/bin/echo -e "<<<" +/bin/echo -e "<<< Iteration ${iter}: ${iterations[$iter]}" +/bin/echo -e "<<<" if (${iterations[$iter]} != "") then ncprep +define+${iterations[$iter]} -f ../bin/nc.scr > ncprep.out else @@ -93,39 +98,39 @@ ncprep -f ../bin/nc.scr > ncprep.out endif if (`tail -1 ncprep.out | grep Failed` != "") then - echo "" + /bin/echo -e "" cat ncprep.out exit endif # Run NC-Verilog compiler -echo "" -echo "\t@@@" -echo "\t@@@ Compiling sources" -echo "\t@@@" +/bin/echo -e "" +/bin/echo -e "\t@@@" +/bin/echo -e "\t@@@ Compiling sources" +/bin/echo -e "\t@@@" ncvlog -NOCOPYRIGHT -f ncvlog.args > ncvlog.out if ($status != 0) then - echo "\t@@@ FAILED" - echo "" + /bin/echo -e "\t@@@ FAILED" + /bin/echo -e "" cat ncvlog.out exit else - echo "\t@@@ Passed" + /bin/echo -e "\t@@@ Passed" endif # Run the NC-Verilog elaborator (build the design hierarchy) -echo "" -echo "\t@@@" -echo "\t@@@ Building design hierarchy (elaboration)" -echo "\t@@@" +/bin/echo -e "" +/bin/echo -e "\t@@@" +/bin/echo -e "\t@@@ Building design hierarchy (elaboration)" +/bin/echo -e "\t@@@" ncelab -NOTIMINGCHECKS -NOCOPYRIGHT -f ncelab.args > ncelab.out if ($status != 0) then - echo "\t@@@ FAILED" - echo "" + /bin/echo -e "\t@@@ FAILED" + /bin/echo -e "" cat ncelab.out exit else - echo "\t@@@ Passed" + /bin/echo -e "\t@@@ Passed" endif # Run the NC-Verilog simulator (simulate the design) @@ -133,17 +138,17 @@ set i = 0; foreach test ($tests) @ i += 1; - echo "" - echo "\t###" - echo "\t### Running test ${i}: ${test}, $maxtimes[$i] ms" - echo "\t###" + /bin/echo -e "" + /bin/echo -e "\t###" + /bin/echo -e "\t### Running test ${i}: ${test}, $maxtimes[$i] ms" + /bin/echo -e "\t###" - echo "database -open waves -into ../out/wave/i${iter}-${test} -default" > sim.tcl - echo "probe -create -shm xess_top -all -variables -depth all" >> sim.tcl - echo "probe -create -shm or1200_monitor -all -variables -depth all" >> sim.tcl - echo "stop -create -time $maxtimes[$i]ms -relative" >> sim.tcl - echo "run" >> sim.tcl - echo "quit" >> sim.tcl + /bin/echo -e "database -open waves -into ../out/wave/i${iter}-${test} -default" > sim.tcl + /bin/echo -e "probe -create -shm xess_top -all -variables -depth all" >> sim.tcl + /bin/echo -e "probe -create -shm or1200_monitor -all -variables -depth all" >> sim.tcl + /bin/echo -e "stop -create -time $maxtimes[$i]ms -relative" >> sim.tcl + /bin/echo -e "run" >> sim.tcl + /bin/echo -e "quit" >> sim.tcl cp ../src/${test}.hex ../src/flash.in ncsim -NOCOPYRIGHT -f ncsim.args > ncsim.out @@ -154,11 +159,11 @@ set magic=`grep report general.log | tail -1 | cut -d'(' -f2 | cut -d')' -f1 | cut -d' ' -f1` set magictime=`tail -1 general.log | cut -d'n' -f1` if ($magic == "deaddead") then - echo "\t### Passed (@time $magictime)" + /bin/echo -e "\t### Passed (@time $magictime)" @ all_tests += 1; else - echo "\t### FAILED (@time $magictime, magic# 0x$magic)" - echo ../log/i${iter}-${test}-general.log: + /bin/echo -e "\t### FAILED (@time $magictime, magic# 0x$magic)" + /bin/echo ../log/i${iter}-${test}-general.log: cat general.log @ failed += 1; @ all_tests += 1; @@ -176,10 +181,10 @@ if ($iterations[$iter] != "") then goto iteration else - echo "" - echo "<<<" - echo "<<< End of Regression Iterations" - echo "<<<" - echo "<<< Failed $failed out of $all_tests" - echo "<<<" + /bin/echo -e "" + /bin/echo -e "<<<" + /bin/echo -e "<<< End of Regression Iterations" + /bin/echo -e "<<<" + /bin/echo -e "<<< Failed $failed out of $all_tests" + /bin/echo -e "<<<" endif
/trunk/orp/orp_soc/sim/bin/nc.scr
131,6 → 131,7
// RTL files (or1200)
//
+incdir+../../rtl/verilog/or1200
../../rtl/verilog/or1200/or1200_iwb_biu.v
../../rtl/verilog/or1200/or1200_wb_biu.v
../../rtl/verilog/or1200/or1200_ctrl.v
../../rtl/verilog/or1200/or1200_cpu.v
170,13 → 171,16
../../rtl/verilog/or1200/or1200_sb.v
../../rtl/verilog/or1200/or1200_sb_fifo.v
../../rtl/verilog/or1200/or1200_mult_mac.v
../../rtl/verilog/or1200/or1200_qmem_top.v
../../rtl/verilog/or1200/or1200_dpram_32x32.v
../../rtl/verilog/or1200/or1200_spram_2048x32.v
../../rtl/verilog/or1200/or1200_spram_2048x32_bw.v
../../rtl/verilog/or1200/or1200_spram_2048x8.v
../../rtl/verilog/or1200/or1200_spram_512x20.v
../../rtl/verilog/or1200/or1200_spram_256x21.v
../../rtl/verilog/or1200/or1200_spram_1024x8.v
../../rtl/verilog/or1200/or1200_spram_1024x32.v
../../rtl/verilog/or1200/or1200_spram_1024x32_bw.v
../../rtl/verilog/or1200/or1200_spram_64x14.v
../../rtl/verilog/or1200/or1200_spram_64x22.v
../../rtl/verilog/or1200/or1200_spram_64x24.v
/trunk/orp/orp_soc/sim/bin/nc_gate.scr
0,0 → 1,164
+libext+.v
+access+wr
+overwrite
+mess
+tcl+sim.tcl
+max_err_count+2
 
//
// Test bench files
//
+incdir+../../bench/verilog
../../bench/verilog/xess_top.v
//../../bench/verilog/or1200_monitor.v
// ../../bench/verilog/sram_init.v
// ../../bench/verilog/dbg_comm.v
../../bench/verilog/xcv_glbl.v
 
//
// Models
//
../../bench/models/512Kx8.v
../../bench/models/vga_model.v
../../bench/models/codec_model.v
+incdir+../../bench/models/28f016s3
../../bench/models/28f016s3/bwsvff.v
../../bench/verilog/dbg_if_model.v
../../bench/verilog/wb_master.v
 
//
// RTL files (top)
//
+incdir+../../rtl/verilog
../../rtl/verilog/xsv_fpga_top.v
../../rtl/verilog/tc_top.v
../../rtl/verilog/tdm_slave_if.v
 
//
// RTL files (audio)
//
+incdir+../../rtl/verilog/audio
../../rtl/verilog/audio/audio_codec_if.v
../../rtl/verilog/audio/audio_top.v
../../rtl/verilog/audio/audio_wb_if.v
../../rtl/verilog/audio/fifo_4095_16.v
../../rtl/verilog/audio/fifo_empty_16.v
 
//
// RTL files (mem_if)
//
+incdir+../../rtl/verilog/mem_if
../../rtl/verilog/mem_if/flash_top.v
../../rtl/verilog/mem_if/sram_top.v
 
//
// RTL files (dbg_interface)
//
+incdir+../../rtl/verilog/dbg_interface
../../rtl/verilog/dbg_interface/dbg_crc8_d1.v
../../rtl/verilog/dbg_interface/dbg_defines.v
../../rtl/verilog/dbg_interface/dbg_register.v
../../rtl/verilog/dbg_interface/dbg_registers.v
../../rtl/verilog/dbg_interface/dbg_sync_clk1_clk2.v
../../rtl/verilog/dbg_interface/dbg_top.v
../../rtl/verilog/dbg_interface/dbg_trace.v
 
//
// RTL files (ssvga)
//
+incdir+../../rtl/verilog/ssvga
../../rtl/verilog/ssvga/crtc_iob.v
../../rtl/verilog/ssvga/ssvga_crtc.v
../../rtl/verilog/ssvga/ssvga_defines.v
../../rtl/verilog/ssvga/ssvga_fifo.v
../../rtl/verilog/ssvga/ssvga_top.v
../../rtl/verilog/ssvga/ssvga_wbm_if.v
../../rtl/verilog/ssvga/ssvga_wbs_if.v
 
//
// RTL files (ethernet)
//
+incdir+../../rtl/verilog/ethernet
../../rtl/verilog/ethernet/eth_clockgen.v
../../rtl/verilog/ethernet/eth_crc.v
../../rtl/verilog/ethernet/eth_fifo.v
../../rtl/verilog/ethernet/eth_maccontrol.v
../../rtl/verilog/ethernet/eth_macstatus.v
../../rtl/verilog/ethernet/eth_miim.v
../../rtl/verilog/ethernet/eth_outputcontrol.v
../../rtl/verilog/ethernet/eth_random.v
../../rtl/verilog/ethernet/eth_receivecontrol.v
../../rtl/verilog/ethernet/eth_register.v
../../rtl/verilog/ethernet/eth_registers.v
../../rtl/verilog/ethernet/eth_rxaddrcheck.v
../../rtl/verilog/ethernet/eth_rxcounters.v
../../rtl/verilog/ethernet/eth_rxethmac.v
../../rtl/verilog/ethernet/eth_rxstatem.v
../../rtl/verilog/ethernet/eth_shiftreg.v
../../rtl/verilog/ethernet/eth_transmitcontrol.v
../../rtl/verilog/ethernet/eth_txcounters.v
../../rtl/verilog/ethernet/eth_txethmac.v
../../rtl/verilog/ethernet/eth_txstatem.v
../../rtl/verilog/ethernet/eth_wishbone.v
../../rtl/verilog/ethernet/eth_spram_256x32.v
../../rtl/verilog/ethernet/eth_top.v
 
//
// RTL files (uart16550)
//
+incdir+../../rtl/verilog/uart16550
../../rtl/verilog/uart16550/raminfr.v
../../rtl/verilog/uart16550/uart_debug_if.v
../../rtl/verilog/uart16550/uart_tfifo.v
../../rtl/verilog/uart16550/uart_rfifo.v
../../rtl/verilog/uart16550/uart_receiver.v
../../rtl/verilog/uart16550/uart_regs.v
../../rtl/verilog/uart16550/uart_transmitter.v
../../rtl/verilog/uart16550/uart_wb.v
../../rtl/verilog/uart16550/uart_top.v
 
//
// RTL files (ps2)
//
+incdir+../../rtl/verilog/ps2
../../rtl/verilog/ps2/ps2_io_ctrl.v
../../rtl/verilog/ps2/ps2_keyboard.v
../../rtl/verilog/ps2/ps2_translation_table.v
../../rtl/verilog/ps2/ps2_wb_if.v
../../rtl/verilog/ps2/ps2_top.v
 
//
// RTL files (or1200)
//
+incdir+../../rtl/verilog/or1200
../../rtl/verilog/or1200/or1200_wb_biu.v
../../../../or1200/syn/synopsys/out/xxx_or1200_topxx.v
 
//
// Library files
//
+incdir+../../syn
../../syn/vs_sc.v
../../syn/vs_hdsp_1024x32.v
../../syn/vs_hdsp_1024x8.v
../../syn/vs_hdsp_2048x32.v
../../syn/vs_hdsp_2048x8.v
../../syn/vs_hdsp_256x32.v
../../syn/vs_hdsp_512x20.v
../../syn/vs_hdsp_64x14.v
../../syn/vs_hdsp_64x22.v
../../syn/vs_hdsp_64x24.v
../../syn/vs_hdtp_32x32.v
+incdir+../../lib/xilinx/coregen
../../lib/xilinx/coregen/XilinxCoreLib/async_fifo_v3_0.v
+incdir+../../lib/xilinx/unisims
../../lib/xilinx/unisims/RAMB4_S16.v
../../lib/xilinx/unisims/RAMB4_S8.v
../../lib/xilinx/unisims/RAMB4_S4.v
../../lib/xilinx/unisims/RAMB4_S2.v
../../lib/xilinx/unisims/RAMB4_S16_S16.v
../../lib/xilinx/unisims/RAM32X1D.v
../../lib/xilinx/unisims/RAMB4_S8_S16.v
../../lib/xilinx/unisims/IBUFG.v
../../lib/xilinx/unisims/BUFG.v
../../lib/xilinx/unisims/CLKDLL.v
trunk/orp/orp_soc/sim/bin/nc_gate.scr Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/orp/orp_soc/sim/bin/run_sw =================================================================== --- trunk/orp/orp_soc/sim/bin/run_sw (revision 1270) +++ trunk/orp/orp_soc/sim/bin/run_sw (revision 1271) @@ -7,15 +7,7 @@ # List all test cases set alldirs=( ../../sw/dhry ../../sw/mmu ../../sw/basic ../../sw/mul ../../sw/except \ ../../sw/cbasic ../../sw/tick ../../sw/syscall ../../sw/uart ) -set alltests=(dhry-nocache-O2 dhry-icdc-O2 \ - mmu-nocache mmu-icdc basic-icdc \ - basic-nocache \ - mul-nocache-O2 mul-icdc-O2 \ - except-nocache except-icdc \ - cbasic-nocache-O2 cbasic-icdc-O0 \ - tick-nocache tick-icdc \ - syscall-nocache syscall-icdc \ - uart-nocache uart-icdc ) +set alltests=`cat ../bin/tests` # Process arguments if ($1 == "single") then @@ -28,45 +20,45 @@ rm -rf ../log/s-* foreach dir ($alldirs) @ i += 1; - echo "" - echo "\t###" - echo "\t### Clean: $dir" - echo "\t###" + /bin/echo -e "" + /bin/echo -e "\t###" + /bin/echo -e "\t### Clean: $dir" + /bin/echo -e "\t###" cd $dir make clean end - echo "" - echo "\t###" - echo "\t### Clean: ../../sw/support" - echo "\t###" + /bin/echo -e "" + /bin/echo -e "\t###" + /bin/echo -e "\t### Clean: ../../sw/support" + /bin/echo -e "\t###" cd ../../sw/support make clean - echo "" - echo "\t###" - echo "\t### Clean: ../../sw/utils" - echo "\t###" + /bin/echo -e "" + /bin/echo -e "\t###" + /bin/echo -e "\t### Clean: ../../sw/utils" + /bin/echo -e "\t###" cd ../../sw/utils make clean exit 0; else if ($1 == "build") then - echo "" - echo "\t###" - echo "\t### Build: ../../sw/utils" - echo "\t###" + /bin/echo -e "" + /bin/echo -e "\t###" + /bin/echo -e "\t### Build: ../../sw/utils" + /bin/echo -e "\t###" cd ../../sw/utils make - echo "" - echo "\t###" - echo "\t### Build: ../../sw/support" - echo "\t###" + /bin/echo -e "" + /bin/echo -e "\t###" + /bin/echo -e "\t### Build: ../../sw/support" + /bin/echo -e "\t###" cd ../../sw/support make foreach dir ($alldirs) @ i += 1; - echo "" - echo "\t###" - echo "\t### Build: $dir" - echo "\t###" + /bin/echo -e "" + /bin/echo -e "\t###" + /bin/echo -e "\t### Build: $dir" + /bin/echo -e "\t###" cd $dir make end @@ -80,13 +72,13 @@ set i = 0; foreach test ($tests) @ i += 1; - echo -n " Test ${i}: ${test}\t" + /bin/echo -n -e " Test ${i}: ${test}\t" if ((${i} % 2) == 0) then - echo "" + /bin/echo -e "" endif end -echo "" +/bin/echo -e "" # Run or1ksim sim: @@ -93,20 +85,20 @@ set i = 0; foreach test ($tests) @ i += 1; - echo "" - echo "\t###" - echo "\t### Running test ${i}: ${test}" - echo "\t###" + /bin/echo -e "" + /bin/echo -e "\t###" + /bin/echo -e "\t### Running test ${i}: ${test}" + /bin/echo -e "\t###" set test_binary=`find $alldirs -name $test.or32` - echo "run 10000000 hush\nq\n" | or32-uclinux-sim -i -f ../../sw/support/orp.cfg $test_binary >& or1ksim.log + /bin/echo -e "run 10000000 hush\nq\n" | or32-uclinux-sim -i -f ../../sw/support/orp.cfg $test_binary >& or1ksim.log set magic=`grep report or1ksim.log | tail -1 | sed -e "s/(sim) //" | cut -d'(' -f2 | cut -d')' -f1 | cut -d' ' -f1` if ($magic == "0xdeaddead") then - echo "\t### Passed" + /bin/echo -e "\t### Passed" @ all_tests += 1; else - echo "\t### FAILED (magic# $magic)" - echo ../log/s-${test}-or1ksim.log: + /bin/echo -e "\t### FAILED (magic# $magic)" + /bin/echo ../log/s-${test}-or1ksim.log: cat or1ksim.log @ failed += 1; @ all_tests += 1; @@ -118,7 +110,7 @@ endif end - echo "" - echo "<<<" - echo "<<< Failed $failed out of $all_tests" - echo "<<<" + /bin/echo -e "" + /bin/echo -e "<<<" + /bin/echo -e "<<< Failed $failed out of $all_tests" + /bin/echo -e "<<<"

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