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/
- from Rev 1272 to Rev 1273
- ↔ Reverse comparison
Rev 1272 → Rev 1273
/trunk/or1200/rtl/verilog/or1200_defines.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.38 2004/04/05 08:29:57 lampret |
// Merged branch_qmem into main tree. |
// |
// Revision 1.35.4.6 2004/02/11 01:40:11 lampret |
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS. |
// |
282,6 → 285,7
// |
// Size/type of insn/data cache if implemented |
// |
// `define OR1200_IC_1W_512B |
// `define OR1200_IC_1W_4KB |
`define OR1200_IC_1W_8KB |
// `define OR1200_DC_1W_4KB |
335,6 → 339,7
// Size/type of insn/data cache if implemented |
// (consider available FPGA memory resources) |
// |
//`define OR1200_IC_1W_512B |
`define OR1200_IC_1W_4KB |
//`define OR1200_IC_1W_8KB |
`define OR1200_DC_1W_4KB |
1271,6 → 1276,14
// |
// IC configurations |
// |
`ifdef OR1200_IC_1W_512B |
`define OR1200_ICSIZE 9 // 512 |
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 7 |
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 8 |
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 9 |
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 5 |
`define OR1200_ICTAG_W 24 |
`endif |
`ifdef OR1200_IC_1W_4KB |
`define OR1200_ICSIZE 12 // 4096 |
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 10 |
/trunk/or1200/rtl/verilog/or1200_spram_32x24.v
0,0 → 1,262
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Generic Single-Port Synchronous RAM //// |
//// //// |
//// This file is part of memory library available from //// |
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ //// |
//// //// |
//// Description //// |
//// This block is a wrapper with common single-port //// |
//// synchronous memory interface for different //// |
//// types of ASIC and FPGA RAMs. Beside universal memory //// |
//// interface it also provides behavioral model of generic //// |
//// single-port synchronous RAM. //// |
//// It should be used in all OPENCORES designs that want to be //// |
//// portable accross different target technologies and //// |
//// independent of target memory. //// |
//// //// |
//// Supported ASIC RAMs are: //// |
//// - Artisan Single-Port Sync RAM //// |
//// - Avant! Two-Port Sync RAM (*) //// |
//// - Virage Single-Port Sync RAM //// |
//// - Virtual Silicon Single-Port Sync RAM //// |
//// //// |
//// Supported FPGA RAMs are: //// |
//// - Xilinx Virtex RAMB4_S16 //// |
//// - Altera LPM //// |
//// //// |
//// To Do: //// |
//// - xilinx rams need external tri-state logic //// |
//// - fix avant! two-port ram //// |
//// - add additional RAMs //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "or1200_defines.v" |
|
module or1200_spram_32x24( |
`ifdef OR1200_BIST |
// RAM BIST |
mbist_si_i, mbist_so_o, mbist_ctrl_i, |
`endif |
// Generic synchronous single-port RAM interface |
clk, rst, ce, we, oe, addr, di, do |
); |
|
// |
// Default address and data buses width |
// |
parameter aw = 5; |
parameter dw = 24; |
|
`ifdef OR1200_BIST |
// |
// RAM BIST |
// |
input mbist_si_i; |
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; |
output mbist_so_o; |
`endif |
|
// |
// Generic synchronous single-port RAM interface |
// |
input clk; // Clock |
input rst; // Reset |
input ce; // Chip enable input |
input we; // Write enable input |
input oe; // Output enable input |
input [aw-1:0] addr; // address bus inputs |
input [dw-1:0] di; // input data bus |
output [dw-1:0] do; // output data bus |
|
// |
// Internal wires and registers |
// |
wire [31:24] unconnected; |
|
`ifdef OR1200_ARTISAN_SSP |
`else |
`ifdef OR1200_VIRTUALSILICON_SSP |
`else |
`ifdef OR1200_BIST |
`endif |
`endif |
`endif |
|
`ifdef OR1200_ARTISAN_SSP |
|
// |
// Instantiation of ASIC memory: |
// |
// Artisan Synchronous Single-Port RAM (ra1sh) |
// |
`ifdef UNUSED |
`else |
`ifdef OR1200_BIST |
`else |
`endif |
`endif |
`ifdef OR1200_BIST |
// RAM BIST |
`endif |
|
`else |
|
`ifdef OR1200_AVANT_ATP |
|
// |
// Instantiation of ASIC memory: |
// |
// Avant! Asynchronous Two-Port RAM |
// |
|
`else |
|
`ifdef OR1200_VIRAGE_SSP |
|
// |
// Instantiation of ASIC memory: |
// |
// Virage Synchronous 1-port R/W RAM |
// |
|
`else |
|
`ifdef OR1200_VIRTUALSILICON_SSP |
|
// |
// Instantiation of ASIC memory: |
// |
// Virtual Silicon Single-Port Synchronous SRAM |
// |
`ifdef UNUSED |
`else |
`ifdef OR1200_BIST |
`else |
`endif |
`endif |
`ifdef OR1200_BIST |
// RAM BIST |
`endif |
|
`else |
|
`ifdef OR1200_XILINX_RAMB4 |
|
// |
// Instantiation of FPGA memory: |
// |
// Virtex/Spartan2 |
// |
|
// |
// Block 0 |
// |
RAMB4_S16 ramb4_s16_0( |
.CLK(clk), |
.RST(rst), |
.ADDR({3'h0, addr}), |
.DI(di[15:0]), |
.EN(ce), |
.WE(we), |
.DO(do[15:0]) |
); |
|
// |
// Block 1 |
// |
RAMB4_S16 ramb4_s16_1( |
.CLK(clk), |
.RST(rst), |
.ADDR({3'h0, addr}), |
.DI({8'h00, di[23:16]}), |
.EN(ce), |
.WE(we), |
.DO({unconnected, do[23:16]}) |
); |
|
`else |
|
`ifdef OR1200_ALTERA_LPM |
|
// |
// Instantiation of FPGA memory: |
// |
// Altera LPM |
// |
// Added By Jamil Khatib |
// |
|
|
`else |
|
// |
// Generic single-port synchronous RAM model |
// |
|
// |
// Generic RAM's registers and wires |
// |
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content |
reg [dw-1:0] do_reg; // RAM data output register |
|
// |
// Data output drivers |
// |
assign do = (oe) ? do_reg : {dw{1'b0}}; |
|
// |
// RAM read and write |
// |
always @(posedge clk) |
if (ce && !we) |
do_reg <= #1 mem[addr]; |
else if (ce && we) |
mem[addr] <= #1 di; |
|
`endif // !OR1200_ALTERA_LPM |
`endif // !OR1200_XILINX_RAMB4_S16 |
`endif // !OR1200_VIRTUALSILICON_SSP |
`endif // !OR1200_VIRAGE_SSP |
`endif // !OR1200_AVANT_ATP |
`endif // !OR1200_ARTISAN_SSP |
|
endmodule |
/trunk/or1200/rtl/verilog/or1200_spram_128x32.v
0,0 → 1,255
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Generic Single-Port Synchronous RAM //// |
//// //// |
//// This file is part of memory library available from //// |
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ //// |
//// //// |
//// Description //// |
//// This block is a wrapper with common single-port //// |
//// synchronous memory interface for different //// |
//// types of ASIC and FPGA RAMs. Beside universal memory //// |
//// interface it also provides behavioral model of generic //// |
//// single-port synchronous RAM. //// |
//// It should be used in all OPENCORES designs that want to be //// |
//// portable accross different target technologies and //// |
//// independent of target memory. //// |
//// //// |
//// Supported ASIC RAMs are: //// |
//// //// |
//// Supported FPGA RAMs are: //// |
//// - Xilinx Virtex RAMB4_S16 //// |
//// //// |
//// To Do: //// |
//// - add support for other RAM's //// |
//// - xilinx rams need external tri-state logic //// |
//// - fix avant! two-port ram //// |
//// - add additional RAMs //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "or1200_defines.v" |
|
module or1200_spram_128x32( |
`ifdef OR1200_BIST |
// RAM BIST |
mbist_si_i, mbist_so_o, mbist_ctrl_i, |
`endif |
// Generic synchronous single-port RAM interface |
clk, rst, ce, we, oe, addr, di, do |
); |
|
// |
// Default address and data buses width |
// |
parameter aw = 7; |
parameter dw = 32; |
|
`ifdef OR1200_BIST |
// |
// RAM BIST |
// |
input mbist_si_i; |
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; |
output mbist_so_o; |
`endif |
|
// |
// Generic synchronous single-port RAM interface |
// |
input clk; // Clock |
input rst; // Reset |
input ce; // Chip enable input |
input we; // Write enable input |
input oe; // Output enable input |
input [aw-1:0] addr; // address bus inputs |
input [dw-1:0] di; // input data bus |
output [dw-1:0] do; // output data bus |
|
// |
// Internal wires and registers |
// |
|
`ifdef OR1200_ARTISAN_SSP |
`else |
`ifdef OR1200_VIRTUALSILICON_SSP |
`else |
`ifdef OR1200_BIST |
`endif |
`endif |
`endif |
|
`ifdef OR1200_ARTISAN_SSP |
|
// |
// Instantiation of ASIC memory: |
// |
// Artisan Synchronous Single-Port RAM (ra1sh) |
// |
`ifdef UNUSED |
`else |
`ifdef OR1200_BIST |
`else |
`endif |
`endif |
`ifdef OR1200_BIST |
`endif |
`else |
|
`ifdef OR1200_AVANT_ATP |
|
// |
// Instantiation of ASIC memory: |
// |
// Avant! Asynchronous Two-Port RAM |
// |
|
`else |
|
`ifdef OR1200_VIRAGE_SSP |
|
// |
// Instantiation of ASIC memory: |
// |
// Virage Synchronous 1-port R/W RAM |
// |
|
`else |
|
`ifdef OR1200_VIRTUALSILICON_SSP |
|
// |
// Instantiation of ASIC memory: |
// |
// Virtual Silicon Single-Port Synchronous SRAM |
// |
`ifdef UNUSED |
`else |
`ifdef OR1200_BIST |
`else |
`endif |
`endif |
`ifdef OR1200_BIST |
// RAM BIST |
`endif |
|
`else |
|
`ifdef OR1200_XILINX_RAMB4 |
|
// |
// Instantiation of FPGA memory: |
// |
// Virtex/Spartan2 |
// |
|
// |
// Block 0 |
// |
RAMB4_S16 ramb4_s16_0( |
.CLK(clk), |
.RST(rst), |
.ADDR({1'b0, addr}), |
.DI(di[15:0]), |
.EN(ce), |
.WE(we), |
.DO(do[15:0]) |
); |
|
// |
// Block 1 |
// |
RAMB4_S16 ramb4_s16_1( |
.CLK(clk), |
.RST(rst), |
.ADDR({1'b0, addr}), |
.DI(di[31:16]), |
.EN(ce), |
.WE(we), |
.DO(do[31:16]) |
); |
|
`else |
|
`ifdef OR1200_ALTERA_LPM |
|
// |
// Instantiation of FPGA memory: |
// |
// Altera LPM |
// |
// Added By Jamil Khatib |
// |
|
|
`else |
|
// |
// Generic single-port synchronous RAM model |
// |
|
// |
// Generic RAM's registers and wires |
// |
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content |
reg [dw-1:0] do_reg; // RAM data output register |
|
// |
// Data output drivers |
// |
assign do = (oe) ? do_reg : {dw{1'b0}}; |
|
// |
// RAM read and write |
// |
always @(posedge clk) |
if (ce && !we) |
do_reg <= #1 mem[addr]; |
else if (ce && we) |
mem[addr] <= #1 di; |
|
`endif // !OR1200_ALTERA_LPM |
`endif // !OR1200_XILINX_RAMB4_S16 |
`endif // !OR1200_VIRTUALSILICON_SSP |
`endif // !OR1200_VIRAGE_SSP |
`endif // !OR1200_AVANT_ATP |
`endif // !OR1200_ARTISAN_SSP |
|
endmodule |
/trunk/or1200/rtl/verilog/or1200_ic_tag.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2004/04/05 08:29:57 lampret |
// Merged branch_qmem into main tree. |
// |
// Revision 1.3.4.1 2003/12/09 11:46:48 simons |
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed. |
// |
139,6 → 142,9
// |
// Instantiation of TAG RAM block |
// |
`ifdef OR1200_IC_1W_512B |
or1200_spram_32x24 ic_tag0( |
`endif |
`ifdef OR1200_IC_1W_4KB |
or1200_spram_256x21 ic_tag0( |
`endif |
/trunk/or1200/rtl/verilog/or1200_ic_ram.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2004/04/05 08:29:57 lampret |
// Merged branch_qmem into main tree. |
// |
// Revision 1.2.4.1 2003/12/09 11:46:48 simons |
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed. |
// |
129,6 → 132,9
// |
// Instantiation of IC RAM block |
// |
`ifdef OR1200_IC_1W_512B |
or1200_spram_128x32 ic_ram0( |
`endif |
`ifdef OR1200_IC_1W_4KB |
or1200_spram_1024x32 ic_ram0( |
`endif |