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URL https://opencores.org/ocsvn/or1k/or1k/trunk

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Rev 1283 → Rev 1284

/trunk/or1200/rtl/verilog/or1200_defines.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.39 2004/04/08 11:00:46 simont
// Add support for 512B instruction cache.
//
// Revision 1.38 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
591,6 → 594,7
`define OR1200_ALUOP_OR 4'd4
`define OR1200_ALUOP_XOR 4'd5
`define OR1200_ALUOP_MUL 4'd6
`define OR1200_ALUOP_CUST5 4'd7
`define OR1200_ALUOP_SHROT 4'd8
`define OR1200_ALUOP_DIV 4'd9
`define OR1200_ALUOP_DIVU 4'd10
761,6 → 765,7
`define OR1200_OR32_SH 6'b110111
`define OR1200_OR32_ALU 6'b111000
`define OR1200_OR32_SFXX 6'b111001
`define OR1200_OR32_CUST5 6'b111100
 
 
/////////////////////////////////////////////////////
/trunk/or1200/rtl/verilog/or1200_alu.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.11 2003/04/24 00:16:07 lampret
// No functional changes. Added defines to disable implementation of multiplier/MAC
//
108,6 → 111,7
module or1200_alu(
a, b, mult_mac_result, macrc_op,
alu_op, shrot_op, comp_op,
cust5_op, cust5_limm,
result, flagforw, flag_we,
cyforw, cy_we, carry
);
124,6 → 128,8
input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
input [4:0] cust5_op;
input [5:0] cust5_limm;
output [width-1:0] result;
output flagforw;
output flag_we;
136,6 → 142,7
//
reg [width-1:0] result;
reg [width-1:0] shifted_rotated;
reg [width-1:0] result_cust5;
reg flagforw;
reg flagcomp;
reg flag_we;
191,6 → 198,9
`else
casex (alu_op) // synopsys full_case parallel_case
`endif
`OR1200_ALUOP_CUST5 : begin
result = result_cust5;
end
`OR1200_ALUOP_SHROT : begin
result = shifted_rotated;
end
242,6 → 252,34
end
 
//
// l.cust5 custom instructions
//
// Examples for move byte, set bit and clear bit
//
always @(cust5_op or cust5_limm or a or b) begin
casex (cust5_op) // synopsys parallel_case
5'h1 : begin
case (cust5_limm)
2'h0: result_cust5 = {a[31:8], b[7:0]};
2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
2'h3: result_cust5 = {b[7:0], a[23:0]};
endcase
end
5'h2 :
result_cust5 = a | (1 << cust5_limm);
5'h3 :
result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));
//
// *** Put here new l.cust5 custom instructions ***
//
default: begin
result_cust5 = a;
end
endcase
end
 
//
// Generate flag and flag write enable
//
always @(alu_op or result_sum or result_and or flagcomp) begin
/trunk/or1200/rtl/verilog/or1200_cpu.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.14 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.12.4.2 2004/02/11 01:40:11 lampret
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
//
307,6 → 310,8
wire [31:0] lsu_addrofs;
wire [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
wire [`OR1200_EXCEPT_WIDTH-1:0] except_type;
wire [4:0] cust5_op;
wire [5:0] cust5_limm;
wire flushpipe;
wire extend_flush;
wire branch_taken;
478,6 → 483,8
.sel_a(sel_a),
.sel_b(sel_b),
.lsu_op(lsu_op),
.cust5_op(cust5_op),
.cust5_limm(cust5_limm),
.multicycle(multicycle),
.spr_addrimm(spr_addrimm),
.wbforw_valid(wbforw_valid),
550,6 → 557,8
.alu_op(alu_op),
.shrot_op(shrot_op),
.comp_op(comp_op),
.cust5_op(cust5_op),
.cust5_limm(cust5_limm),
.result(alu_dataout),
.flagforw(flagforw),
.flag_we(flag_we),
/trunk/or1200/rtl/verilog/or1200_ctrl.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.8.4.1 2004/02/11 01:40:11 lampret
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
//
119,6 → 122,7
id_freeze, ex_freeze, wb_freeze, flushpipe, if_insn, ex_insn, branch_op, branch_taken,
rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op, rf_addrw, rfwb_op,
wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,
cust5_op, cust5_limm,
multicycle, spr_addrimm, wbforw_valid, du_hwbkpt, sig_syscall, sig_trap,
force_dslot_fetch, no_more_dslot, ex_void, id_macrc_op, ex_macrc_op, rfe, except_illegal
);
154,6 → 158,8
output [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
output [`OR1200_COMPOP_WIDTH-1:0] comp_op;
output [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
output [4:0] cust5_op;
output [6:0] cust5_limm;
output [15:0] spr_addrimm;
input wbforw_valid;
input du_hwbkpt;
240,8 → 246,14
`endif
 
//
// cust5_op, cust5_limm (L immediate)
//
assign cust5_op = ex_insn[4:0];
assign cust5_limm = ex_insn[10:5];
 
//
//
//
assign rfe = (pre_branch_op == `OR1200_BRANCHOP_RFE) | (branch_op == `OR1200_BRANCHOP_RFE);
 
//
545,6 → 557,12
// SFXX instructions
`OR1200_OR32_SFXX:
sel_imm <= #1 1'b0;
 
`ifdef OR1200_OR32_CUST5
// l.cust5 instructions
`OR1200_OR32_CUST5:
sel_imm <= #1 1'b0;
`endif
// l.nop
`OR1200_OR32_NOP:
608,6 → 626,9
`OR1200_OR32_SH,
`OR1200_OR32_ALU,
`OR1200_OR32_SFXX,
`ifdef OR1200_OR32_CUST5
`OR1200_OR32_CUST5,
`endif
`OR1200_OR32_NOP:
except_illegal <= #1 1'b0;
 
700,6 → 721,12
// SFXX instructions
`OR1200_OR32_SFXX:
alu_op <= #1 `OR1200_ALUOP_COMP;
 
`ifdef OR1200_OR32_CUST5
// l.cust5 instructions
`OR1200_OR32_CUST5:
alu_op <= #1 `OR1200_ALUOP_CUST5;
`endif
// Default
default: begin
837,7 → 864,13
// ALU instructions except the one with immediate
`OR1200_OR32_ALU:
rfwb_op <= #1 `OR1200_RFWBOP_ALU;
 
`ifdef OR1200_OR32_CUST5
// l.cust5 instructions
`OR1200_OR32_CUST5:
rfwb_op <= #1 `OR1200_RFWBOP_ALU;
`endif
 
// Instructions w/o register-file write-back
default: begin
rfwb_op <= #1 `OR1200_RFWBOP_NOP;

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