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/trunk/rtl/verilog_TRIAL/reg_pc.v
0,0 → 1,280
`define false 1'b 0
`define FALSE 1'b 0
`define true 1'b 1
`define TRUE 1'b 1
 
`timescale 1 ns / 1 ns
 
 
// Verilog Entity R6502_TC.Reg_PC.symbol
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 19:07:21 07.01.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
 
module Reg_PC (
adr_i,
clk_clk_i,
ld_i,
ld_pc_i,
offset_i,
rst_rst_n_i,
sel_pc_in_i,
sel_pc_val_i,
adr_nxt_pc_o,
adr_pc_o);
 
input [15:0] adr_i;
input clk_clk_i;
input [1:0] ld_i;
input ld_pc_i;
input [15:0] offset_i;
input rst_rst_n_i;
input sel_pc_in_i;
input [1:0] sel_pc_val_i;
output [15:0] adr_nxt_pc_o;
output [15:0] adr_pc_o;
 
 
// Jens-D. Gutschmidt Project: R6502_TC
// scantara2003@yahoo.de
// COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
//
// This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// CVS Revisins History
//
// $Log: not supported by cvs2svn $
// <<-- more -->>
// Title: Program Counter Logic
// Path: R6502_TC/Reg_PC/struct
// Edited: by eda on 07 Jan 2009
//
// Verilog Architecture R6502_TC.Reg_PC.struct
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 19:07:21 07.01.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
wire [15:0] adr_nxt_pc_o;
wire [15:0] adr_pc_o;
 
// Declarations
reg [7:0] adr_pc_high_o_i;
reg [7:0] adr_pc_low_o_i;
reg [15:0] adr_pc_o_i;
wire ci_o_i;
reg cout_pc_o_i;
wire load3_o_i;
wire load_o_i;
reg [7:0] offset_high_o_i;
reg [7:0] offset_low_o_i;
reg [7:0] val_o_i;
wire [7:0] val_one;
wire [7:0] val_zero;
 
// Implicit buffer signal declarations
wire [15:0] adr_pc_o_internal;
reg [15:0] adr_nxt_pc_o_internal;
 
// ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
reg [7:0] mw_U_0reg_cval;
 
// ModuleWare signal declarations(v1.9) for instance 'U_4' of 'adff'
reg [7:0] mw_U_4reg_cval;
 
// ModuleWare signal declarations(v1.9) for instance 'U_3' of 'split'
wire [15:0] mw_U_3temp_din;
 
// ModuleWare signal declarations(v1.9) for instance 'U_5' of 'split'
wire [15:0] mw_U_5temp_din;
 
// ModuleWare code(v1.9) for instance 'U_2' of 'add'
reg [8:0] u_2combo_proc_temp_din0;
reg [8:0] u_2combo_proc_temp_din1;
reg [8:0] u_2combo_proc_temp_sum;
reg u_2combo_proc_temp_carry;
reg [8:0] u_11combo_proc_temp_din0;
reg [8:0] u_11combo_proc_temp_din1;
reg [8:0] u_11combo_proc_temp_sum;
reg u_11combo_proc_temp_carry;
reg [15:0] u_3combo_proc_temp_din;
reg [15:0] u_5combo_proc_temp_din;
 
 
always @(adr_pc_low_o_i or val_o_i)
begin : u_2combo_proc
u_2combo_proc_temp_din0 = {1'b 0, adr_pc_low_o_i};
u_2combo_proc_temp_din1 = {1'b 0, val_o_i};
u_2combo_proc_temp_carry = 1'b 0;
u_2combo_proc_temp_sum = u_2combo_proc_temp_din0 + u_2combo_proc_temp_din1 + u_2combo_proc_temp_carry;
adr_nxt_pc_o_internal[7:0] <= u_2combo_proc_temp_sum[7:0];
cout_pc_o_i <= u_2combo_proc_temp_sum[8];
end
 
// ModuleWare code(v1.9) for instance 'U_11' of 'add'
 
always @(adr_pc_high_o_i or offset_high_o_i or ci_o_i)
begin : u_11combo_proc
u_11combo_proc_temp_din0 = {1'b 0, adr_pc_high_o_i};
u_11combo_proc_temp_din1 = {1'b 0, offset_high_o_i};
u_11combo_proc_temp_carry = ci_o_i;
u_11combo_proc_temp_sum = u_11combo_proc_temp_din0 + u_11combo_proc_temp_din1 + u_11combo_proc_temp_carry;
adr_nxt_pc_o_internal[15:8] <= u_11combo_proc_temp_sum[7:0];
end
 
// ModuleWare code(v1.9) for instance 'U_0' of 'adff'
assign adr_pc_o_internal[7:0] = mw_U_0reg_cval;
 
always @(clk_clk_i or rst_rst_n_i)
begin : u_0seq_proc
if (rst_rst_n_i == 1'b 0 | rst_rst_n_i == 1'b 0)
begin
mw_U_0reg_cval <= 8'b 00000000;
end
else if (clk_clk_i /* ignored attribute: 'EVENT */ & clk_clk_i == 1'b 1 )
begin
if (load_o_i == 1'b 1 | load_o_i == 1'b 1)
begin
mw_U_0reg_cval <= adr_nxt_pc_o_internal[7:0];
end
end
end
 
// ModuleWare code(v1.9) for instance 'U_4' of 'adff'
assign adr_pc_o_internal[15:8] = mw_U_4reg_cval;
 
always @(clk_clk_i or rst_rst_n_i)
begin : u_4seq_proc
if (rst_rst_n_i == 1'b 0 | rst_rst_n_i == 1'b 0)
begin
mw_U_4reg_cval <= 8'b 00000000;
end
else if (clk_clk_i /* ignored attribute: 'EVENT */ & clk_clk_i == 1'b 1 )
begin
if (load3_o_i == 1'b 1 | load3_o_i == 1'b 1)
begin
mw_U_4reg_cval <= adr_nxt_pc_o_internal[15:8];
end
end
end
 
// ModuleWare code(v1.9) for instance 'U_6' of 'and'
assign load_o_i = ld_pc_i & ld_i[0];
 
// ModuleWare code(v1.9) for instance 'U_7' of 'and'
assign load3_o_i = ld_pc_i & ld_i[1];
 
// ModuleWare code(v1.9) for instance 'U_10' of 'and'
assign ci_o_i = cout_pc_o_i & ld_pc_i;
 
// ModuleWare code(v1.9) for instance 'U_1' of 'constval'
assign val_zero = 8'b 00000000;
 
// ModuleWare code(v1.9) for instance 'U_9' of 'constval'
assign val_one = 8'b 00000001;
 
// ModuleWare code(v1.9) for instance 'U_8' of 'mux'
 
always @(adr_pc_o_internal or adr_i or sel_pc_in_i)
begin : u_8combo_proc
case (sel_pc_in_i)
1'b 0,
1'b 0:
begin
adr_pc_o_i <= adr_pc_o_internal;
end
1'b 1,
1'b 1:
begin
adr_pc_o_i <= adr_i;
end
default:
begin
adr_pc_o_i <= {16{1'b X}};
end
endcase
end
 
// ModuleWare code(v1.9) for instance 'U_13' of 'mux'
 
always @(val_one or val_zero or offset_low_o_i or sel_pc_val_i)
begin : u_13combo_proc
case (sel_pc_val_i)
2'b 00,
2'b 00,
2'b 00,
2'b 00:
begin
val_o_i <= val_one;
end
2'b 01,
2'b 01,
2'b 01,
2'b 01:
begin
val_o_i <= val_zero;
end
2'b 10,
2'b 10,
2'b 10,
2'b 10:
begin
val_o_i <= offset_low_o_i;
end
2'b 11,
2'b 11,
2'b 11,
2'b 11:
begin
val_o_i <= val_zero;
end
default:
begin
val_o_i <= {8{1'b X}};
end
endcase
end
 
// ModuleWare code(v1.9) for instance 'U_3' of 'split'
assign mw_U_3temp_din = adr_pc_o_i;
 
always @(mw_U_3temp_din)
begin : u_3combo_proc
u_3combo_proc_temp_din = mw_U_3temp_din[15:0];
adr_pc_low_o_i <= u_3combo_proc_temp_din[7:0];
adr_pc_high_o_i <= u_3combo_proc_temp_din[15:8];
end
 
// ModuleWare code(v1.9) for instance 'U_5' of 'split'
assign mw_U_5temp_din = offset_i;
 
always @(mw_U_5temp_din)
begin : u_5combo_proc
u_5combo_proc_temp_din = mw_U_5temp_din[15:0];
offset_low_o_i <= u_5combo_proc_temp_din[7:0];
offset_high_o_i <= u_5combo_proc_temp_din[15:8];
end
 
// Instance port mappings.
// Implicit buffered output assignments
assign adr_pc_o = adr_pc_o_internal;
assign adr_nxt_pc_o = adr_nxt_pc_o_internal;
 
// Architecture declarations
// Internal signal declarations
 
endmodule // module Reg_PC
 
/trunk/rtl/verilog_TRIAL/reg_sp.v
0,0 → 1,169
`define false 1'b 0
`define FALSE 1'b 0
`define true 1'b 1
`define TRUE 1'b 1
 
`timescale 1 ns / 1 ns
 
 
// Verilog Entity R6502_TC.Reg_SP.symbol
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 18:23:46 07.01.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
 
module Reg_SP (
adr_low_i,
clk_clk_i,
ld_low_i,
ld_sp_i,
rst_rst_n_i,
sel_sp_as_i,
sel_sp_in_i,
adr_sp_o);
 
input [7:0] adr_low_i;
input clk_clk_i;
input ld_low_i;
input ld_sp_i;
input rst_rst_n_i;
input sel_sp_as_i;
input sel_sp_in_i;
output [15:0] adr_sp_o;
 
 
// Jens-D. Gutschmidt Project: R6502_TC
// scantara2003@yahoo.de
// COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
//
// This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// CVS Revisins History
//
// $Log: not supported by cvs2svn $
// <<-- more -->>
// Title: Stack Pointer Logic
// Path: R6502_TC/Reg_SP/struct
// Edited: by eda on 01 Jan 2009
//
// Verilog Architecture R6502_TC.Reg_SP.struct
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 18:23:46 07.01.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
wire [15:0] adr_sp_o;
 
// Declarations
wire [7:0] adr_sp_low_o_i;
wire load_o_i;
reg [7:0] result_low1_o_i;
reg [7:0] result_low_o_i;
wire sp_as_n_o_i;
wire [7:0] val_one;
 
// Implicit buffer signal declarations
wire [15:0] adr_sp_o_internal;
 
// ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
reg [7:0] mw_U_0reg_cval;
 
// ModuleWare code(v1.9) for instance 'U_11' of 'addsub'
reg [8:0] u_11combo_proc_temp_din0;
reg [8:0] u_11combo_proc_temp_din1;
reg [8:0] u_11combo_proc_temp_sum;
reg u_11combo_proc_temp_carry;
 
 
always @(adr_sp_low_o_i or val_one or sp_as_n_o_i)
begin : u_11combo_proc
u_11combo_proc_temp_din0 = {1'b 0, adr_sp_low_o_i};
u_11combo_proc_temp_din1 = {1'b 0, val_one};
u_11combo_proc_temp_carry = 1'b 0;
if (sp_as_n_o_i == 1'b 1 | sp_as_n_o_i == 1'b 1)
begin
u_11combo_proc_temp_sum = u_11combo_proc_temp_din0 + u_11combo_proc_temp_din1 + u_11combo_proc_temp_carry;
end
else
begin
u_11combo_proc_temp_sum = u_11combo_proc_temp_din0 - u_11combo_proc_temp_din1 - u_11combo_proc_temp_carry;
end
result_low_o_i <= u_11combo_proc_temp_sum[7:0];
end
 
// ModuleWare code(v1.9) for instance 'U_0' of 'adff'
assign adr_sp_o_internal[7:0] = mw_U_0reg_cval;
 
always @(clk_clk_i or rst_rst_n_i)
begin : u_0seq_proc
if (rst_rst_n_i == 1'b 0 | rst_rst_n_i == 1'b 0)
begin
mw_U_0reg_cval <= 8'b 00000000;
end
else if (clk_clk_i /* ignored attribute: 'EVENT */ & clk_clk_i == 1'b 1 )
begin
if (load_o_i == 1'b 1 | load_o_i == 1'b 1)
begin
mw_U_0reg_cval <= result_low1_o_i;
end
end
end
 
// ModuleWare code(v1.9) for instance 'U_6' of 'and'
assign load_o_i = ld_sp_i & ld_low_i;
 
// ModuleWare code(v1.9) for instance 'U_3' of 'buff'
assign adr_sp_o_internal[15:8] = val_one;
 
// ModuleWare code(v1.9) for instance 'U_4' of 'constval'
assign val_one = 8'b 00000001;
 
// ModuleWare code(v1.9) for instance 'U_2' of 'inv'
assign sp_as_n_o_i = ~sel_sp_as_i;
 
// ModuleWare code(v1.9) for instance 'U_8' of 'mux'
 
always @(result_low_o_i or adr_low_i or sel_sp_in_i)
begin : u_8combo_proc
case (sel_sp_in_i)
1'b 0,
1'b 0:
begin
result_low1_o_i <= result_low_o_i;
end
1'b 1,
1'b 1:
begin
result_low1_o_i <= adr_low_i;
end
default:
begin
result_low1_o_i <= {8{1'b X}};
end
endcase
end
 
// ModuleWare code(v1.9) for instance 'U_10' of 'tap'
assign adr_sp_low_o_i = adr_sp_o_internal[7:0];
 
// Instance port mappings.
// Implicit buffered output assignments
assign adr_sp_o = adr_sp_o_internal;
 
// Architecture declarations
// Internal signal declarations
 
endmodule // module Reg_SP
 
/trunk/rtl/verilog_TRIAL/r6502_tc.v
0,0 → 1,107
`define false 1'b 0
`define FALSE 1'b 0
`define true 1'b 1
`define TRUE 1'b 1
 
`timescale 1 ns / 1 ns
 
 
// Verilog Entity R6502_TC.R6502_TC.symbol
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 19:21:55 07.01.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
 
module R6502_TC (
clk_clk_i,
d_i,
irq_n_i,
nmi_n_i,
rdy_i,
rst_rst_n_i,
so_n_i,
a_o,
d_o,
rd_o,
sync_o,
wr_n_o,
wr_o);
 
input clk_clk_i;
input [7:0] d_i;
input irq_n_i;
input nmi_n_i;
input rdy_i;
input rst_rst_n_i;
input so_n_i;
output [15:0] a_o;
output [7:0] d_o;
output rd_o;
output sync_o;
output wr_n_o;
output wr_o;
 
 
// Jens-D. Gutschmidt Project: R6502_TC
// scantara2003@yahoo.de
// COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
//
// This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// CVS Revisins History
//
// $Log: not supported by cvs2svn $
// <<-- more -->>
// Title: Top Level
// Path: R6502_TC/R6502_TC/struct
// Edited: by eda on 04 Jan 2009
//
// Verilog Architecture R6502_TC.R6502_TC.struct
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 19:21:55 07.01.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
wire [15:0] a_o;
wire [7:0] d_o;
wire rd_o;
wire sync_o;
wire wr_n_o;
wire wr_o;
 
// Declarations
 
// Instance port mappings.
 
Core U_0 (.clk_clk_i(clk_clk_i),
.d_i(d_i),
.irq_n_i(irq_n_i),
.nmi_n_i(nmi_n_i),
.rdy_i(rdy_i),
.rst_rst_n_i(rst_rst_n_i),
.so_n_i(so_n_i),
.a_o(a_o),
.d_o(d_o),
.rd_o(rd_o),
.sync_o(sync_o),
.wr_n_o(wr_n_o),
.wr_o(wr_o));
 
// Architecture declarations
// Internal signal declarations
// Component Declarations
 
endmodule // module R6502_TC
 
/trunk/rtl/verilog_TRIAL/fsm_execution_unit.v
0,0 → 1,6586
`define false 1'b 0
`define FALSE 1'b 0
`define true 1'b 1
`define TRUE 1'b 1
 
`timescale 1 ns / 1 ns
 
 
// Verilog Entity R6502_TC.FSM_Execution_Unit.symbol
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 19:21:47 07.01.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
 
module FSM_Execution_Unit (
adr_nxt_pc_i,
adr_pc_i,
adr_sp_i,
clk_clk_i,
d_alu_i,
d_i,
d_regs_out_i,
irq_n_i,
nmi_i,
q_a_i,
q_x_i,
q_y_i,
rdy_i,
reg_0flag_i,
reg_1flag_i,
reg_7flag_i,
rst_rst_n_i,
so_n_i,
a_o,
adr_o,
ch_a_o,
ch_b_o,
d_o,
d_regs_in_o,
fetch_o,
ld_o,
ld_pc_o,
ld_sp_o,
load_regs_o,
offset_o,
rd_o,
sel_pc_in_o,
sel_pc_val_o,
sel_rb_in_o,
sel_rb_out_o,
sel_reg_o,
sel_sp_as_o,
sel_sp_in_o,
sync_o,
wr_n_o,
wr_o);
 
input [15:0] adr_nxt_pc_i;
input [15:0] adr_pc_i;
input [15:0] adr_sp_i;
input clk_clk_i;
input [7:0] d_alu_i;
input [7:0] d_i;
input [7:0] d_regs_out_i;
input irq_n_i;
input nmi_i;
input [7:0] q_a_i;
input [7:0] q_x_i;
input [7:0] q_y_i;
input rdy_i;
input reg_0flag_i;
input reg_1flag_i;
input reg_7flag_i;
input rst_rst_n_i;
input so_n_i;
output [15:0] a_o;
output [15:0] adr_o;
output [7:0] ch_a_o;
output [7:0] ch_b_o;
output [7:0] d_o;
output [7:0] d_regs_in_o;
output fetch_o;
output [1:0] ld_o;
output ld_pc_o;
output ld_sp_o;
output load_regs_o;
output [15:0] offset_o;
output rd_o;
output sel_pc_in_o;
output [1:0] sel_pc_val_o;
output [1:0] sel_rb_in_o;
output [1:0] sel_rb_out_o;
output [1:0] sel_reg_o;
output sel_sp_as_o;
output sel_sp_in_o;
output sync_o;
output wr_n_o;
output wr_o;
 
 
// Jens-D. Gutschmidt Project: R6502_TC
// scantara2003@yahoo.de
// COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
//
// This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// CVS Revisins History
//
// $Log: not supported by cvs2svn $
// <<-- more -->>
// Title: FSM Execution Unit for all op codes
// Path: R6502_TC/FSM_Execution_Unit/fsm
// Edited: by eda on 07 Jan 2009
//
// Verilog Architecture R6502_TC.FSM_Execution_Unit.fsm
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 19:21:50 07.01.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
reg [15:0] a_o;
reg [15:0] adr_o;
reg [7:0] ch_a_o;
reg [7:0] ch_b_o;
wire [7:0] d_o;
reg [7:0] d_regs_in_o;
reg fetch_o;
reg [1:0] ld_o;
reg ld_pc_o;
reg ld_sp_o;
reg load_regs_o;
reg [15:0] offset_o;
wire rd_o;
reg sel_pc_in_o;
reg [1:0] sel_pc_val_o;
reg [1:0] sel_rb_in_o;
reg [1:0] sel_rb_out_o;
reg [1:0] sel_reg_o;
reg sel_sp_as_o;
reg sel_sp_in_o;
wire sync_o;
wire wr_n_o;
wire wr_o;
 
// Declarations
reg [7:0] reg_F;
reg reg_sel_pc_in;
reg [1:0] reg_sel_pc_val;
reg [1:0] reg_sel_rb_in;
reg [1:0] reg_sel_rb_out;
reg [1:0] reg_sel_reg;
reg reg_sel_sp_as;
reg reg_sel_sp_in;
reg [7:0] sig_D_OUT;
reg [15:0] sig_PC;
reg sig_RD;
reg sig_RWn;
reg sig_SYNC;
reg sig_WR;
reg [8:0] zw_ALU;
reg [4:0] zw_ALU1;
reg [4:0] zw_ALU2;
reg [4:0] zw_ALU3;
reg [4:0] zw_ALU4;
reg [3:0] zw_ALU5;
reg [3:0] zw_ALU6;
reg zw_REG_NMI;
reg [7:0] zw_REG_OP;
reg [7:0] zw_b1;
reg [7:0] zw_b2;
reg [7:0] zw_b3;
reg [7:0] zw_b4;
reg zw_so;
parameter FETCH = 8'b 00000000;
parameter s1 = 8'b 00000001;
parameter s2 = 8'b 00000011;
parameter s5 = 8'b 00000010;
parameter s3 = 8'b 00000110;
parameter s4 = 8'b 00000111;
parameter s12 = 8'b 00000101;
parameter s16 = 8'b 00000100;
parameter s17 = 8'b 00001100;
parameter s24 = 8'b 00001101;
parameter s25 = 8'b 00001111;
parameter s271 = 8'b 00001110;
parameter s273 = 8'b 00001010;
parameter s304 = 8'b 00001011;
parameter s307 = 8'b 00001001;
parameter s177 = 8'b 00001000;
parameter s180 = 8'b 00011000;
parameter s181 = 8'b 00011001;
parameter s182 = 8'b 00011011;
parameter s183 = 8'b 00011010;
parameter s184 = 8'b 00011110;
parameter s185 = 8'b 00011111;
parameter s186 = 8'b 00011101;
parameter s187 = 8'b 00011100;
parameter s188 = 8'b 00010100;
parameter s189 = 8'b 00010101;
parameter s190 = 8'b 00010111;
parameter s191 = 8'b 00010110;
parameter s192 = 8'b 00010010;
parameter s193 = 8'b 00010011;
parameter s377 = 8'b 00010001;
parameter s381 = 8'b 00010000;
parameter s378 = 8'b 00110000;
parameter s382 = 8'b 00110001;
parameter s379 = 8'b 00110011;
parameter s383 = 8'b 00110010;
parameter s384 = 8'b 00110110;
parameter s380 = 8'b 00110111;
parameter s385 = 8'b 00110101;
parameter s386 = 8'b 00110100;
parameter s387 = 8'b 00111100;
parameter s388 = 8'b 00111101;
parameter s389 = 8'b 00111111;
parameter s391 = 8'b 00111110;
parameter s392 = 8'b 00111010;
parameter s390 = 8'b 00111011;
parameter s393 = 8'b 00111001;
parameter s394 = 8'b 00111000;
parameter s395 = 8'b 00101000;
parameter s396 = 8'b 00101001;
parameter s397 = 8'b 00101011;
parameter s398 = 8'b 00101010;
parameter s399 = 8'b 00101110;
parameter s400 = 8'b 00101111;
parameter s401 = 8'b 00101101;
parameter s526 = 8'b 00101100;
parameter s527 = 8'b 00100100;
parameter s528 = 8'b 00100101;
parameter s529 = 8'b 00100111;
parameter s530 = 8'b 00100110;
parameter s531 = 8'b 00100010;
parameter s544 = 8'b 00100011;
parameter s545 = 8'b 00100001;
parameter s546 = 8'b 00100000;
parameter s547 = 8'b 01100000;
parameter s549 = 8'b 01100001;
parameter s550 = 8'b 01100011;
parameter s404 = 8'b 01100010;
parameter s556 = 8'b 01100110;
parameter s557 = 8'b 01100111;
parameter s579 = 8'b 01100101;
parameter s201 = 8'b 01100100;
parameter s202 = 8'b 01101100;
parameter s210 = 8'b 01101101;
parameter s211 = 8'b 01101111;
parameter s215 = 8'b 01101110;
parameter s217 = 8'b 01101010;
parameter s218 = 8'b 01101011;
parameter s222 = 8'b 01101001;
parameter s223 = 8'b 01101000;
parameter s224 = 8'b 01111000;
parameter s225 = 8'b 01111001;
parameter s226 = 8'b 01111011;
parameter s243 = 8'b 01111010;
parameter s244 = 8'b 01111110;
parameter s247 = 8'b 01111111;
parameter s344 = 8'b 01111101;
parameter s343 = 8'b 01111100;
parameter s250 = 8'b 01110100;
parameter s251 = 8'b 01110101;
parameter s351 = 8'b 01110111;
parameter s361 = 8'b 01110110;
parameter s360 = 8'b 01110010;
parameter s403 = 8'b 01110011;
parameter s406 = 8'b 01110001;
parameter s407 = 8'b 01110000;
parameter s409 = 8'b 01010000;
parameter s412 = 8'b 01010001;
parameter s413 = 8'b 01010011;
parameter s416 = 8'b 01010010;
parameter s418 = 8'b 01010110;
parameter s510 = 8'b 01010111;
parameter s553 = 8'b 01010101;
parameter s555 = 8'b 01010100;
parameter s558 = 8'b 01011100;
parameter s560 = 8'b 01011101;
parameter s561 = 8'b 01011111;
parameter s563 = 8'b 01011110;
parameter s564 = 8'b 01011010;
parameter s565 = 8'b 01011011;
parameter s566 = 8'b 01011001;
parameter s266 = 8'b 01011000;
parameter s301 = 8'b 01001000;
parameter s302 = 8'b 01001001;
parameter RES = 8'b 01001011;
parameter s511 = 8'b 01001010;
parameter s559 = 8'b 01001110;
parameter s562 = 8'b 01001111;
parameter s567 = 8'b 01001101;
parameter s568 = 8'b 01001100;
parameter s569 = 8'b 01000100;
parameter s570 = 8'b 01000101;
parameter s571 = 8'b 01000111;
parameter s572 = 8'b 01000110;
parameter s573 = 8'b 01000010;
parameter s574 = 8'b 01000011;
parameter s548 = 8'b 01000001;
parameter s551 = 8'b 01000000;
parameter s552 = 8'b 11000000;
parameter s575 = 8'b 11000001;
parameter s576 = 8'b 11000011;
parameter s577 = 8'b 11000010;
parameter s532 = 8'b 11000110;
parameter s533 = 8'b 11000111;
parameter s534 = 8'b 11000101;
parameter s535 = 8'b 11000100;
parameter s536 = 8'b 11001100;
parameter s537 = 8'b 11001101;
 
// Declare current and next state signals
reg [7:0] current_state;
reg [7:0] next_state;
 
// Declare any pre-registered internal signals
reg [7:0] d_o_cld;
reg rd_o_cld;
reg sync_o_cld;
reg wr_n_o_cld;
reg wr_o_cld;
 
// ---------------------------------------------------------------
 
 
always @(posedge clk_clk_i or negedge rst_rst_n_i)
begin : clocked_proc
if (rst_rst_n_i == 1'b 0)
begin
current_state <= RES;
 
// Default Reset Values
d_o_cld <= 8'h 00;
rd_o_cld <= 1'b 0;
sync_o_cld <= 1'b 0;
wr_n_o_cld <= 1'b 1;
wr_o_cld <= 1'b 0;
reg_F <= 8'b 00000100;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_rb_in <= 2'b 00;
reg_sel_rb_out <= 2'b 00;
reg_sel_reg <= 2'b 00;
reg_sel_sp_as <= 1'b 0;
reg_sel_sp_in <= 1'b 0;
sig_PC <= 16'h 0000;
zw_REG_NMI <= 1'b 0;
zw_REG_OP <= 8'h 00;
zw_b1 <= 8'h 00;
zw_b2 <= 8'h 00;
zw_b3 <= 8'h 00;
zw_b4 <= 8'h 00;
zw_so <= 1'b 0;
end
else
begin
current_state <= next_state;
 
// Default Assignment To Internals
reg_F <= {reg_F[7], (zw_so | reg_F[6]), reg_F[5:0]};
reg_sel_pc_in <= reg_sel_pc_in;
reg_sel_pc_val <= reg_sel_pc_val;
reg_sel_rb_in <= reg_sel_rb_in;
reg_sel_rb_out <= reg_sel_rb_out;
reg_sel_reg <= reg_sel_reg;
reg_sel_sp_as <= reg_sel_sp_as;
reg_sel_sp_in <= reg_sel_sp_in;
sig_PC <= sig_PC;
zw_REG_NMI <= zw_REG_NMI | nmi_i;
zw_REG_OP <= zw_REG_OP;
zw_b1 <= zw_b1;
zw_b2 <= zw_b2;
zw_b3 <= zw_b3;
zw_b4 <= zw_b4;
zw_so <= (zw_so | ~so_n_i) & ~reg_F[6];
d_o_cld <= sig_D_OUT;
rd_o_cld <= sig_RD;
sync_o_cld <= sig_SYNC;
wr_n_o_cld <= sig_RWn;
wr_o_cld <= sig_WR;
 
// Combined Actions
case (current_state)
FETCH:
begin
zw_REG_OP <= d_i;
if (nmi_i == 1'b 1 & rdy_i == 1'b 1)
begin
sig_PC <= adr_nxt_pc_i;
zw_REG_NMI <= 1'b 0;
end
else if (irq_n_i == 1'b 0 & reg_F[2] == 1'b 0 &
rdy_i == 1'b 1 )
begin
sig_PC <= adr_nxt_pc_i;
end
else if ((d_i == 8'h 69 | d_i == 8'h 65 |
d_i == 8'h 75 | d_i == 8'h 6D |
d_i == 8'h 7D | d_i == 8'h 79 |
d_i == 8'h 61 | d_i == 8'h 71) &
rdy_i == 1'b 1 )
begin
sig_PC <= adr_nxt_pc_i;
reg_sel_reg <= 2'b 00;
reg_sel_rb_in <= 2'b 11;
zw_b1[0] <= reg_F[7];
end
else if ((d_i == 8'h 06 | d_i == 8'h 16 |
d_i == 8'h 0E | d_i == 8'h 1E) &
rdy_i == 1'b 1 )
begin
sig_PC <= adr_nxt_pc_i;
end
else if ((d_i == 8'h 90 | d_i == 8'h B0 |
d_i == 8'h F0 | d_i == 8'h 30 |
d_i == 8'h D0 | d_i == 8'h 10 |
d_i == 8'h 50 | d_i == 8'h 70) &
rdy_i == 1'b 1 )
begin
sig_PC <= adr_nxt_pc_i;
zw_b3 <= adr_nxt_pc_i[15:8];
end
else if ((d_i == 8'h 24 | d_i == 8'h 2C) &
rdy_i == 1'b 1 )
begin
sig_PC <= adr_nxt_pc_i;
end
else if (d_i == 8'h 00 & rdy_i == 1'b 1 )
begin
sig_PC <= adr_nxt_pc_i;
end
else if (d_i == 8'h 18 & rdy_i == 1'b 1 )
;
else if (d_i == 8'h D8 & rdy_i == 1'b 1 )
;
else if (d_i == 8'h 58 & rdy_i == 1'b 1 )
;
else if (d_i == 8'h B8 & rdy_i == 1'b 1 )
;
else if ((d_i == 8'h E0 | d_i == 8'h E4 |
d_i == 8'h EC) & rdy_i == 1'b 1 )
begin
reg_sel_rb_out <= 2'b 01;
sig_PC <= adr_nxt_pc_i;
end
else if ((d_i == 8'h C0 | d_i == 8'h C4 |
d_i == 8'h CC) & rdy_i == 1'b 1 )
begin
reg_sel_rb_out <= 2'b 10;
sig_PC <= adr_nxt_pc_i;
end
else if ((d_i == 8'h C6 | d_i == 8'h D6 |
d_i == 8'h CE | d_i == 8'h DE) &
rdy_i == 1'b 1 )
begin
zw_b4 <= 8'h FF;
sig_PC <= adr_nxt_pc_i;
end
else if (d_i == 8'h CA & rdy_i == 1'b 1 )
begin
reg_sel_rb_out <= 2'b 01;
reg_sel_reg <= 2'b 01;
reg_sel_rb_in <= 2'b 11;
zw_b4 <= 8'h FF;
end
else if (d_i == 8'h 88 & rdy_i == 1'b 1 )
begin
reg_sel_rb_out <= 2'b 10;
reg_sel_reg <= 2'b 10;
reg_sel_rb_in <= 2'b 11;
zw_b4 <= 8'h FF;
end
else if ((d_i == 8'h 49 | d_i == 8'h 45 |
d_i == 8'h 55 | d_i == 8'h 4D |
d_i == 8'h 5D | d_i == 8'h 59 |
d_i == 8'h 41 | d_i == 8'h 51 |
d_i == 8'h 09 | d_i == 8'h 05 |
d_i == 8'h 15 | d_i == 8'h 0D |
d_i == 8'h 1D | d_i == 8'h 19 |
d_i == 8'h 01 | d_i == 8'h 11 |
d_i == 8'h 29 | d_i == 8'h 25 |
d_i == 8'h 35 | d_i == 8'h 2D |
d_i == 8'h 3D | d_i == 8'h 39 |
d_i == 8'h 21 | d_i == 8'h 31 |
d_i == 8'h C9 | d_i == 8'h C5 |
d_i == 8'h D5 | d_i == 8'h CD |
d_i == 8'h DD | d_i == 8'h D9 |
d_i == 8'h C1 | d_i == 8'h D1) &
rdy_i == 1'b 1 )
begin
reg_sel_rb_out <= 2'b 00;
reg_sel_reg <= 2'b 00;
reg_sel_rb_in <= 2'b 11;
sig_PC <= adr_nxt_pc_i;
end
else if ((d_i == 8'h E6 | d_i == 8'h F6 |
d_i == 8'h EE | d_i == 8'h FE) &
rdy_i == 1'b 1 )
begin
zw_b4 <= 8'h 01;
sig_PC <= adr_nxt_pc_i;
end
else if (d_i == 8'h E8 & rdy_i == 1'b 1 )
begin
reg_sel_rb_out <= 2'b 01;
reg_sel_reg <= 2'b 01;
reg_sel_rb_in <= 2'b 11;
zw_b4 <= 8'h 01;
end
else if (d_i == 8'h C8 & rdy_i == 1'b 1 )
begin
reg_sel_rb_out <= 2'b 10;
reg_sel_reg <= 2'b 10;
reg_sel_rb_in <= 2'b 11;
zw_b4 <= 8'h 01;
end
else if ((d_i == 8'h 4C | d_i == 8'h 6C) &
rdy_i == 1'b 1 )
begin
sig_PC <= adr_nxt_pc_i;
end
else if (d_i == 8'h 20 & rdy_i == 1'b 1 )
begin
sig_PC <= adr_nxt_pc_i;
end
else if ((d_i == 8'h A9 | d_i == 8'h A5 |
d_i == 8'h B5 | d_i == 8'h AD |
d_i == 8'h BD | d_i == 8'h B9 |
d_i == 8'h A1 | d_i == 8'h B1) &
rdy_i == 1'b 1 )
begin
reg_sel_reg <= 2'b 00;
reg_sel_rb_in <= 2'b 11;
sig_PC <= adr_nxt_pc_i;
end
else if ((d_i == 8'h A2 | d_i == 8'h A6 |
d_i == 8'h B6 | d_i == 8'h AE |
d_i == 8'h BE) & rdy_i == 1'b 1 )
begin
reg_sel_reg <= 2'b 01;
reg_sel_rb_in <= 2'b 11;
sig_PC <= adr_nxt_pc_i;
end
else if ((d_i == 8'h A0 | d_i == 8'h A4 |
d_i == 8'h B4 | d_i == 8'h AC |
d_i == 8'h BC) & rdy_i == 1'b 1 )
begin
reg_sel_reg <= 2'b 10;
reg_sel_rb_in <= 2'b 11;
sig_PC <= adr_nxt_pc_i;
end
else if ((d_i == 8'h 46 | d_i == 8'h 56 |
d_i == 8'h 4E | d_i == 8'h 5E) &
rdy_i == 1'b 1 )
begin
sig_PC <= adr_nxt_pc_i;
end
else if (d_i == 8'h EA & rdy_i == 1'b 1 )
;
else if (d_i == 8'h 48 & rdy_i == 1'b 1 )
begin
sig_PC <= adr_nxt_pc_i;
end
else if (d_i == 8'h 08 & rdy_i == 1'b 1 )
begin
sig_PC <= adr_nxt_pc_i;
end
else if (d_i == 8'h 68 & rdy_i == 1'b 1 )
begin
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 0;
reg_sel_reg <= 2'b 00;
reg_sel_rb_in <= 2'b 11;
end
else if (d_i == 8'h 28 & rdy_i == 1'b 1 )
begin
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 0;
end
else if ((d_i == 8'h 26 | d_i == 8'h 36 |
d_i == 8'h 2E | d_i == 8'h 3E) &
rdy_i == 1'b 1 )
begin
sig_PC <= adr_nxt_pc_i;
end
else if ((d_i == 8'h 66 | d_i == 8'h 76 |
d_i == 8'h 6E | d_i == 8'h 7E) &
rdy_i == 1'b 1 )
begin
sig_PC <= adr_nxt_pc_i;
end
else if (d_i == 8'h 40 & rdy_i == 1'b 1 )
begin
sig_PC <= adr_nxt_pc_i;
end
else if (d_i == 8'h 60 & rdy_i == 1'b 1 )
begin
sig_PC <= adr_nxt_pc_i;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 0;
end
else if ((d_i == 8'h E9 | d_i == 8'h E5 |
d_i == 8'h F5 | d_i == 8'h ED |
d_i == 8'h FD | d_i == 8'h F9 |
d_i == 8'h E1 | d_i == 8'h F1) &
rdy_i == 1'b 1 )
begin
sig_PC <= adr_nxt_pc_i;
reg_sel_reg <= 2'b 00;
reg_sel_rb_in <= 2'b 11;
zw_b1[0] <= reg_F[7];
end
else if (d_i == 8'h 38 & rdy_i == 1'b 1 )
;
else if (d_i == 8'h F8 & rdy_i == 1'b 1 )
;
else if (d_i == 8'h 78 & rdy_i == 1'b 1 )
;
else if ((d_i == 8'h 85 | d_i == 8'h 95 |
d_i == 8'h 8D | d_i == 8'h 9D |
d_i == 8'h 99 | d_i == 8'h 81 |
d_i == 8'h 91) & rdy_i == 1'b 1 )
begin
reg_sel_rb_out <= 2'b 00;
sig_PC <= adr_nxt_pc_i;
end
else if ((d_i == 8'h 86 | d_i == 8'h 96 |
d_i == 8'h 8E) & rdy_i == 1'b 1 )
begin
reg_sel_rb_out <= 2'b 01;
sig_PC <= adr_nxt_pc_i;
end
else if ((d_i == 8'h 84 | d_i == 8'h 94 |
d_i == 8'h 8C) & rdy_i == 1'b 1 )
begin
reg_sel_rb_out <= 2'b 10;
sig_PC <= adr_nxt_pc_i;
end
else if (d_i == 8'h AA & rdy_i == 1'b 1 )
begin
reg_sel_rb_out <= 2'b 00;
reg_sel_reg <= 2'b 01;
reg_sel_rb_in <= 2'b 00;
reg_sel_sp_in <= 1'b 1;
reg_sel_sp_as <= 1'b 0;
end
else if (d_i == 8'h 0A & rdy_i == 1'b 1 )
begin
reg_sel_rb_out <= 2'b 00;
reg_sel_reg <= 2'b 00;
reg_sel_rb_in <= 2'b 11;
end
else if (d_i == 8'h 4A & rdy_i == 1'b 1 )
begin
reg_sel_rb_out <= 2'b 00;
reg_sel_reg <= 2'b 00;
reg_sel_rb_in <= 2'b 11;
end
else if (d_i == 8'h 2A & rdy_i == 1'b 1 )
begin
reg_sel_rb_out <= 2'b 00;
reg_sel_reg <= 2'b 00;
reg_sel_rb_in <= 2'b 11;
end
else if (d_i == 8'h 6A & rdy_i == 1'b 1 )
begin
reg_sel_rb_out <= 2'b 00;
reg_sel_reg <= 2'b 00;
reg_sel_rb_in <= 2'b 11;
end
else if (d_i == 8'h A8 & rdy_i == 1'b 1 )
begin
reg_sel_rb_out <= 2'b 00;
reg_sel_reg <= 2'b 10;
reg_sel_rb_in <= 2'b 00;
reg_sel_sp_in <= 1'b 1;
reg_sel_sp_as <= 1'b 0;
end
else if (d_i == 8'h 98 & rdy_i == 1'b 1 )
begin
reg_sel_rb_out <= 2'b 10;
reg_sel_reg <= 2'b 00;
reg_sel_rb_in <= 2'b 01;
reg_sel_sp_in <= 1'b 1;
reg_sel_sp_as <= 1'b 0;
end
else if (d_i == 8'h BA & rdy_i == 1'b 1 )
begin
reg_sel_rb_out <= 2'b 01;
reg_sel_reg <= 2'b 01;
reg_sel_rb_in <= 2'b 11;
reg_sel_sp_in <= 1'b 1;
reg_sel_sp_as <= 1'b 0;
end
else if (d_i == 8'h 8A & rdy_i == 1'b 1 )
begin
reg_sel_rb_out <= 2'b 01;
reg_sel_reg <= 2'b 00;
reg_sel_rb_in <= 2'b 10;
reg_sel_sp_in <= 1'b 1;
reg_sel_sp_as <= 1'b 0;
end
else if (d_i == 8'h 9A & rdy_i == 1'b 1 )
begin
reg_sel_rb_out <= 2'b 01;
reg_sel_reg <= 2'b 11;
reg_sel_rb_in <= 2'b 11;
reg_sel_sp_in <= 1'b 1;
reg_sel_sp_as <= 1'b 0;
end
end
s1:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s2:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[0] <= 1'b 1;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s5:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[3] <= 1'b 1;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s3:
begin
sig_PC <= adr_pc_i;
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[2] <= 1'b 1;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s4:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 9A)
begin
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h BA )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s12:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[0] <= 1'b 0;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s16:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[3] <= 1'b 0;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s17:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[2] <= 1'b 0;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s24:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[6] <= 1'b 0;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s25:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s271:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 4C)
begin
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 11;
zw_b1 <= d_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 6C )
begin
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 00;
zw_b1 <= d_i;
end
end
s273:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
zw_b2 <= d_i;
end
end
s304:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {zw_b2, adr_pc_i[7:0]};
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 11;
zw_b1 <= d_i;
end
end
s307:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s177:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 85 |
zw_REG_OP == 8'h 86 | zw_REG_OP == 8'h 84))
begin
sig_PC <= {8'h 00, d_i};
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 95 |
zw_REG_OP == 8'h 94) )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 8D |
zw_REG_OP == 8'h 8E | zw_REG_OP == 8'h 8C) )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 9D )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 99 )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 91 )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 81 )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 96 )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
end
s180:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
end
end
s181:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, zw_b1};
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
end
s182:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
end
end
s183:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
end
end
s184:
begin
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
s185:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, zw_b1};
end
end
s186:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, zw_b1};
end
end
s187:
begin
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
s188:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, d_alu_i};
zw_b1 <= d_i;
end
end
s189:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
end
end
s190:
begin
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
s191:
begin
sig_PC <= {zw_b3, zw_b1};
end
s192:
begin
sig_PC <= {d_i, zw_b1};
end
s193:
begin
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
s377:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
end
end
s381:
begin
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
s378:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
end
end
s382:
begin
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
s383:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
end
end
s384:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s385:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
end
end
s386:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F <= d_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s387:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
end
end
s388:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
end
end
s389:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
reg_F <= d_i;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 11;
end
end
s391:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
end
end
s392:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s390:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
end
end
s393:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
end
end
s394:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 00;
end
end
s395:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
end
end
s396:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s397:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
end
end
s399:
begin
sig_PC <= adr_sp_i;
end
s400:
begin
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 11;
end
s401:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1[7:0]};
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s526:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
end
end
s527:
begin
sig_PC <= adr_sp_i;
end
s528:
begin
sig_PC <= adr_sp_i;
end
s529:
begin
sig_PC <= 16'h FFFE;
end
s530:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
reg_F[2] <= 1'b 1;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s531:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= 16'h FFFF;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 11;
zw_b1 <= d_i;
end
end
s544:
begin
sig_PC <= adr_sp_i;
end
s545:
begin
sig_PC <= adr_sp_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
end
s546:
begin
sig_PC <= adr_pc_i;
end
s547:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
zw_b1 <= d_i;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 11;
end
end
s549:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s550:
begin
sig_PC <= adr_sp_i;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 00;
end
s404:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[0] <= q_a_i[7];
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s556:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[0] <= q_a_i[0];
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s557:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[0] <= q_a_i[7];
reg_F[0] <= q_a_i[7];
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s579:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[0] <= q_a_i[0];
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s201:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A5 |
zw_REG_OP == 8'h A6 | zw_REG_OP == 8'h A4 |
zw_REG_OP == 8'h 45 | zw_REG_OP == 8'h 05 |
zw_REG_OP == 8'h 25 | zw_REG_OP == 8'h C5 |
zw_REG_OP == 8'h E4 | zw_REG_OP == 8'h C4))
begin
sig_PC <= {8'h 00, d_i};
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 |
zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 |
zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 |
zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 |
zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) &
(zw_REG_OP == 8'h 09 | zw_REG_OP == 8'h 05 |
zw_REG_OP == 8'h 15 | zw_REG_OP == 8'h 0D |
zw_REG_OP == 8'h 1D | zw_REG_OP == 8'h 19 |
zw_REG_OP == 8'h 01 | zw_REG_OP == 8'h 11) )
begin
sig_PC <= adr_nxt_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 |
zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 |
zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 |
zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 |
zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) &
(zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 45 |
zw_REG_OP == 8'h 55 | zw_REG_OP == 8'h 4D |
zw_REG_OP == 8'h 5D | zw_REG_OP == 8'h 59 |
zw_REG_OP == 8'h 41 | zw_REG_OP == 8'h 51) )
begin
sig_PC <= adr_nxt_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 |
zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 |
zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 |
zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 |
zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) &
(zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h 25 |
zw_REG_OP == 8'h 35 | zw_REG_OP == 8'h 2D |
zw_REG_OP == 8'h 3D | zw_REG_OP == 8'h 39 |
zw_REG_OP == 8'h 21 | zw_REG_OP == 8'h 31) )
begin
sig_PC <= adr_nxt_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 |
zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 |
zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 |
zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 |
zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) &
(zw_REG_OP == 8'h C9 | zw_REG_OP == 8'h C5 |
zw_REG_OP == 8'h D5 | zw_REG_OP == 8'h CD |
zw_REG_OP == 8'h DD | zw_REG_OP == 8'h D9 |
zw_REG_OP == 8'h C1 | zw_REG_OP == 8'h D1 |
zw_REG_OP == 8'h C0 | zw_REG_OP == 8'h E0 |
zw_REG_OP == 8'h C4 | zw_REG_OP == 8'h E4 |
zw_REG_OP == 8'h CC | zw_REG_OP == 8'h EC) )
begin
sig_PC <= adr_nxt_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[0] <= zw_ALU[8];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 |
zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 |
zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 |
zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 |
zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) )
begin
sig_PC <= adr_nxt_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h B5 |
zw_REG_OP == 8'h B4 | zw_REG_OP == 8'h 55 |
zw_REG_OP == 8'h 15 | zw_REG_OP == 8'h 35 |
zw_REG_OP == 8'h D5) )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h AD |
zw_REG_OP == 8'h AE | zw_REG_OP == 8'h AC |
zw_REG_OP == 8'h 4D | zw_REG_OP == 8'h 0D |
zw_REG_OP == 8'h 2D | zw_REG_OP == 8'h CD |
zw_REG_OP == 8'h EC | zw_REG_OP == 8'h CC) )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h BD |
zw_REG_OP == 8'h BC | zw_REG_OP == 8'h 5D |
zw_REG_OP == 8'h 1D | zw_REG_OP == 8'h 3D |
zw_REG_OP == 8'h DD) )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h B9 |
zw_REG_OP == 8'h BE | zw_REG_OP == 8'h 59 |
zw_REG_OP == 8'h 19 | zw_REG_OP == 8'h 39 |
zw_REG_OP == 8'h D9) )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h B1 |
zw_REG_OP == 8'h 51 | zw_REG_OP == 8'h 11 |
zw_REG_OP == 8'h 31 | zw_REG_OP == 8'h D1) )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A1 |
zw_REG_OP == 8'h 41 | zw_REG_OP == 8'h 01 |
zw_REG_OP == 8'h 21 | zw_REG_OP == 8'h C1) )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h B6 )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
end
s202:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
end
end
s210:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
end
end
s211:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
end
end
s215:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, zw_b1};
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
end
s217:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, zw_b1};
end
end
s218:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, zw_b1};
end
end
s222:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, d_alu_i};
zw_b1 <= d_i;
end
end
s223:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
end
end
s224:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 09 |
zw_REG_OP == 8'h 05 | zw_REG_OP == 8'h 15 |
zw_REG_OP == 8'h 0D | zw_REG_OP == 8'h 1D |
zw_REG_OP == 8'h 19 | zw_REG_OP == 8'h 01 |
zw_REG_OP == 8'h 11))
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 49 |
zw_REG_OP == 8'h 45 | zw_REG_OP == 8'h 55 |
zw_REG_OP == 8'h 4D | zw_REG_OP == 8'h 5D |
zw_REG_OP == 8'h 59 | zw_REG_OP == 8'h 41 |
zw_REG_OP == 8'h 51) )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 29 |
zw_REG_OP == 8'h 25 | zw_REG_OP == 8'h 35 |
zw_REG_OP == 8'h 2D | zw_REG_OP == 8'h 3D |
zw_REG_OP == 8'h 39 | zw_REG_OP == 8'h 21 |
zw_REG_OP == 8'h 31) )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h C9 |
zw_REG_OP == 8'h C5 | zw_REG_OP == 8'h D5 |
zw_REG_OP == 8'h CD | zw_REG_OP == 8'h DD |
zw_REG_OP == 8'h D9 | zw_REG_OP == 8'h C1 |
zw_REG_OP == 8'h D1 | zw_REG_OP == 8'h C0 |
zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C4 |
zw_REG_OP == 8'h E4 | zw_REG_OP == 8'h CC |
zw_REG_OP == 8'h EC) )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[0] <= zw_ALU[8];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s225:
begin
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 09 | zw_REG_OP == 8'h 05 |
zw_REG_OP == 8'h 15 | zw_REG_OP == 8'h 0D |
zw_REG_OP == 8'h 1D | zw_REG_OP == 8'h 19 |
zw_REG_OP == 8'h 01 | zw_REG_OP == 8'h 11))
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 45 |
zw_REG_OP == 8'h 55 | zw_REG_OP == 8'h 4D |
zw_REG_OP == 8'h 5D | zw_REG_OP == 8'h 59 |
zw_REG_OP == 8'h 41 | zw_REG_OP == 8'h 51) )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h 25 |
zw_REG_OP == 8'h 35 | zw_REG_OP == 8'h 2D |
zw_REG_OP == 8'h 3D | zw_REG_OP == 8'h 39 |
zw_REG_OP == 8'h 21 | zw_REG_OP == 8'h 31) )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h C9 | zw_REG_OP == 8'h C5 |
zw_REG_OP == 8'h D5 | zw_REG_OP == 8'h CD |
zw_REG_OP == 8'h DD | zw_REG_OP == 8'h D9 |
zw_REG_OP == 8'h C1 | zw_REG_OP == 8'h D1 |
zw_REG_OP == 8'h C0 | zw_REG_OP == 8'h E0 |
zw_REG_OP == 8'h C4 | zw_REG_OP == 8'h E4 |
zw_REG_OP == 8'h CC | zw_REG_OP == 8'h EC) )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[0] <= zw_ALU[8];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 )
begin
sig_PC <= {zw_b3, zw_b1};
end
end
s226:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h C6 |
zw_REG_OP == 8'h E6))
begin
sig_PC <= {8'h 00, d_i};
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h D6 |
zw_REG_OP == 8'h F6) )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h CE |
zw_REG_OP == 8'h EE) )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h DE |
zw_REG_OP == 8'h FE) )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
end
s243:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
end
end
s244:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
end
end
s247:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, zw_b1};
end
end
s344:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {zw_b3, zw_b1};
end
end
s343:
begin
if (rdy_i == 1'b 1)
begin
zw_b1 <= d_alu_i;
end
end
s251:
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
s351:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 24)
begin
sig_PC <= {8'h 00, d_i};
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 2C )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end
end
s361:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[7] <= d_i[7];
reg_F[6] <= d_i[6];
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s360:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
end
end
s403:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 1E |
zw_REG_OP == 8'h 7E | zw_REG_OP == 8'h 3E |
zw_REG_OP == 8'h 5E))
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 06 |
zw_REG_OP == 8'h 66 | zw_REG_OP == 8'h 26 |
zw_REG_OP == 8'h 46) )
begin
sig_PC <= {8'h 00, d_i};
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 16 |
zw_REG_OP == 8'h 76 | zw_REG_OP == 8'h 36 |
zw_REG_OP == 8'h 56) )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 0E |
zw_REG_OP == 8'h 6E | zw_REG_OP == 8'h 2E |
zw_REG_OP == 8'h 4E) )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end
end
s406:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
end
end
s407:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
end
end
s409:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, zw_b1};
end
end
s412:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {zw_b3, zw_b1};
end
end
s416:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 06 |
zw_REG_OP == 8'h 16 | zw_REG_OP == 8'h 0E |
zw_REG_OP == 8'h 1E))
begin
zw_b1 <= {d_i[6:0], 1'b 0};
zw_b2[0] <= d_i[7];
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 46 |
zw_REG_OP == 8'h 56 | zw_REG_OP == 8'h 4E |
zw_REG_OP == 8'h 5E) )
begin
zw_b1 <= {1'b 0, d_i[7:1]};
zw_b2[0] <= d_i[0];
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 26 |
zw_REG_OP == 8'h 36 | zw_REG_OP == 8'h 2E |
zw_REG_OP == 8'h 3E) )
begin
zw_b1 <= {d_i[6:0], reg_F[0]};
zw_b2[0] <= d_i[7];
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 66 |
zw_REG_OP == 8'h 76 | zw_REG_OP == 8'h 6E |
zw_REG_OP == 8'h 7E) )
begin
zw_b1 <= {reg_F[0], d_i[7:1]};
zw_b2[0] <= d_i[0];
end
end
s418:
begin
sig_PC <= adr_pc_i;
reg_F[0] <= zw_b2[0];
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
s510:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 65)
begin
sig_PC <= {8'h 00, d_i};
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 69 &
reg_F[3] == 1'b 0 )
begin
sig_PC <= adr_nxt_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU[8];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 75 )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 6D )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 7D )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 79 )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 71 )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 61 )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 69 &
reg_F[3] == 1'b 1 )
begin
sig_PC <= adr_nxt_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU4[4];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s553:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
end
end
s555:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
end
end
s558:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, zw_b1};
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
end
s560:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, zw_b1};
end
end
s561:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, zw_b1};
end
end
s563:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, d_alu_i};
zw_b1 <= d_i;
end
end
s564:
begin
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 0)
begin
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU[8];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 1 )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU4[4];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 )
begin
sig_PC <= {zw_b3, zw_b1};
end
end
s565:
begin
if (rdy_i == 1'b 1 & reg_F[3] == 1'b 0)
begin
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU[8];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & reg_F[3] == 1'b 1 )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU4[4];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s566:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
end
end
s266:
begin
if (rdy_i == 1'b 1 & (reg_F[0] == 1'b 1 &
zw_REG_OP == 8'h 90 | reg_F[0] == 1'b 0 &
zw_REG_OP == 8'h B0 | reg_F[1] == 1'b 0 &
zw_REG_OP == 8'h F0 | reg_F[7] == 1'b 0 &
zw_REG_OP == 8'h 30 | reg_F[1] == 1'b 1 &
zw_REG_OP == 8'h D0 | reg_F[7] == 1'b 1 &
zw_REG_OP == 8'h 10 | reg_F[6] == 1'b 1 &
zw_REG_OP == 8'h 50 | reg_F[6] == 1'b 0 &
zw_REG_OP == 8'h 70))
begin
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 )
begin
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 10;
zw_b2 <= d_i;
end
end
s301:
begin
if (rdy_i == 1'b 1 & zw_b3 == adr_nxt_pc_i[15:8])
begin
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 )
begin
sig_PC <= {zw_b3, adr_nxt_pc_i[7:0]};
end
end
s302:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
RES:
begin
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
s511:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E5)
begin
sig_PC <= {8'h 00, d_i};
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E9 &
reg_F[3] == 1'b 0 )
begin
sig_PC <= adr_nxt_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU[8];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F5 )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h ED )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h FD )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F9 )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F1 )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E1 )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E9 &
reg_F[3] == 1'b 1 )
begin
sig_PC <= adr_nxt_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU2[4];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s559:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
end
end
s562:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
end
end
s567:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
end
end
s568:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, zw_b1};
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
end
s569:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, zw_b1};
end
end
s570:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, zw_b1};
end
end
s571:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
end
end
s572:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, d_alu_i};
zw_b1 <= d_i;
end
end
s573:
begin
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 0)
begin
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU[8];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 1 )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU2[4];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 )
begin
sig_PC <= {zw_b3, zw_b1};
end
end
s574:
begin
if (rdy_i == 1'b 1 & reg_F[3] == 1'b 0)
begin
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU[8];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & reg_F[3] == 1'b 1 )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU2[4];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s548:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
end
end
s551:
begin
sig_PC <= adr_sp_i;
end
s552:
begin
sig_PC <= adr_sp_i;
end
s575:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= 16'h FFFF;
zw_b1 <= d_i;
end
end
s576:
begin
sig_PC <= 16'h FFFE;
end
s577:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
reg_F[2] <= 1'b 1;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s532:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
end
end
s533:
begin
sig_PC <= adr_sp_i;
end
s534:
begin
sig_PC <= adr_sp_i;
end
s535:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= 16'h FFFB;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 11;
zw_b1 <= d_i;
end
end
s536:
begin
sig_PC <= 16'h FFFA;
end
s537:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
default:
;
endcase
end
end
 
// ---------------------------------------------------------------
 
// ---------------------------------------------------------------
 
always @(adr_nxt_pc_i or current_state or d_i or irq_n_i or nmi_i
or rdy_i or reg_F or zw_REG_OP or zw_b2 or zw_b3)
begin : nextstate_proc
case (current_state)
FETCH:
begin
if (nmi_i == 1'b 1 & rdy_i == 1'b 1)
begin
next_state <= s532;
end
else if (irq_n_i == 1'b 0 & reg_F[2] == 1'b 0 &
rdy_i == 1'b 1 )
begin
next_state <= s548;
end
else if ((d_i == 8'h 69 | d_i == 8'h 65 |
d_i == 8'h 75 | d_i == 8'h 6D |
d_i == 8'h 7D | d_i == 8'h 79 |
d_i == 8'h 61 | d_i == 8'h 71) &
rdy_i == 1'b 1 )
begin
next_state <= s510;
end
else if ((d_i == 8'h 06 | d_i == 8'h 16 |
d_i == 8'h 0E | d_i == 8'h 1E) &
rdy_i == 1'b 1 )
begin
next_state <= s403;
end
else if ((d_i == 8'h 90 | d_i == 8'h B0 |
d_i == 8'h F0 | d_i == 8'h 30 |
d_i == 8'h D0 | d_i == 8'h 10 |
d_i == 8'h 50 | d_i == 8'h 70) &
rdy_i == 1'b 1 )
begin
next_state <= s266;
end
else if ((d_i == 8'h 24 | d_i == 8'h 2C) &
rdy_i == 1'b 1 )
begin
next_state <= s351;
end
else if (d_i == 8'h 00 & rdy_i == 1'b 1 )
begin
next_state <= s526;
end
else if (d_i == 8'h 18 & rdy_i == 1'b 1 )
begin
next_state <= s12;
end
else if (d_i == 8'h D8 & rdy_i == 1'b 1 )
begin
next_state <= s16;
end
else if (d_i == 8'h 58 & rdy_i == 1'b 1 )
begin
next_state <= s17;
end
else if (d_i == 8'h B8 & rdy_i == 1'b 1 )
begin
next_state <= s24;
end
else if ((d_i == 8'h E0 | d_i == 8'h E4 |
d_i == 8'h EC) & rdy_i == 1'b 1 )
begin
next_state <= s201;
end
else if ((d_i == 8'h C0 | d_i == 8'h C4 |
d_i == 8'h CC) & rdy_i == 1'b 1 )
begin
next_state <= s201;
end
else if ((d_i == 8'h C6 | d_i == 8'h D6 |
d_i == 8'h CE | d_i == 8'h DE) &
rdy_i == 1'b 1 )
begin
next_state <= s226;
end
else if (d_i == 8'h CA & rdy_i == 1'b 1 )
begin
next_state <= s25;
end
else if (d_i == 8'h 88 & rdy_i == 1'b 1 )
begin
next_state <= s25;
end
else if ((d_i == 8'h 49 | d_i == 8'h 45 |
d_i == 8'h 55 | d_i == 8'h 4D |
d_i == 8'h 5D | d_i == 8'h 59 |
d_i == 8'h 41 | d_i == 8'h 51 |
d_i == 8'h 09 | d_i == 8'h 05 |
d_i == 8'h 15 | d_i == 8'h 0D |
d_i == 8'h 1D | d_i == 8'h 19 |
d_i == 8'h 01 | d_i == 8'h 11 |
d_i == 8'h 29 | d_i == 8'h 25 |
d_i == 8'h 35 | d_i == 8'h 2D |
d_i == 8'h 3D | d_i == 8'h 39 |
d_i == 8'h 21 | d_i == 8'h 31 |
d_i == 8'h C9 | d_i == 8'h C5 |
d_i == 8'h D5 | d_i == 8'h CD |
d_i == 8'h DD | d_i == 8'h D9 |
d_i == 8'h C1 | d_i == 8'h D1) &
rdy_i == 1'b 1 )
begin
next_state <= s201;
end
else if ((d_i == 8'h E6 | d_i == 8'h F6 |
d_i == 8'h EE | d_i == 8'h FE) &
rdy_i == 1'b 1 )
begin
next_state <= s226;
end
else if (d_i == 8'h E8 & rdy_i == 1'b 1 )
begin
next_state <= s25;
end
else if (d_i == 8'h C8 & rdy_i == 1'b 1 )
begin
next_state <= s25;
end
else if ((d_i == 8'h 4C | d_i == 8'h 6C) &
rdy_i == 1'b 1 )
begin
next_state <= s271;
end
else if (d_i == 8'h 20 & rdy_i == 1'b 1 )
begin
next_state <= s397;
end
else if ((d_i == 8'h A9 | d_i == 8'h A5 |
d_i == 8'h B5 | d_i == 8'h AD |
d_i == 8'h BD | d_i == 8'h B9 |
d_i == 8'h A1 | d_i == 8'h B1) &
rdy_i == 1'b 1 )
begin
next_state <= s201;
end
else if ((d_i == 8'h A2 | d_i == 8'h A6 |
d_i == 8'h B6 | d_i == 8'h AE |
d_i == 8'h BE) & rdy_i == 1'b 1 )
begin
next_state <= s201;
end
else if ((d_i == 8'h A0 | d_i == 8'h A4 |
d_i == 8'h B4 | d_i == 8'h AC |
d_i == 8'h BC) & rdy_i == 1'b 1 )
begin
next_state <= s201;
end
else if ((d_i == 8'h 46 | d_i == 8'h 56 |
d_i == 8'h 4E | d_i == 8'h 5E) &
rdy_i == 1'b 1 )
begin
next_state <= s403;
end
else if (d_i == 8'h EA & rdy_i == 1'b 1 )
begin
next_state <= s1;
end
else if (d_i == 8'h 48 & rdy_i == 1'b 1 )
begin
next_state <= s377;
end
else if (d_i == 8'h 08 & rdy_i == 1'b 1 )
begin
next_state <= s378;
end
else if (d_i == 8'h 68 & rdy_i == 1'b 1 )
begin
next_state <= s379;
end
else if (d_i == 8'h 28 & rdy_i == 1'b 1 )
begin
next_state <= s380;
end
else if ((d_i == 8'h 26 | d_i == 8'h 36 |
d_i == 8'h 2E | d_i == 8'h 3E) &
rdy_i == 1'b 1 )
begin
next_state <= s403;
end
else if ((d_i == 8'h 66 | d_i == 8'h 76 |
d_i == 8'h 6E | d_i == 8'h 7E) &
rdy_i == 1'b 1 )
begin
next_state <= s403;
end
else if (d_i == 8'h 40 & rdy_i == 1'b 1 )
begin
next_state <= s387;
end
else if (d_i == 8'h 60 & rdy_i == 1'b 1 )
begin
next_state <= s390;
end
else if ((d_i == 8'h E9 | d_i == 8'h E5 |
d_i == 8'h F5 | d_i == 8'h ED |
d_i == 8'h FD | d_i == 8'h F9 |
d_i == 8'h E1 | d_i == 8'h F1) &
rdy_i == 1'b 1 )
begin
next_state <= s511;
end
else if (d_i == 8'h 38 & rdy_i == 1'b 1 )
begin
next_state <= s2;
end
else if (d_i == 8'h F8 & rdy_i == 1'b 1 )
begin
next_state <= s5;
end
else if (d_i == 8'h 78 & rdy_i == 1'b 1 )
begin
next_state <= s3;
end
else if ((d_i == 8'h 85 | d_i == 8'h 95 |
d_i == 8'h 8D | d_i == 8'h 9D |
d_i == 8'h 99 | d_i == 8'h 81 |
d_i == 8'h 91) & rdy_i == 1'b 1 )
begin
next_state <= s177;
end
else if ((d_i == 8'h 86 | d_i == 8'h 96 |
d_i == 8'h 8E) & rdy_i == 1'b 1 )
begin
next_state <= s177;
end
else if ((d_i == 8'h 84 | d_i == 8'h 94 |
d_i == 8'h 8C) & rdy_i == 1'b 1 )
begin
next_state <= s177;
end
else if (d_i == 8'h AA & rdy_i == 1'b 1 )
begin
next_state <= s4;
end
else if (d_i == 8'h 0A & rdy_i == 1'b 1 )
begin
next_state <= s404;
end
else if (d_i == 8'h 4A & rdy_i == 1'b 1 )
begin
next_state <= s556;
end
else if (d_i == 8'h 2A & rdy_i == 1'b 1 )
begin
next_state <= s557;
end
else if (d_i == 8'h 6A & rdy_i == 1'b 1 )
begin
next_state <= s579;
end
else if (d_i == 8'h A8 & rdy_i == 1'b 1 )
begin
next_state <= s4;
end
else if (d_i == 8'h 98 & rdy_i == 1'b 1 )
begin
next_state <= s4;
end
else if (d_i == 8'h BA & rdy_i == 1'b 1 )
begin
next_state <= s4;
end
else if (d_i == 8'h 8A & rdy_i == 1'b 1 )
begin
next_state <= s4;
end
else if (d_i == 8'h 9A & rdy_i == 1'b 1 )
begin
next_state <= s4;
end
else if (rdy_i == 1'b 1 )
begin
next_state <= s1;
end
else
begin
next_state <= FETCH;
end
end
s1:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s1;
end
end
s2:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s2;
end
end
s5:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s5;
end
end
s3:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s3;
end
end
s4:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 9A)
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h BA )
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 )
begin
next_state <= FETCH;
end
else
begin
next_state <= s4;
end
end
s12:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s12;
end
end
s16:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s16;
end
end
s17:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s17;
end
end
s24:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s24;
end
end
s25:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s25;
end
end
s271:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 4C)
begin
next_state <= s307;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 6C )
begin
next_state <= s273;
end
else
begin
next_state <= s271;
end
end
s273:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s304;
end
else
begin
next_state <= s273;
end
end
s304:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s307;
end
else
begin
next_state <= s304;
end
end
s307:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s307;
end
end
s177:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 85 |
zw_REG_OP == 8'h 86 | zw_REG_OP == 8'h 84))
begin
next_state <= s184;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 95 |
zw_REG_OP == 8'h 94) )
begin
next_state <= s185;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 8D |
zw_REG_OP == 8'h 8E | zw_REG_OP == 8'h 8C) )
begin
next_state <= s183;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 9D )
begin
next_state <= s182;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 99 )
begin
next_state <= s180;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 91 )
begin
next_state <= s181;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 81 )
begin
next_state <= s186;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 96 )
begin
next_state <= s185;
end
else
begin
next_state <= s177;
end
end
s180:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s191;
end
else
begin
next_state <= s180;
end
end
s181:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s189;
end
else
begin
next_state <= s181;
end
end
s182:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s191;
end
else
begin
next_state <= s182;
end
end
s183:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s187;
end
else
begin
next_state <= s183;
end
end
s184:
begin
next_state <= FETCH;
end
s185:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s190;
end
else
begin
next_state <= s185;
end
end
s186:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s188;
end
else
begin
next_state <= s186;
end
end
s187:
begin
next_state <= FETCH;
end
s188:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s192;
end
else
begin
next_state <= s188;
end
end
s189:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s191;
end
else
begin
next_state <= s189;
end
end
s190:
begin
next_state <= FETCH;
end
s191:
begin
next_state <= s193;
end
s192:
begin
next_state <= s193;
end
s193:
begin
next_state <= FETCH;
end
s377:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s381;
end
else
begin
next_state <= s377;
end
end
s381:
begin
next_state <= FETCH;
end
s378:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s382;
end
else
begin
next_state <= s378;
end
end
s382:
begin
next_state <= FETCH;
end
s379:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s383;
end
else
begin
next_state <= s379;
end
end
s383:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s384;
end
else
begin
next_state <= s383;
end
end
s384:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s384;
end
end
s380:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s385;
end
else
begin
next_state <= s380;
end
end
s385:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s386;
end
else
begin
next_state <= s385;
end
end
s386:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s386;
end
end
s387:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s388;
end
else
begin
next_state <= s387;
end
end
s388:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s389;
end
else
begin
next_state <= s388;
end
end
s389:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s391;
end
else
begin
next_state <= s389;
end
end
s391:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s392;
end
else
begin
next_state <= s391;
end
end
s392:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s392;
end
end
s390:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s393;
end
else
begin
next_state <= s390;
end
end
s393:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s394;
end
else
begin
next_state <= s393;
end
end
s394:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s395;
end
else
begin
next_state <= s394;
end
end
s395:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s396;
end
else
begin
next_state <= s395;
end
end
s396:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s396;
end
end
s397:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s398;
end
else
begin
next_state <= s397;
end
end
s398:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s399;
end
else
begin
next_state <= s398;
end
end
s399:
begin
next_state <= s400;
end
s400:
begin
next_state <= s401;
end
s401:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s401;
end
end
s526:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s527;
end
else
begin
next_state <= s526;
end
end
s527:
begin
next_state <= s528;
end
s528:
begin
next_state <= s529;
end
s529:
begin
next_state <= s531;
end
s530:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s530;
end
end
s531:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s530;
end
else
begin
next_state <= s531;
end
end
s544:
begin
next_state <= s550;
end
s545:
begin
next_state <= s546;
end
s546:
begin
next_state <= s547;
end
s547:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s549;
end
else
begin
next_state <= s547;
end
end
s549:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s549;
end
end
s550:
begin
next_state <= s545;
end
s404:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s404;
end
end
s556:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s556;
end
end
s557:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s557;
end
end
s579:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s579;
end
end
s201:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A5 |
zw_REG_OP == 8'h A6 | zw_REG_OP == 8'h A4 |
zw_REG_OP == 8'h 45 | zw_REG_OP == 8'h 05 |
zw_REG_OP == 8'h 25 | zw_REG_OP == 8'h C5 |
zw_REG_OP == 8'h E4 | zw_REG_OP == 8'h C4))
begin
next_state <= s224;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 |
zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 |
zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 |
zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 |
zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) &
(zw_REG_OP == 8'h 09 | zw_REG_OP == 8'h 05 |
zw_REG_OP == 8'h 15 | zw_REG_OP == 8'h 0D |
zw_REG_OP == 8'h 1D | zw_REG_OP == 8'h 19 |
zw_REG_OP == 8'h 01 | zw_REG_OP == 8'h 11) )
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 |
zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 |
zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 |
zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 |
zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) &
(zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 45 |
zw_REG_OP == 8'h 55 | zw_REG_OP == 8'h 4D |
zw_REG_OP == 8'h 5D | zw_REG_OP == 8'h 59 |
zw_REG_OP == 8'h 41 | zw_REG_OP == 8'h 51) )
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 |
zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 |
zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 |
zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 |
zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) &
(zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h 25 |
zw_REG_OP == 8'h 35 | zw_REG_OP == 8'h 2D |
zw_REG_OP == 8'h 3D | zw_REG_OP == 8'h 39 |
zw_REG_OP == 8'h 21 | zw_REG_OP == 8'h 31) )
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 |
zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 |
zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 |
zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 |
zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) &
(zw_REG_OP == 8'h C9 | zw_REG_OP == 8'h C5 |
zw_REG_OP == 8'h D5 | zw_REG_OP == 8'h CD |
zw_REG_OP == 8'h DD | zw_REG_OP == 8'h D9 |
zw_REG_OP == 8'h C1 | zw_REG_OP == 8'h D1 |
zw_REG_OP == 8'h C0 | zw_REG_OP == 8'h E0 |
zw_REG_OP == 8'h C4 | zw_REG_OP == 8'h E4 |
zw_REG_OP == 8'h CC | zw_REG_OP == 8'h EC) )
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 |
zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 |
zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 |
zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 |
zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) )
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h B5 |
zw_REG_OP == 8'h B4 | zw_REG_OP == 8'h 55 |
zw_REG_OP == 8'h 15 | zw_REG_OP == 8'h 35 |
zw_REG_OP == 8'h D5) )
begin
next_state <= s217;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h AD |
zw_REG_OP == 8'h AE | zw_REG_OP == 8'h AC |
zw_REG_OP == 8'h 4D | zw_REG_OP == 8'h 0D |
zw_REG_OP == 8'h 2D | zw_REG_OP == 8'h CD |
zw_REG_OP == 8'h EC | zw_REG_OP == 8'h CC) )
begin
next_state <= s202;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h BD |
zw_REG_OP == 8'h BC | zw_REG_OP == 8'h 5D |
zw_REG_OP == 8'h 1D | zw_REG_OP == 8'h 3D |
zw_REG_OP == 8'h DD) )
begin
next_state <= s210;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h B9 |
zw_REG_OP == 8'h BE | zw_REG_OP == 8'h 59 |
zw_REG_OP == 8'h 19 | zw_REG_OP == 8'h 39 |
zw_REG_OP == 8'h D9) )
begin
next_state <= s211;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h B1 |
zw_REG_OP == 8'h 51 | zw_REG_OP == 8'h 11 |
zw_REG_OP == 8'h 31 | zw_REG_OP == 8'h D1) )
begin
next_state <= s215;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A1 |
zw_REG_OP == 8'h 41 | zw_REG_OP == 8'h 01 |
zw_REG_OP == 8'h 21 | zw_REG_OP == 8'h C1) )
begin
next_state <= s218;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h B6 )
begin
next_state <= s217;
end
else
begin
next_state <= s201;
end
end
s202:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s224;
end
else
begin
next_state <= s202;
end
end
s210:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s225;
end
else
begin
next_state <= s210;
end
end
s211:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s225;
end
else
begin
next_state <= s211;
end
end
s215:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s223;
end
else
begin
next_state <= s215;
end
end
s217:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s224;
end
else
begin
next_state <= s217;
end
end
s218:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s222;
end
else
begin
next_state <= s218;
end
end
s222:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s202;
end
else
begin
next_state <= s222;
end
end
s223:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s225;
end
else
begin
next_state <= s223;
end
end
s224:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 09 |
zw_REG_OP == 8'h 05 | zw_REG_OP == 8'h 15 |
zw_REG_OP == 8'h 0D | zw_REG_OP == 8'h 1D |
zw_REG_OP == 8'h 19 | zw_REG_OP == 8'h 01 |
zw_REG_OP == 8'h 11))
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 49 |
zw_REG_OP == 8'h 45 | zw_REG_OP == 8'h 55 |
zw_REG_OP == 8'h 4D | zw_REG_OP == 8'h 5D |
zw_REG_OP == 8'h 59 | zw_REG_OP == 8'h 41 |
zw_REG_OP == 8'h 51) )
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 29 |
zw_REG_OP == 8'h 25 | zw_REG_OP == 8'h 35 |
zw_REG_OP == 8'h 2D | zw_REG_OP == 8'h 3D |
zw_REG_OP == 8'h 39 | zw_REG_OP == 8'h 21 |
zw_REG_OP == 8'h 31) )
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h C9 |
zw_REG_OP == 8'h C5 | zw_REG_OP == 8'h D5 |
zw_REG_OP == 8'h CD | zw_REG_OP == 8'h DD |
zw_REG_OP == 8'h D9 | zw_REG_OP == 8'h C1 |
zw_REG_OP == 8'h D1 | zw_REG_OP == 8'h C0 |
zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C4 |
zw_REG_OP == 8'h E4 | zw_REG_OP == 8'h CC |
zw_REG_OP == 8'h EC) )
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 )
begin
next_state <= FETCH;
end
else
begin
next_state <= s224;
end
end
s225:
begin
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 09 | zw_REG_OP == 8'h 05 |
zw_REG_OP == 8'h 15 | zw_REG_OP == 8'h 0D |
zw_REG_OP == 8'h 1D | zw_REG_OP == 8'h 19 |
zw_REG_OP == 8'h 01 | zw_REG_OP == 8'h 11))
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 45 |
zw_REG_OP == 8'h 55 | zw_REG_OP == 8'h 4D |
zw_REG_OP == 8'h 5D | zw_REG_OP == 8'h 59 |
zw_REG_OP == 8'h 41 | zw_REG_OP == 8'h 51) )
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h 25 |
zw_REG_OP == 8'h 35 | zw_REG_OP == 8'h 2D |
zw_REG_OP == 8'h 3D | zw_REG_OP == 8'h 39 |
zw_REG_OP == 8'h 21 | zw_REG_OP == 8'h 31) )
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h C9 | zw_REG_OP == 8'h C5 |
zw_REG_OP == 8'h D5 | zw_REG_OP == 8'h CD |
zw_REG_OP == 8'h DD | zw_REG_OP == 8'h D9 |
zw_REG_OP == 8'h C1 | zw_REG_OP == 8'h D1 |
zw_REG_OP == 8'h C0 | zw_REG_OP == 8'h E0 |
zw_REG_OP == 8'h C4 | zw_REG_OP == 8'h E4 |
zw_REG_OP == 8'h CC | zw_REG_OP == 8'h EC) )
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 )
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 )
begin
next_state <= s224;
end
else
begin
next_state <= s225;
end
end
s226:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h C6 |
zw_REG_OP == 8'h E6))
begin
next_state <= s343;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h D6 |
zw_REG_OP == 8'h F6) )
begin
next_state <= s247;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h CE |
zw_REG_OP == 8'h EE) )
begin
next_state <= s243;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h DE |
zw_REG_OP == 8'h FE) )
begin
next_state <= s244;
end
else
begin
next_state <= s226;
end
end
s243:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s343;
end
else
begin
next_state <= s243;
end
end
s244:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s344;
end
else
begin
next_state <= s244;
end
end
s247:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s343;
end
else
begin
next_state <= s247;
end
end
s344:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s343;
end
else
begin
next_state <= s344;
end
end
s343:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s250;
end
else
begin
next_state <= s343;
end
end
s250:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s251;
end
else
begin
next_state <= s250;
end
end
s251:
begin
next_state <= FETCH;
end
s351:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 24)
begin
next_state <= s361;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 2C )
begin
next_state <= s360;
end
else
begin
next_state <= s351;
end
end
s361:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s361;
end
end
s360:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s361;
end
else
begin
next_state <= s360;
end
end
s403:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 1E |
zw_REG_OP == 8'h 7E | zw_REG_OP == 8'h 3E |
zw_REG_OP == 8'h 5E))
begin
next_state <= s407;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 06 |
zw_REG_OP == 8'h 66 | zw_REG_OP == 8'h 26 |
zw_REG_OP == 8'h 46) )
begin
next_state <= s413;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 16 |
zw_REG_OP == 8'h 76 | zw_REG_OP == 8'h 36 |
zw_REG_OP == 8'h 56) )
begin
next_state <= s409;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 0E |
zw_REG_OP == 8'h 6E | zw_REG_OP == 8'h 2E |
zw_REG_OP == 8'h 4E) )
begin
next_state <= s406;
end
else
begin
next_state <= s403;
end
end
s406:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s413;
end
else
begin
next_state <= s406;
end
end
s407:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s412;
end
else
begin
next_state <= s407;
end
end
s409:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s413;
end
else
begin
next_state <= s409;
end
end
s412:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s413;
end
else
begin
next_state <= s412;
end
end
s413:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s416;
end
else
begin
next_state <= s413;
end
end
s416:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 06 |
zw_REG_OP == 8'h 16 | zw_REG_OP == 8'h 0E |
zw_REG_OP == 8'h 1E))
begin
next_state <= s418;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 46 |
zw_REG_OP == 8'h 56 | zw_REG_OP == 8'h 4E |
zw_REG_OP == 8'h 5E) )
begin
next_state <= s418;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 26 |
zw_REG_OP == 8'h 36 | zw_REG_OP == 8'h 2E |
zw_REG_OP == 8'h 3E) )
begin
next_state <= s418;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 66 |
zw_REG_OP == 8'h 76 | zw_REG_OP == 8'h 6E |
zw_REG_OP == 8'h 7E) )
begin
next_state <= s418;
end
else
begin
next_state <= s416;
end
end
s418:
begin
next_state <= FETCH;
end
s510:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 65)
begin
next_state <= s565;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 69 &
reg_F[3] == 1'b 0 )
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 75 )
begin
next_state <= s560;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 6D )
begin
next_state <= s553;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 7D )
begin
next_state <= s555;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 79 )
begin
next_state <= s555;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 71 )
begin
next_state <= s558;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 61 )
begin
next_state <= s561;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 69 &
reg_F[3] == 1'b 1 )
begin
next_state <= FETCH;
end
else
begin
next_state <= s510;
end
end
s553:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s565;
end
else
begin
next_state <= s553;
end
end
s555:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s564;
end
else
begin
next_state <= s555;
end
end
s558:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s566;
end
else
begin
next_state <= s558;
end
end
s560:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s565;
end
else
begin
next_state <= s560;
end
end
s561:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s563;
end
else
begin
next_state <= s561;
end
end
s563:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s553;
end
else
begin
next_state <= s563;
end
end
s564:
begin
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 0)
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 1 )
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 )
begin
next_state <= s565;
end
else
begin
next_state <= s564;
end
end
s565:
begin
if (rdy_i == 1'b 1 & reg_F[3] == 1'b 0)
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & reg_F[3] == 1'b 1 )
begin
next_state <= FETCH;
end
else
begin
next_state <= s565;
end
end
s566:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s564;
end
else
begin
next_state <= s566;
end
end
s266:
begin
if (rdy_i == 1'b 1 & (reg_F[0] == 1'b 1 &
zw_REG_OP == 8'h 90 | reg_F[0] == 1'b 0 &
zw_REG_OP == 8'h B0 | reg_F[1] == 1'b 0 &
zw_REG_OP == 8'h F0 | reg_F[7] == 1'b 0 &
zw_REG_OP == 8'h 30 | reg_F[1] == 1'b 1 &
zw_REG_OP == 8'h D0 | reg_F[7] == 1'b 1 &
zw_REG_OP == 8'h 10 | reg_F[6] == 1'b 1 &
zw_REG_OP == 8'h 50 | reg_F[6] == 1'b 0 &
zw_REG_OP == 8'h 70))
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 )
begin
next_state <= s301;
end
else
begin
next_state <= s266;
end
end
s301:
begin
if (rdy_i == 1'b 1 & zw_b3 == adr_nxt_pc_i[15:8])
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 )
begin
next_state <= s302;
end
else
begin
next_state <= s301;
end
end
s302:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s302;
end
end
RES:
begin
next_state <= s544;
end
s511:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E5)
begin
next_state <= s574;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E9 &
reg_F[3] == 1'b 0 )
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F5 )
begin
next_state <= s569;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h ED )
begin
next_state <= s559;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h FD )
begin
next_state <= s562;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F9 )
begin
next_state <= s567;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F1 )
begin
next_state <= s568;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E1 )
begin
next_state <= s570;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E9 &
reg_F[3] == 1'b 1 )
begin
next_state <= FETCH;
end
else
begin
next_state <= s511;
end
end
s559:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s574;
end
else
begin
next_state <= s559;
end
end
s562:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s573;
end
else
begin
next_state <= s562;
end
end
s567:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s573;
end
else
begin
next_state <= s567;
end
end
s568:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s571;
end
else
begin
next_state <= s568;
end
end
s569:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s574;
end
else
begin
next_state <= s569;
end
end
s570:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s572;
end
else
begin
next_state <= s570;
end
end
s571:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s573;
end
else
begin
next_state <= s571;
end
end
s572:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s559;
end
else
begin
next_state <= s572;
end
end
s573:
begin
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 0)
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 1 )
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 )
begin
next_state <= s574;
end
else
begin
next_state <= s573;
end
end
s574:
begin
if (rdy_i == 1'b 1 & reg_F[3] == 1'b 0)
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & reg_F[3] == 1'b 1 )
begin
next_state <= FETCH;
end
else
begin
next_state <= s574;
end
end
s548:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s551;
end
else
begin
next_state <= s548;
end
end
s551:
begin
next_state <= s552;
end
s552:
begin
next_state <= s576;
end
s575:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s577;
end
else
begin
next_state <= s575;
end
end
s576:
begin
next_state <= s575;
end
s577:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s577;
end
end
s532:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s533;
end
else
begin
next_state <= s532;
end
end
s533:
begin
next_state <= s534;
end
s534:
begin
next_state <= s536;
end
s535:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s537;
end
else
begin
next_state <= s535;
end
end
s536:
begin
next_state <= s535;
end
s537:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s537;
end
end
default:
begin
next_state <= RES;
end
endcase
end
 
// ---------------------------------------------------------------
 
// ---------------------------------------------------------------
 
always @(adr_nxt_pc_i or adr_pc_i or adr_sp_i or current_state or d_alu_i
or d_i or d_regs_out_i or irq_n_i or nmi_i or q_a_i
or q_x_i or q_y_i or rdy_i or reg_F or reg_sel_pc_in
or reg_sel_pc_val or reg_sel_rb_in or reg_sel_rb_out or reg_sel_reg or reg_sel_sp_as
or reg_sel_sp_in or sig_PC or zw_ALU or zw_ALU1 or zw_ALU2
or zw_ALU3 or zw_ALU4 or zw_ALU5 or zw_ALU6 or zw_REG_OP
or zw_b1 or zw_b2 or zw_b3 or zw_b4)
begin : output_proc
a_o <= sig_PC;
adr_o <= 16'h 0000;
ch_a_o <= 8'h 00;
ch_b_o <= 8'h 00;
d_regs_in_o <= 8'h 00;
fetch_o <= 1'b 0;
ld_o <= 2'b 00;
ld_pc_o <= 1'b 0;
ld_sp_o <= 1'b 0;
load_regs_o <= 1'b 0;
offset_o <= 16'h 0000;
sel_pc_in_o <= reg_sel_pc_in;
sel_pc_val_o <= reg_sel_pc_val;
sel_rb_in_o <= reg_sel_rb_in;
sel_rb_out_o <= reg_sel_rb_out;
sel_reg_o <= reg_sel_reg;
sel_sp_as_o <= reg_sel_sp_as;
sel_sp_in_o <= reg_sel_sp_in;
 
// Default Assignment To Internals
sig_D_OUT <= 8'h 00;
sig_RD <= 1'b 1;
sig_RWn <= 1'b 1;
sig_SYNC <= 1'b 0;
sig_WR <= 1'b 0;
zw_ALU <= {1'b 0, 8'h 00};
zw_ALU1 <= {1'b 0, 4'h 0};
zw_ALU2 <= {1'b 0, 4'h 0};
zw_ALU3 <= {1'b 0, 4'h 0};
zw_ALU4 <= {1'b 0, 4'h 0};
zw_ALU5 <= 4'h 0;
zw_ALU6 <= 4'h 0;
 
// Combined Actions
case (current_state)
FETCH:
begin
sig_RWn <= 1'b 1;
sig_RD <= 1'b 1;
sig_SYNC <= ~rdy_i;
if (nmi_i == 1'b 1 & rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (irq_n_i == 1'b 0 & reg_F[2] == 1'b 0 &
rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if ((d_i == 8'h 69 | d_i == 8'h 65 |
d_i == 8'h 75 | d_i == 8'h 6D |
d_i == 8'h 7D | d_i == 8'h 79 |
d_i == 8'h 61 | d_i == 8'h 71) &
rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if ((d_i == 8'h 06 | d_i == 8'h 16 |
d_i == 8'h 0E | d_i == 8'h 1E) &
rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if ((d_i == 8'h 90 | d_i == 8'h B0 |
d_i == 8'h F0 | d_i == 8'h 30 |
d_i == 8'h D0 | d_i == 8'h 10 |
d_i == 8'h 50 | d_i == 8'h 70) &
rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if ((d_i == 8'h 24 | d_i == 8'h 2C) &
rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h 00 & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h 18 & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h D8 & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h 58 & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h B8 & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if ((d_i == 8'h E0 | d_i == 8'h E4 |
d_i == 8'h EC) & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if ((d_i == 8'h C0 | d_i == 8'h C4 |
d_i == 8'h CC) & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if ((d_i == 8'h C6 | d_i == 8'h D6 |
d_i == 8'h CE | d_i == 8'h DE) &
rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h CA & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h 88 & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if ((d_i == 8'h 49 | d_i == 8'h 45 |
d_i == 8'h 55 | d_i == 8'h 4D |
d_i == 8'h 5D | d_i == 8'h 59 |
d_i == 8'h 41 | d_i == 8'h 51 |
d_i == 8'h 09 | d_i == 8'h 05 |
d_i == 8'h 15 | d_i == 8'h 0D |
d_i == 8'h 1D | d_i == 8'h 19 |
d_i == 8'h 01 | d_i == 8'h 11 |
d_i == 8'h 29 | d_i == 8'h 25 |
d_i == 8'h 35 | d_i == 8'h 2D |
d_i == 8'h 3D | d_i == 8'h 39 |
d_i == 8'h 21 | d_i == 8'h 31 |
d_i == 8'h C9 | d_i == 8'h C5 |
d_i == 8'h D5 | d_i == 8'h CD |
d_i == 8'h DD | d_i == 8'h D9 |
d_i == 8'h C1 | d_i == 8'h D1) &
rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if ((d_i == 8'h E6 | d_i == 8'h F6 |
d_i == 8'h EE | d_i == 8'h FE) &
rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h E8 & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h C8 & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if ((d_i == 8'h 4C | d_i == 8'h 6C) &
rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h 20 & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if ((d_i == 8'h A9 | d_i == 8'h A5 |
d_i == 8'h B5 | d_i == 8'h AD |
d_i == 8'h BD | d_i == 8'h B9 |
d_i == 8'h A1 | d_i == 8'h B1) &
rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if ((d_i == 8'h A2 | d_i == 8'h A6 |
d_i == 8'h B6 | d_i == 8'h AE |
d_i == 8'h BE) & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if ((d_i == 8'h A0 | d_i == 8'h A4 |
d_i == 8'h B4 | d_i == 8'h AC |
d_i == 8'h BC) & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if ((d_i == 8'h 46 | d_i == 8'h 56 |
d_i == 8'h 4E | d_i == 8'h 5E) &
rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h EA & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h 48 & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h 08 & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h 68 & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h 28 & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if ((d_i == 8'h 26 | d_i == 8'h 36 |
d_i == 8'h 2E | d_i == 8'h 3E) &
rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if ((d_i == 8'h 66 | d_i == 8'h 76 |
d_i == 8'h 6E | d_i == 8'h 7E) &
rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h 40 & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h 60 & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if ((d_i == 8'h E9 | d_i == 8'h E5 |
d_i == 8'h F5 | d_i == 8'h ED |
d_i == 8'h FD | d_i == 8'h F9 |
d_i == 8'h E1 | d_i == 8'h F1) &
rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h 38 & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h F8 & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h 78 & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if ((d_i == 8'h 85 | d_i == 8'h 95 |
d_i == 8'h 8D | d_i == 8'h 9D |
d_i == 8'h 99 | d_i == 8'h 81 |
d_i == 8'h 91) & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if ((d_i == 8'h 86 | d_i == 8'h 96 |
d_i == 8'h 8E) & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if ((d_i == 8'h 84 | d_i == 8'h 94 |
d_i == 8'h 8C) & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h AA & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h 0A & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h 4A & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h 2A & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h 6A & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h A8 & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h 98 & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h BA & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h 8A & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (d_i == 8'h 9A & rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s1:
begin
if (rdy_i == 1'b 1)
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s2:
begin
if (rdy_i == 1'b 1)
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s5:
begin
if (rdy_i == 1'b 1)
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s3:
begin
if (rdy_i == 1'b 1)
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s4:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 9A)
begin
adr_o <= {8'h 01, d_regs_out_i};
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h BA )
begin
d_regs_in_o <= adr_sp_i[7:0];
ch_a_o <= adr_sp_i[7:0];
ch_b_o <= 8'h 00;
load_regs_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 )
begin
ch_a_o <= d_regs_out_i;
ch_b_o <= 8'h 00;
load_regs_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s12:
begin
if (rdy_i == 1'b 1)
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s16:
begin
if (rdy_i == 1'b 1)
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s17:
begin
if (rdy_i == 1'b 1)
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s24:
begin
if (rdy_i == 1'b 1)
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s25:
begin
if (rdy_i == 1'b 1)
begin
d_regs_in_o <= d_alu_i;
ch_a_o <= d_regs_out_i;
ch_b_o <= zw_b4;
load_regs_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s273:
begin
if (rdy_i == 1'b 1)
begin
adr_o <= {d_i, zw_b1};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s307:
begin
if (rdy_i == 1'b 1)
begin
adr_o <= {d_i, zw_b1};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s177:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 85 |
zw_REG_OP == 8'h 86 | zw_REG_OP == 8'h 84))
begin
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= d_regs_out_i;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 95 |
zw_REG_OP == 8'h 94) )
begin
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 8D |
zw_REG_OP == 8'h 8E | zw_REG_OP == 8'h 8C) )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 9D )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 99 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 91 )
begin
ch_a_o <= d_i;
ch_b_o <= 8'h 01;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 81 )
begin
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 96 )
begin
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end
end
s180:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= {7'b 0000000, zw_b2[0]};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s181:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end
end
s182:
begin
sig_RWn <= 1'b 1;
sig_RD <= 1'b 1;
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= {7'b 0000000, zw_b2[0]};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s183:
begin
if (rdy_i == 1'b 1)
begin
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= d_regs_out_i;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s184:
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
s185:
begin
if (rdy_i == 1'b 1)
begin
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= d_regs_out_i;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s187:
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
s188:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= zw_b1;
ch_b_o <= 8'h 01;
end
end
s189:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= {7'b 0000000, zw_b2[0]};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s190:
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
s191:
begin
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= d_regs_out_i;
end
s192:
begin
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= d_regs_out_i;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
s193:
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
s377:
begin
if (rdy_i == 1'b 1)
begin
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= q_a_i;
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
end
end
s381:
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
s378:
begin
if (rdy_i == 1'b 1)
begin
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= reg_F;
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
end
end
s382:
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
s379:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
end
end
s384:
begin
if (rdy_i == 1'b 1)
begin
d_regs_in_o <= d_i;
load_regs_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= 8'h 00;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s380:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
end
end
s386:
begin
if (rdy_i == 1'b 1)
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s387:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
end
end
s388:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
end
end
s389:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
end
end
s392:
begin
if (rdy_i == 1'b 1)
begin
adr_o <= {d_i, zw_b1};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s390:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
end
end
s393:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
end
end
s395:
begin
if (rdy_i == 1'b 1)
begin
adr_o <= {d_i, zw_b1};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s396:
begin
if (rdy_i == 1'b 1)
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s397:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
ld_pc_o <= 1'b 1;
end
end
s398:
begin
if (rdy_i == 1'b 1)
begin
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= adr_pc_i[15:8];
end
end
s399:
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= adr_pc_i[7:0];
end
s401:
begin
if (rdy_i == 1'b 1)
begin
adr_o <= {d_i, zw_b1};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s526:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
ld_pc_o <= 1'b 1;
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= adr_pc_i[15:8];
end
end
s527:
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= adr_pc_i[7:0];
end
s528:
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= reg_F | 8'h 10;
end
s530:
begin
if (rdy_i == 1'b 1)
begin
adr_o <= {d_i, zw_b1};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s544:
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
end
s545:
begin
adr_o <= 16'h FFFB;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
s546:
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
s549:
begin
if (rdy_i == 1'b 1)
begin
adr_o <= {d_i, zw_b1};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s550:
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
end
s404:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= {q_a_i[6:0], 1'b 0};
ch_b_o <= 8'h 00;
d_regs_in_o <= {q_a_i[6:0], 1'b 0};
load_regs_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s556:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= {1'b 0, q_a_i[7:1]};
ch_b_o <= 8'h 00;
d_regs_in_o <= {1'b 0, q_a_i[7:1]};
load_regs_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s557:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= {q_a_i[6:0], reg_F[0]};
ch_b_o <= 8'h 00;
d_regs_in_o <= {q_a_i[6:0], reg_F[0]};
load_regs_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s579:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= {reg_F[0], q_a_i[7:1]};
ch_b_o <= 8'h 00;
d_regs_in_o <= {reg_F[0], q_a_i[7:1]};
load_regs_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s201:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A5 |
zw_REG_OP == 8'h A6 | zw_REG_OP == 8'h A4 |
zw_REG_OP == 8'h 45 | zw_REG_OP == 8'h 05 |
zw_REG_OP == 8'h 25 | zw_REG_OP == 8'h C5 |
zw_REG_OP == 8'h E4 | zw_REG_OP == 8'h C4))
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 |
zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 |
zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 |
zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 |
zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) &
(zw_REG_OP == 8'h 09 | zw_REG_OP == 8'h 05 |
zw_REG_OP == 8'h 15 | zw_REG_OP == 8'h 0D |
zw_REG_OP == 8'h 1D | zw_REG_OP == 8'h 19 |
zw_REG_OP == 8'h 01 | zw_REG_OP == 8'h 11) )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
d_regs_in_o <= d_i | q_a_i;
load_regs_o <= 1'b 1;
ch_a_o <= d_i | q_a_i;
ch_b_o <= 8'h 00;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 |
zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 |
zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 |
zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 |
zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) &
(zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 45 |
zw_REG_OP == 8'h 55 | zw_REG_OP == 8'h 4D |
zw_REG_OP == 8'h 5D | zw_REG_OP == 8'h 59 |
zw_REG_OP == 8'h 41 | zw_REG_OP == 8'h 51) )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
d_regs_in_o <= d_i ^ q_a_i;
load_regs_o <= 1'b 1;
ch_a_o <= d_i ^ q_a_i;
ch_b_o <= 8'h 00;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 |
zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 |
zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 |
zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 |
zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) &
(zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h 25 |
zw_REG_OP == 8'h 35 | zw_REG_OP == 8'h 2D |
zw_REG_OP == 8'h 3D | zw_REG_OP == 8'h 39 |
zw_REG_OP == 8'h 21 | zw_REG_OP == 8'h 31) )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
d_regs_in_o <= d_i & q_a_i;
load_regs_o <= 1'b 1;
ch_a_o <= d_i & q_a_i;
ch_b_o <= 8'h 00;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 |
zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 |
zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 |
zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 |
zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) &
(zw_REG_OP == 8'h C9 | zw_REG_OP == 8'h C5 |
zw_REG_OP == 8'h D5 | zw_REG_OP == 8'h CD |
zw_REG_OP == 8'h DD | zw_REG_OP == 8'h D9 |
zw_REG_OP == 8'h C1 | zw_REG_OP == 8'h D1 |
zw_REG_OP == 8'h C0 | zw_REG_OP == 8'h E0 |
zw_REG_OP == 8'h C4 | zw_REG_OP == 8'h E4 |
zw_REG_OP == 8'h CC | zw_REG_OP == 8'h EC) )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
zw_ALU <= {1'b 0, d_regs_out_i} + {1'b 0, (~d_i)} +
1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 |
zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 |
zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 |
zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 |
zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
d_regs_in_o <= d_i;
load_regs_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= 8'h 00;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h B5 |
zw_REG_OP == 8'h B4 | zw_REG_OP == 8'h 55 |
zw_REG_OP == 8'h 15 | zw_REG_OP == 8'h 35 |
zw_REG_OP == 8'h D5) )
begin
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h AD |
zw_REG_OP == 8'h AE | zw_REG_OP == 8'h AC |
zw_REG_OP == 8'h 4D | zw_REG_OP == 8'h 0D |
zw_REG_OP == 8'h 2D | zw_REG_OP == 8'h CD |
zw_REG_OP == 8'h EC | zw_REG_OP == 8'h CC) )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h BD |
zw_REG_OP == 8'h BC | zw_REG_OP == 8'h 5D |
zw_REG_OP == 8'h 1D | zw_REG_OP == 8'h 3D |
zw_REG_OP == 8'h DD) )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h B9 |
zw_REG_OP == 8'h BE | zw_REG_OP == 8'h 59 |
zw_REG_OP == 8'h 19 | zw_REG_OP == 8'h 39 |
zw_REG_OP == 8'h D9) )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h B1 |
zw_REG_OP == 8'h 51 | zw_REG_OP == 8'h 11 |
zw_REG_OP == 8'h 31 | zw_REG_OP == 8'h D1) )
begin
ch_a_o <= d_i;
ch_b_o <= 8'h 01;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A1 |
zw_REG_OP == 8'h 41 | zw_REG_OP == 8'h 01 |
zw_REG_OP == 8'h 21 | zw_REG_OP == 8'h C1) )
begin
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h B6 )
begin
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end
end
s202:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s210:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= {7'b 0000000, zw_b2[0]};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s211:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= {7'b 0000000, zw_b2[0]};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s215:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end
end
s217:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s222:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= zw_b1;
ch_b_o <= 8'h 01;
end
end
s223:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= {7'b 0000000, zw_b2[0]};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s224:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 09 |
zw_REG_OP == 8'h 05 | zw_REG_OP == 8'h 15 |
zw_REG_OP == 8'h 0D | zw_REG_OP == 8'h 1D |
zw_REG_OP == 8'h 19 | zw_REG_OP == 8'h 01 |
zw_REG_OP == 8'h 11))
begin
d_regs_in_o <= d_i | q_a_i;
load_regs_o <= 1'b 1;
ch_a_o <= d_i | q_a_i;
ch_b_o <= 8'h 00;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 49 |
zw_REG_OP == 8'h 45 | zw_REG_OP == 8'h 55 |
zw_REG_OP == 8'h 4D | zw_REG_OP == 8'h 5D |
zw_REG_OP == 8'h 59 | zw_REG_OP == 8'h 41 |
zw_REG_OP == 8'h 51) )
begin
d_regs_in_o <= d_i ^ q_a_i;
load_regs_o <= 1'b 1;
ch_a_o <= d_i ^ q_a_i;
ch_b_o <= 8'h 00;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 29 |
zw_REG_OP == 8'h 25 | zw_REG_OP == 8'h 35 |
zw_REG_OP == 8'h 2D | zw_REG_OP == 8'h 3D |
zw_REG_OP == 8'h 39 | zw_REG_OP == 8'h 21 |
zw_REG_OP == 8'h 31) )
begin
d_regs_in_o <= d_i & q_a_i;
load_regs_o <= 1'b 1;
ch_a_o <= d_i & q_a_i;
ch_b_o <= 8'h 00;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h C9 |
zw_REG_OP == 8'h C5 | zw_REG_OP == 8'h D5 |
zw_REG_OP == 8'h CD | zw_REG_OP == 8'h DD |
zw_REG_OP == 8'h D9 | zw_REG_OP == 8'h C1 |
zw_REG_OP == 8'h D1 | zw_REG_OP == 8'h C0 |
zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C4 |
zw_REG_OP == 8'h E4 | zw_REG_OP == 8'h CC |
zw_REG_OP == 8'h EC) )
begin
zw_ALU <= {1'b 0, d_regs_out_i} + {1'b 0, (~d_i)} +
1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 )
begin
d_regs_in_o <= d_i;
load_regs_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= 8'h 00;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s225:
begin
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 09 | zw_REG_OP == 8'h 05 |
zw_REG_OP == 8'h 15 | zw_REG_OP == 8'h 0D |
zw_REG_OP == 8'h 1D | zw_REG_OP == 8'h 19 |
zw_REG_OP == 8'h 01 | zw_REG_OP == 8'h 11))
begin
d_regs_in_o <= d_i | q_a_i;
load_regs_o <= 1'b 1;
ch_a_o <= d_i | q_a_i;
ch_b_o <= 8'h 00;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 45 |
zw_REG_OP == 8'h 55 | zw_REG_OP == 8'h 4D |
zw_REG_OP == 8'h 5D | zw_REG_OP == 8'h 59 |
zw_REG_OP == 8'h 41 | zw_REG_OP == 8'h 51) )
begin
d_regs_in_o <= d_i ^ q_a_i;
load_regs_o <= 1'b 1;
ch_a_o <= d_i ^ q_a_i;
ch_b_o <= 8'h 00;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h 25 |
zw_REG_OP == 8'h 35 | zw_REG_OP == 8'h 2D |
zw_REG_OP == 8'h 3D | zw_REG_OP == 8'h 39 |
zw_REG_OP == 8'h 21 | zw_REG_OP == 8'h 31) )
begin
d_regs_in_o <= d_i & q_a_i;
load_regs_o <= 1'b 1;
ch_a_o <= d_i & q_a_i;
ch_b_o <= 8'h 00;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h C9 | zw_REG_OP == 8'h C5 |
zw_REG_OP == 8'h D5 | zw_REG_OP == 8'h CD |
zw_REG_OP == 8'h DD | zw_REG_OP == 8'h D9 |
zw_REG_OP == 8'h C1 | zw_REG_OP == 8'h D1 |
zw_REG_OP == 8'h C0 | zw_REG_OP == 8'h E0 |
zw_REG_OP == 8'h C4 | zw_REG_OP == 8'h E4 |
zw_REG_OP == 8'h CC | zw_REG_OP == 8'h EC) )
begin
zw_ALU <= {1'b 0, d_regs_out_i} + {1'b 0, (~d_i)} +
1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 )
begin
d_regs_in_o <= d_i;
load_regs_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= 8'h 00;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s226:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h C6 |
zw_REG_OP == 8'h E6))
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h D6 |
zw_REG_OP == 8'h F6) )
begin
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h CE |
zw_REG_OP == 8'h EE) )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h DE |
zw_REG_OP == 8'h FE) )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
end
s243:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s244:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= {7'b 0000000, zw_b2[0]};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s247:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s343:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= zw_b4;
end
end
s250:
begin
if (rdy_i == 1'b 1)
begin
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= zw_b1;
end
end
s251:
begin
ch_a_o <= zw_b1;
ch_b_o <= 8'h 00;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
s351:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 24)
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 2C )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s361:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= q_a_i & d_i;
ch_b_o <= 8'h 00;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s360:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s403:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 1E |
zw_REG_OP == 8'h 7E | zw_REG_OP == 8'h 3E |
zw_REG_OP == 8'h 5E))
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 06 |
zw_REG_OP == 8'h 66 | zw_REG_OP == 8'h 26 |
zw_REG_OP == 8'h 46) )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 16 |
zw_REG_OP == 8'h 76 | zw_REG_OP == 8'h 36 |
zw_REG_OP == 8'h 56) )
begin
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 0E |
zw_REG_OP == 8'h 6E | zw_REG_OP == 8'h 2E |
zw_REG_OP == 8'h 4E) )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s406:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s407:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= {7'b 0000000, zw_b2[0]};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s409:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s416:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 06 |
zw_REG_OP == 8'h 16 | zw_REG_OP == 8'h 0E |
zw_REG_OP == 8'h 1E))
begin
sig_D_OUT <= {d_i[6:0], 1'b 0};
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 46 |
zw_REG_OP == 8'h 56 | zw_REG_OP == 8'h 4E |
zw_REG_OP == 8'h 5E) )
begin
sig_D_OUT <= {1'b 0, d_i[7:1]};
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 26 |
zw_REG_OP == 8'h 36 | zw_REG_OP == 8'h 2E |
zw_REG_OP == 8'h 3E) )
begin
sig_D_OUT <= {d_i[6:0], reg_F[0]};
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 66 |
zw_REG_OP == 8'h 76 | zw_REG_OP == 8'h 6E |
zw_REG_OP == 8'h 7E) )
begin
sig_D_OUT <= {reg_F[0], d_i[7:1]};
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
end
end
s418:
begin
ch_a_o <= zw_b1;
ch_b_o <= 8'h 00;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
s510:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 65)
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 69 &
reg_F[3] == 1'b 0 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU <= {1'b 0, q_a_i} + {1'b 0, d_i} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 75 )
begin
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 6D )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 7D )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 79 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 71 )
begin
ch_a_o <= d_i;
ch_b_o <= 8'h 01;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 61 )
begin
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 69 &
reg_F[3] == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU[7:4] <= zw_ALU2[3:0] + zw_ALU6[2:0];
zw_ALU[3:0] <= zw_ALU1[3:0] + zw_ALU5[2:0];
zw_ALU6[2:0] <= {(zw_ALU2[4] | zw_ALU4[4]), (zw_ALU2[4] | zw_ALU4[4]),
1'b 0};
zw_ALU5[2:0] <= {(zw_ALU1[4] | zw_ALU3[4]), (zw_ALU1[4] | zw_ALU3[4]),
1'b 0};
zw_ALU4 <= {1'b 0, zw_ALU2[3:0]} + 6;
zw_ALU2 <= {1'b 0, q_a_i[7:4]} + {1'b 0, d_i[7:4]} +
(zw_ALU1[4] | zw_ALU3[4]);
zw_ALU3 <= {1'b 0, zw_ALU1[3:0]} + 6;
zw_ALU1 <= {1'b 0, q_a_i[3:0]} + {1'b 0, d_i[3:0]} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s553:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s555:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= 8'h 01;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s558:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end
end
s560:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s563:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= zw_b1;
ch_b_o <= 8'h 01;
end
end
s564:
begin
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 0)
begin
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU <= {1'b 0, q_a_i} + {1'b 0, d_i} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 1 )
begin
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU[7:4] <= zw_ALU2[3:0] + zw_ALU6[2:0];
zw_ALU[3:0] <= zw_ALU1[3:0] + zw_ALU5[2:0];
zw_ALU6[2:0] <= {(zw_ALU2[4] | zw_ALU4[4]), (zw_ALU2[4] | zw_ALU4[4]),
1'b 0};
zw_ALU5[2:0] <= {(zw_ALU1[4] | zw_ALU3[4]), (zw_ALU1[4] | zw_ALU3[4]),
1'b 0};
zw_ALU4 <= {1'b 0, zw_ALU2[3:0]} + 6;
zw_ALU2 <= {1'b 0, q_a_i[7:4]} + {1'b 0, d_i[7:4]} +
(zw_ALU1[4] | zw_ALU3[4]);
zw_ALU3 <= {1'b 0, zw_ALU1[3:0]} + 6;
zw_ALU1 <= {1'b 0, q_a_i[3:0]} + {1'b 0, d_i[3:0]} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s565:
begin
if (rdy_i == 1'b 1 & reg_F[3] == 1'b 0)
begin
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU <= {1'b 0, q_a_i} + {1'b 0, d_i} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & reg_F[3] == 1'b 1 )
begin
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU[7:4] <= zw_ALU2[3:0] + zw_ALU6[2:0];
zw_ALU[3:0] <= zw_ALU1[3:0] + zw_ALU5[2:0];
zw_ALU6[2:0] <= {(zw_ALU2[4] | zw_ALU4[4]), (zw_ALU2[4] | zw_ALU4[4]),
1'b 0};
zw_ALU5[2:0] <= {(zw_ALU1[4] | zw_ALU3[4]), (zw_ALU1[4] | zw_ALU3[4]),
1'b 0};
zw_ALU4 <= {1'b 0, zw_ALU2[3:0]} + 6;
zw_ALU2 <= {1'b 0, q_a_i[7:4]} + {1'b 0, d_i[7:4]} +
(zw_ALU1[4] | zw_ALU3[4]);
zw_ALU3 <= {1'b 0, zw_ALU1[3:0]} + 6;
zw_ALU1 <= {1'b 0, q_a_i[3:0]} + {1'b 0, d_i[3:0]} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s566:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= 8'h 01;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s266:
begin
if (rdy_i == 1'b 1 & (reg_F[0] == 1'b 1 &
zw_REG_OP == 8'h 90 | reg_F[0] == 1'b 0 &
zw_REG_OP == 8'h B0 | reg_F[1] == 1'b 0 &
zw_REG_OP == 8'h F0 | reg_F[7] == 1'b 0 &
zw_REG_OP == 8'h 30 | reg_F[1] == 1'b 1 &
zw_REG_OP == 8'h D0 | reg_F[7] == 1'b 1 &
zw_REG_OP == 8'h 10 | reg_F[6] == 1'b 1 &
zw_REG_OP == 8'h 50 | reg_F[6] == 1'b 0 &
zw_REG_OP == 8'h 70))
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s301:
begin
if (rdy_i == 1'b 1 & zw_b3 == adr_nxt_pc_i[15:8])
begin
offset_o <= {zw_b2[7], zw_b2[7], zw_b2[7], zw_b2[7],
zw_b2[7], zw_b2[7], zw_b2[7], zw_b2[7],
zw_b2[7], zw_b2[6:0]};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 )
begin
offset_o <= {zw_b2[7], zw_b2[7], zw_b2[7], zw_b2[7],
zw_b2[7], zw_b2[7], zw_b2[7], zw_b2[7],
zw_b2[7], zw_b2[6:0]};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s302:
begin
if (rdy_i == 1'b 1)
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
RES:
begin
sig_RWn <= 1'b 1;
sig_RD <= 1'b 1;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ld_sp_o <= 1'b 1;
sig_RWn <= 1'b 1;
sig_RD <= 1'b 1;
end
s511:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E5)
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E9 &
reg_F[3] == 1'b 0 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU <= {1'b 0, q_a_i} + {1'b 0, (~d_i)} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F5 )
begin
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h ED )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h FD )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F9 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F1 )
begin
ch_a_o <= d_i;
ch_b_o <= 8'h 01;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E1 )
begin
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E9 &
reg_F[3] == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU[7:4] <= zw_ALU2[3:0] + zw_ALU6;
zw_ALU[3:0] <= zw_ALU1[3:0] + zw_ALU5;
zw_ALU6 <= {(zw_ALU4[4] | ~zw_ALU2[4]), 1'b 0, (zw_ALU4[4] |
~zw_ALU2[4]), 1'b 0};
zw_ALU5 <= {(zw_ALU3[4] | ~zw_ALU1[4]), 1'b 0, (zw_ALU3[4] |
~zw_ALU1[4]), 1'b 0};
zw_ALU4 <= {1'b 0, zw_ALU2[3:0]} + 6;
zw_ALU2 <= {1'b 0, q_a_i[7:4]} + {1'b 0, (~d_i[7:4])} +
zw_ALU1[4];
zw_ALU3 <= {1'b 0, zw_ALU1[3:0]} + 6;
zw_ALU1 <= {1'b 0, q_a_i[3:0]} + {1'b 0, (~d_i[3:0])} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s559:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s562:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= 8'h 01;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s567:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= 8'h 01;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s568:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end
end
s569:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s571:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= 8'h 01;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s572:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= zw_b1;
ch_b_o <= 8'h 01;
end
end
s573:
begin
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 0)
begin
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU <= {1'b 0, q_a_i} + {1'b 0, (~d_i)} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 1 )
begin
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU[7:4] <= zw_ALU2[3:0] + zw_ALU6;
zw_ALU[3:0] <= zw_ALU1[3:0] + zw_ALU5;
zw_ALU6 <= {(zw_ALU4[4] | ~zw_ALU2[4]), 1'b 0, (zw_ALU4[4] |
~zw_ALU2[4]), 1'b 0};
zw_ALU5 <= {(zw_ALU3[4] | ~zw_ALU1[4]), 1'b 0, (zw_ALU3[4] |
~zw_ALU1[4]), 1'b 0};
zw_ALU4 <= {1'b 0, zw_ALU2[3:0]} + 6;
zw_ALU2 <= {1'b 0, q_a_i[7:4]} + {1'b 0, (~d_i[7:4])} +
zw_ALU1[4];
zw_ALU3 <= {1'b 0, zw_ALU1[3:0]} + 6;
zw_ALU1 <= {1'b 0, q_a_i[3:0]} + {1'b 0, (~d_i[3:0])} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s574:
begin
if (rdy_i == 1'b 1 & reg_F[3] == 1'b 0)
begin
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU <= {1'b 0, q_a_i} + {1'b 0, (~d_i)} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & reg_F[3] == 1'b 1 )
begin
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU[7:4] <= zw_ALU2[3:0] + zw_ALU6;
zw_ALU[3:0] <= zw_ALU1[3:0] + zw_ALU5;
zw_ALU6 <= {(zw_ALU4[4] | ~zw_ALU2[4]), 1'b 0, (zw_ALU4[4] |
~zw_ALU2[4]), 1'b 0};
zw_ALU5 <= {(zw_ALU3[4] | ~zw_ALU1[4]), 1'b 0, (zw_ALU3[4] |
~zw_ALU1[4]), 1'b 0};
zw_ALU4 <= {1'b 0, zw_ALU2[3:0]} + 6;
zw_ALU2 <= {1'b 0, q_a_i[7:4]} + {1'b 0, (~d_i[7:4])} +
zw_ALU1[4];
zw_ALU3 <= {1'b 0, zw_ALU1[3:0]} + 6;
zw_ALU1 <= {1'b 0, q_a_i[3:0]} + {1'b 0, (~d_i[3:0])} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s548:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
ld_pc_o <= 1'b 1;
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= adr_pc_i[15:8];
end
end
s551:
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= adr_pc_i[7:0];
end
s552:
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= reg_F;
end
s577:
begin
if (rdy_i == 1'b 1)
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s532:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
ld_pc_o <= 1'b 1;
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= adr_pc_i[15:8];
end
end
s533:
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= adr_pc_i[7:0];
end
s534:
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= reg_F;
end
s537:
begin
if (rdy_i == 1'b 1)
begin
adr_o <= {d_i, zw_b1};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
default:
;
endcase
end
 
// Concurrent Statements
// Clocked output assignments
 
// ---------------------------------------------------------------
// Default Assignment
assign d_o = d_o_cld;
assign rd_o = rd_o_cld;
assign sync_o = sync_o_cld;
assign wr_n_o = wr_n_o_cld;
assign wr_o = wr_o_cld;
 
// Architecture Declarations
 
endmodule // module FSM_Execution_Unit
 
/trunk/rtl/verilog_TRIAL/core.v
0,0 → 1,230
`define false 1'b 0
`define FALSE 1'b 0
`define true 1'b 1
`define TRUE 1'b 1
 
`timescale 1 ns / 1 ns
 
 
// Verilog Entity R6502_TC.Core.symbol
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 19:21:54 07.01.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
 
module Core (
clk_clk_i,
d_i,
irq_n_i,
nmi_n_i,
rdy_i,
rst_rst_n_i,
so_n_i,
a_o,
d_o,
rd_o,
sync_o,
wr_n_o,
wr_o);
 
input clk_clk_i;
input [7:0] d_i;
input irq_n_i;
input nmi_n_i;
input rdy_i;
input rst_rst_n_i;
input so_n_i;
output [15:0] a_o;
output [7:0] d_o;
output rd_o;
output sync_o;
output wr_n_o;
output wr_o;
 
 
// Jens-D. Gutschmidt Project: R6502_TC
// scantara2003@yahoo.de
// COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
//
// This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version
// 3 of the License, or any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
// PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// CVS Revisins History
//
// $Log: not supported by cvs2svn $
// <<-- more -->>
// Title: Core
// Path: R6502_TC/Core/struct
// Edited: by eda on 07 Jan 2009
//
// Verilog Architecture R6502_TC.Core.struct
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 19:21:55 07.01.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
wire [15:0] a_o;
wire [7:0] d_o;
wire rd_o;
wire sync_o;
wire wr_n_o;
wire wr_o;
 
// Declarations
wire [15:0] adr_nxt_pc_o_i;
wire [15:0] adr_o_i;
wire [15:0] adr_pc_o_i;
wire [15:0] adr_sp_o_i;
wire [7:0] ch_a_o_i;
wire [7:0] ch_b_o_i;
wire d_alu_n_o_i;
reg [7:0] d_alu_o_i;
wire d_alu_or_o_i;
wire [7:0] d_regs_in_o_i;
wire [7:0] d_regs_out_o_i;
wire fetch_o_i;
wire [1:0] ld_o_i;
wire ld_pc_o_i;
wire ld_sp_o_i;
wire load_regs_o_i;
wire nmi_o_i;
wire [15:0] offset_o_i;
wire [7:0] q_a_o_i;
wire [7:0] q_x_o_i;
wire [7:0] q_y_o_i;
reg reg_0flag_o_i;
wire reg_1flag_o_i;
wire reg_7flag_o_i;
wire sel_pc_in_o_i;
wire [1:0] sel_pc_val_o_i;
wire [1:0] sel_rb_in_o_i;
wire [1:0] sel_rb_out_o_i;
wire [1:0] sel_reg_o_i;
wire sel_sp_as_o_i;
wire sel_sp_in_o_i;
 
// Component Declarations
 
// ModuleWare code(v1.9) for instance 'U_11' of 'add'
reg [8:0] u_11combo_proc_temp_din0;
reg [8:0] u_11combo_proc_temp_din1;
reg [8:0] u_11combo_proc_temp_sum;
reg u_11combo_proc_temp_carry;
 
 
always @(ch_a_o_i or ch_b_o_i)
begin : u_11combo_proc
u_11combo_proc_temp_din0 = {1'b 0, ch_a_o_i};
u_11combo_proc_temp_din1 = {1'b 0, ch_b_o_i};
u_11combo_proc_temp_carry = 1'b 0;
u_11combo_proc_temp_sum = u_11combo_proc_temp_din0 + u_11combo_proc_temp_din1 + u_11combo_proc_temp_carry;
d_alu_o_i <= u_11combo_proc_temp_sum[7:0];
reg_0flag_o_i <= u_11combo_proc_temp_sum[8];
end
 
// ModuleWare code(v1.9) for instance 'U_8' of 'inv'
assign reg_1flag_o_i = ~d_alu_or_o_i;
 
// ModuleWare code(v1.9) for instance 'U_9' of 'inv'
assign reg_7flag_o_i = ~d_alu_n_o_i;
 
// ModuleWare code(v1.9) for instance 'U_10' of 'inv'
assign d_alu_n_o_i = ~d_alu_o_i[7];
 
// ModuleWare code(v1.9) for instance 'U_7' of 'por'
assign d_alu_or_o_i = d_alu_o_i[0] | d_alu_o_i[1] | d_alu_o_i[2] | d_alu_o_i[3] |
d_alu_o_i[4] | d_alu_o_i[5] | d_alu_o_i[6] | d_alu_o_i[7];
 
// Instance port mappings.
FSM_Execution_Unit U_4 (.adr_nxt_pc_i(adr_nxt_pc_o_i),
.adr_pc_i(adr_pc_o_i),
.adr_sp_i(adr_sp_o_i),
.clk_clk_i(clk_clk_i),
.d_alu_i(d_alu_o_i),
.d_i(d_i),
.d_regs_out_i(d_regs_out_o_i),
.irq_n_i(irq_n_i),
.nmi_i(nmi_o_i),
.q_a_i(q_a_o_i),
.q_x_i(q_x_o_i),
.q_y_i(q_y_o_i),
.rdy_i(rdy_i),
.reg_0flag_i(reg_0flag_o_i),
.reg_1flag_i(reg_1flag_o_i),
.reg_7flag_i(reg_7flag_o_i),
.rst_rst_n_i(rst_rst_n_i),
.so_n_i(so_n_i),
.a_o(a_o),
.adr_o(adr_o_i),
.ch_a_o(ch_a_o_i),
.ch_b_o(ch_b_o_i),
.d_o(d_o),
.d_regs_in_o(d_regs_in_o_i),
.fetch_o(fetch_o_i),
.ld_o(ld_o_i),
.ld_pc_o(ld_pc_o_i),
.ld_sp_o(ld_sp_o_i),
.load_regs_o(load_regs_o_i),
.offset_o(offset_o_i),
.rd_o(rd_o),
.sel_pc_in_o(sel_pc_in_o_i),
.sel_pc_val_o(sel_pc_val_o_i),
.sel_rb_in_o(sel_rb_in_o_i),
.sel_rb_out_o(sel_rb_out_o_i),
.sel_reg_o(sel_reg_o_i),
.sel_sp_as_o(sel_sp_as_o_i),
.sel_sp_in_o(sel_sp_in_o_i),
.sync_o(sync_o),
.wr_n_o(wr_n_o),
.wr_o(wr_o));
FSM_NMI U_6 (.clk_clk_i(clk_clk_i),
.fetch_i(fetch_o_i),
.nmi_n_i(nmi_n_i),
.rst_rst_n_i(rst_rst_n_i),
.nmi_o(nmi_o_i));
RegBank_AXY U_2 (.clk_clk_i(clk_clk_i),
.d_regs_in_i(d_regs_in_o_i),
.load_regs_i(load_regs_o_i),
.rst_rst_n_i(rst_rst_n_i),
.sel_rb_in_i(sel_rb_in_o_i),
.sel_rb_out_i(sel_rb_out_o_i),
.sel_reg_i(sel_reg_o_i),
.d_regs_out_o(d_regs_out_o_i),
.q_a_o(q_a_o_i),
.q_x_o(q_x_o_i),
.q_y_o(q_y_o_i));
Reg_PC U_0 (.adr_i(adr_o_i),
.clk_clk_i(clk_clk_i),
.ld_i(ld_o_i),
.ld_pc_i(ld_pc_o_i),
.offset_i(offset_o_i),
.rst_rst_n_i(rst_rst_n_i),
.sel_pc_in_i(sel_pc_in_o_i),
.sel_pc_val_i(sel_pc_val_o_i),
.adr_nxt_pc_o(adr_nxt_pc_o_i),
.adr_pc_o(adr_pc_o_i));
Reg_SP U_1 (.adr_low_i(adr_o_i[7:0]),
.clk_clk_i(clk_clk_i),
.ld_low_i(ld_o_i[0]),
.ld_sp_i(ld_sp_o_i),
.rst_rst_n_i(rst_rst_n_i),
.sel_sp_as_i(sel_sp_as_o_i),
.sel_sp_in_i(sel_sp_in_o_i),
.adr_sp_o(adr_sp_o_i));
 
// Architecture declarations
// Internal signal declarations
 
endmodule // module Core
 
/trunk/rtl/verilog_TRIAL/fsm_nmi.v
0,0 → 1,172
`define false 1'b 0
`define FALSE 1'b 0
`define true 1'b 1
`define TRUE 1'b 1
 
`timescale 1 ns / 1 ns
 
 
// Verilog Entity R6502_TC.FSM_NMI.symbol
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 18:46:08 07.01.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
 
module FSM_NMI (
clk_clk_i,
fetch_i,
nmi_n_i,
rst_rst_n_i,
nmi_o);
 
input clk_clk_i;
input fetch_i;
input nmi_n_i;
input rst_rst_n_i;
output nmi_o;
 
 
// Jens-D. Gutschmidt Project: R6502_TC
// scantara2003@yahoo.de
// COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
//
// This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// CVS Revisins History
//
// $Log: not supported by cvs2svn $
// <<-- more -->>
// Title: FSM for NMI
// Path: R6502_TC/FSM_NMI/fsm
// Edited: by eda on 07 Jan 2009
//
// Verilog Architecture R6502_TC.FSM_NMI.fsm
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 18:46:08 07.01.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
wire nmi_o;
 
// Declarations
parameter idle = 2'b 00;
parameter idle1 = 2'b 01;
parameter idle2 = 2'b 11;
parameter IMP = 2'b 10;
 
// Declare current and next state signals
reg [1:0] current_state;
reg [1:0] next_state;
 
// Declare any pre-registered internal signals
reg nmi_o_cld;
 
// ---------------------------------------------------------------
 
 
always @(posedge clk_clk_i or negedge rst_rst_n_i)
begin : clocked_proc
if (rst_rst_n_i == 1'b 0)
begin
current_state <= idle;
 
// Default Reset Values
nmi_o_cld <= 1'b 0;
end
else
begin
current_state <= next_state;
 
// Default Assignment To Internals
nmi_o_cld <= 1'b 0;
 
// Combined Actions
case (current_state)
IMP:
begin
nmi_o_cld <= 1'b 1;
end
default:
;
endcase
end
end
 
// ---------------------------------------------------------------
 
// ---------------------------------------------------------------
 
always @(current_state or fetch_i or nmi_n_i)
begin : nextstate_proc
case (current_state)
idle:
begin
if (nmi_n_i == 1'b 1)
begin
next_state <= idle1;
end
else
begin
next_state <= idle;
end
end
idle1:
begin
if (nmi_n_i == 1'b 0)
begin
next_state <= idle2;
end
else
begin
next_state <= idle1;
end
end
idle2:
begin
if (nmi_n_i == 1'b 0)
begin
next_state <= IMP;
end
else
begin
next_state <= idle;
end
end
IMP:
begin
if (fetch_i == 1'b 1)
begin
next_state <= idle;
end
else
begin
next_state <= IMP;
end
end
default:
begin
next_state <= idle;
end
endcase
end
 
// Concurrent Statements
// Clocked output assignments
 
// ---------------------------------------------------------------
assign nmi_o = nmi_o_cld;
 
endmodule // module FSM_NMI
 
/trunk/rtl/verilog_TRIAL/regbank_axy.v
0,0 → 1,282
`define false 1'b 0
`define FALSE 1'b 0
`define true 1'b 1
`define TRUE 1'b 1
 
`timescale 1 ns / 1 ns
 
 
// Verilog Entity R6502_TC.RegBank_AXY.symbol
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 18:23:46 07.01.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
 
module RegBank_AXY (
clk_clk_i,
d_regs_in_i,
load_regs_i,
rst_rst_n_i,
sel_rb_in_i,
sel_rb_out_i,
sel_reg_i,
d_regs_out_o,
q_a_o,
q_x_o,
q_y_o);
 
input clk_clk_i;
input [7:0] d_regs_in_i;
input load_regs_i;
input rst_rst_n_i;
input [1:0] sel_rb_in_i;
input [1:0] sel_rb_out_i;
input [1:0] sel_reg_i;
output [7:0] d_regs_out_o;
output [7:0] q_a_o;
output [7:0] q_x_o;
output [7:0] q_y_o;
 
 
// Jens-D. Gutschmidt Project: R6502_TC
// scantara2003@yahoo.de
// COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
//
// This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// CVS Revisins History
//
// $Log: not supported by cvs2svn $
// <<-- more -->>
// Title: Register Bank for register A, X and Y
// Path: R6502_TC/RegBank_AXY/struct
// Edited: by eda on 02 Jan 2009
//
// Verilog Architecture R6502_TC.RegBank_AXY.struct
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 18:23:46 07.01.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
reg [7:0] d_regs_out_o;
wire [7:0] q_a_o;
wire [7:0] q_x_o;
wire [7:0] q_y_o;
 
// Declarations
reg [2:0] ld;
wire load1_o_i;
wire load2_o_i;
wire load_o_i;
reg [7:0] q_mux_o_i;
wire [7:0] val_zero;
 
// Implicit buffer signal declarations
wire [7:0] q_a_o_internal;
wire [7:0] q_x_o_internal;
wire [7:0] q_y_o_internal;
 
// ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
reg [7:0] mw_U_0reg_cval;
 
// ModuleWare signal declarations(v1.9) for instance 'U_4' of 'adff'
reg [7:0] mw_U_4reg_cval;
 
// ModuleWare signal declarations(v1.9) for instance 'U_5' of 'adff'
reg [7:0] mw_U_5reg_cval;
 
// ModuleWare code(v1.9) for instance 'U_0' of 'adff'
 
assign q_a_o_internal = mw_U_0reg_cval;
 
always @(clk_clk_i or rst_rst_n_i)
begin : u_0seq_proc
if (rst_rst_n_i == 1'b 0 | rst_rst_n_i == 1'b 0)
begin
mw_U_0reg_cval <= 8'b 00000000;
end
else if (clk_clk_i /* ignored attribute: 'EVENT */ & clk_clk_i == 1'b 1 )
begin
if (load_o_i == 1'b 1 | load_o_i == 1'b 1)
begin
mw_U_0reg_cval <= q_mux_o_i;
end
end
end
 
// ModuleWare code(v1.9) for instance 'U_4' of 'adff'
assign q_x_o_internal = mw_U_4reg_cval;
 
always @(clk_clk_i or rst_rst_n_i)
begin : u_4seq_proc
if (rst_rst_n_i == 1'b 0 | rst_rst_n_i == 1'b 0)
begin
mw_U_4reg_cval <= 8'b 00000000;
end
else if (clk_clk_i /* ignored attribute: 'EVENT */ & clk_clk_i == 1'b 1 )
begin
if (load1_o_i == 1'b 1 | load1_o_i == 1'b 1)
begin
mw_U_4reg_cval <= q_mux_o_i;
end
end
end
 
// ModuleWare code(v1.9) for instance 'U_5' of 'adff'
assign q_y_o_internal = mw_U_5reg_cval;
 
always @(clk_clk_i or rst_rst_n_i)
begin : u_5seq_proc
if (rst_rst_n_i == 1'b 0 | rst_rst_n_i == 1'b 0)
begin
mw_U_5reg_cval <= 8'b 00000000;
end
else if (clk_clk_i /* ignored attribute: 'EVENT */ & clk_clk_i == 1'b 1 )
begin
if (load2_o_i == 1'b 1 | load2_o_i == 1'b 1)
begin
mw_U_5reg_cval <= q_mux_o_i;
end
end
end
 
// ModuleWare code(v1.9) for instance 'U_6' of 'and'
assign load_o_i = load_regs_i & ld[0];
 
// ModuleWare code(v1.9) for instance 'U_7' of 'and'
assign load1_o_i = load_regs_i & ld[1];
 
// ModuleWare code(v1.9) for instance 'U_8' of 'and'
assign load2_o_i = load_regs_i & ld[2];
 
// ModuleWare code(v1.9) for instance 'U_11' of 'constval'
assign val_zero = 8'b 00000000;
 
// ModuleWare code(v1.9) for instance 'U_1' of 'decoder1'
 
always @(sel_reg_i)
begin : u_1combo_proc
ld <= {3{1'b 0}};
case (sel_reg_i)
2'b 00:
begin
ld[0] <= 1'b 1;
end
2'b 01:
begin
ld[1] <= 1'b 1;
end
2'b 10:
begin
ld[2] <= 1'b 1;
end
default:
begin
ld <= {3{1'b 0}};
end
endcase
end
 
// ModuleWare code(v1.9) for instance 'U_2' of 'mux'
 
always @(q_a_o_internal or q_x_o_internal or q_y_o_internal or val_zero or sel_rb_out_i)
begin : u_2combo_proc
case (sel_rb_out_i)
2'b 00,
2'b 00,
2'b 00,
2'b 00:
begin
d_regs_out_o <= q_a_o_internal;
end
2'b 01,
2'b 01,
2'b 01,
2'b 01:
begin
d_regs_out_o <= q_x_o_internal;
end
2'b 10,
2'b 10,
2'b 10,
2'b 10:
begin
d_regs_out_o <= q_y_o_internal;
end
2'b 11,
2'b 11,
2'b 11,
2'b 11:
begin
d_regs_out_o <= val_zero;
end
default:
begin
d_regs_out_o <= {8{1'b X}};
end
endcase
end
 
// ModuleWare code(v1.9) for instance 'U_3' of 'mux'
 
always @(q_a_o_internal or q_y_o_internal or q_x_o_internal or d_regs_in_i or sel_rb_in_i)
begin : u_3combo_proc
case (sel_rb_in_i)
2'b 00,
2'b 00,
2'b 00,
2'b 00:
begin
q_mux_o_i <= q_a_o_internal;
end
2'b 01,
2'b 01,
2'b 01,
2'b 01:
begin
q_mux_o_i <= q_y_o_internal;
end
2'b 10,
2'b 10,
2'b 10,
2'b 10:
begin
q_mux_o_i <= q_x_o_internal;
end
2'b 11,
2'b 11,
2'b 11,
2'b 11:
begin
q_mux_o_i <= d_regs_in_i;
end
default:
begin
q_mux_o_i <= {8{1'b X}};
end
endcase
end
 
// Instance port mappings.
// Implicit buffered output assignments
assign q_a_o = q_a_o_internal;
assign q_x_o = q_x_o_internal;
assign q_y_o = q_y_o_internal;
 
// Architecture declarations
// Internal signal declarations
 
endmodule // module RegBank_AXY
 
/trunk/rtl/vhdl/R6502_TC_config.vhd File deleted
/trunk/rtl/vhdl/reg_pc.vhd
1,8 → 1,8
-- VHDL Entity R6502_TC.Reg_PC.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:53:05 04.01.2009
-- by - eda.UNKNOWN (TEST)
-- at - 19:07:21 07.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
10,24 → 10,23
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
entity Reg_PC is
port(
adr_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic;
ld_i : in std_logic_vector (1 downto 0);
ld_pc_i : in std_logic;
offset_i : in std_logic_vector (15 downto 0);
rst_rst_n_i : in std_logic;
sel_pc_as_i : in std_logic;
sel_pc_in_i : in std_logic;
sel_pc_val_i : in std_logic_vector (1 downto 0);
adr_nxt_pc_o : out std_logic_vector (15 downto 0);
adr_pc_o : out std_logic_vector (15 downto 0)
ENTITY Reg_PC IS
PORT(
adr_i : IN std_logic_vector (15 DOWNTO 0);
clk_clk_i : IN std_logic;
ld_i : IN std_logic_vector (1 DOWNTO 0);
ld_pc_i : IN std_logic;
offset_i : IN std_logic_vector (15 DOWNTO 0);
rst_rst_n_i : IN std_logic;
sel_pc_in_i : IN std_logic;
sel_pc_val_i : IN std_logic_vector (1 DOWNTO 0);
adr_nxt_pc_o : OUT std_logic_vector (15 DOWNTO 0);
adr_pc_o : OUT std_logic_vector (15 DOWNTO 0)
);
 
-- Declarations
 
end Reg_PC ;
END Reg_PC ;
 
-- Jens-D. Gutschmidt Project: R6502_TC
-- scantara2003@yahoo.de
47,13 → 46,13
-- <<-- more -->>
-- Title: Program Counter Logic
-- Path: R6502_TC/Reg_PC/struct
-- Edited: by eda on 01 Jan 2009
-- Edited: by eda on 07 Jan 2009
--
-- VHDL Architecture R6502_TC.Reg_PC.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:53:06 04.01.2009
-- by - eda.UNKNOWN (TEST)
-- at - 19:07:21 07.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
62,114 → 61,107
USE ieee.std_logic_arith.all;
 
 
architecture struct of Reg_PC is
ARCHITECTURE struct OF Reg_PC IS
 
-- Architecture declarations
 
-- Internal signal declarations
signal adr_pc_high_o_i : std_logic_vector(7 downto 0);
signal adr_pc_low_o_i : std_logic_vector(7 downto 0);
signal adr_pc_o_i : std_logic_vector(15 downto 0);
signal as_n_o_i : std_logic;
signal ci_o_i : std_logic;
signal cout_pc_o_i : std_logic;
signal load3_o_i : std_logic;
signal load_o_i : std_logic;
signal offset_high_o_i : std_logic_vector(7 downto 0);
signal offset_low_o_i : std_logic_vector(7 downto 0);
signal val_o_i : std_logic_vector(7 downto 0);
signal val_one : std_logic_vector(7 downto 0);
signal val_zero : std_logic_vector(7 downto 0);
SIGNAL adr_pc_high_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL adr_pc_low_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL adr_pc_o_i : std_logic_vector(15 DOWNTO 0);
SIGNAL ci_o_i : std_logic;
SIGNAL cout_pc_o_i : std_logic;
SIGNAL load3_o_i : std_logic;
SIGNAL load_o_i : std_logic;
SIGNAL offset_high_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL offset_low_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL val_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL val_one : std_logic_vector(7 DOWNTO 0);
SIGNAL val_zero : std_logic_vector(7 DOWNTO 0);
 
-- Implicit buffer signal declarations
signal adr_pc_o_internal : std_logic_vector (15 downto 0);
signal adr_nxt_pc_o_internal : std_logic_vector (15 downto 0);
SIGNAL adr_pc_o_internal : std_logic_vector (15 DOWNTO 0);
SIGNAL adr_nxt_pc_o_internal : std_logic_vector (15 DOWNTO 0);
 
 
-- ModuleWare signal declarations(v1.9) for instance 'U_11' of 'addsub'
signal mw_U_11temp_din0 : std_logic_vector(8 downto 0);
signal mw_U_11temp_din1 : std_logic_vector(8 downto 0);
signal mw_U_11sum : unsigned(8 downto 0);
 
-- ModuleWare signal declarations(v1.9) for instance 'U_12' of 'addsub'
signal mw_U_12temp_din0 : std_logic_vector(8 downto 0);
signal mw_U_12temp_din1 : std_logic_vector(8 downto 0);
signal mw_U_12sum : unsigned(8 downto 0);
 
-- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
signal mw_U_0reg_cval : std_logic_vector(7 downto 0);
SIGNAL mw_U_0reg_cval : std_logic_vector(7 DOWNTO 0);
 
-- ModuleWare signal declarations(v1.9) for instance 'U_4' of 'adff'
signal mw_U_4reg_cval : std_logic_vector(7 downto 0);
SIGNAL mw_U_4reg_cval : std_logic_vector(7 DOWNTO 0);
 
-- ModuleWare signal declarations(v1.9) for instance 'U_3' of 'split'
SIGNAL mw_U_3temp_din : std_logic_vector(15 DOWNTO 0);
 
begin
-- ModuleWare signal declarations(v1.9) for instance 'U_5' of 'split'
SIGNAL mw_U_5temp_din : std_logic_vector(15 DOWNTO 0);
 
-- ModuleWare code(v1.9) for instance 'U_11' of 'addsub'
mw_U_11temp_din0 <= '0' & adr_pc_low_o_i;
mw_U_11temp_din1 <= '0' & val_o_i;
u_11combo_proc: process (mw_U_11temp_din0, mw_U_11temp_din1, as_n_o_i)
variable temp_carry : std_logic;
begin
 
BEGIN
 
-- ModuleWare code(v1.9) for instance 'U_2' of 'add'
u_2combo_proc: PROCESS (adr_pc_low_o_i, val_o_i)
VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0);
VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0);
VARIABLE temp_sum : unsigned(8 DOWNTO 0);
VARIABLE temp_carry : std_logic;
BEGIN
temp_din0 := '0' & adr_pc_low_o_i;
temp_din1 := '0' & val_o_i;
temp_carry := '0';
if (as_n_o_i = '1') then
mw_U_11sum <= unsigned(mw_U_11temp_din0) + unsigned(mw_U_11temp_din1) + temp_carry;
else
mw_U_11sum <= unsigned(mw_U_11temp_din0) - unsigned(mw_U_11temp_din1) - temp_carry;
end if;
end process u_11combo_proc;
adr_nxt_pc_o_internal(7 DOWNTO 0) <= conv_std_logic_vector(mw_U_11sum(7 downto 0),8);
cout_pc_o_i <= mw_U_11sum(8);
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
adr_nxt_pc_o_internal(7 DOWNTO 0) <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8);
cout_pc_o_i <= temp_sum(8) ;
END PROCESS u_2combo_proc;
 
-- ModuleWare code(v1.9) for instance 'U_12' of 'addsub'
mw_U_12temp_din0 <= '0' & adr_pc_high_o_i;
mw_U_12temp_din1 <= '0' & offset_high_o_i;
u_12combo_proc: process (mw_U_12temp_din0, mw_U_12temp_din1, as_n_o_i, ci_o_i)
variable temp_carry : std_logic;
begin
-- ModuleWare code(v1.9) for instance 'U_11' of 'add'
u_11combo_proc: PROCESS (adr_pc_high_o_i, offset_high_o_i, ci_o_i)
VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0);
VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0);
VARIABLE temp_sum : unsigned(8 DOWNTO 0);
VARIABLE temp_carry : std_logic;
BEGIN
temp_din0 := '0' & adr_pc_high_o_i;
temp_din1 := '0' & offset_high_o_i;
temp_carry := ci_o_i;
if (as_n_o_i = '1') then
mw_U_12sum <= unsigned(mw_U_12temp_din0) + unsigned(mw_U_12temp_din1) + temp_carry;
else
mw_U_12sum <= unsigned(mw_U_12temp_din0) - unsigned(mw_U_12temp_din1) - temp_carry;
end if;
end process u_12combo_proc;
adr_nxt_pc_o_internal(15 DOWNTO 8) <= conv_std_logic_vector(mw_U_12sum(7 downto 0),8);
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
adr_nxt_pc_o_internal(15 DOWNTO 8) <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8);
END PROCESS u_11combo_proc;
 
-- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
adr_pc_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
u_0seq_proc: process (clk_clk_i, rst_rst_n_i)
begin
if (rst_rst_n_i = '0') then
u_0seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
BEGIN
IF (rst_rst_n_i = '0' OR rst_rst_n_i = 'L') THEN
mw_U_0reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1') then
if (load_o_i = '1') then
ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
IF (load_o_i = '1' OR load_o_i = 'H') THEN
mw_U_0reg_cval <= adr_nxt_pc_o_internal(7 DOWNTO 0);
end if;
end if;
end process u_0seq_proc;
END IF;
END IF;
END PROCESS u_0seq_proc;
 
-- ModuleWare code(v1.9) for instance 'U_4' of 'adff'
adr_pc_o_internal(15 DOWNTO 8) <= mw_U_4reg_cval;
u_4seq_proc: process (clk_clk_i, rst_rst_n_i)
begin
if (rst_rst_n_i = '0') then
u_4seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
BEGIN
IF (rst_rst_n_i = '0' OR rst_rst_n_i = 'L') THEN
mw_U_4reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1') then
if (load3_o_i = '1') then
ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
IF (load3_o_i = '1' OR load3_o_i = 'H') THEN
mw_U_4reg_cval <= adr_nxt_pc_o_internal(15 DOWNTO 8);
end if;
end if;
end process u_4seq_proc;
END IF;
END IF;
END PROCESS u_4seq_proc;
 
-- ModuleWare code(v1.9) for instance 'U_6' of 'and'
load_o_i <= ld_pc_i and ld_i(0);
load_o_i <= ld_pc_i AND ld_i(0);
 
-- ModuleWare code(v1.9) for instance 'U_7' of 'and'
load3_o_i <= ld_pc_i and ld_i(1);
load3_o_i <= ld_pc_i AND ld_i(1);
 
-- ModuleWare code(v1.9) for instance 'U_10' of 'and'
ci_o_i <= cout_pc_o_i and ld_pc_i;
ci_o_i <= cout_pc_o_i AND ld_pc_i;
 
-- ModuleWare code(v1.9) for instance 'U_1' of 'constval'
val_zero <= "00000000";
177,39 → 169,48
-- ModuleWare code(v1.9) for instance 'U_9' of 'constval'
val_one <= "00000001";
 
-- ModuleWare code(v1.9) for instance 'U_2' of 'inv'
as_n_o_i <= not(sel_pc_as_i);
 
-- ModuleWare code(v1.9) for instance 'U_8' of 'mux'
u_8combo_proc: process(adr_pc_o_internal, adr_i, sel_pc_in_i)
begin
case sel_pc_in_i is
when '0' => adr_pc_o_i <= adr_pc_o_internal;
when '1' => adr_pc_o_i <= adr_i;
when others => adr_pc_o_i <= (others => 'X');
end case;
end process u_8combo_proc;
u_8combo_proc: PROCESS(adr_pc_o_internal, adr_i, sel_pc_in_i)
BEGIN
CASE sel_pc_in_i IS
WHEN '0'|'L' => adr_pc_o_i <= adr_pc_o_internal;
WHEN '1'|'H' => adr_pc_o_i <= adr_i;
WHEN OTHERS => adr_pc_o_i <= (OTHERS => 'X');
END CASE;
END PROCESS u_8combo_proc;
 
-- ModuleWare code(v1.9) for instance 'U_13' of 'mux'
u_13combo_proc: process(val_one, val_zero, offset_low_o_i,
u_13combo_proc: PROCESS(val_one, val_zero, offset_low_o_i,
sel_pc_val_i)
begin
case sel_pc_val_i is
when "00" => val_o_i <= val_one;
when "01" => val_o_i <= val_zero;
when "10" => val_o_i <= offset_low_o_i;
when "11" => val_o_i <= val_zero;
when others => val_o_i <= (others => 'X');
end case;
end process u_13combo_proc;
BEGIN
CASE sel_pc_val_i IS
WHEN "00"|"L0"|"0L"|"LL" => val_o_i <= val_one;
WHEN "01"|"L1"|"0H"|"LH" => val_o_i <= val_zero;
WHEN "10"|"H0"|"1L"|"HL" => val_o_i <= offset_low_o_i;
WHEN "11"|"H1"|"1H"|"HH" => val_o_i <= val_zero;
WHEN OTHERS => val_o_i <= (OTHERS => 'X');
END CASE;
END PROCESS u_13combo_proc;
 
-- ModuleWare code(v1.9) for instance 'U_3' of 'split'
adr_pc_low_o_i <= adr_pc_o_i(7 downto 0);
adr_pc_high_o_i <= adr_pc_o_i(15 downto 8);
mw_U_3temp_din <= adr_pc_o_i;
u_3combo_proc: PROCESS (mw_U_3temp_din)
VARIABLE temp_din: std_logic_vector(15 DOWNTO 0);
BEGIN
temp_din := mw_U_3temp_din(15 DOWNTO 0);
adr_pc_low_o_i <= temp_din(7 DOWNTO 0);
adr_pc_high_o_i <= temp_din(15 DOWNTO 8);
END PROCESS u_3combo_proc;
 
-- ModuleWare code(v1.9) for instance 'U_5' of 'split'
offset_low_o_i <= offset_i(7 downto 0);
offset_high_o_i <= offset_i(15 downto 8);
mw_U_5temp_din <= offset_i;
u_5combo_proc: PROCESS (mw_U_5temp_din)
VARIABLE temp_din: std_logic_vector(15 DOWNTO 0);
BEGIN
temp_din := mw_U_5temp_din(15 DOWNTO 0);
offset_low_o_i <= temp_din(7 DOWNTO 0);
offset_high_o_i <= temp_din(15 DOWNTO 8);
END PROCESS u_5combo_proc;
 
-- Instance port mappings.
 
217,4 → 218,4
adr_pc_o <= adr_pc_o_internal;
adr_nxt_pc_o <= adr_nxt_pc_o_internal;
 
end struct;
END struct;
/trunk/rtl/vhdl/reg_sp.vhd
1,8 → 1,8
-- VHDL Entity R6502_TC.Reg_SP.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:53:06 04.01.2009
-- by - eda.UNKNOWN (TEST)
-- at - 18:23:46 07.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
10,21 → 10,21
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
entity Reg_SP is
port(
adr_low_i : in std_logic_vector (7 downto 0);
clk_clk_i : in std_logic;
ld_low_i : in std_logic;
ld_sp_i : in std_logic;
rst_rst_n_i : in std_logic;
sel_sp_as_i : in std_logic;
sel_sp_in_i : in std_logic;
adr_sp_o : out std_logic_vector (15 downto 0)
ENTITY Reg_SP IS
PORT(
adr_low_i : IN std_logic_vector (7 DOWNTO 0);
clk_clk_i : IN std_logic;
ld_low_i : IN std_logic;
ld_sp_i : IN std_logic;
rst_rst_n_i : IN std_logic;
sel_sp_as_i : IN std_logic;
sel_sp_in_i : IN std_logic;
adr_sp_o : OUT std_logic_vector (15 DOWNTO 0)
);
 
-- Declarations
 
end Reg_SP ;
END Reg_SP ;
 
-- Jens-D. Gutschmidt Project: R6502_TC
-- scantara2003@yahoo.de
49,8 → 49,8
-- VHDL Architecture R6502_TC.Reg_SP.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:53:06 04.01.2009
-- by - eda.UNKNOWN (TEST)
-- at - 18:23:46 07.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
59,63 → 59,61
USE ieee.std_logic_arith.all;
 
 
architecture struct of Reg_SP is
ARCHITECTURE struct OF Reg_SP IS
 
-- Architecture declarations
 
-- Internal signal declarations
signal adr_sp_low_o_i : std_logic_vector(7 downto 0);
signal load_o_i : std_logic;
signal result_low1_o_i : std_logic_vector(7 downto 0);
signal result_low_o_i : std_logic_vector(7 downto 0);
signal sp_as_n_o_i : std_logic;
signal val_one : std_logic_vector(7 downto 0);
SIGNAL adr_sp_low_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL load_o_i : std_logic;
SIGNAL result_low1_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL result_low_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL sp_as_n_o_i : std_logic;
SIGNAL val_one : std_logic_vector(7 DOWNTO 0);
 
-- Implicit buffer signal declarations
signal adr_sp_o_internal : std_logic_vector (15 downto 0);
SIGNAL adr_sp_o_internal : std_logic_vector (15 DOWNTO 0);
 
 
-- ModuleWare signal declarations(v1.9) for instance 'U_11' of 'addsub'
signal mw_U_11temp_din0 : std_logic_vector(8 downto 0);
signal mw_U_11temp_din1 : std_logic_vector(8 downto 0);
signal mw_U_11sum : unsigned(8 downto 0);
 
-- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
signal mw_U_0reg_cval : std_logic_vector(7 downto 0);
SIGNAL mw_U_0reg_cval : std_logic_vector(7 DOWNTO 0);
 
 
begin
BEGIN
 
-- ModuleWare code(v1.9) for instance 'U_11' of 'addsub'
mw_U_11temp_din0 <= '0' & adr_sp_low_o_i;
mw_U_11temp_din1 <= '0' & val_one;
u_11combo_proc: process (mw_U_11temp_din0, mw_U_11temp_din1, sp_as_n_o_i)
variable temp_carry : std_logic;
begin
u_11combo_proc: PROCESS (adr_sp_low_o_i, val_one, sp_as_n_o_i)
VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0);
VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0);
VARIABLE temp_sum : unsigned(8 DOWNTO 0);
VARIABLE temp_carry : std_logic;
BEGIN
temp_din0 := '0' & adr_sp_low_o_i;
temp_din1 := '0' & val_one;
temp_carry := '0';
if (sp_as_n_o_i = '1') then
mw_U_11sum <= unsigned(mw_U_11temp_din0) + unsigned(mw_U_11temp_din1) + temp_carry;
else
mw_U_11sum <= unsigned(mw_U_11temp_din0) - unsigned(mw_U_11temp_din1) - temp_carry;
end if;
end process u_11combo_proc;
result_low_o_i <= conv_std_logic_vector(mw_U_11sum(7 downto 0),8);
IF (sp_as_n_o_i = '1' OR sp_as_n_o_i = 'H') THEN
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
ELSE
temp_sum := unsigned(temp_din0) - unsigned(temp_din1) - temp_carry;
END IF;
result_low_o_i <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8);
END PROCESS u_11combo_proc;
 
-- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
adr_sp_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
u_0seq_proc: process (clk_clk_i, rst_rst_n_i)
begin
if (rst_rst_n_i = '0') then
u_0seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
BEGIN
IF (rst_rst_n_i = '0' OR rst_rst_n_i = 'L') THEN
mw_U_0reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1') then
if (load_o_i = '1') then
ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
IF (load_o_i = '1' OR load_o_i = 'H') THEN
mw_U_0reg_cval <= result_low1_o_i;
end if;
end if;
end process u_0seq_proc;
END IF;
END IF;
END PROCESS u_0seq_proc;
 
-- ModuleWare code(v1.9) for instance 'U_6' of 'and'
load_o_i <= ld_sp_i and ld_low_i;
load_o_i <= ld_sp_i AND ld_low_i;
 
-- ModuleWare code(v1.9) for instance 'U_3' of 'buff'
adr_sp_o_internal(15 DOWNTO 8) <= val_one;
124,20 → 122,20
val_one <= "00000001";
 
-- ModuleWare code(v1.9) for instance 'U_2' of 'inv'
sp_as_n_o_i <= not(sel_sp_as_i);
sp_as_n_o_i <= NOT(sel_sp_as_i);
 
-- ModuleWare code(v1.9) for instance 'U_8' of 'mux'
u_8combo_proc: process(result_low_o_i, adr_low_i, sel_sp_in_i)
begin
case sel_sp_in_i is
when '0' => result_low1_o_i <= result_low_o_i;
when '1' => result_low1_o_i <= adr_low_i;
when others => result_low1_o_i <= (others => 'X');
end case;
end process u_8combo_proc;
u_8combo_proc: PROCESS(result_low_o_i, adr_low_i, sel_sp_in_i)
BEGIN
CASE sel_sp_in_i IS
WHEN '0'|'L' => result_low1_o_i <= result_low_o_i;
WHEN '1'|'H' => result_low1_o_i <= adr_low_i;
WHEN OTHERS => result_low1_o_i <= (OTHERS => 'X');
END CASE;
END PROCESS u_8combo_proc;
 
-- ModuleWare code(v1.9) for instance 'U_10' of 'tap'
adr_sp_low_o_i <= adr_sp_o_internal(7 downto 0);
adr_sp_low_o_i <= adr_sp_o_internal(7 DOWNTO 0);
 
-- Instance port mappings.
 
144,4 → 142,4
-- Implicit buffered output assignments
adr_sp_o <= adr_sp_o_internal;
 
end struct;
END struct;
/trunk/rtl/vhdl/r6502_tc.vhd
1,8 → 1,8
-- VHDL Entity R6502_TC.R6502_TC.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:53:22 04.01.2009
-- by - eda.UNKNOWN (TEST)
-- at - 19:21:55 07.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
10,26 → 10,26
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
entity R6502_TC is
port(
clk_clk_i : in std_logic;
d_i : in std_logic_vector (7 downto 0);
irq_n_i : in std_logic;
nmi_n_i : in std_logic;
rdy_i : in std_logic;
rst_rst_n_i : in std_logic;
so_n_i : in std_logic;
a_o : out std_logic_vector (15 downto 0);
d_o : out std_logic_vector (7 downto 0);
rd_o : out std_logic;
sync_o : out std_logic;
wr_n_o : out std_logic;
wr_o : out std_logic
ENTITY R6502_TC IS
PORT(
clk_clk_i : IN std_logic;
d_i : IN std_logic_vector (7 DOWNTO 0);
irq_n_i : IN std_logic;
nmi_n_i : IN std_logic;
rdy_i : IN std_logic;
rst_rst_n_i : IN std_logic;
so_n_i : IN std_logic;
a_o : OUT std_logic_vector (15 DOWNTO 0);
d_o : OUT std_logic_vector (7 DOWNTO 0);
rd_o : OUT std_logic;
sync_o : OUT std_logic;
wr_n_o : OUT std_logic;
wr_o : OUT std_logic
);
 
-- Declarations
 
end R6502_TC ;
END R6502_TC ;
 
-- Jens-D. Gutschmidt Project: R6502_TC
-- scantara2003@yahoo.de
54,8 → 54,8
-- VHDL Architecture R6502_TC.R6502_TC.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:53:22 04.01.2009
-- by - eda.UNKNOWN (TEST)
-- at - 19:21:55 07.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
62,9 → 62,8
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
library R6502_TC;
 
architecture struct of R6502_TC is
ARCHITECTURE struct OF R6502_TC IS
 
-- Architecture declarations
 
72,35 → 71,30
 
 
-- Component Declarations
component Core
port (
clk_clk_i : in std_logic ;
d_i : in std_logic_vector (7 downto 0);
irq_n_i : in std_logic ;
nmi_n_i : in std_logic ;
rdy_i : in std_logic ;
rst_rst_n_i : in std_logic ;
so_n_i : in std_logic ;
a_o : out std_logic_vector (15 downto 0);
d_o : out std_logic_vector (7 downto 0);
rd_o : out std_logic ;
sync_o : out std_logic ;
wr_n_o : out std_logic ;
wr_o : out std_logic
COMPONENT Core
PORT (
clk_clk_i : IN std_logic ;
d_i : IN std_logic_vector (7 DOWNTO 0);
irq_n_i : IN std_logic ;
nmi_n_i : IN std_logic ;
rdy_i : IN std_logic ;
rst_rst_n_i : IN std_logic ;
so_n_i : IN std_logic ;
a_o : OUT std_logic_vector (15 DOWNTO 0);
d_o : OUT std_logic_vector (7 DOWNTO 0);
rd_o : OUT std_logic ;
sync_o : OUT std_logic ;
wr_n_o : OUT std_logic ;
wr_o : OUT std_logic
);
end component;
END COMPONENT;
 
-- Optional embedded configurations
-- pragma synthesis_off
for all : Core use entity R6502_TC.Core;
-- pragma synthesis_on
 
BEGIN
 
begin
 
-- Instance port mappings.
U_0 : Core
port map (
PORT MAP (
clk_clk_i => clk_clk_i,
d_i => d_i,
irq_n_i => irq_n_i,
116,4 → 110,4
wr_o => wr_o
);
 
end struct;
END struct;
/trunk/rtl/vhdl/fsm_execution_unit.vhd
1,8 → 1,8
-- VHDL Entity R6502_TC.FSM_Execution_Unit.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:53:07 04.01.2009
-- by - eda.UNKNOWN (TEST)
-- at - 19:21:47 07.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
10,55 → 10,54
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
entity FSM_Execution_Unit is
port(
adr_nxt_pc_i : in std_logic_vector (15 downto 0);
adr_pc_i : in std_logic_vector (15 downto 0);
adr_sp_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic;
d_alu_i : in std_logic_vector ( 7 downto 0 );
d_i : in std_logic_vector ( 7 downto 0 );
d_regs_out_i : in std_logic_vector ( 7 downto 0 );
irq_n_i : in std_logic;
nmi_i : in std_logic;
q_a_i : in std_logic_vector ( 7 downto 0 );
q_x_i : in std_logic_vector ( 7 downto 0 );
q_y_i : in std_logic_vector ( 7 downto 0 );
rdy_i : in std_logic;
reg_0flag_i : in std_logic;
reg_1flag_i : in std_logic;
reg_7flag_i : in std_logic;
rst_rst_n_i : in std_logic;
so_n_i : in std_logic;
a_o : out std_logic_vector (15 downto 0);
adr_o : out std_logic_vector (15 downto 0);
ch_a_o : out std_logic_vector ( 7 downto 0 );
ch_b_o : out std_logic_vector ( 7 downto 0 );
d_o : out std_logic_vector ( 7 downto 0 );
d_regs_in_o : out std_logic_vector ( 7 downto 0 );
fetch_o : out std_logic;
ld_o : out std_logic_vector ( 1 downto 0 );
ld_pc_o : out std_logic;
ld_sp_o : out std_logic;
load_regs_o : out std_logic;
offset_o : out std_logic_vector ( 15 downto 0 );
rd_o : out std_logic;
sel_pc_as_o : out std_logic;
sel_pc_in_o : out std_logic;
sel_pc_val_o : out std_logic_vector ( 1 downto 0 );
sel_rb_in_o : out std_logic_vector ( 1 downto 0 );
sel_rb_out_o : out std_logic_vector ( 1 downto 0 );
sel_reg_o : out std_logic_vector ( 1 downto 0 );
sel_sp_as_o : out std_logic;
sel_sp_in_o : out std_logic;
sync_o : out std_logic;
wr_n_o : out std_logic;
wr_o : out std_logic
ENTITY FSM_Execution_Unit IS
PORT(
adr_nxt_pc_i : IN std_logic_vector (15 DOWNTO 0);
adr_pc_i : IN std_logic_vector (15 DOWNTO 0);
adr_sp_i : IN std_logic_vector (15 DOWNTO 0);
clk_clk_i : IN std_logic;
d_alu_i : IN std_logic_vector ( 7 DOWNTO 0 );
d_i : IN std_logic_vector ( 7 DOWNTO 0 );
d_regs_out_i : IN std_logic_vector ( 7 DOWNTO 0 );
irq_n_i : IN std_logic;
nmi_i : IN std_logic;
q_a_i : IN std_logic_vector ( 7 DOWNTO 0 );
q_x_i : IN std_logic_vector ( 7 DOWNTO 0 );
q_y_i : IN std_logic_vector ( 7 DOWNTO 0 );
rdy_i : IN std_logic;
reg_0flag_i : IN std_logic;
reg_1flag_i : IN std_logic;
reg_7flag_i : IN std_logic;
rst_rst_n_i : IN std_logic;
so_n_i : IN std_logic;
a_o : OUT std_logic_vector (15 DOWNTO 0);
adr_o : OUT std_logic_vector (15 DOWNTO 0);
ch_a_o : OUT std_logic_vector ( 7 DOWNTO 0 );
ch_b_o : OUT std_logic_vector ( 7 DOWNTO 0 );
d_o : OUT std_logic_vector ( 7 DOWNTO 0 );
d_regs_in_o : OUT std_logic_vector ( 7 DOWNTO 0 );
fetch_o : OUT std_logic;
ld_o : OUT std_logic_vector ( 1 DOWNTO 0 );
ld_pc_o : OUT std_logic;
ld_sp_o : OUT std_logic;
load_regs_o : OUT std_logic;
offset_o : OUT std_logic_vector ( 15 DOWNTO 0 );
rd_o : OUT std_logic;
sel_pc_in_o : OUT std_logic;
sel_pc_val_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_rb_in_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_rb_out_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_reg_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_sp_as_o : OUT std_logic;
sel_sp_in_o : OUT std_logic;
sync_o : OUT std_logic;
wr_n_o : OUT std_logic;
wr_o : OUT std_logic
);
 
-- Declarations
 
end FSM_Execution_Unit ;
END FSM_Execution_Unit ;
 
-- Jens-D. Gutschmidt Project: R6502_TC
 
96,14 → 95,14
 
-- Path: R6502_TC/FSM_Execution_Unit/fsm
 
-- Edited: by eda on 04 Jan 2009
-- Edited: by eda on 07 Jan 2009
 
--
-- VHDL Architecture R6502_TC.FSM_Execution_Unit.fsm
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:53:08 04.01.2009
-- by - eda.UNKNOWN (TEST)
-- at - 19:21:50 07.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
111,215 → 110,202
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
architecture fsm of FSM_Execution_Unit is
ARCHITECTURE fsm OF FSM_Execution_Unit IS
 
-- Architecture Declarations
signal reg_F : std_logic_vector( 7 DOWNTO 0 );
signal reg_PC : std_logic_vector(15 DOWNTO 0);
signal reg_PC1 : std_logic_vector( 15 DOWNTO 0 );
signal reg_sel_pc_as : std_logic;
signal reg_sel_pc_in : std_logic;
signal reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_reg : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_sp_as : std_logic;
signal reg_sel_sp_in : std_logic;
signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );
signal sig_PC : std_logic_vector(15 DOWNTO 0);
signal sig_RD : std_logic;
signal sig_RWn : std_logic;
signal sig_SYNC : std_logic;
signal sig_WR : std_logic;
signal zw_ALU : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU1 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU2 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU3 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU4 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU5 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU6 : std_logic_vector( 8 DOWNTO 0 );
signal zw_PC : std_logic_vector( 15 DOWNTO 0 );
signal zw_REG_ALU : std_logic_vector( 8 DOWNTO 0 );
signal zw_REG_NMI : std_logic;
signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );
signal zw_REG_sig_PC : std_logic_vector(15 DOWNTO 0);
signal zw_b1 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b2 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b3 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b4 : std_logic_vector( 7 DOWNTO 0 );
signal zw_so : std_logic;
signal zw_w1 : std_logic_vector( 15 DOWNTO 0 );
signal zw_w2 : std_logic_vector( 15 DOWNTO 0 );
signal zw_w3 : std_logic_vector( 15 DOWNTO 0 );
SIGNAL reg_F : std_logic_vector( 7 DOWNTO 0 );
SIGNAL reg_sel_pc_in : std_logic;
SIGNAL reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 );
SIGNAL reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 );
SIGNAL reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 );
SIGNAL reg_sel_reg : std_logic_vector( 1 DOWNTO 0 );
SIGNAL reg_sel_sp_as : std_logic;
SIGNAL reg_sel_sp_in : std_logic;
SIGNAL sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );
SIGNAL sig_PC : std_logic_vector(15 DOWNTO 0);
SIGNAL sig_RD : std_logic;
SIGNAL sig_RWn : std_logic;
SIGNAL sig_SYNC : std_logic;
SIGNAL sig_WR : std_logic;
SIGNAL zw_ALU : std_logic_vector( 8 DOWNTO 0 );
SIGNAL zw_ALU1 : std_logic_vector( 4 DOWNTO 0 );
SIGNAL zw_ALU2 : std_logic_vector( 4 DOWNTO 0 );
SIGNAL zw_ALU3 : std_logic_vector( 4 DOWNTO 0 );
SIGNAL zw_ALU4 : std_logic_vector( 4 DOWNTO 0 );
SIGNAL zw_ALU5 : std_logic_vector( 3 DOWNTO 0 );
SIGNAL zw_ALU6 : std_logic_vector( 3 DOWNTO 0 );
SIGNAL zw_REG_NMI : std_logic;
SIGNAL zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );
SIGNAL zw_b1 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL zw_b2 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL zw_b3 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL zw_b4 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL zw_so : std_logic;
 
subtype state_type is
std_logic_vector(7 downto 0);
SUBTYPE STATE_TYPE IS
std_logic_vector(7 DOWNTO 0);
-- State vector declaration
attribute state_vector : string;
attribute state_vector of fsm : architecture is "current_state";
 
-- Hard encoding
constant FETCH : state_type := "00000000";
constant s1 : state_type := "00000001";
constant s2 : state_type := "00000011";
constant s5 : state_type := "00000010";
constant s3 : state_type := "00000110";
constant s4 : state_type := "00000111";
constant s12 : state_type := "00000101";
constant s16 : state_type := "00000100";
constant s17 : state_type := "00001100";
constant s24 : state_type := "00001101";
constant s25 : state_type := "00001111";
constant s271 : state_type := "00001110";
constant s273 : state_type := "00001010";
constant s304 : state_type := "00001011";
constant s307 : state_type := "00001001";
constant s177 : state_type := "00001000";
constant s180 : state_type := "00011000";
constant s181 : state_type := "00011001";
constant s182 : state_type := "00011011";
constant s183 : state_type := "00011010";
constant s184 : state_type := "00011110";
constant s185 : state_type := "00011111";
constant s186 : state_type := "00011101";
constant s187 : state_type := "00011100";
constant s188 : state_type := "00010100";
constant s189 : state_type := "00010101";
constant s190 : state_type := "00010111";
constant s191 : state_type := "00010110";
constant s192 : state_type := "00010010";
constant s193 : state_type := "00010011";
constant s377 : state_type := "00010001";
constant s381 : state_type := "00010000";
constant s378 : state_type := "00110000";
constant s382 : state_type := "00110001";
constant s379 : state_type := "00110011";
constant s383 : state_type := "00110010";
constant s384 : state_type := "00110110";
constant s380 : state_type := "00110111";
constant s385 : state_type := "00110101";
constant s386 : state_type := "00110100";
constant s387 : state_type := "00111100";
constant s388 : state_type := "00111101";
constant s389 : state_type := "00111111";
constant s391 : state_type := "00111110";
constant s392 : state_type := "00111010";
constant s390 : state_type := "00111011";
constant s393 : state_type := "00111001";
constant s394 : state_type := "00111000";
constant s395 : state_type := "00101000";
constant s396 : state_type := "00101001";
constant s397 : state_type := "00101011";
constant s398 : state_type := "00101010";
constant s399 : state_type := "00101110";
constant s400 : state_type := "00101111";
constant s401 : state_type := "00101101";
constant s526 : state_type := "00101100";
constant s527 : state_type := "00100100";
constant s528 : state_type := "00100101";
constant s529 : state_type := "00100111";
constant s530 : state_type := "00100110";
constant s531 : state_type := "00100010";
constant s544 : state_type := "00100011";
constant s545 : state_type := "00100001";
constant s546 : state_type := "00100000";
constant s547 : state_type := "01100000";
constant s549 : state_type := "01100001";
constant s550 : state_type := "01100011";
constant s404 : state_type := "01100010";
constant s556 : state_type := "01100110";
constant s557 : state_type := "01100111";
constant s579 : state_type := "01100101";
constant s201 : state_type := "01100100";
constant s202 : state_type := "01101100";
constant s210 : state_type := "01101101";
constant s211 : state_type := "01101111";
constant s215 : state_type := "01101110";
constant s217 : state_type := "01101010";
constant s218 : state_type := "01101011";
constant s222 : state_type := "01101001";
constant s223 : state_type := "01101000";
constant s224 : state_type := "01111000";
constant s225 : state_type := "01111001";
constant s226 : state_type := "01111011";
constant s243 : state_type := "01111010";
constant s244 : state_type := "01111110";
constant s247 : state_type := "01111111";
constant s344 : state_type := "01111101";
constant s343 : state_type := "01111100";
constant s250 : state_type := "01110100";
constant s251 : state_type := "01110101";
constant s351 : state_type := "01110111";
constant s361 : state_type := "01110110";
constant s360 : state_type := "01110010";
constant s403 : state_type := "01110011";
constant s406 : state_type := "01110001";
constant s407 : state_type := "01110000";
constant s409 : state_type := "01010000";
constant s412 : state_type := "01010001";
constant s413 : state_type := "01010011";
constant s416 : state_type := "01010010";
constant s418 : state_type := "01010110";
constant s510 : state_type := "01010111";
constant s553 : state_type := "01010101";
constant s555 : state_type := "01010100";
constant s558 : state_type := "01011100";
constant s560 : state_type := "01011101";
constant s561 : state_type := "01011111";
constant s563 : state_type := "01011110";
constant s564 : state_type := "01011010";
constant s565 : state_type := "01011011";
constant s566 : state_type := "01011001";
constant s266 : state_type := "01011000";
constant s301 : state_type := "01001000";
constant s302 : state_type := "01001001";
constant RES : state_type := "01001011";
constant s511 : state_type := "01001010";
constant s559 : state_type := "01001110";
constant s562 : state_type := "01001111";
constant s567 : state_type := "01001101";
constant s568 : state_type := "01001100";
constant s569 : state_type := "01000100";
constant s570 : state_type := "01000101";
constant s571 : state_type := "01000111";
constant s572 : state_type := "01000110";
constant s573 : state_type := "01000010";
constant s574 : state_type := "01000011";
constant s548 : state_type := "01000001";
constant s551 : state_type := "01000000";
constant s552 : state_type := "11000000";
constant s575 : state_type := "11000001";
constant s576 : state_type := "11000011";
constant s577 : state_type := "11000010";
constant s532 : state_type := "11000110";
constant s533 : state_type := "11000111";
constant s534 : state_type := "11000101";
constant s535 : state_type := "11000100";
constant s536 : state_type := "11001100";
constant s537 : state_type := "11001101";
CONSTANT FETCH : STATE_TYPE := "00000000";
CONSTANT s1 : STATE_TYPE := "00000001";
CONSTANT s2 : STATE_TYPE := "00000011";
CONSTANT s5 : STATE_TYPE := "00000010";
CONSTANT s3 : STATE_TYPE := "00000110";
CONSTANT s4 : STATE_TYPE := "00000111";
CONSTANT s12 : STATE_TYPE := "00000101";
CONSTANT s16 : STATE_TYPE := "00000100";
CONSTANT s17 : STATE_TYPE := "00001100";
CONSTANT s24 : STATE_TYPE := "00001101";
CONSTANT s25 : STATE_TYPE := "00001111";
CONSTANT s271 : STATE_TYPE := "00001110";
CONSTANT s273 : STATE_TYPE := "00001010";
CONSTANT s304 : STATE_TYPE := "00001011";
CONSTANT s307 : STATE_TYPE := "00001001";
CONSTANT s177 : STATE_TYPE := "00001000";
CONSTANT s180 : STATE_TYPE := "00011000";
CONSTANT s181 : STATE_TYPE := "00011001";
CONSTANT s182 : STATE_TYPE := "00011011";
CONSTANT s183 : STATE_TYPE := "00011010";
CONSTANT s184 : STATE_TYPE := "00011110";
CONSTANT s185 : STATE_TYPE := "00011111";
CONSTANT s186 : STATE_TYPE := "00011101";
CONSTANT s187 : STATE_TYPE := "00011100";
CONSTANT s188 : STATE_TYPE := "00010100";
CONSTANT s189 : STATE_TYPE := "00010101";
CONSTANT s190 : STATE_TYPE := "00010111";
CONSTANT s191 : STATE_TYPE := "00010110";
CONSTANT s192 : STATE_TYPE := "00010010";
CONSTANT s193 : STATE_TYPE := "00010011";
CONSTANT s377 : STATE_TYPE := "00010001";
CONSTANT s381 : STATE_TYPE := "00010000";
CONSTANT s378 : STATE_TYPE := "00110000";
CONSTANT s382 : STATE_TYPE := "00110001";
CONSTANT s379 : STATE_TYPE := "00110011";
CONSTANT s383 : STATE_TYPE := "00110010";
CONSTANT s384 : STATE_TYPE := "00110110";
CONSTANT s380 : STATE_TYPE := "00110111";
CONSTANT s385 : STATE_TYPE := "00110101";
CONSTANT s386 : STATE_TYPE := "00110100";
CONSTANT s387 : STATE_TYPE := "00111100";
CONSTANT s388 : STATE_TYPE := "00111101";
CONSTANT s389 : STATE_TYPE := "00111111";
CONSTANT s391 : STATE_TYPE := "00111110";
CONSTANT s392 : STATE_TYPE := "00111010";
CONSTANT s390 : STATE_TYPE := "00111011";
CONSTANT s393 : STATE_TYPE := "00111001";
CONSTANT s394 : STATE_TYPE := "00111000";
CONSTANT s395 : STATE_TYPE := "00101000";
CONSTANT s396 : STATE_TYPE := "00101001";
CONSTANT s397 : STATE_TYPE := "00101011";
CONSTANT s398 : STATE_TYPE := "00101010";
CONSTANT s399 : STATE_TYPE := "00101110";
CONSTANT s400 : STATE_TYPE := "00101111";
CONSTANT s401 : STATE_TYPE := "00101101";
CONSTANT s526 : STATE_TYPE := "00101100";
CONSTANT s527 : STATE_TYPE := "00100100";
CONSTANT s528 : STATE_TYPE := "00100101";
CONSTANT s529 : STATE_TYPE := "00100111";
CONSTANT s530 : STATE_TYPE := "00100110";
CONSTANT s531 : STATE_TYPE := "00100010";
CONSTANT s544 : STATE_TYPE := "00100011";
CONSTANT s545 : STATE_TYPE := "00100001";
CONSTANT s546 : STATE_TYPE := "00100000";
CONSTANT s547 : STATE_TYPE := "01100000";
CONSTANT s549 : STATE_TYPE := "01100001";
CONSTANT s550 : STATE_TYPE := "01100011";
CONSTANT s404 : STATE_TYPE := "01100010";
CONSTANT s556 : STATE_TYPE := "01100110";
CONSTANT s557 : STATE_TYPE := "01100111";
CONSTANT s579 : STATE_TYPE := "01100101";
CONSTANT s201 : STATE_TYPE := "01100100";
CONSTANT s202 : STATE_TYPE := "01101100";
CONSTANT s210 : STATE_TYPE := "01101101";
CONSTANT s211 : STATE_TYPE := "01101111";
CONSTANT s215 : STATE_TYPE := "01101110";
CONSTANT s217 : STATE_TYPE := "01101010";
CONSTANT s218 : STATE_TYPE := "01101011";
CONSTANT s222 : STATE_TYPE := "01101001";
CONSTANT s223 : STATE_TYPE := "01101000";
CONSTANT s224 : STATE_TYPE := "01111000";
CONSTANT s225 : STATE_TYPE := "01111001";
CONSTANT s226 : STATE_TYPE := "01111011";
CONSTANT s243 : STATE_TYPE := "01111010";
CONSTANT s244 : STATE_TYPE := "01111110";
CONSTANT s247 : STATE_TYPE := "01111111";
CONSTANT s344 : STATE_TYPE := "01111101";
CONSTANT s343 : STATE_TYPE := "01111100";
CONSTANT s250 : STATE_TYPE := "01110100";
CONSTANT s251 : STATE_TYPE := "01110101";
CONSTANT s351 : STATE_TYPE := "01110111";
CONSTANT s361 : STATE_TYPE := "01110110";
CONSTANT s360 : STATE_TYPE := "01110010";
CONSTANT s403 : STATE_TYPE := "01110011";
CONSTANT s406 : STATE_TYPE := "01110001";
CONSTANT s407 : STATE_TYPE := "01110000";
CONSTANT s409 : STATE_TYPE := "01010000";
CONSTANT s412 : STATE_TYPE := "01010001";
CONSTANT s413 : STATE_TYPE := "01010011";
CONSTANT s416 : STATE_TYPE := "01010010";
CONSTANT s418 : STATE_TYPE := "01010110";
CONSTANT s510 : STATE_TYPE := "01010111";
CONSTANT s553 : STATE_TYPE := "01010101";
CONSTANT s555 : STATE_TYPE := "01010100";
CONSTANT s558 : STATE_TYPE := "01011100";
CONSTANT s560 : STATE_TYPE := "01011101";
CONSTANT s561 : STATE_TYPE := "01011111";
CONSTANT s563 : STATE_TYPE := "01011110";
CONSTANT s564 : STATE_TYPE := "01011010";
CONSTANT s565 : STATE_TYPE := "01011011";
CONSTANT s566 : STATE_TYPE := "01011001";
CONSTANT s266 : STATE_TYPE := "01011000";
CONSTANT s301 : STATE_TYPE := "01001000";
CONSTANT s302 : STATE_TYPE := "01001001";
CONSTANT RES : STATE_TYPE := "01001011";
CONSTANT s511 : STATE_TYPE := "01001010";
CONSTANT s559 : STATE_TYPE := "01001110";
CONSTANT s562 : STATE_TYPE := "01001111";
CONSTANT s567 : STATE_TYPE := "01001101";
CONSTANT s568 : STATE_TYPE := "01001100";
CONSTANT s569 : STATE_TYPE := "01000100";
CONSTANT s570 : STATE_TYPE := "01000101";
CONSTANT s571 : STATE_TYPE := "01000111";
CONSTANT s572 : STATE_TYPE := "01000110";
CONSTANT s573 : STATE_TYPE := "01000010";
CONSTANT s574 : STATE_TYPE := "01000011";
CONSTANT s548 : STATE_TYPE := "01000001";
CONSTANT s551 : STATE_TYPE := "01000000";
CONSTANT s552 : STATE_TYPE := "11000000";
CONSTANT s575 : STATE_TYPE := "11000001";
CONSTANT s576 : STATE_TYPE := "11000011";
CONSTANT s577 : STATE_TYPE := "11000010";
CONSTANT s532 : STATE_TYPE := "11000110";
CONSTANT s533 : STATE_TYPE := "11000111";
CONSTANT s534 : STATE_TYPE := "11000101";
CONSTANT s535 : STATE_TYPE := "11000100";
CONSTANT s536 : STATE_TYPE := "11001100";
CONSTANT s537 : STATE_TYPE := "11001101";
 
-- Declare current and next state signals
signal current_state : state_type;
signal next_state : state_type;
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;
 
-- Declare any pre-registered internal signals
signal d_o_cld : std_logic_vector ( 7 downto 0 );
signal rd_o_cld : std_logic ;
signal sync_o_cld : std_logic ;
signal wr_n_o_cld : std_logic ;
signal wr_o_cld : std_logic ;
SIGNAL d_o_cld : std_logic_vector ( 7 DOWNTO 0 );
SIGNAL rd_o_cld : std_logic ;
SIGNAL sync_o_cld : std_logic ;
SIGNAL wr_n_o_cld : std_logic ;
SIGNAL wr_o_cld : std_logic ;
 
begin
BEGIN
 
-----------------------------------------------------------------
clocked_proc : process (
clocked_proc : PROCESS (
clk_clk_i,
rst_rst_n_i
)
-----------------------------------------------------------------
begin
if (rst_rst_n_i = '0') then
BEGIN
IF (rst_rst_n_i = '0') THEN
current_state <= RES;
-- Default Reset Values
d_o_cld <= X"00";
328,9 → 314,6
wr_n_o_cld <= '1';
wr_o_cld <= '0';
reg_F <= "00000100";
reg_PC <= X"0000";
reg_PC1 <= X"0000";
reg_sel_pc_as <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_rb_in <= "00";
339,26 → 322,17
reg_sel_sp_as <= '0';
reg_sel_sp_in <= '0';
sig_PC <= X"0000";
zw_PC <= X"0000";
zw_REG_ALU <= '0' & X"00";
zw_REG_NMI <= '0';
zw_REG_OP <= X"00";
zw_REG_sig_PC <= X"0000";
zw_b1 <= X"00";
zw_b2 <= X"00";
zw_b3 <= X"00";
zw_b4 <= X"00";
zw_so <= '0';
zw_w1 <= X"0000";
zw_w2 <= X"0000";
zw_w3 <= X"0000";
elsif (clk_clk_i'event and clk_clk_i = '1') then
ELSIF (clk_clk_i'EVENT AND clk_clk_i = '1') THEN
current_state <= next_state;
-- Default Assignment To Internals
reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0);
reg_PC <= reg_PC;
reg_PC1 <= reg_PC1;
reg_sel_pc_as <= reg_sel_pc_as;
reg_sel_pc_in <= reg_sel_pc_in;
reg_sel_pc_val <= reg_sel_pc_val;
reg_sel_rb_in <= reg_sel_rb_in;
367,19 → 341,13
reg_sel_sp_as <= reg_sel_sp_as;
reg_sel_sp_in <= reg_sel_sp_in;
sig_PC <= sig_PC;
zw_PC <= zw_PC;
zw_REG_ALU <= zw_REG_ALU;
zw_REG_NMI <= zw_REG_NMI or nmi_i;
zw_REG_OP <= zw_REG_OP;
zw_REG_sig_PC <= zw_REG_sig_PC;
zw_b1 <= zw_b1;
zw_b2 <= zw_b2;
zw_b3 <= zw_b3;
zw_b4 <= zw_b4;
zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6)));
zw_w1 <= zw_w1;
zw_w2 <= zw_w2;
zw_w3 <= zw_w3;
d_o_cld <= sig_D_OUT;
rd_o_cld <= sig_RD;
sync_o_cld <= sig_SYNC;
387,16 → 355,16
wr_o_cld <= sig_WR;
 
-- Combined Actions
case current_state is
when FETCH =>
CASE current_state IS
WHEN FETCH =>
zw_REG_OP <= d_i;
if ((nmi_i = '1') and (rdy_i = '1')) then
IF ((nmi_i = '1') AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
zw_REG_NMI <= '0';
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
ELSIF ((irq_n_i = '0' and
reg_F(2) = '0') AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"69" or
ELSIF ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
403,17 → 371,17
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") and (rdy_i = '1')) then
d_i = X"71") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
zw_b1(0) <= reg_F(7);
elsif ((d_i = X"06" or
ELSIF ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") and (rdy_i = '1')) then
d_i = X"1E") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"90" or
ELSIF ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
420,45 → 388,45
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") and (rdy_i = '1')) then
d_i = X"70") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
zw_b3 <= adr_nxt_pc_i (15 downto 8);
elsif ((d_i = X"24" or
d_i = X"2C") and (rdy_i = '1')) then
ELSIF ((d_i = X"24" or
d_i = X"2C") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"00") and (rdy_i = '1')) then
ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"18") and (rdy_i = '1')) then
elsif ((d_i = X"D8") and (rdy_i = '1')) then
elsif ((d_i = X"58") and (rdy_i = '1')) then
elsif ((d_i = X"B8") and (rdy_i = '1')) then
elsif ((d_i = X"E0" or
ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") and (rdy_i = '1')) then
d_i = X"EC") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "01";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"C0" or
ELSIF ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") and (rdy_i = '1')) then
d_i = X"CC") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "10";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"C6" or
ELSIF ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") and (rdy_i = '1')) then
d_i = X"DE") AND (rdy_i = '1')) THEN
zw_b4 <= X"FF";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"CA") and (rdy_i = '1')) then
ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
zw_b4 <= X"FF";
elsif ((d_i = X"88") and (rdy_i = '1')) then
ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "10";
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
zw_b4 <= X"FF";
elsif ((d_i = X"49" or
ELSIF ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
489,33 → 457,33
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") and (rdy_i = '1')) then
d_i = X"D1") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"E6" or
ELSIF ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") and (rdy_i = '1')) then
d_i = X"FE") AND (rdy_i = '1')) THEN
zw_b4 <= X"01";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"E8") and (rdy_i = '1')) then
ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
zw_b4 <= X"01";
elsif ((d_i = X"C8") and (rdy_i = '1')) then
ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "10";
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
zw_b4 <= X"01";
elsif ((d_i = X"4C" or
d_i = X"6C") and (rdy_i = '1')) then
ELSIF ((d_i = X"4C" or
d_i = X"6C") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"20") and (rdy_i = '1')) then
ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"A9" or
ELSIF ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
522,62 → 490,62
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") and (rdy_i = '1')) then
d_i = X"B1") AND (rdy_i = '1')) THEN
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"A2" or
ELSIF ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") and (rdy_i = '1')) then
d_i = X"BE") AND (rdy_i = '1')) THEN
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"A0" or
ELSIF ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") and (rdy_i = '1')) then
d_i = X"BC") AND (rdy_i = '1')) THEN
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"46" or
ELSIF ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") and (rdy_i = '1')) then
d_i = X"5E") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"EA") and (rdy_i = '1')) then
elsif ((d_i = X"48") and (rdy_i = '1')) then
ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"08") and (rdy_i = '1')) then
ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"68") and (rdy_i = '1')) then
ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"28") and (rdy_i = '1')) then
ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
elsif ((d_i = X"26" or
ELSIF ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") and (rdy_i = '1')) then
d_i = X"3E") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"66" or
ELSIF ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") and (rdy_i = '1')) then
d_i = X"7E") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"40") and (rdy_i = '1')) then
ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"60") and (rdy_i = '1')) then
ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
elsif ((d_i = X"E9" or
ELSIF ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
584,573 → 552,573
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") and (rdy_i = '1')) then
d_i = X"F1") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
zw_b1(0) <= reg_F(7);
elsif ((d_i = X"38") and (rdy_i = '1')) then
elsif ((d_i = X"F8") and (rdy_i = '1')) then
elsif ((d_i = X"78") and (rdy_i = '1')) then
elsif ((d_i = X"85" or
ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91") and (rdy_i = '1')) then
d_i = X"91") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "00";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"86" or
ELSIF ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") and (rdy_i = '1')) then
d_i = X"8E") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "01";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"84" or
ELSIF ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") and (rdy_i = '1')) then
d_i = X"8C") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "10";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"AA") and (rdy_i = '1')) then
ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "00";
reg_sel_reg <= "01";
reg_sel_rb_in <= "00";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"0A") and (rdy_i = '1')) then
ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"4A") and (rdy_i = '1')) then
ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"2A") and (rdy_i = '1')) then
ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"6A") and (rdy_i = '1')) then
ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"A8") and (rdy_i = '1')) then
ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "00";
reg_sel_reg <= "10";
reg_sel_rb_in <= "00";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"98") and (rdy_i = '1')) then
ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "10";
reg_sel_reg <= "00";
reg_sel_rb_in <= "01";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"BA") and (rdy_i = '1')) then
ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"8A") and (rdy_i = '1')) then
ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "01";
reg_sel_reg <= "00";
reg_sel_rb_in <= "10";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"9A") and (rdy_i = '1')) then
ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "01";
reg_sel_reg <= "11";
reg_sel_rb_in <= "11";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
end if;
when s1 =>
if (rdy_i = '1') then
END IF;
WHEN s1 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s2 =>
if (rdy_i = '1') then
END IF;
WHEN s2 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s5 =>
if (rdy_i = '1') then
END IF;
WHEN s5 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(3) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s3 =>
END IF;
WHEN s3 =>
sig_PC <= adr_pc_i;
if (rdy_i = '1') then
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(2) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s4 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
END IF;
WHEN s4 =>
IF (rdy_i = '1' and
zw_REG_OP = X"9A") THEN
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"BA") THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s12 =>
if (rdy_i = '1') then
END IF;
WHEN s12 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s16 =>
if (rdy_i = '1') then
END IF;
WHEN s16 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(3) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s17 =>
if (rdy_i = '1') then
END IF;
WHEN s17 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(2) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s24 =>
if (rdy_i = '1') then
END IF;
WHEN s24 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(6) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s25 =>
if (rdy_i = '1') then
END IF;
WHEN s25 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s271 =>
if (rdy_i = '1' and
zw_REG_OP = X"4C") then
END IF;
WHEN s271 =>
IF (rdy_i = '1' and
zw_REG_OP = X"4C") THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"6C") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"6C") THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
zw_b1 <= d_i;
end if;
when s273 =>
if (rdy_i = '1') then
END IF;
WHEN s273 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
zw_b2 <= d_i;
end if;
when s304 =>
if (rdy_i = '1') then
END IF;
WHEN s304 =>
IF (rdy_i = '1') THEN
sig_PC <= zw_b2 & adr_pc_i(7 downto 0);
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
end if;
when s307 =>
if (rdy_i = '1') then
END IF;
WHEN s307 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s177 =>
if (rdy_i = '1' and
END IF;
WHEN s177 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) then
zw_REG_OP = X"84")) THEN
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) then
zw_REG_OP = X"94")) THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) then
zw_REG_OP = X"8C")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"9D") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"9D") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"99") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"91") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"81") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"96") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
end if;
when s180 =>
if (rdy_i = '1') then
END IF;
WHEN s180 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s181 =>
if (rdy_i = '1') then
END IF;
WHEN s181 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s182 =>
if (rdy_i = '1') then
END IF;
WHEN s182 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s183 =>
if (rdy_i = '1') then
END IF;
WHEN s183 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
end if;
when s184 =>
END IF;
WHEN s184 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s185 =>
if (rdy_i = '1') then
WHEN s185 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
end if;
when s186 =>
if (rdy_i = '1') then
END IF;
WHEN s186 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
end if;
when s187 =>
END IF;
WHEN s187 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s188 =>
if (rdy_i = '1') then
WHEN s188 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s189 =>
if (rdy_i = '1') then
END IF;
WHEN s189 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s190 =>
END IF;
WHEN s190 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s191 =>
WHEN s191 =>
sig_PC <= zw_b3 & zw_b1;
when s192 =>
WHEN s192 =>
sig_PC <= d_i & zw_b1;
when s193 =>
WHEN s193 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s377 =>
if (rdy_i = '1') then
WHEN s377 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
end if;
when s381 =>
END IF;
WHEN s381 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s378 =>
if (rdy_i = '1') then
WHEN s378 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
end if;
when s382 =>
END IF;
WHEN s382 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s383 =>
if (rdy_i = '1') then
WHEN s383 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
end if;
when s384 =>
if (rdy_i = '1') then
END IF;
WHEN s384 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s385 =>
if (rdy_i = '1') then
END IF;
WHEN s385 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
end if;
when s386 =>
if (rdy_i = '1') then
END IF;
WHEN s386 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F <= d_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s387 =>
if (rdy_i = '1') then
END IF;
WHEN s387 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
end if;
when s388 =>
if (rdy_i = '1') then
END IF;
WHEN s388 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
end if;
when s389 =>
if (rdy_i = '1') then
END IF;
WHEN s389 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
reg_F <= d_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
end if;
when s391 =>
if (rdy_i = '1') then
END IF;
WHEN s391 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
end if;
when s392 =>
if (rdy_i = '1') then
END IF;
WHEN s392 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s390 =>
if (rdy_i = '1') then
END IF;
WHEN s390 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
end if;
when s393 =>
if (rdy_i = '1') then
END IF;
WHEN s393 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
end if;
when s394 =>
if (rdy_i = '1') then
END IF;
WHEN s394 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
end if;
when s395 =>
if (rdy_i = '1') then
END IF;
WHEN s395 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
end if;
when s396 =>
if (rdy_i = '1') then
END IF;
WHEN s396 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s397 =>
if (rdy_i = '1') then
END IF;
WHEN s397 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
end if;
when s399 =>
END IF;
WHEN s399 =>
sig_PC <= adr_sp_i;
when s400 =>
WHEN s400 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
when s401 =>
if (rdy_i = '1') then
WHEN s401 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1 (7 downto 0);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s526 =>
if (rdy_i = '1') then
END IF;
WHEN s526 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
end if;
when s527 =>
END IF;
WHEN s527 =>
sig_PC <= adr_sp_i;
when s528 =>
WHEN s528 =>
sig_PC <= adr_sp_i;
when s529 =>
WHEN s529 =>
sig_PC <= X"FFFE";
when s530 =>
if (rdy_i = '1') then
WHEN s530 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
reg_F(2) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s531 =>
if (rdy_i = '1') then
END IF;
WHEN s531 =>
IF (rdy_i = '1') THEN
sig_PC <= X"FFFF";
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
end if;
when s544 =>
END IF;
WHEN s544 =>
sig_PC <= adr_sp_i;
when s545 =>
WHEN s545 =>
sig_PC <= adr_sp_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
when s546 =>
WHEN s546 =>
sig_PC <= adr_pc_i;
when s547 =>
if (rdy_i = '1') then
WHEN s547 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
zw_w1 (7 downto 0) <= d_i;
zw_b1 <= d_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
end if;
when s549 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_w1 (7 downto 0);
END IF;
WHEN s549 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s550 =>
END IF;
WHEN s550 =>
sig_PC <= adr_sp_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
when s404 =>
if (rdy_i = '1') then
WHEN s404 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(7);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s556 =>
if (rdy_i = '1') then
END IF;
WHEN s556 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s557 =>
if (rdy_i = '1') then
END IF;
WHEN s557 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(7);
reg_F(0) <= q_a_i(7);
1157,81 → 1125,81
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s579 =>
if (rdy_i = '1') then
END IF;
WHEN s579 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s201 =>
if (rdy_i = '1' and
END IF;
WHEN s201 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN
sig_PC <= X"00" & d_i;
elsif ((rdy_i = '1' and
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' and
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' and
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' and
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
1239,30 → 1207,30
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) then
zw_REG_OP = X"D5")) THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
1271,132 → 1239,132
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) then
zw_REG_OP = X"CC")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) then
zw_REG_OP = X"DD")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) then
zw_REG_OP = X"D9")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) then
zw_REG_OP = X"D1")) THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) then
zw_REG_OP = X"C1")) THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"B6") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
end if;
when s202 =>
if (rdy_i = '1') then
END IF;
WHEN s202 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
end if;
when s210 =>
if (rdy_i = '1') then
END IF;
WHEN s210 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s211 =>
if (rdy_i = '1') then
END IF;
WHEN s211 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s215 =>
if (rdy_i = '1') then
END IF;
WHEN s215 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s217 =>
if (rdy_i = '1') then
END IF;
WHEN s217 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
end if;
when s218 =>
if (rdy_i = '1') then
END IF;
WHEN s218 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
end if;
when s222 =>
if (rdy_i = '1') then
END IF;
WHEN s222 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s223 =>
if (rdy_i = '1') then
END IF;
WHEN s223 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s224 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
END IF;
WHEN s224 =>
IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
1404,68 → 1372,68
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s225 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
END IF;
WHEN s225 =>
IF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
1473,194 → 1441,194
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
sig_PC <= zw_b3 & zw_b1;
end if;
when s226 =>
if (rdy_i = '1' and
END IF;
WHEN s226 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
zw_REG_OP = X"E6")) THEN
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
zw_REG_OP = X"F6")) THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
zw_REG_OP = X"EE")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
zw_REG_OP = X"FE")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s243 =>
if (rdy_i = '1') then
END IF;
WHEN s243 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
end if;
when s244 =>
if (rdy_i = '1') then
END IF;
WHEN s244 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s247 =>
if (rdy_i = '1') then
END IF;
WHEN s247 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
end if;
when s344 =>
if (rdy_i = '1') then
END IF;
WHEN s344 =>
IF (rdy_i = '1') THEN
sig_PC <= zw_b3 & zw_b1;
end if;
when s343 =>
if (rdy_i = '1') then
END IF;
WHEN s343 =>
IF (rdy_i = '1') THEN
zw_b1 <= d_alu_i;
end if;
when s251 =>
END IF;
WHEN s251 =>
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s351 =>
if (rdy_i = '1' and
zw_REG_OP = X"24") then
WHEN s351 =>
IF (rdy_i = '1' and
zw_REG_OP = X"24") THEN
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"2C") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end if;
when s361 =>
if (rdy_i = '1') then
END IF;
WHEN s361 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= d_i(7);
reg_F(6) <= d_i(6);
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s360 =>
if (rdy_i = '1') then
END IF;
WHEN s360 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
end if;
when s403 =>
if (rdy_i = '1' and
END IF;
WHEN s403 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
zw_REG_OP = X"5E")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) then
zw_REG_OP = X"46")) THEN
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
zw_REG_OP = X"56")) THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) then
zw_REG_OP = X"4E")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end if;
when s406 =>
if (rdy_i = '1') then
END IF;
WHEN s406 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
end if;
when s407 =>
if (rdy_i = '1') then
END IF;
WHEN s407 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s409 =>
if (rdy_i = '1') then
END IF;
WHEN s409 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
end if;
when s412 =>
if (rdy_i = '1') then
END IF;
WHEN s412 =>
IF (rdy_i = '1') THEN
sig_PC <= zw_b3 & zw_b1;
end if;
when s416 =>
if (rdy_i = '1' and
END IF;
WHEN s416 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) then
zw_REG_OP = X"1E")) THEN
zw_b1 <= d_i(6 downto 0) & '0';
zw_b2(0) <= d_i(7);
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) then
zw_REG_OP = X"5E")) THEN
zw_b1 <= '0' & d_i(7 downto 1);
zw_b2(0) <= d_i(0);
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) then
zw_REG_OP = X"3E")) THEN
zw_b1 <= d_i(6 downto 0) & reg_F(0);
zw_b2(0) <= d_i(7);
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) then
zw_REG_OP = X"7E")) THEN
zw_b1 <= reg_F(0) & d_i(7 downto 1);
zw_b2(0) <= d_i(0);
end if;
when s418 =>
END IF;
WHEN s418 =>
sig_PC <= adr_pc_i;
reg_F(0) <= zw_b2(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s510 =>
if (rdy_i = '1' and
zw_REG_OP = X"65") then
WHEN s510 =>
IF (rdy_i = '1' and
zw_REG_OP = X"65") THEN
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
reg_F(3) = '0') THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
1670,39 → 1638,39
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"75") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"6D") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"7D") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"79") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"71") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"61") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
reg_F(3) = '1') THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
1712,43 → 1680,43
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s553 =>
if (rdy_i = '1') then
END IF;
WHEN s553 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
end if;
when s555 =>
if (rdy_i = '1') then
END IF;
WHEN s555 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s558 =>
if (rdy_i = '1') then
END IF;
WHEN s558 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s560 =>
if (rdy_i = '1') then
END IF;
WHEN s560 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
end if;
when s561 =>
if (rdy_i = '1') then
END IF;
WHEN s561 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
end if;
when s563 =>
if (rdy_i = '1') then
END IF;
WHEN s563 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s564 =>
if (rdy_i = '1' AND
END IF;
WHEN s564 =>
IF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
reg_F(3) = '0') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
1758,13 → 1726,13
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' AND
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
reg_F(3) = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
1774,16 → 1742,16
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
sig_PC <= zw_b3 & zw_b1;
end if;
when s565 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
END IF;
WHEN s565 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
1793,12 → 1761,12
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
1808,18 → 1776,18
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s566 =>
if (rdy_i = '1') then
END IF;
WHEN s566 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s266 =>
if (rdy_i = '1' and (
END IF;
WHEN s266 =>
IF (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
1827,58 → 1795,57
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) then
(reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "10";
zw_b2 <= d_i;
end if;
when s301 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
END IF;
WHEN s301 =>
IF (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0);
end if;
when s302 =>
if (rdy_i = '1') then
END IF;
WHEN s302 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when RES =>
END IF;
WHEN RES =>
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_pc_as <= '0';
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s511 =>
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
WHEN s511 =>
IF (rdy_i = '1' and
zw_REG_OP = X"E5") THEN
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
reg_F(3) = '0') THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
1888,39 → 1855,39
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F5") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"ED") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"FD") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F9") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F1") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E1") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
reg_F(3) = '1') THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
1930,53 → 1897,53
(zw_ALU(0)));
reg_F(0) <= zw_ALU2(4);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s559 =>
if (rdy_i = '1') then
END IF;
WHEN s559 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
end if;
when s562 =>
if (rdy_i = '1') then
END IF;
WHEN s562 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s567 =>
if (rdy_i = '1') then
END IF;
WHEN s567 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s568 =>
if (rdy_i = '1') then
END IF;
WHEN s568 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s569 =>
if (rdy_i = '1') then
END IF;
WHEN s569 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
end if;
when s570 =>
if (rdy_i = '1') then
END IF;
WHEN s570 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
end if;
when s571 =>
if (rdy_i = '1') then
END IF;
WHEN s571 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s572 =>
if (rdy_i = '1') then
END IF;
WHEN s572 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s573 =>
if (rdy_i = '1' AND
END IF;
WHEN s573 =>
IF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
reg_F(3) = '0') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
1986,13 → 1953,13
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' AND
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
reg_F(3) = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
2002,16 → 1969,16
(zw_ALU(0)));
reg_F(0) <= zw_ALU2(4);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
sig_PC <= zw_b3 & zw_b1;
end if;
when s574 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
END IF;
WHEN s574 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
2021,12 → 1988,12
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
2036,71 → 2003,71
(zw_ALU(0)));
reg_F(0) <= zw_ALU2(4);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s548 =>
if (rdy_i = '1') then
END IF;
WHEN s548 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
end if;
when s551 =>
END IF;
WHEN s551 =>
sig_PC <= adr_sp_i;
when s552 =>
WHEN s552 =>
sig_PC <= adr_sp_i;
when s575 =>
if (rdy_i = '1') then
WHEN s575 =>
IF (rdy_i = '1') THEN
sig_PC <= X"FFFF";
zw_b1 <= d_i;
end if;
when s576 =>
END IF;
WHEN s576 =>
sig_PC <= X"FFFE";
when s577 =>
if (rdy_i = '1') then
WHEN s577 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
reg_F(2) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s532 =>
if (rdy_i = '1') then
END IF;
WHEN s532 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
end if;
when s533 =>
END IF;
WHEN s533 =>
sig_PC <= adr_sp_i;
when s534 =>
WHEN s534 =>
sig_PC <= adr_sp_i;
when s535 =>
if (rdy_i = '1') then
WHEN s535 =>
IF (rdy_i = '1') THEN
sig_PC <= X"FFFB";
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
end if;
when s536 =>
END IF;
WHEN s536 =>
sig_PC <= X"FFFA";
when s537 =>
if (rdy_i = '1') then
WHEN s537 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when others =>
null;
end case;
end if;
end process clocked_proc;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END PROCESS clocked_proc;
-----------------------------------------------------------------
nextstate_proc : process (
nextstate_proc : PROCESS (
adr_nxt_pc_i,
current_state,
d_i,
2113,15 → 2080,15
zw_b3
)
-----------------------------------------------------------------
begin
case current_state is
when FETCH =>
if ((nmi_i = '1') and (rdy_i = '1')) then
BEGIN
CASE current_state IS
WHEN FETCH =>
IF ((nmi_i = '1') AND (rdy_i = '1')) THEN
next_state <= s532;
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
ELSIF ((irq_n_i = '0' and
reg_F(2) = '0') AND (rdy_i = '1')) THEN
next_state <= s548;
elsif ((d_i = X"69" or
ELSIF ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
2128,14 → 2095,14
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") and (rdy_i = '1')) then
d_i = X"71") AND (rdy_i = '1')) THEN
next_state <= s510;
elsif ((d_i = X"06" or
ELSIF ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") and (rdy_i = '1')) then
d_i = X"1E") AND (rdy_i = '1')) THEN
next_state <= s403;
elsif ((d_i = X"90" or
ELSIF ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
2142,39 → 2109,39
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") and (rdy_i = '1')) then
d_i = X"70") AND (rdy_i = '1')) THEN
next_state <= s266;
elsif ((d_i = X"24" or
d_i = X"2C") and (rdy_i = '1')) then
ELSIF ((d_i = X"24" or
d_i = X"2C") AND (rdy_i = '1')) THEN
next_state <= s351;
elsif ((d_i = X"00") and (rdy_i = '1')) then
ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN
next_state <= s526;
elsif ((d_i = X"18") and (rdy_i = '1')) then
ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN
next_state <= s12;
elsif ((d_i = X"D8") and (rdy_i = '1')) then
ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN
next_state <= s16;
elsif ((d_i = X"58") and (rdy_i = '1')) then
ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN
next_state <= s17;
elsif ((d_i = X"B8") and (rdy_i = '1')) then
ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN
next_state <= s24;
elsif ((d_i = X"E0" or
ELSIF ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") and (rdy_i = '1')) then
d_i = X"EC") AND (rdy_i = '1')) THEN
next_state <= s201;
elsif ((d_i = X"C0" or
ELSIF ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") and (rdy_i = '1')) then
d_i = X"CC") AND (rdy_i = '1')) THEN
next_state <= s201;
elsif ((d_i = X"C6" or
ELSIF ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") and (rdy_i = '1')) then
d_i = X"DE") AND (rdy_i = '1')) THEN
next_state <= s226;
elsif ((d_i = X"CA") and (rdy_i = '1')) then
ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN
next_state <= s25;
elsif ((d_i = X"88") and (rdy_i = '1')) then
ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN
next_state <= s25;
elsif ((d_i = X"49" or
ELSIF ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
2205,23 → 2172,23
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") and (rdy_i = '1')) then
d_i = X"D1") AND (rdy_i = '1')) THEN
next_state <= s201;
elsif ((d_i = X"E6" or
ELSIF ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") and (rdy_i = '1')) then
d_i = X"FE") AND (rdy_i = '1')) THEN
next_state <= s226;
elsif ((d_i = X"E8") and (rdy_i = '1')) then
ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN
next_state <= s25;
elsif ((d_i = X"C8") and (rdy_i = '1')) then
ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN
next_state <= s25;
elsif ((d_i = X"4C" or
d_i = X"6C") and (rdy_i = '1')) then
ELSIF ((d_i = X"4C" or
d_i = X"6C") AND (rdy_i = '1')) THEN
next_state <= s271;
elsif ((d_i = X"20") and (rdy_i = '1')) then
ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN
next_state <= s397;
elsif ((d_i = X"A9" or
ELSIF ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
2228,50 → 2195,50
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") and (rdy_i = '1')) then
d_i = X"B1") AND (rdy_i = '1')) THEN
next_state <= s201;
elsif ((d_i = X"A2" or
ELSIF ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") and (rdy_i = '1')) then
d_i = X"BE") AND (rdy_i = '1')) THEN
next_state <= s201;
elsif ((d_i = X"A0" or
ELSIF ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") and (rdy_i = '1')) then
d_i = X"BC") AND (rdy_i = '1')) THEN
next_state <= s201;
elsif ((d_i = X"46" or
ELSIF ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") and (rdy_i = '1')) then
d_i = X"5E") AND (rdy_i = '1')) THEN
next_state <= s403;
elsif ((d_i = X"EA") and (rdy_i = '1')) then
ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN
next_state <= s1;
elsif ((d_i = X"48") and (rdy_i = '1')) then
ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN
next_state <= s377;
elsif ((d_i = X"08") and (rdy_i = '1')) then
ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN
next_state <= s378;
elsif ((d_i = X"68") and (rdy_i = '1')) then
ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN
next_state <= s379;
elsif ((d_i = X"28") and (rdy_i = '1')) then
ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN
next_state <= s380;
elsif ((d_i = X"26" or
ELSIF ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") and (rdy_i = '1')) then
d_i = X"3E") AND (rdy_i = '1')) THEN
next_state <= s403;
elsif ((d_i = X"66" or
ELSIF ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") and (rdy_i = '1')) then
d_i = X"7E") AND (rdy_i = '1')) THEN
next_state <= s403;
elsif ((d_i = X"40") and (rdy_i = '1')) then
ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN
next_state <= s387;
elsif ((d_i = X"60") and (rdy_i = '1')) then
ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN
next_state <= s390;
elsif ((d_i = X"E9" or
ELSIF ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
2278,494 → 2245,494
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") and (rdy_i = '1')) then
d_i = X"F1") AND (rdy_i = '1')) THEN
next_state <= s511;
elsif ((d_i = X"38") and (rdy_i = '1')) then
ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN
next_state <= s2;
elsif ((d_i = X"F8") and (rdy_i = '1')) then
ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN
next_state <= s5;
elsif ((d_i = X"78") and (rdy_i = '1')) then
ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN
next_state <= s3;
elsif ((d_i = X"85" or
ELSIF ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91") and (rdy_i = '1')) then
d_i = X"91") AND (rdy_i = '1')) THEN
next_state <= s177;
elsif ((d_i = X"86" or
ELSIF ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") and (rdy_i = '1')) then
d_i = X"8E") AND (rdy_i = '1')) THEN
next_state <= s177;
elsif ((d_i = X"84" or
ELSIF ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") and (rdy_i = '1')) then
d_i = X"8C") AND (rdy_i = '1')) THEN
next_state <= s177;
elsif ((d_i = X"AA") and (rdy_i = '1')) then
ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN
next_state <= s4;
elsif ((d_i = X"0A") and (rdy_i = '1')) then
ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN
next_state <= s404;
elsif ((d_i = X"4A") and (rdy_i = '1')) then
ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN
next_state <= s556;
elsif ((d_i = X"2A") and (rdy_i = '1')) then
ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN
next_state <= s557;
elsif ((d_i = X"6A") and (rdy_i = '1')) then
ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN
next_state <= s579;
elsif ((d_i = X"A8") and (rdy_i = '1')) then
ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN
next_state <= s4;
elsif ((d_i = X"98") and (rdy_i = '1')) then
ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN
next_state <= s4;
elsif ((d_i = X"BA") and (rdy_i = '1')) then
ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN
next_state <= s4;
elsif ((d_i = X"8A") and (rdy_i = '1')) then
ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN
next_state <= s4;
elsif ((d_i = X"9A") and (rdy_i = '1')) then
ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN
next_state <= s4;
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
next_state <= s1;
else
ELSE
next_state <= FETCH;
end if;
when s1 =>
if (rdy_i = '1') then
END IF;
WHEN s1 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s1;
end if;
when s2 =>
if (rdy_i = '1') then
END IF;
WHEN s2 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s2;
end if;
when s5 =>
if (rdy_i = '1') then
END IF;
WHEN s5 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s5;
end if;
when s3 =>
if (rdy_i = '1') then
END IF;
WHEN s3 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s3;
end if;
when s4 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
END IF;
WHEN s4 =>
IF (rdy_i = '1' and
zw_REG_OP = X"9A") THEN
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"BA") THEN
next_state <= FETCH;
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s4;
end if;
when s12 =>
if (rdy_i = '1') then
END IF;
WHEN s12 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s12;
end if;
when s16 =>
if (rdy_i = '1') then
END IF;
WHEN s16 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s16;
end if;
when s17 =>
if (rdy_i = '1') then
END IF;
WHEN s17 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s17;
end if;
when s24 =>
if (rdy_i = '1') then
END IF;
WHEN s24 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s24;
end if;
when s25 =>
if (rdy_i = '1') then
END IF;
WHEN s25 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s25;
end if;
when s271 =>
if (rdy_i = '1' and
zw_REG_OP = X"4C") then
END IF;
WHEN s271 =>
IF (rdy_i = '1' and
zw_REG_OP = X"4C") THEN
next_state <= s307;
elsif (rdy_i = '1' and
zw_REG_OP = X"6C") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"6C") THEN
next_state <= s273;
else
ELSE
next_state <= s271;
end if;
when s273 =>
if (rdy_i = '1') then
END IF;
WHEN s273 =>
IF (rdy_i = '1') THEN
next_state <= s304;
else
ELSE
next_state <= s273;
end if;
when s304 =>
if (rdy_i = '1') then
END IF;
WHEN s304 =>
IF (rdy_i = '1') THEN
next_state <= s307;
else
ELSE
next_state <= s304;
end if;
when s307 =>
if (rdy_i = '1') then
END IF;
WHEN s307 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s307;
end if;
when s177 =>
if (rdy_i = '1' and
END IF;
WHEN s177 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) then
zw_REG_OP = X"84")) THEN
next_state <= s184;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) then
zw_REG_OP = X"94")) THEN
next_state <= s185;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) then
zw_REG_OP = X"8C")) THEN
next_state <= s183;
elsif (rdy_i = '1' and
zw_REG_OP = X"9D") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"9D") THEN
next_state <= s182;
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"99") THEN
next_state <= s180;
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"91") THEN
next_state <= s181;
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"81") THEN
next_state <= s186;
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"96") THEN
next_state <= s185;
else
ELSE
next_state <= s177;
end if;
when s180 =>
if (rdy_i = '1') then
END IF;
WHEN s180 =>
IF (rdy_i = '1') THEN
next_state <= s191;
else
ELSE
next_state <= s180;
end if;
when s181 =>
if (rdy_i = '1') then
END IF;
WHEN s181 =>
IF (rdy_i = '1') THEN
next_state <= s189;
else
ELSE
next_state <= s181;
end if;
when s182 =>
if (rdy_i = '1') then
END IF;
WHEN s182 =>
IF (rdy_i = '1') THEN
next_state <= s191;
else
ELSE
next_state <= s182;
end if;
when s183 =>
if (rdy_i = '1') then
END IF;
WHEN s183 =>
IF (rdy_i = '1') THEN
next_state <= s187;
else
ELSE
next_state <= s183;
end if;
when s184 =>
END IF;
WHEN s184 =>
next_state <= FETCH;
when s185 =>
if (rdy_i = '1') then
WHEN s185 =>
IF (rdy_i = '1') THEN
next_state <= s190;
else
ELSE
next_state <= s185;
end if;
when s186 =>
if (rdy_i = '1') then
END IF;
WHEN s186 =>
IF (rdy_i = '1') THEN
next_state <= s188;
else
ELSE
next_state <= s186;
end if;
when s187 =>
END IF;
WHEN s187 =>
next_state <= FETCH;
when s188 =>
if (rdy_i = '1') then
WHEN s188 =>
IF (rdy_i = '1') THEN
next_state <= s192;
else
ELSE
next_state <= s188;
end if;
when s189 =>
if (rdy_i = '1') then
END IF;
WHEN s189 =>
IF (rdy_i = '1') THEN
next_state <= s191;
else
ELSE
next_state <= s189;
end if;
when s190 =>
END IF;
WHEN s190 =>
next_state <= FETCH;
when s191 =>
WHEN s191 =>
next_state <= s193;
when s192 =>
WHEN s192 =>
next_state <= s193;
when s193 =>
WHEN s193 =>
next_state <= FETCH;
when s377 =>
if (rdy_i = '1') then
WHEN s377 =>
IF (rdy_i = '1') THEN
next_state <= s381;
else
ELSE
next_state <= s377;
end if;
when s381 =>
END IF;
WHEN s381 =>
next_state <= FETCH;
when s378 =>
if (rdy_i = '1') then
WHEN s378 =>
IF (rdy_i = '1') THEN
next_state <= s382;
else
ELSE
next_state <= s378;
end if;
when s382 =>
END IF;
WHEN s382 =>
next_state <= FETCH;
when s379 =>
if (rdy_i = '1') then
WHEN s379 =>
IF (rdy_i = '1') THEN
next_state <= s383;
else
ELSE
next_state <= s379;
end if;
when s383 =>
if (rdy_i = '1') then
END IF;
WHEN s383 =>
IF (rdy_i = '1') THEN
next_state <= s384;
else
ELSE
next_state <= s383;
end if;
when s384 =>
if (rdy_i = '1') then
END IF;
WHEN s384 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s384;
end if;
when s380 =>
if (rdy_i = '1') then
END IF;
WHEN s380 =>
IF (rdy_i = '1') THEN
next_state <= s385;
else
ELSE
next_state <= s380;
end if;
when s385 =>
if (rdy_i = '1') then
END IF;
WHEN s385 =>
IF (rdy_i = '1') THEN
next_state <= s386;
else
ELSE
next_state <= s385;
end if;
when s386 =>
if (rdy_i = '1') then
END IF;
WHEN s386 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s386;
end if;
when s387 =>
if (rdy_i = '1') then
END IF;
WHEN s387 =>
IF (rdy_i = '1') THEN
next_state <= s388;
else
ELSE
next_state <= s387;
end if;
when s388 =>
if (rdy_i = '1') then
END IF;
WHEN s388 =>
IF (rdy_i = '1') THEN
next_state <= s389;
else
ELSE
next_state <= s388;
end if;
when s389 =>
if (rdy_i = '1') then
END IF;
WHEN s389 =>
IF (rdy_i = '1') THEN
next_state <= s391;
else
ELSE
next_state <= s389;
end if;
when s391 =>
if (rdy_i = '1') then
END IF;
WHEN s391 =>
IF (rdy_i = '1') THEN
next_state <= s392;
else
ELSE
next_state <= s391;
end if;
when s392 =>
if (rdy_i = '1') then
END IF;
WHEN s392 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s392;
end if;
when s390 =>
if (rdy_i = '1') then
END IF;
WHEN s390 =>
IF (rdy_i = '1') THEN
next_state <= s393;
else
ELSE
next_state <= s390;
end if;
when s393 =>
if (rdy_i = '1') then
END IF;
WHEN s393 =>
IF (rdy_i = '1') THEN
next_state <= s394;
else
ELSE
next_state <= s393;
end if;
when s394 =>
if (rdy_i = '1') then
END IF;
WHEN s394 =>
IF (rdy_i = '1') THEN
next_state <= s395;
else
ELSE
next_state <= s394;
end if;
when s395 =>
if (rdy_i = '1') then
END IF;
WHEN s395 =>
IF (rdy_i = '1') THEN
next_state <= s396;
else
ELSE
next_state <= s395;
end if;
when s396 =>
if (rdy_i = '1') then
END IF;
WHEN s396 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s396;
end if;
when s397 =>
if (rdy_i = '1') then
END IF;
WHEN s397 =>
IF (rdy_i = '1') THEN
next_state <= s398;
else
ELSE
next_state <= s397;
end if;
when s398 =>
if (rdy_i = '1') then
END IF;
WHEN s398 =>
IF (rdy_i = '1') THEN
next_state <= s399;
else
ELSE
next_state <= s398;
end if;
when s399 =>
END IF;
WHEN s399 =>
next_state <= s400;
when s400 =>
WHEN s400 =>
next_state <= s401;
when s401 =>
if (rdy_i = '1') then
WHEN s401 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s401;
end if;
when s526 =>
if (rdy_i = '1') then
END IF;
WHEN s526 =>
IF (rdy_i = '1') THEN
next_state <= s527;
else
ELSE
next_state <= s526;
end if;
when s527 =>
END IF;
WHEN s527 =>
next_state <= s528;
when s528 =>
WHEN s528 =>
next_state <= s529;
when s529 =>
WHEN s529 =>
next_state <= s531;
when s530 =>
if (rdy_i = '1') then
WHEN s530 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s530;
end if;
when s531 =>
if (rdy_i = '1') then
END IF;
WHEN s531 =>
IF (rdy_i = '1') THEN
next_state <= s530;
else
ELSE
next_state <= s531;
end if;
when s544 =>
END IF;
WHEN s544 =>
next_state <= s550;
when s545 =>
WHEN s545 =>
next_state <= s546;
when s546 =>
WHEN s546 =>
next_state <= s547;
when s547 =>
if (rdy_i = '1') then
WHEN s547 =>
IF (rdy_i = '1') THEN
next_state <= s549;
else
ELSE
next_state <= s547;
end if;
when s549 =>
if (rdy_i = '1') then
END IF;
WHEN s549 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s549;
end if;
when s550 =>
END IF;
WHEN s550 =>
next_state <= s545;
when s404 =>
if (rdy_i = '1') then
WHEN s404 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s404;
end if;
when s556 =>
if (rdy_i = '1') then
END IF;
WHEN s556 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s556;
end if;
when s557 =>
if (rdy_i = '1') then
END IF;
WHEN s557 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s557;
end if;
when s579 =>
if (rdy_i = '1') then
END IF;
WHEN s579 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s579;
end if;
when s201 =>
if (rdy_i = '1' and
END IF;
WHEN s201 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN
next_state <= s224;
elsif ((rdy_i = '1' and
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
next_state <= FETCH;
elsif ((rdy_i = '1' and
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
next_state <= FETCH;
elsif ((rdy_i = '1' and
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
next_state <= FETCH;
elsif ((rdy_i = '1' and
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
next_state <= FETCH;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN
next_state <= FETCH;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) then
zw_REG_OP = X"D5")) THEN
next_state <= s217;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
2774,426 → 2741,426
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) then
zw_REG_OP = X"CC")) THEN
next_state <= s202;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) then
zw_REG_OP = X"DD")) THEN
next_state <= s210;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) then
zw_REG_OP = X"D9")) THEN
next_state <= s211;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) then
zw_REG_OP = X"D1")) THEN
next_state <= s215;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) then
zw_REG_OP = X"C1")) THEN
next_state <= s218;
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"B6") THEN
next_state <= s217;
else
ELSE
next_state <= s201;
end if;
when s202 =>
if (rdy_i = '1') then
END IF;
WHEN s202 =>
IF (rdy_i = '1') THEN
next_state <= s224;
else
ELSE
next_state <= s202;
end if;
when s210 =>
if (rdy_i = '1') then
END IF;
WHEN s210 =>
IF (rdy_i = '1') THEN
next_state <= s225;
else
ELSE
next_state <= s210;
end if;
when s211 =>
if (rdy_i = '1') then
END IF;
WHEN s211 =>
IF (rdy_i = '1') THEN
next_state <= s225;
else
ELSE
next_state <= s211;
end if;
when s215 =>
if (rdy_i = '1') then
END IF;
WHEN s215 =>
IF (rdy_i = '1') THEN
next_state <= s223;
else
ELSE
next_state <= s215;
end if;
when s217 =>
if (rdy_i = '1') then
END IF;
WHEN s217 =>
IF (rdy_i = '1') THEN
next_state <= s224;
else
ELSE
next_state <= s217;
end if;
when s218 =>
if (rdy_i = '1') then
END IF;
WHEN s218 =>
IF (rdy_i = '1') THEN
next_state <= s222;
else
ELSE
next_state <= s218;
end if;
when s222 =>
if (rdy_i = '1') then
END IF;
WHEN s222 =>
IF (rdy_i = '1') THEN
next_state <= s202;
else
ELSE
next_state <= s222;
end if;
when s223 =>
if (rdy_i = '1') then
END IF;
WHEN s223 =>
IF (rdy_i = '1') THEN
next_state <= s225;
else
ELSE
next_state <= s223;
end if;
when s224 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
END IF;
WHEN s224 =>
IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
next_state <= FETCH;
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
next_state <= FETCH;
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
next_state <= FETCH;
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
next_state <= FETCH;
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s224;
end if;
when s225 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
END IF;
WHEN s225 =>
IF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
next_state <= FETCH;
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
next_state <= FETCH;
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
next_state <= FETCH;
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
next_state <= FETCH;
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0') THEN
next_state <= FETCH;
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
next_state <= s224;
else
ELSE
next_state <= s225;
end if;
when s226 =>
if (rdy_i = '1' and
END IF;
WHEN s226 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
zw_REG_OP = X"E6")) THEN
next_state <= s343;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
zw_REG_OP = X"F6")) THEN
next_state <= s247;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
zw_REG_OP = X"EE")) THEN
next_state <= s243;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
zw_REG_OP = X"FE")) THEN
next_state <= s244;
else
ELSE
next_state <= s226;
end if;
when s243 =>
if (rdy_i = '1') then
END IF;
WHEN s243 =>
IF (rdy_i = '1') THEN
next_state <= s343;
else
ELSE
next_state <= s243;
end if;
when s244 =>
if (rdy_i = '1') then
END IF;
WHEN s244 =>
IF (rdy_i = '1') THEN
next_state <= s344;
else
ELSE
next_state <= s244;
end if;
when s247 =>
if (rdy_i = '1') then
END IF;
WHEN s247 =>
IF (rdy_i = '1') THEN
next_state <= s343;
else
ELSE
next_state <= s247;
end if;
when s344 =>
if (rdy_i = '1') then
END IF;
WHEN s344 =>
IF (rdy_i = '1') THEN
next_state <= s343;
else
ELSE
next_state <= s344;
end if;
when s343 =>
if (rdy_i = '1') then
END IF;
WHEN s343 =>
IF (rdy_i = '1') THEN
next_state <= s250;
else
ELSE
next_state <= s343;
end if;
when s250 =>
if (rdy_i = '1') then
END IF;
WHEN s250 =>
IF (rdy_i = '1') THEN
next_state <= s251;
else
ELSE
next_state <= s250;
end if;
when s251 =>
END IF;
WHEN s251 =>
next_state <= FETCH;
when s351 =>
if (rdy_i = '1' and
zw_REG_OP = X"24") then
WHEN s351 =>
IF (rdy_i = '1' and
zw_REG_OP = X"24") THEN
next_state <= s361;
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"2C") THEN
next_state <= s360;
else
ELSE
next_state <= s351;
end if;
when s361 =>
if (rdy_i = '1') then
END IF;
WHEN s361 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s361;
end if;
when s360 =>
if (rdy_i = '1') then
END IF;
WHEN s360 =>
IF (rdy_i = '1') THEN
next_state <= s361;
else
ELSE
next_state <= s360;
end if;
when s403 =>
if (rdy_i = '1' and
END IF;
WHEN s403 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
zw_REG_OP = X"5E")) THEN
next_state <= s407;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) then
zw_REG_OP = X"46")) THEN
next_state <= s413;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
zw_REG_OP = X"56")) THEN
next_state <= s409;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) then
zw_REG_OP = X"4E")) THEN
next_state <= s406;
else
ELSE
next_state <= s403;
end if;
when s406 =>
if (rdy_i = '1') then
END IF;
WHEN s406 =>
IF (rdy_i = '1') THEN
next_state <= s413;
else
ELSE
next_state <= s406;
end if;
when s407 =>
if (rdy_i = '1') then
END IF;
WHEN s407 =>
IF (rdy_i = '1') THEN
next_state <= s412;
else
ELSE
next_state <= s407;
end if;
when s409 =>
if (rdy_i = '1') then
END IF;
WHEN s409 =>
IF (rdy_i = '1') THEN
next_state <= s413;
else
ELSE
next_state <= s409;
end if;
when s412 =>
if (rdy_i = '1') then
END IF;
WHEN s412 =>
IF (rdy_i = '1') THEN
next_state <= s413;
else
ELSE
next_state <= s412;
end if;
when s413 =>
if (rdy_i = '1') then
END IF;
WHEN s413 =>
IF (rdy_i = '1') THEN
next_state <= s416;
else
ELSE
next_state <= s413;
end if;
when s416 =>
if (rdy_i = '1' and
END IF;
WHEN s416 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) then
zw_REG_OP = X"1E")) THEN
next_state <= s418;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) then
zw_REG_OP = X"5E")) THEN
next_state <= s418;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) then
zw_REG_OP = X"3E")) THEN
next_state <= s418;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) then
zw_REG_OP = X"7E")) THEN
next_state <= s418;
else
ELSE
next_state <= s416;
end if;
when s418 =>
END IF;
WHEN s418 =>
next_state <= FETCH;
when s510 =>
if (rdy_i = '1' and
zw_REG_OP = X"65") then
WHEN s510 =>
IF (rdy_i = '1' and
zw_REG_OP = X"65") THEN
next_state <= s565;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
reg_F(3) = '0') THEN
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"75") THEN
next_state <= s560;
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"6D") THEN
next_state <= s553;
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"7D") THEN
next_state <= s555;
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"79") THEN
next_state <= s555;
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"71") THEN
next_state <= s558;
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"61") THEN
next_state <= s561;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
reg_F(3) = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s510;
end if;
when s553 =>
if (rdy_i = '1') then
END IF;
WHEN s553 =>
IF (rdy_i = '1') THEN
next_state <= s565;
else
ELSE
next_state <= s553;
end if;
when s555 =>
if (rdy_i = '1') then
END IF;
WHEN s555 =>
IF (rdy_i = '1') THEN
next_state <= s564;
else
ELSE
next_state <= s555;
end if;
when s558 =>
if (rdy_i = '1') then
END IF;
WHEN s558 =>
IF (rdy_i = '1') THEN
next_state <= s566;
else
ELSE
next_state <= s558;
end if;
when s560 =>
if (rdy_i = '1') then
END IF;
WHEN s560 =>
IF (rdy_i = '1') THEN
next_state <= s565;
else
ELSE
next_state <= s560;
end if;
when s561 =>
if (rdy_i = '1') then
END IF;
WHEN s561 =>
IF (rdy_i = '1') THEN
next_state <= s563;
else
ELSE
next_state <= s561;
end if;
when s563 =>
if (rdy_i = '1') then
END IF;
WHEN s563 =>
IF (rdy_i = '1') THEN
next_state <= s553;
else
ELSE
next_state <= s563;
end if;
when s564 =>
if (rdy_i = '1' AND
END IF;
WHEN s564 =>
IF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
reg_F(3) = '0') THEN
next_state <= FETCH;
elsif (rdy_i = '1' AND
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
reg_F(3) = '1') THEN
next_state <= FETCH;
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
next_state <= s565;
else
ELSE
next_state <= s564;
end if;
when s565 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
END IF;
WHEN s565 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
next_state <= FETCH;
elsif (rdy_i = '1' and
reg_F(3) = '1') then
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s565;
end if;
when s566 =>
if (rdy_i = '1') then
END IF;
WHEN s566 =>
IF (rdy_i = '1') THEN
next_state <= s564;
else
ELSE
next_state <= s566;
end if;
when s266 =>
if (rdy_i = '1' and (
END IF;
WHEN s266 =>
IF (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
3201,190 → 3168,190
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) then
(reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN
next_state <= FETCH;
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
next_state <= s301;
else
ELSE
next_state <= s266;
end if;
when s301 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
END IF;
WHEN s301 =>
IF (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN
next_state <= FETCH;
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
next_state <= s302;
else
ELSE
next_state <= s301;
end if;
when s302 =>
if (rdy_i = '1') then
END IF;
WHEN s302 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s302;
end if;
when RES =>
END IF;
WHEN RES =>
next_state <= s544;
when s511 =>
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
WHEN s511 =>
IF (rdy_i = '1' and
zw_REG_OP = X"E5") THEN
next_state <= s574;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
reg_F(3) = '0') THEN
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F5") THEN
next_state <= s569;
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"ED") THEN
next_state <= s559;
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"FD") THEN
next_state <= s562;
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F9") THEN
next_state <= s567;
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F1") THEN
next_state <= s568;
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E1") THEN
next_state <= s570;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
reg_F(3) = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s511;
end if;
when s559 =>
if (rdy_i = '1') then
END IF;
WHEN s559 =>
IF (rdy_i = '1') THEN
next_state <= s574;
else
ELSE
next_state <= s559;
end if;
when s562 =>
if (rdy_i = '1') then
END IF;
WHEN s562 =>
IF (rdy_i = '1') THEN
next_state <= s573;
else
ELSE
next_state <= s562;
end if;
when s567 =>
if (rdy_i = '1') then
END IF;
WHEN s567 =>
IF (rdy_i = '1') THEN
next_state <= s573;
else
ELSE
next_state <= s567;
end if;
when s568 =>
if (rdy_i = '1') then
END IF;
WHEN s568 =>
IF (rdy_i = '1') THEN
next_state <= s571;
else
ELSE
next_state <= s568;
end if;
when s569 =>
if (rdy_i = '1') then
END IF;
WHEN s569 =>
IF (rdy_i = '1') THEN
next_state <= s574;
else
ELSE
next_state <= s569;
end if;
when s570 =>
if (rdy_i = '1') then
END IF;
WHEN s570 =>
IF (rdy_i = '1') THEN
next_state <= s572;
else
ELSE
next_state <= s570;
end if;
when s571 =>
if (rdy_i = '1') then
END IF;
WHEN s571 =>
IF (rdy_i = '1') THEN
next_state <= s573;
else
ELSE
next_state <= s571;
end if;
when s572 =>
if (rdy_i = '1') then
END IF;
WHEN s572 =>
IF (rdy_i = '1') THEN
next_state <= s559;
else
ELSE
next_state <= s572;
end if;
when s573 =>
if (rdy_i = '1' AND
END IF;
WHEN s573 =>
IF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
reg_F(3) = '0') THEN
next_state <= FETCH;
elsif (rdy_i = '1' AND
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
reg_F(3) = '1') THEN
next_state <= FETCH;
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
next_state <= s574;
else
ELSE
next_state <= s573;
end if;
when s574 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
END IF;
WHEN s574 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
next_state <= FETCH;
elsif (rdy_i = '1' and
reg_F(3) = '1') then
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s574;
end if;
when s548 =>
if (rdy_i = '1') then
END IF;
WHEN s548 =>
IF (rdy_i = '1') THEN
next_state <= s551;
else
ELSE
next_state <= s548;
end if;
when s551 =>
END IF;
WHEN s551 =>
next_state <= s552;
when s552 =>
WHEN s552 =>
next_state <= s576;
when s575 =>
if (rdy_i = '1') then
WHEN s575 =>
IF (rdy_i = '1') THEN
next_state <= s577;
else
ELSE
next_state <= s575;
end if;
when s576 =>
END IF;
WHEN s576 =>
next_state <= s575;
when s577 =>
if (rdy_i = '1') then
WHEN s577 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s577;
end if;
when s532 =>
if (rdy_i = '1') then
END IF;
WHEN s532 =>
IF (rdy_i = '1') THEN
next_state <= s533;
else
ELSE
next_state <= s532;
end if;
when s533 =>
END IF;
WHEN s533 =>
next_state <= s534;
when s534 =>
WHEN s534 =>
next_state <= s536;
when s535 =>
if (rdy_i = '1') then
WHEN s535 =>
IF (rdy_i = '1') THEN
next_state <= s537;
else
ELSE
next_state <= s535;
end if;
when s536 =>
END IF;
WHEN s536 =>
next_state <= s535;
when s537 =>
if (rdy_i = '1') then
WHEN s537 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
else
ELSE
next_state <= s537;
end if;
when others =>
END IF;
WHEN OTHERS =>
next_state <= RES;
end case;
end process nextstate_proc;
END CASE;
END PROCESS nextstate_proc;
-----------------------------------------------------------------
output_proc : process (
output_proc : PROCESS (
adr_nxt_pc_i,
adr_pc_i,
adr_sp_i,
3399,7 → 3366,6
q_y_i,
rdy_i,
reg_F,
reg_sel_pc_as,
reg_sel_pc_in,
reg_sel_pc_val,
reg_sel_rb_in,
3419,11 → 3385,10
zw_b1,
zw_b2,
zw_b3,
zw_b4,
zw_w1
zw_b4
)
-----------------------------------------------------------------
begin
BEGIN
-- Default Assignment
a_o <= sig_PC;
adr_o <= X"0000";
3436,7 → 3401,6
ld_sp_o <= '0';
load_regs_o <= '0';
offset_o <= X"0000";
sel_pc_as_o <= reg_sel_pc_as;
sel_pc_in_o <= reg_sel_pc_in;
sel_pc_val_o <= reg_sel_pc_val;
sel_rb_in_o <= reg_sel_rb_in;
3451,27 → 3415,27
sig_SYNC <= '0';
sig_WR <= '0';
zw_ALU <= '0' & X"00";
zw_ALU1 <= '0' & X"00";
zw_ALU2 <= '0' & X"00";
zw_ALU3 <= '0' & X"00";
zw_ALU4 <= '0' & X"00";
zw_ALU5 <= '0' & X"00";
zw_ALU6 <= '0' & X"00";
zw_ALU1 <= '0' & X"0";
zw_ALU2 <= '0' & X"0";
zw_ALU3 <= '0' & X"0";
zw_ALU4 <= '0' & X"0";
zw_ALU5 <= X"0";
zw_ALU6 <= X"0";
 
-- Combined Actions
case current_state is
when FETCH =>
CASE current_state IS
WHEN FETCH =>
sig_RWn <= '1';
sig_RD <= '1';
sig_SYNC <= NOT (rdy_i);
if ((nmi_i = '1') and (rdy_i = '1')) then
IF ((nmi_i = '1') AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
ELSIF ((irq_n_i = '0' and
reg_F(2) = '0') AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"69" or
ELSIF ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
3478,16 → 3442,16
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") and (rdy_i = '1')) then
d_i = X"71") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"06" or
ELSIF ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") and (rdy_i = '1')) then
d_i = X"1E") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"90" or
ELSIF ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
3494,51 → 3458,51
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") and (rdy_i = '1')) then
d_i = X"70") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"24" or
d_i = X"2C") and (rdy_i = '1')) then
ELSIF ((d_i = X"24" or
d_i = X"2C") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"00") and (rdy_i = '1')) then
ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"18") and (rdy_i = '1')) then
ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"D8") and (rdy_i = '1')) then
ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"58") and (rdy_i = '1')) then
ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"B8") and (rdy_i = '1')) then
ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"E0" or
ELSIF ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") and (rdy_i = '1')) then
d_i = X"EC") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"C0" or
ELSIF ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") and (rdy_i = '1')) then
d_i = X"CC") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"C6" or
ELSIF ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") and (rdy_i = '1')) then
d_i = X"DE") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"CA") and (rdy_i = '1')) then
ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"88") and (rdy_i = '1')) then
ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"49" or
ELSIF ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
3569,29 → 3533,29
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") and (rdy_i = '1')) then
d_i = X"D1") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"E6" or
ELSIF ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") and (rdy_i = '1')) then
d_i = X"FE") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"E8") and (rdy_i = '1')) then
ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"C8") and (rdy_i = '1')) then
ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"4C" or
d_i = X"6C") and (rdy_i = '1')) then
ELSIF ((d_i = X"4C" or
d_i = X"6C") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"20") and (rdy_i = '1')) then
ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A9" or
ELSIF ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
3598,63 → 3562,63
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") and (rdy_i = '1')) then
d_i = X"B1") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A2" or
ELSIF ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") and (rdy_i = '1')) then
d_i = X"BE") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A0" or
ELSIF ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") and (rdy_i = '1')) then
d_i = X"BC") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"46" or
ELSIF ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") and (rdy_i = '1')) then
d_i = X"5E") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"EA") and (rdy_i = '1')) then
ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"48") and (rdy_i = '1')) then
ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"08") and (rdy_i = '1')) then
ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"68") and (rdy_i = '1')) then
ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"28") and (rdy_i = '1')) then
ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"26" or
ELSIF ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") and (rdy_i = '1')) then
d_i = X"3E") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"66" or
ELSIF ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") and (rdy_i = '1')) then
d_i = X"7E") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"40") and (rdy_i = '1')) then
ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"60") and (rdy_i = '1')) then
ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"E9" or
ELSIF ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
3661,107 → 3625,107
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") and (rdy_i = '1')) then
d_i = X"F1") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"38") and (rdy_i = '1')) then
ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"F8") and (rdy_i = '1')) then
ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"78") and (rdy_i = '1')) then
ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"85" or
ELSIF ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91") and (rdy_i = '1')) then
d_i = X"91") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"86" or
ELSIF ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") and (rdy_i = '1')) then
d_i = X"8E") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"84" or
ELSIF ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") and (rdy_i = '1')) then
d_i = X"8C") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"AA") and (rdy_i = '1')) then
ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"0A") and (rdy_i = '1')) then
ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"4A") and (rdy_i = '1')) then
ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"2A") and (rdy_i = '1')) then
ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"6A") and (rdy_i = '1')) then
ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A8") and (rdy_i = '1')) then
ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"98") and (rdy_i = '1')) then
ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"BA") and (rdy_i = '1')) then
ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"8A") and (rdy_i = '1')) then
ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"9A") and (rdy_i = '1')) then
ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s1 =>
if (rdy_i = '1') then
END IF;
WHEN s1 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s2 =>
if (rdy_i = '1') then
END IF;
WHEN s2 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s5 =>
if (rdy_i = '1') then
END IF;
WHEN s5 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s3 =>
if (rdy_i = '1') then
END IF;
WHEN s3 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s4 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
END IF;
WHEN s4 =>
IF (rdy_i = '1' and
zw_REG_OP = X"9A") THEN
adr_o <= X"01" & d_regs_out_i;
ld_o <= "11";
ld_sp_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"BA") THEN
d_regs_in_o <= adr_sp_i (7 downto 0);
ch_a_o <= adr_sp_i (7 downto 0);
ch_b_o <= X"00";
3768,35 → 3732,35
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
ch_a_o <= d_regs_out_i;
ch_b_o <= X"00";
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s12 =>
if (rdy_i = '1') then
END IF;
WHEN s12 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s16 =>
if (rdy_i = '1') then
END IF;
WHEN s16 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s17 =>
if (rdy_i = '1') then
END IF;
WHEN s17 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s24 =>
if (rdy_i = '1') then
END IF;
WHEN s24 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s25 =>
if (rdy_i = '1') then
END IF;
WHEN s25 =>
IF (rdy_i = '1') THEN
d_regs_in_o <= d_alu_i;
ch_a_o <= d_regs_out_i;
ch_b_o <= zw_b4;
3803,26 → 3767,26
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s273 =>
if (rdy_i = '1') then
END IF;
WHEN s273 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s307 =>
if (rdy_i = '1') then
END IF;
WHEN s307 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s177 =>
if (rdy_i = '1' and
END IF;
WHEN s177 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) then
zw_REG_OP = X"84")) THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
3829,65 → 3793,65
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) then
zw_REG_OP = X"94")) THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) then
zw_REG_OP = X"8C")) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"9D") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"9D") THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"99") THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"91") THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"81") THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"96") THEN
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s180 =>
if (rdy_i = '1') then
END IF;
WHEN s180 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s181 =>
if (rdy_i = '1') then
END IF;
WHEN s181 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s182 =>
END IF;
WHEN s182 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s183 =>
if (rdy_i = '1') then
END IF;
WHEN s183 =>
IF (rdy_i = '1') THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
3894,12 → 3858,12
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s184 =>
END IF;
WHEN s184 =>
sig_SYNC <= '1';
fetch_o <= '1';
when s185 =>
if (rdy_i = '1') then
WHEN s185 =>
IF (rdy_i = '1') THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
3906,31 → 3870,31
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s187 =>
END IF;
WHEN s187 =>
sig_SYNC <= '1';
fetch_o <= '1';
when s188 =>
if (rdy_i = '1') then
WHEN s188 =>
IF (rdy_i = '1') THEN
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s189 =>
if (rdy_i = '1') then
END IF;
WHEN s189 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s190 =>
END IF;
WHEN s190 =>
sig_SYNC <= '1';
fetch_o <= '1';
when s191 =>
WHEN s191 =>
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
when s192 =>
WHEN s192 =>
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
3937,11 → 3901,11
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
when s193 =>
WHEN s193 =>
sig_SYNC <= '1';
fetch_o <= '1';
when s377 =>
if (rdy_i = '1') then
WHEN s377 =>
IF (rdy_i = '1') THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
3948,12 → 3912,12
sig_D_OUT <= q_a_i;
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s381 =>
END IF;
WHEN s381 =>
sig_SYNC <= '1';
fetch_o <= '1';
when s378 =>
if (rdy_i = '1') then
WHEN s378 =>
IF (rdy_i = '1') THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
3960,17 → 3924,17
sig_D_OUT <= reg_F;
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s382 =>
END IF;
WHEN s382 =>
sig_SYNC <= '1';
fetch_o <= '1';
when s379 =>
if (rdy_i = '1') then
WHEN s379 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s384 =>
if (rdy_i = '1') then
END IF;
WHEN s384 =>
IF (rdy_i = '1') THEN
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
3977,75 → 3941,75
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s380 =>
if (rdy_i = '1') then
END IF;
WHEN s380 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s386 =>
if (rdy_i = '1') then
END IF;
WHEN s386 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s387 =>
if (rdy_i = '1') then
END IF;
WHEN s387 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s388 =>
if (rdy_i = '1') then
END IF;
WHEN s388 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s389 =>
if (rdy_i = '1') then
END IF;
WHEN s389 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s392 =>
if (rdy_i = '1') then
END IF;
WHEN s392 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s390 =>
if (rdy_i = '1') then
END IF;
WHEN s390 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s393 =>
if (rdy_i = '1') then
END IF;
WHEN s393 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s395 =>
if (rdy_i = '1') then
END IF;
WHEN s395 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s396 =>
if (rdy_i = '1') then
END IF;
WHEN s396 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s397 =>
if (rdy_i = '1') then
END IF;
WHEN s397 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
end if;
when s398 =>
if (rdy_i = '1') then
END IF;
WHEN s398 =>
IF (rdy_i = '1') THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
end if;
when s399 =>
END IF;
WHEN s399 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
4052,16 → 4016,16
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
when s401 =>
if (rdy_i = '1') then
WHEN s401 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s526 =>
if (rdy_i = '1') then
END IF;
WHEN s526 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
4069,8 → 4033,8
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
end if;
when s527 =>
END IF;
WHEN s527 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
4077,7 → 4041,7
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
when s528 =>
WHEN s528 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
4084,37 → 4048,37
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F OR X"10";
when s530 =>
if (rdy_i = '1') then
WHEN s530 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s544 =>
END IF;
WHEN s544 =>
ld_o <= "11";
ld_sp_o <= '1';
when s545 =>
WHEN s545 =>
adr_o <= X"FFFB";
ld_o <= "11";
ld_pc_o <= '1';
when s546 =>
WHEN s546 =>
ld_o <= "11";
ld_pc_o <= '1';
when s549 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_w1 (7 downto 0);
WHEN s549 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s550 =>
END IF;
WHEN s550 =>
ld_o <= "11";
ld_sp_o <= '1';
when s404 =>
if (rdy_i = '1') then
WHEN s404 =>
IF (rdy_i = '1') THEN
ch_a_o <= q_a_i (6 downto 0) & '0';
ch_b_o <= X"00";
d_regs_in_o <= q_a_i (6 downto 0) & '0';
4121,9 → 4085,9
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s556 =>
if (rdy_i = '1') then
END IF;
WHEN s556 =>
IF (rdy_i = '1') THEN
ch_a_o <= '0' & q_a_i (7 downto 1);
ch_b_o <= X"00";
d_regs_in_o <= '0' & q_a_i (7 downto 1);
4130,9 → 4094,9
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s557 =>
if (rdy_i = '1') then
END IF;
WHEN s557 =>
IF (rdy_i = '1') THEN
ch_a_o <= q_a_i (6 downto 0) & reg_F(0);
ch_b_o <= X"00";
d_regs_in_o <= q_a_i (6 downto 0) & reg_F(0);
4139,9 → 4103,9
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s579 =>
if (rdy_i = '1') then
END IF;
WHEN s579 =>
IF (rdy_i = '1') THEN
ch_a_o <= reg_F(0) & q_a_i (7 downto 1);
ch_b_o <= X"00";
d_regs_in_o <= reg_F(0) & q_a_i (7 downto 1);
4148,21 → 4112,21
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s201 =>
if (rdy_i = '1' and
END IF;
WHEN s201 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif ((rdy_i = '1' and
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i OR q_a_i;
4171,12 → 4135,12
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1' and
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i XOR q_a_i;
4185,12 → 4149,12
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1' and
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i AND q_a_i;
4199,23 → 4163,23
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1' and
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
ld_o <= "11";
ld_pc_o <= '1';
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i;
4224,15 → 4188,15
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) then
zw_REG_OP = X"D5")) THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
4241,98 → 4205,98
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) then
zw_REG_OP = X"CC")) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) then
zw_REG_OP = X"DD")) THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) then
zw_REG_OP = X"D9")) THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) then
zw_REG_OP = X"D1")) THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) then
zw_REG_OP = X"C1")) THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"B6") THEN
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s202 =>
if (rdy_i = '1') then
END IF;
WHEN s202 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s210 =>
if (rdy_i = '1') then
END IF;
WHEN s210 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s211 =>
if (rdy_i = '1') then
END IF;
WHEN s211 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s215 =>
if (rdy_i = '1') then
END IF;
WHEN s215 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s217 =>
if (rdy_i = '1') then
END IF;
WHEN s217 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s222 =>
if (rdy_i = '1') then
END IF;
WHEN s222 =>
IF (rdy_i = '1') THEN
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s223 =>
if (rdy_i = '1') then
END IF;
WHEN s223 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s224 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
END IF;
WHEN s224 =>
IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
4339,10 → 4303,10
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
4349,10 → 4313,10
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
4359,17 → 4323,17
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
4376,13 → 4340,13
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s225 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
END IF;
WHEN s225 =>
IF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
4389,11 → 4353,11
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
4400,11 → 4364,11
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
4411,19 → 4375,19
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0') THEN
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
4430,187 → 4394,187
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s226 =>
if (rdy_i = '1' and
END IF;
WHEN s226 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
zw_REG_OP = X"E6")) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
zw_REG_OP = X"F6")) THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
zw_REG_OP = X"EE")) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
zw_REG_OP = X"FE")) THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end if;
when s243 =>
if (rdy_i = '1') then
END IF;
WHEN s243 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s244 =>
if (rdy_i = '1') then
END IF;
WHEN s244 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s247 =>
if (rdy_i = '1') then
END IF;
WHEN s247 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s343 =>
if (rdy_i = '1') then
END IF;
WHEN s343 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= zw_b4;
end if;
when s250 =>
if (rdy_i = '1') then
END IF;
WHEN s250 =>
IF (rdy_i = '1') THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= zw_b1;
end if;
when s251 =>
END IF;
WHEN s251 =>
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
when s351 =>
if (rdy_i = '1' and
zw_REG_OP = X"24") then
WHEN s351 =>
IF (rdy_i = '1' and
zw_REG_OP = X"24") THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"2C") THEN
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s361 =>
if (rdy_i = '1') then
END IF;
WHEN s361 =>
IF (rdy_i = '1') THEN
ch_a_o <= q_a_i AND d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s360 =>
if (rdy_i = '1') then
END IF;
WHEN s360 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s403 =>
if (rdy_i = '1' and
END IF;
WHEN s403 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
zw_REG_OP = X"5E")) THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) then
zw_REG_OP = X"46")) THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
zw_REG_OP = X"56")) THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) then
zw_REG_OP = X"4E")) THEN
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s406 =>
if (rdy_i = '1') then
END IF;
WHEN s406 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s407 =>
if (rdy_i = '1') then
END IF;
WHEN s407 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s409 =>
if (rdy_i = '1') then
END IF;
WHEN s409 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s416 =>
if (rdy_i = '1' and
END IF;
WHEN s416 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) then
zw_REG_OP = X"1E")) THEN
sig_D_OUT <= d_i(6 downto 0) & '0';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) then
zw_REG_OP = X"5E")) THEN
sig_D_OUT <= '0' & d_i(7 downto 1);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) then
zw_REG_OP = X"3E")) THEN
sig_D_OUT <= d_i(6 downto 0) & reg_F(0);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) then
zw_REG_OP = X"7E")) THEN
sig_D_OUT <= reg_F(0) & d_i(7 downto 1);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
end if;
when s418 =>
END IF;
WHEN s418 =>
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
when s510 =>
if (rdy_i = '1' and
zw_REG_OP = X"65") then
WHEN s510 =>
IF (rdy_i = '1' and
zw_REG_OP = X"65") THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
reg_F(3) = '0') THEN
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
4618,151 → 4582,145
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"75") THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"6D") THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"7D") THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"79") THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"71") THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"61") THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
reg_F(3) = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(7 downto 5));
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
zw_ALU6(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0';
zw_ALU5(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0';
zw_ALU6(2 downto 0) <= (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
zw_ALU5(2 downto 0) <= (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & d_i(3 downto 0)) + reg_F(0);
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s553 =>
if (rdy_i = '1') then
END IF;
WHEN s553 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s555 =>
if (rdy_i = '1') then
END IF;
WHEN s555 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s558 =>
if (rdy_i = '1') then
END IF;
WHEN s558 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s560 =>
if (rdy_i = '1') then
END IF;
WHEN s560 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s563 =>
if (rdy_i = '1') then
END IF;
WHEN s563 =>
IF (rdy_i = '1') THEN
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s564 =>
if (rdy_i = '1' AND
END IF;
WHEN s564 =>
IF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
reg_F(3) = '0') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' AND
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
reg_F(3) = '1') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(7 downto 5));
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
zw_ALU6(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0';
zw_ALU5(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0';
zw_ALU6(2 downto 0) <= (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
zw_ALU5(2 downto 0) <= (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & d_i(3 downto 0)) + reg_F(0);
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s565 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
END IF;
WHEN s565 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(7 downto 5));
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
zw_ALU6(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0';
zw_ALU5(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0';
zw_ALU6(2 downto 0) <= (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
zw_ALU5(2 downto 0) <= (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & d_i(3 downto 0)) + reg_F(0);
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s566 =>
if (rdy_i = '1') then
END IF;
WHEN s566 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s266 =>
if (rdy_i = '1' and (
END IF;
WHEN s266 =>
IF (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
4770,18 → 4728,18
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) then
(reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s301 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
END IF;
WHEN s301 =>
IF (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
ld_o <= "11";
4788,18 → 4746,18
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s302 =>
if (rdy_i = '1') then
END IF;
WHEN s302 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when RES =>
END IF;
WHEN RES =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
4808,14 → 4766,14
ld_sp_o <= '1';
sig_RWn <= '1';
sig_RD <= '1';
when s511 =>
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
WHEN s511 =>
IF (rdy_i = '1' and
zw_REG_OP = X"E5") THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
reg_F(3) = '0') THEN
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
4823,170 → 4781,152
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F5") THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"ED") THEN
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"FD") THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F9") THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F1") THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E1") THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
reg_F(3) = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) +
unsigned ((zw_ALU6(8 downto 5)));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) +
unsigned ((zw_ALU5(8 downto 5)));
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5);
zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' &
(zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' &
(zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU6 <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5 <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & NOT (d_i(3 downto 0))) + reg_F(0);
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s559 =>
if (rdy_i = '1') then
END IF;
WHEN s559 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s562 =>
if (rdy_i = '1') then
END IF;
WHEN s562 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s567 =>
if (rdy_i = '1') then
END IF;
WHEN s567 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s568 =>
if (rdy_i = '1') then
END IF;
WHEN s568 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s569 =>
if (rdy_i = '1') then
END IF;
WHEN s569 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s571 =>
if (rdy_i = '1') then
END IF;
WHEN s571 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s572 =>
if (rdy_i = '1') then
END IF;
WHEN s572 =>
IF (rdy_i = '1') THEN
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s573 =>
if (rdy_i = '1' AND
END IF;
WHEN s573 =>
IF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
reg_F(3) = '0') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' AND
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
reg_F(3) = '1') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) +
unsigned ((zw_ALU6(8 downto 5)));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) +
unsigned ((zw_ALU5(8 downto 5)));
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5);
zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' &
(zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' &
(zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU6 <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5 <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & NOT (d_i(3 downto 0))) + reg_F(0);
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s574 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
END IF;
WHEN s574 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) +
unsigned ((zw_ALU6(8 downto 5)));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) +
unsigned ((zw_ALU5(8 downto 5)));
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5);
zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' &
(zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' &
(zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU6 <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5 <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & NOT (d_i(3 downto 0))) + reg_F(0);
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s548 =>
if (rdy_i = '1') then
END IF;
WHEN s548 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
4994,8 → 4934,8
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
end if;
when s551 =>
END IF;
WHEN s551 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
5002,7 → 4942,7
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
when s552 =>
WHEN s552 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
5009,13 → 4949,13
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F;
when s577 =>
if (rdy_i = '1') then
WHEN s577 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s532 =>
if (rdy_i = '1') then
END IF;
WHEN s532 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
5023,8 → 4963,8
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
end if;
when s533 =>
END IF;
WHEN s533 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
5031,7 → 4971,7
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
when s534 =>
WHEN s534 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
5038,18 → 4978,18
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F;
when s537 =>
if (rdy_i = '1') then
WHEN s537 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when others =>
null;
end case;
end process output_proc;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS output_proc;
-- Concurrent Statements
-- Clocked output assignments
5058,4 → 4998,4
sync_o <= sync_o_cld;
wr_n_o <= wr_n_o_cld;
wr_o <= wr_o_cld;
end fsm;
END fsm;
/trunk/rtl/vhdl/core.vhd
1,8 → 1,8
-- VHDL Entity R6502_TC.Core.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:53:21 04.01.2009
-- by - eda.UNKNOWN (TEST)
-- at - 19:21:54 07.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
10,26 → 10,26
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
entity Core is
port(
clk_clk_i : in std_logic;
d_i : in std_logic_vector (7 downto 0);
irq_n_i : in std_logic;
nmi_n_i : in std_logic;
rdy_i : in std_logic;
rst_rst_n_i : in std_logic;
so_n_i : in std_logic;
a_o : out std_logic_vector (15 downto 0);
d_o : out std_logic_vector (7 downto 0);
rd_o : out std_logic;
sync_o : out std_logic;
wr_n_o : out std_logic;
wr_o : out std_logic
ENTITY Core IS
PORT(
clk_clk_i : IN std_logic;
d_i : IN std_logic_vector (7 DOWNTO 0);
irq_n_i : IN std_logic;
nmi_n_i : IN std_logic;
rdy_i : IN std_logic;
rst_rst_n_i : IN std_logic;
so_n_i : IN std_logic;
a_o : OUT std_logic_vector (15 DOWNTO 0);
d_o : OUT std_logic_vector (7 DOWNTO 0);
rd_o : OUT std_logic;
sync_o : OUT std_logic;
wr_n_o : OUT std_logic;
wr_o : OUT std_logic
);
 
-- Declarations
 
end Core ;
END Core ;
 
-- Jens-D. Gutschmidt Project: R6502_TC
-- scantara2003@yahoo.de
49,13 → 49,13
-- <<-- more -->>
-- Title: Core
-- Path: R6502_TC/Core/struct
-- Edited: by eda on 04 Jan 2009
-- Edited: by eda on 07 Jan 2009
--
-- VHDL Architecture R6502_TC.Core.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:53:22 04.01.2009
-- by - eda.UNKNOWN (TEST)
-- at - 19:21:55 07.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
63,190 → 63,175
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
library R6502_TC;
 
architecture struct of Core is
ARCHITECTURE struct OF Core IS
 
-- Architecture declarations
 
-- Internal signal declarations
signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0);
signal adr_o_i : std_logic_vector(15 downto 0);
signal adr_pc_o_i : std_logic_vector(15 downto 0);
signal adr_sp_o_i : std_logic_vector(15 downto 0);
signal ch_a_o_i : std_logic_vector(7 downto 0);
signal ch_b_o_i : std_logic_vector(7 downto 0);
signal d_alu_n_o_i : std_logic;
signal d_alu_o_i : std_logic_vector(7 downto 0);
signal d_alu_or_o_i : std_logic;
signal d_regs_in_o_i : std_logic_vector(7 downto 0);
signal d_regs_out_o_i : std_logic_vector(7 downto 0);
signal fetch_o_i : std_logic;
signal ld_o_i : std_logic_vector(1 downto 0);
signal ld_pc_o_i : std_logic;
signal ld_sp_o_i : std_logic;
signal load_regs_o_i : std_logic;
signal nmi_o_i : std_logic;
signal offset_o_i : std_logic_vector(15 downto 0);
signal q_a_o_i : std_logic_vector(7 downto 0);
signal q_x_o_i : std_logic_vector(7 downto 0);
signal q_y_o_i : std_logic_vector(7 downto 0);
signal reg_0flag_o_i : std_logic;
signal reg_1flag_o_i : std_logic;
signal reg_7flag_o_i : std_logic;
signal sel_pc_as_o_i : std_logic;
signal sel_pc_in_o_i : std_logic;
signal sel_pc_val_o_i : std_logic_vector(1 downto 0);
signal sel_rb_in_o_i : std_logic_vector(1 downto 0);
signal sel_rb_out_o_i : std_logic_vector(1 downto 0);
signal sel_reg_o_i : std_logic_vector(1 downto 0);
signal sel_sp_as_o_i : std_logic;
signal sel_sp_in_o_i : std_logic;
SIGNAL adr_nxt_pc_o_i : std_logic_vector(15 DOWNTO 0);
SIGNAL adr_o_i : std_logic_vector(15 DOWNTO 0);
SIGNAL adr_pc_o_i : std_logic_vector(15 DOWNTO 0);
SIGNAL adr_sp_o_i : std_logic_vector(15 DOWNTO 0);
SIGNAL ch_a_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL ch_b_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL d_alu_n_o_i : std_logic;
SIGNAL d_alu_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL d_alu_or_o_i : std_logic;
SIGNAL d_regs_in_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL d_regs_out_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL fetch_o_i : std_logic;
SIGNAL ld_o_i : std_logic_vector(1 DOWNTO 0);
SIGNAL ld_pc_o_i : std_logic;
SIGNAL ld_sp_o_i : std_logic;
SIGNAL load_regs_o_i : std_logic;
SIGNAL nmi_o_i : std_logic;
SIGNAL offset_o_i : std_logic_vector(15 DOWNTO 0);
SIGNAL q_a_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL q_x_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL q_y_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL reg_0flag_o_i : std_logic;
SIGNAL reg_1flag_o_i : std_logic;
SIGNAL reg_7flag_o_i : std_logic;
SIGNAL sel_pc_in_o_i : std_logic;
SIGNAL sel_pc_val_o_i : std_logic_vector(1 DOWNTO 0);
SIGNAL sel_rb_in_o_i : std_logic_vector(1 DOWNTO 0);
SIGNAL sel_rb_out_o_i : std_logic_vector(1 DOWNTO 0);
SIGNAL sel_reg_o_i : std_logic_vector(1 DOWNTO 0);
SIGNAL sel_sp_as_o_i : std_logic;
SIGNAL sel_sp_in_o_i : std_logic;
 
 
-- ModuleWare signal declarations(v1.9) for instance 'U_11' of 'add'
signal mw_U_11temp_din0 : std_logic_vector(8 downto 0);
signal mw_U_11temp_din1 : std_logic_vector(8 downto 0);
signal mw_U_11sum : unsigned(8 downto 0);
 
-- Component Declarations
component FSM_Execution_Unit
port (
adr_nxt_pc_i : in std_logic_vector (15 downto 0);
adr_pc_i : in std_logic_vector (15 downto 0);
adr_sp_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic ;
d_alu_i : in std_logic_vector ( 7 downto 0 );
d_i : in std_logic_vector ( 7 downto 0 );
d_regs_out_i : in std_logic_vector ( 7 downto 0 );
irq_n_i : in std_logic ;
nmi_i : in std_logic ;
q_a_i : in std_logic_vector ( 7 downto 0 );
q_x_i : in std_logic_vector ( 7 downto 0 );
q_y_i : in std_logic_vector ( 7 downto 0 );
rdy_i : in std_logic ;
reg_0flag_i : in std_logic ;
reg_1flag_i : in std_logic ;
reg_7flag_i : in std_logic ;
rst_rst_n_i : in std_logic ;
so_n_i : in std_logic ;
a_o : out std_logic_vector (15 downto 0);
adr_o : out std_logic_vector (15 downto 0);
ch_a_o : out std_logic_vector ( 7 downto 0 );
ch_b_o : out std_logic_vector ( 7 downto 0 );
d_o : out std_logic_vector ( 7 downto 0 );
d_regs_in_o : out std_logic_vector ( 7 downto 0 );
fetch_o : out std_logic ;
ld_o : out std_logic_vector ( 1 downto 0 );
ld_pc_o : out std_logic ;
ld_sp_o : out std_logic ;
load_regs_o : out std_logic ;
offset_o : out std_logic_vector ( 15 downto 0 );
rd_o : out std_logic ;
sel_pc_as_o : out std_logic ;
sel_pc_in_o : out std_logic ;
sel_pc_val_o : out std_logic_vector ( 1 downto 0 );
sel_rb_in_o : out std_logic_vector ( 1 downto 0 );
sel_rb_out_o : out std_logic_vector ( 1 downto 0 );
sel_reg_o : out std_logic_vector ( 1 downto 0 );
sel_sp_as_o : out std_logic ;
sel_sp_in_o : out std_logic ;
sync_o : out std_logic ;
wr_n_o : out std_logic ;
wr_o : out std_logic
COMPONENT FSM_Execution_Unit
PORT (
adr_nxt_pc_i : IN std_logic_vector (15 DOWNTO 0);
adr_pc_i : IN std_logic_vector (15 DOWNTO 0);
adr_sp_i : IN std_logic_vector (15 DOWNTO 0);
clk_clk_i : IN std_logic ;
d_alu_i : IN std_logic_vector ( 7 DOWNTO 0 );
d_i : IN std_logic_vector ( 7 DOWNTO 0 );
d_regs_out_i : IN std_logic_vector ( 7 DOWNTO 0 );
irq_n_i : IN std_logic ;
nmi_i : IN std_logic ;
q_a_i : IN std_logic_vector ( 7 DOWNTO 0 );
q_x_i : IN std_logic_vector ( 7 DOWNTO 0 );
q_y_i : IN std_logic_vector ( 7 DOWNTO 0 );
rdy_i : IN std_logic ;
reg_0flag_i : IN std_logic ;
reg_1flag_i : IN std_logic ;
reg_7flag_i : IN std_logic ;
rst_rst_n_i : IN std_logic ;
so_n_i : IN std_logic ;
a_o : OUT std_logic_vector (15 DOWNTO 0);
adr_o : OUT std_logic_vector (15 DOWNTO 0);
ch_a_o : OUT std_logic_vector ( 7 DOWNTO 0 );
ch_b_o : OUT std_logic_vector ( 7 DOWNTO 0 );
d_o : OUT std_logic_vector ( 7 DOWNTO 0 );
d_regs_in_o : OUT std_logic_vector ( 7 DOWNTO 0 );
fetch_o : OUT std_logic ;
ld_o : OUT std_logic_vector ( 1 DOWNTO 0 );
ld_pc_o : OUT std_logic ;
ld_sp_o : OUT std_logic ;
load_regs_o : OUT std_logic ;
offset_o : OUT std_logic_vector ( 15 DOWNTO 0 );
rd_o : OUT std_logic ;
sel_pc_in_o : OUT std_logic ;
sel_pc_val_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_rb_in_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_rb_out_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_reg_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_sp_as_o : OUT std_logic ;
sel_sp_in_o : OUT std_logic ;
sync_o : OUT std_logic ;
wr_n_o : OUT std_logic ;
wr_o : OUT std_logic
);
end component;
component FSM_NMI
port (
clk_clk_i : in std_logic ;
fetch_i : in std_logic ;
nmi_n_i : in std_logic ;
rst_rst_n_i : in std_logic ;
nmi_o : out std_logic
END COMPONENT;
COMPONENT FSM_NMI
PORT (
clk_clk_i : IN std_logic ;
fetch_i : IN std_logic ;
nmi_n_i : IN std_logic ;
rst_rst_n_i : IN std_logic ;
nmi_o : OUT std_logic
);
end component;
component RegBank_AXY
port (
clk_clk_i : in std_logic ;
d_regs_in_i : in std_logic_vector (7 downto 0);
load_regs_i : in std_logic ;
rst_rst_n_i : in std_logic ;
sel_rb_in_i : in std_logic_vector (1 downto 0);
sel_rb_out_i : in std_logic_vector (1 downto 0);
sel_reg_i : in std_logic_vector (1 downto 0);
d_regs_out_o : out std_logic_vector (7 downto 0);
q_a_o : out std_logic_vector (7 downto 0);
q_x_o : out std_logic_vector (7 downto 0);
q_y_o : out std_logic_vector (7 downto 0)
END COMPONENT;
COMPONENT RegBank_AXY
PORT (
clk_clk_i : IN std_logic ;
d_regs_in_i : IN std_logic_vector (7 DOWNTO 0);
load_regs_i : IN std_logic ;
rst_rst_n_i : IN std_logic ;
sel_rb_in_i : IN std_logic_vector (1 DOWNTO 0);
sel_rb_out_i : IN std_logic_vector (1 DOWNTO 0);
sel_reg_i : IN std_logic_vector (1 DOWNTO 0);
d_regs_out_o : OUT std_logic_vector (7 DOWNTO 0);
q_a_o : OUT std_logic_vector (7 DOWNTO 0);
q_x_o : OUT std_logic_vector (7 DOWNTO 0);
q_y_o : OUT std_logic_vector (7 DOWNTO 0)
);
end component;
component Reg_PC
port (
adr_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic ;
ld_i : in std_logic_vector (1 downto 0);
ld_pc_i : in std_logic ;
offset_i : in std_logic_vector (15 downto 0);
rst_rst_n_i : in std_logic ;
sel_pc_as_i : in std_logic ;
sel_pc_in_i : in std_logic ;
sel_pc_val_i : in std_logic_vector (1 downto 0);
adr_nxt_pc_o : out std_logic_vector (15 downto 0);
adr_pc_o : out std_logic_vector (15 downto 0)
END COMPONENT;
COMPONENT Reg_PC
PORT (
adr_i : IN std_logic_vector (15 DOWNTO 0);
clk_clk_i : IN std_logic ;
ld_i : IN std_logic_vector (1 DOWNTO 0);
ld_pc_i : IN std_logic ;
offset_i : IN std_logic_vector (15 DOWNTO 0);
rst_rst_n_i : IN std_logic ;
sel_pc_in_i : IN std_logic ;
sel_pc_val_i : IN std_logic_vector (1 DOWNTO 0);
adr_nxt_pc_o : OUT std_logic_vector (15 DOWNTO 0);
adr_pc_o : OUT std_logic_vector (15 DOWNTO 0)
);
end component;
component Reg_SP
port (
adr_low_i : in std_logic_vector (7 downto 0);
clk_clk_i : in std_logic ;
ld_low_i : in std_logic ;
ld_sp_i : in std_logic ;
rst_rst_n_i : in std_logic ;
sel_sp_as_i : in std_logic ;
sel_sp_in_i : in std_logic ;
adr_sp_o : out std_logic_vector (15 downto 0)
END COMPONENT;
COMPONENT Reg_SP
PORT (
adr_low_i : IN std_logic_vector (7 DOWNTO 0);
clk_clk_i : IN std_logic ;
ld_low_i : IN std_logic ;
ld_sp_i : IN std_logic ;
rst_rst_n_i : IN std_logic ;
sel_sp_as_i : IN std_logic ;
sel_sp_in_i : IN std_logic ;
adr_sp_o : OUT std_logic_vector (15 DOWNTO 0)
);
end component;
END COMPONENT;
 
-- Optional embedded configurations
-- pragma synthesis_off
for all : FSM_Execution_Unit use entity R6502_TC.FSM_Execution_Unit;
for all : FSM_NMI use entity R6502_TC.FSM_NMI;
for all : RegBank_AXY use entity R6502_TC.RegBank_AXY;
for all : Reg_PC use entity R6502_TC.Reg_PC;
for all : Reg_SP use entity R6502_TC.Reg_SP;
-- pragma synthesis_on
 
BEGIN
 
begin
 
-- ModuleWare code(v1.9) for instance 'U_11' of 'add'
mw_U_11temp_din0 <= '0' & ch_a_o_i;
mw_U_11temp_din1 <= '0' & ch_b_o_i;
u_11combo_proc: process (mw_U_11temp_din0, mw_U_11temp_din1)
variable temp_carry : std_logic;
begin
u_11combo_proc: PROCESS (ch_a_o_i, ch_b_o_i)
VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0);
VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0);
VARIABLE temp_sum : unsigned(8 DOWNTO 0);
VARIABLE temp_carry : std_logic;
BEGIN
temp_din0 := '0' & ch_a_o_i;
temp_din1 := '0' & ch_b_o_i;
temp_carry := '0';
mw_U_11sum <= unsigned(mw_U_11temp_din0) + unsigned(mw_U_11temp_din1) + temp_carry;
end process u_11combo_proc;
d_alu_o_i <= conv_std_logic_vector(mw_U_11sum(7 downto 0),8);
reg_0flag_o_i <= mw_U_11sum(8) ;
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
d_alu_o_i <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8);
reg_0flag_o_i <= temp_sum(8) ;
END PROCESS u_11combo_proc;
 
-- ModuleWare code(v1.9) for instance 'U_8' of 'inv'
reg_1flag_o_i <= not(d_alu_or_o_i);
reg_1flag_o_i <= NOT(d_alu_or_o_i);
 
-- ModuleWare code(v1.9) for instance 'U_9' of 'inv'
reg_7flag_o_i <= not(d_alu_n_o_i);
reg_7flag_o_i <= NOT(d_alu_n_o_i);
 
-- ModuleWare code(v1.9) for instance 'U_10' of 'inv'
d_alu_n_o_i <= not(d_alu_o_i(7));
d_alu_n_o_i <= NOT(d_alu_o_i(7));
 
-- ModuleWare code(v1.9) for instance 'U_7' of 'por'
d_alu_or_o_i <= d_alu_o_i(0) or d_alu_o_i(1) or d_alu_o_i(2) or d_alu_o_i(3) or d_alu_o_i(4) or d_alu_o_i(5) or d_alu_o_i(6) or d_alu_o_i(7);
d_alu_or_o_i <= d_alu_o_i(0) OR d_alu_o_i(1) OR d_alu_o_i(2) OR d_alu_o_i(3) OR d_alu_o_i(4) OR d_alu_o_i(5) OR d_alu_o_i(6) OR d_alu_o_i(7);
 
-- Instance port mappings.
U_4 : FSM_Execution_Unit
port map (
PORT MAP (
adr_nxt_pc_i => adr_nxt_pc_o_i,
adr_pc_i => adr_pc_o_i,
adr_sp_i => adr_sp_o_i,
278,7 → 263,6
load_regs_o => load_regs_o_i,
offset_o => offset_o_i,
rd_o => rd_o,
sel_pc_as_o => sel_pc_as_o_i,
sel_pc_in_o => sel_pc_in_o_i,
sel_pc_val_o => sel_pc_val_o_i,
sel_rb_in_o => sel_rb_in_o_i,
291,7 → 275,7
wr_o => wr_o
);
U_6 : FSM_NMI
port map (
PORT MAP (
clk_clk_i => clk_clk_i,
fetch_i => fetch_o_i,
nmi_n_i => nmi_n_i,
299,7 → 283,7
nmi_o => nmi_o_i
);
U_2 : RegBank_AXY
port map (
PORT MAP (
clk_clk_i => clk_clk_i,
d_regs_in_i => d_regs_in_o_i,
load_regs_i => load_regs_o_i,
313,7 → 297,7
q_y_o => q_y_o_i
);
U_0 : Reg_PC
port map (
PORT MAP (
adr_i => adr_o_i,
clk_clk_i => clk_clk_i,
ld_i => ld_o_i,
320,7 → 304,6
ld_pc_i => ld_pc_o_i,
offset_i => offset_o_i,
rst_rst_n_i => rst_rst_n_i,
sel_pc_as_i => sel_pc_as_o_i,
sel_pc_in_i => sel_pc_in_o_i,
sel_pc_val_i => sel_pc_val_o_i,
adr_nxt_pc_o => adr_nxt_pc_o_i,
327,7 → 310,7
adr_pc_o => adr_pc_o_i
);
U_1 : Reg_SP
port map (
PORT MAP (
adr_low_i => adr_o_i(7 DOWNTO 0),
clk_clk_i => clk_clk_i,
ld_low_i => ld_o_i(0),
338,4 → 321,4
adr_sp_o => adr_sp_o_i
);
 
end struct;
END struct;
/trunk/rtl/vhdl/fsm_nmi.vhd
1,8 → 1,8
-- VHDL Entity R6502_TC.FSM_NMI.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:53:21 04.01.2009
-- by - eda.UNKNOWN (TEST)
-- at - 18:46:08 07.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
10,18 → 10,18
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
entity FSM_NMI is
port(
clk_clk_i : in std_logic;
fetch_i : in std_logic;
nmi_n_i : in std_logic;
rst_rst_n_i : in std_logic;
nmi_o : out std_logic
ENTITY FSM_NMI IS
PORT(
clk_clk_i : IN std_logic;
fetch_i : IN std_logic;
nmi_n_i : IN std_logic;
rst_rst_n_i : IN std_logic;
nmi_o : OUT std_logic
);
 
-- Declarations
 
end FSM_NMI ;
END FSM_NMI ;
 
-- Jens-D. Gutschmidt Project: R6502_TC
 
59,14 → 59,14
 
-- Path: R6502_TC/FSM_NMI/fsm
 
-- Edited: by eda on 03 Jan 2009
-- Edited: by eda on 07 Jan 2009
 
--
-- VHDL Architecture R6502_TC.FSM_NMI.fsm
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:53:21 04.01.2009
-- by - eda.UNKNOWN (TEST)
-- at - 18:46:08 07.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
74,94 → 74,91
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
architecture fsm of FSM_NMI is
ARCHITECTURE fsm OF FSM_NMI IS
 
type state_type is (
idle,
idle1,
idle2,
IMP
);
SUBTYPE STATE_TYPE IS
std_logic_vector(1 DOWNTO 0);
-- State vector declaration
attribute state_vector : string;
attribute state_vector of fsm : architecture is "current_state";
-- Hard encoding
CONSTANT idle : STATE_TYPE := "00";
CONSTANT idle1 : STATE_TYPE := "01";
CONSTANT idle2 : STATE_TYPE := "11";
CONSTANT IMP : STATE_TYPE := "10";
 
-- Declare current and next state signals
signal current_state : state_type;
signal next_state : state_type;
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;
 
-- Declare any pre-registered internal signals
signal nmi_o_cld : std_logic ;
SIGNAL nmi_o_cld : std_logic ;
 
begin
BEGIN
 
-----------------------------------------------------------------
clocked_proc : process (
clocked_proc : PROCESS (
clk_clk_i,
rst_rst_n_i
)
-----------------------------------------------------------------
begin
if (rst_rst_n_i = '0') then
BEGIN
IF (rst_rst_n_i = '0') THEN
current_state <= idle;
-- Default Reset Values
nmi_o_cld <= '0';
elsif (clk_clk_i'event and clk_clk_i = '1') then
ELSIF (clk_clk_i'EVENT AND clk_clk_i = '1') THEN
current_state <= next_state;
-- Default Assignment To Internals
nmi_o_cld <= '0';
 
-- Combined Actions
case current_state is
when IMP =>
CASE current_state IS
WHEN IMP =>
nmi_o_cld <= '1';
when others =>
null;
end case;
end if;
end process clocked_proc;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END PROCESS clocked_proc;
-----------------------------------------------------------------
nextstate_proc : process (
nextstate_proc : PROCESS (
current_state,
fetch_i,
nmi_n_i
)
-----------------------------------------------------------------
begin
case current_state is
-- <<< REQ1
when idle =>
if (nmi_n_i = '1') then
BEGIN
CASE current_state IS
WHEN idle =>
IF (nmi_n_i = '1') THEN
next_state <= idle1;
else
ELSE
next_state <= idle;
end if;
when idle1 =>
if (nmi_n_i = '0') then
END IF;
WHEN idle1 =>
IF (nmi_n_i = '0') THEN
next_state <= idle2;
else
ELSE
next_state <= idle1;
end if;
when idle2 =>
if (nmi_n_i = '0') then
END IF;
WHEN idle2 =>
IF (nmi_n_i = '0') THEN
next_state <= IMP;
else
ELSE
next_state <= idle;
end if;
when IMP =>
if (fetch_i = '1') then
END IF;
WHEN IMP =>
IF (fetch_i = '1') THEN
next_state <= idle;
else
ELSE
next_state <= IMP;
end if;
when others =>
END IF;
WHEN OTHERS =>
next_state <= idle;
end case;
end process nextstate_proc;
END CASE;
END PROCESS nextstate_proc;
-- Concurrent Statements
-- Clocked output assignments
nmi_o <= nmi_o_cld;
end fsm;
END fsm;
/trunk/rtl/vhdl/regbank_axy.vhd
1,8 → 1,8
-- VHDL Entity R6502_TC.RegBank_AXY.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:53:06 04.01.2009
-- by - eda.UNKNOWN (TEST)
-- at - 18:23:46 07.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
10,24 → 10,24
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
entity RegBank_AXY is
port(
clk_clk_i : in std_logic;
d_regs_in_i : in std_logic_vector (7 downto 0);
load_regs_i : in std_logic;
rst_rst_n_i : in std_logic;
sel_rb_in_i : in std_logic_vector (1 downto 0);
sel_rb_out_i : in std_logic_vector (1 downto 0);
sel_reg_i : in std_logic_vector (1 downto 0);
d_regs_out_o : out std_logic_vector (7 downto 0);
q_a_o : out std_logic_vector (7 downto 0);
q_x_o : out std_logic_vector (7 downto 0);
q_y_o : out std_logic_vector (7 downto 0)
ENTITY RegBank_AXY IS
PORT(
clk_clk_i : IN std_logic;
d_regs_in_i : IN std_logic_vector (7 DOWNTO 0);
load_regs_i : IN std_logic;
rst_rst_n_i : IN std_logic;
sel_rb_in_i : IN std_logic_vector (1 DOWNTO 0);
sel_rb_out_i : IN std_logic_vector (1 DOWNTO 0);
sel_reg_i : IN std_logic_vector (1 DOWNTO 0);
d_regs_out_o : OUT std_logic_vector (7 DOWNTO 0);
q_a_o : OUT std_logic_vector (7 DOWNTO 0);
q_x_o : OUT std_logic_vector (7 DOWNTO 0);
q_y_o : OUT std_logic_vector (7 DOWNTO 0)
);
 
-- Declarations
 
end RegBank_AXY ;
END RegBank_AXY ;
 
-- Jens-D. Gutschmidt Project: R6502_TC
-- scantara2003@yahoo.de
52,8 → 52,8
-- VHDL Architecture R6502_TC.RegBank_AXY.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:53:07 04.01.2009
-- by - eda.UNKNOWN (TEST)
-- at - 18:23:46 07.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
62,124 → 62,124
USE ieee.std_logic_arith.all;
 
 
architecture struct of RegBank_AXY is
ARCHITECTURE struct OF RegBank_AXY IS
 
-- Architecture declarations
 
-- Internal signal declarations
signal ld : std_logic_vector(2 downto 0);
signal load1_o_i : std_logic;
signal load2_o_i : std_logic;
signal load_o_i : std_logic;
signal q_mux_o_i : std_logic_vector(7 downto 0);
signal val_zero : std_logic_vector(7 downto 0);
SIGNAL ld : std_logic_vector(2 DOWNTO 0);
SIGNAL load1_o_i : std_logic;
SIGNAL load2_o_i : std_logic;
SIGNAL load_o_i : std_logic;
SIGNAL q_mux_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL val_zero : std_logic_vector(7 DOWNTO 0);
 
-- Implicit buffer signal declarations
signal q_a_o_internal : std_logic_vector (7 downto 0);
signal q_x_o_internal : std_logic_vector (7 downto 0);
signal q_y_o_internal : std_logic_vector (7 downto 0);
SIGNAL q_a_o_internal : std_logic_vector (7 DOWNTO 0);
SIGNAL q_x_o_internal : std_logic_vector (7 DOWNTO 0);
SIGNAL q_y_o_internal : std_logic_vector (7 DOWNTO 0);
 
 
-- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
signal mw_U_0reg_cval : std_logic_vector(7 downto 0);
SIGNAL mw_U_0reg_cval : std_logic_vector(7 DOWNTO 0);
 
-- ModuleWare signal declarations(v1.9) for instance 'U_4' of 'adff'
signal mw_U_4reg_cval : std_logic_vector(7 downto 0);
SIGNAL mw_U_4reg_cval : std_logic_vector(7 DOWNTO 0);
 
-- ModuleWare signal declarations(v1.9) for instance 'U_5' of 'adff'
signal mw_U_5reg_cval : std_logic_vector(7 downto 0);
SIGNAL mw_U_5reg_cval : std_logic_vector(7 DOWNTO 0);
 
 
begin
BEGIN
 
-- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
q_a_o_internal <= mw_U_0reg_cval;
u_0seq_proc: process (clk_clk_i, rst_rst_n_i)
begin
if (rst_rst_n_i = '0') then
u_0seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
BEGIN
IF (rst_rst_n_i = '0' OR rst_rst_n_i = 'L') THEN
mw_U_0reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1') then
if (load_o_i = '1') then
ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
IF (load_o_i = '1' OR load_o_i = 'H') THEN
mw_U_0reg_cval <= q_mux_o_i;
end if;
end if;
end process u_0seq_proc;
END IF;
END IF;
END PROCESS u_0seq_proc;
 
-- ModuleWare code(v1.9) for instance 'U_4' of 'adff'
q_x_o_internal <= mw_U_4reg_cval;
u_4seq_proc: process (clk_clk_i, rst_rst_n_i)
begin
if (rst_rst_n_i = '0') then
u_4seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
BEGIN
IF (rst_rst_n_i = '0' OR rst_rst_n_i = 'L') THEN
mw_U_4reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1') then
if (load1_o_i = '1') then
ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
IF (load1_o_i = '1' OR load1_o_i = 'H') THEN
mw_U_4reg_cval <= q_mux_o_i;
end if;
end if;
end process u_4seq_proc;
END IF;
END IF;
END PROCESS u_4seq_proc;
 
-- ModuleWare code(v1.9) for instance 'U_5' of 'adff'
q_y_o_internal <= mw_U_5reg_cval;
u_5seq_proc: process (clk_clk_i, rst_rst_n_i)
begin
if (rst_rst_n_i = '0') then
u_5seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
BEGIN
IF (rst_rst_n_i = '0' OR rst_rst_n_i = 'L') THEN
mw_U_5reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1') then
if (load2_o_i = '1') then
ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
IF (load2_o_i = '1' OR load2_o_i = 'H') THEN
mw_U_5reg_cval <= q_mux_o_i;
end if;
end if;
end process u_5seq_proc;
END IF;
END IF;
END PROCESS u_5seq_proc;
 
-- ModuleWare code(v1.9) for instance 'U_6' of 'and'
load_o_i <= load_regs_i and ld(0);
load_o_i <= load_regs_i AND ld(0);
 
-- ModuleWare code(v1.9) for instance 'U_7' of 'and'
load1_o_i <= load_regs_i and ld(1);
load1_o_i <= load_regs_i AND ld(1);
 
-- ModuleWare code(v1.9) for instance 'U_8' of 'and'
load2_o_i <= load_regs_i and ld(2);
load2_o_i <= load_regs_i AND ld(2);
 
-- ModuleWare code(v1.9) for instance 'U_11' of 'constval'
val_zero <= "00000000";
 
-- ModuleWare code(v1.9) for instance 'U_1' of 'decoder1'
u_1combo_proc: process (sel_reg_i)
begin
ld <= (others => '0');
case sel_reg_i is
when "00" => ld(0) <= '1';
when "01" => ld(1) <= '1';
when "10" => ld(2) <= '1';
when others => ld <= (others => '0');
end case;
end process u_1combo_proc;
u_1combo_proc: PROCESS (sel_reg_i)
BEGIN
ld <= (OTHERS => '0');
CASE sel_reg_i IS
WHEN "00" => ld(0) <= '1';
WHEN "01" => ld(1) <= '1';
WHEN "10" => ld(2) <= '1';
WHEN OTHERS => ld <= (OTHERS => '0');
END CASE;
END PROCESS u_1combo_proc;
 
-- ModuleWare code(v1.9) for instance 'U_2' of 'mux'
u_2combo_proc: process(q_a_o_internal, q_x_o_internal, q_y_o_internal,
u_2combo_proc: PROCESS(q_a_o_internal, q_x_o_internal, q_y_o_internal,
val_zero, sel_rb_out_i)
begin
case sel_rb_out_i is
when "00" => d_regs_out_o <= q_a_o_internal;
when "01" => d_regs_out_o <= q_x_o_internal;
when "10" => d_regs_out_o <= q_y_o_internal;
when "11" => d_regs_out_o <= val_zero;
when others => d_regs_out_o <= (others => 'X');
end case;
end process u_2combo_proc;
BEGIN
CASE sel_rb_out_i IS
WHEN "00"|"L0"|"0L"|"LL" => d_regs_out_o <= q_a_o_internal;
WHEN "01"|"L1"|"0H"|"LH" => d_regs_out_o <= q_x_o_internal;
WHEN "10"|"H0"|"1L"|"HL" => d_regs_out_o <= q_y_o_internal;
WHEN "11"|"H1"|"1H"|"HH" => d_regs_out_o <= val_zero;
WHEN OTHERS => d_regs_out_o <= (OTHERS => 'X');
END CASE;
END PROCESS u_2combo_proc;
 
-- ModuleWare code(v1.9) for instance 'U_3' of 'mux'
u_3combo_proc: process(q_a_o_internal, q_y_o_internal, q_x_o_internal,
u_3combo_proc: PROCESS(q_a_o_internal, q_y_o_internal, q_x_o_internal,
d_regs_in_i, sel_rb_in_i)
begin
case sel_rb_in_i is
when "00" => q_mux_o_i <= q_a_o_internal;
when "01" => q_mux_o_i <= q_y_o_internal;
when "10" => q_mux_o_i <= q_x_o_internal;
when "11" => q_mux_o_i <= d_regs_in_i;
when others => q_mux_o_i <= (others => 'X');
end case;
end process u_3combo_proc;
BEGIN
CASE sel_rb_in_i IS
WHEN "00"|"L0"|"0L"|"LL" => q_mux_o_i <= q_a_o_internal;
WHEN "01"|"L1"|"0H"|"LH" => q_mux_o_i <= q_y_o_internal;
WHEN "10"|"H0"|"1L"|"HL" => q_mux_o_i <= q_x_o_internal;
WHEN "11"|"H1"|"1H"|"HH" => q_mux_o_i <= d_regs_in_i;
WHEN OTHERS => q_mux_o_i <= (OTHERS => 'X');
END CASE;
END PROCESS u_3combo_proc;
 
-- Instance port mappings.
 
188,4 → 188,4
q_x_o <= q_x_o_internal;
q_y_o <= q_y_o_internal;
 
end struct;
END struct;

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