URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 13 to Rev 14
- ↔ Reverse comparison
Rev 13 → Rev 14
/neorv32/trunk/.ci/install.sh
3,12 → 3,16
# Abort if any command returns != 0 |
set -e |
|
# Toolchain to be used |
TOOLCHAIN_V=riscv32-unknown-elf.gcc-10.1.0.rv32i.ilp32.newlib |
|
# Download toolchain |
wget https://github.com/stnolting/riscv_gcc_prebuilt/raw/master/data/riscv32-unknown-elf.gcc-9.2.0.rv32i.ilp32.tar.gz |
echo "Downloading prebuilt RISC-V GCC toolchain ($TOOLCHAIN_V)..." |
wget https://github.com/stnolting/riscv_gcc_prebuilt/raw/master/data/$TOOLCHAIN_V.tar.gz |
|
# Decompress |
mkdir riscv |
tar -xzf riscv32-unknown-elf.gcc-9.2.0.rv32i.ilp32.tar.gz -C riscv/ |
tar -xzf $TOOLCHAIN_V.tar.gz -C riscv/ |
pwd |
ls -al |
ls -al riscv/ |
/neorv32/trunk/docs/figures/neorv32_cpu.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/neorv32/trunk/docs/figures/neorv32_processor.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/neorv32/trunk/docs/NEORV32.pdf
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/neorv32/trunk/rtl/core/neorv32_clic.vhd
File deleted
/neorv32/trunk/rtl/core/neorv32_application_image.vhd
1,5 → 1,5
-- The NEORV32 Processor by Stephan Nolting, https://github.com/stnolting/neorv32 |
-- Auto-generated memory init file (for APPLICATION) from source file <cpu_test/main.bin> |
-- Auto-generated memory init file (for APPLICATION) from source file <blink_led/main.bin> |
|
library ieee; |
use ieee.std_logic_1164.all; |
8,1211 → 8,1009
|
type application_init_image_t is array (0 to 65535) of std_ulogic_vector(31 downto 0); |
constant application_init_image : application_init_image_t := ( |
00000000 => x"00930001", |
00000001 => x"81130000", |
00000002 => x"01930000", |
00000003 => x"82130001", |
00000004 => x"02930001", |
00000005 => x"83130002", |
00000006 => x"03930002", |
00000007 => x"84130003", |
00000008 => x"04930003", |
00000009 => x"85130004", |
00000010 => x"05930004", |
00000011 => x"86130005", |
00000012 => x"06930005", |
00000013 => x"87130006", |
00000014 => x"07930006", |
00000015 => x"88130007", |
00000016 => x"08930007", |
00000017 => x"89130008", |
00000018 => x"09930008", |
00000019 => x"8a130009", |
00000020 => x"0a930009", |
00000021 => x"8b13000a", |
00000022 => x"0b93000a", |
00000023 => x"8c13000b", |
00000024 => x"0c93000b", |
00000025 => x"8d13000c", |
00000026 => x"0d93000c", |
00000027 => x"8e13000d", |
00000028 => x"0e93000d", |
00000029 => x"8f13000e", |
00000030 => x"0f93000e", |
00000031 => x"0001000f", |
00000000 => x"00000093", |
00000001 => x"00008113", |
00000002 => x"00010193", |
00000003 => x"00018213", |
00000004 => x"00020293", |
00000005 => x"00028313", |
00000006 => x"00030393", |
00000007 => x"00038413", |
00000008 => x"00040493", |
00000009 => x"00048513", |
00000010 => x"00050593", |
00000011 => x"00058613", |
00000012 => x"00060693", |
00000013 => x"00068713", |
00000014 => x"00070793", |
00000015 => x"00078813", |
00000016 => x"00080893", |
00000017 => x"00088913", |
00000018 => x"00090993", |
00000019 => x"00098a13", |
00000020 => x"000a0a93", |
00000021 => x"000a8b13", |
00000022 => x"000b0b93", |
00000023 => x"000b8c13", |
00000024 => x"000c0c93", |
00000025 => x"000c8d13", |
00000026 => x"000d0d93", |
00000027 => x"000d8e13", |
00000028 => x"000e0e93", |
00000029 => x"000e8f13", |
00000030 => x"000f0f93", |
00000031 => x"00000013", |
00000032 => x"ff402583", |
00000033 => x"ffc02603", |
00000034 => x"00c58133", |
00000035 => x"04131171", |
00000036 => x"01970001", |
00000037 => x"81938000", |
00000038 => x"05977ee1", |
00000039 => x"85930000", |
00000040 => x"90730965", |
00000041 => x"25833055", |
00000042 => x"0617ff40", |
00000043 => x"06130000", |
00000044 => x"06931506", |
00000045 => x"c1900200", |
00000046 => x"16fd0591", |
00000047 => x"fed01de3", |
00000048 => x"f8000593", |
00000049 => x"0005a023", |
00000050 => x"1de30591", |
00000051 => x"0597feb0", |
00000052 => x"85938000", |
00000053 => x"8613fba5", |
00000054 => x"d66382c1", |
00000055 => x"802300c5", |
00000056 => x"05850005", |
00000057 => x"1597bfdd", |
00000058 => x"85930000", |
00000059 => x"06171e65", |
00000060 => x"06138000", |
00000061 => x"0697f926", |
00000062 => x"86938000", |
00000063 => x"5963f926", |
00000064 => x"870300d6", |
00000065 => x"00230005", |
00000066 => x"058500e6", |
00000067 => x"bfc50605", |
00000068 => x"00000513", |
00000069 => x"00000593", |
00000070 => x"0ee000ef", |
00000071 => x"30047073", |
00000072 => x"10500073", |
00000073 => x"0013a001", |
00000074 => x"00130000", |
00000075 => x"00010000", |
00000076 => x"f8810113", |
00000077 => x"c20ec006", |
00000078 => x"c616c412", |
00000079 => x"ca1ec81a", |
00000080 => x"ce26cc22", |
00000081 => x"d22ed02a", |
00000082 => x"d636d432", |
00000083 => x"da3ed83a", |
00000084 => x"de46dc42", |
00000085 => x"c2cec0ca", |
00000086 => x"c6d6c4d2", |
00000087 => x"cadec8da", |
00000088 => x"cee6cce2", |
00000089 => x"d2eed0ea", |
00000090 => x"d6f6d4f2", |
00000091 => x"dafed8fa", |
00000092 => x"342022f3", |
00000093 => x"00f2f313", |
00000094 => x"2083030a", |
00000095 => x"9306ff40", |
00000096 => x"341020f3", |
00000097 => x"0002cd63", |
00000098 => x"00009283", |
00000099 => x"00300393", |
00000100 => x"0072f2b3", |
00000101 => x"96630089", |
00000102 => x"00890072", |
00000103 => x"0313a019", |
00000104 => x"22830403", |
00000105 => x"11710003", |
00000106 => x"80e7c006", |
00000107 => x"40820002", |
00000108 => x"90730111", |
00000109 => x"40823410", |
00000110 => x"42224192", |
00000111 => x"434242b2", |
00000112 => x"446243d2", |
00000113 => x"550244f2", |
00000114 => x"56225592", |
00000115 => x"574256b2", |
00000116 => x"586257d2", |
00000117 => x"490658f2", |
00000118 => x"4a264996", |
00000119 => x"4b464ab6", |
00000120 => x"4c664bd6", |
00000121 => x"5d064cf6", |
00000122 => x"5e265d96", |
00000123 => x"5f465eb6", |
00000124 => x"01135fd6", |
00000125 => x"00730781", |
00000126 => x"80823020", |
00000127 => x"00000000", |
00000128 => x"00000000", |
00000129 => x"71390000", |
00000130 => x"dc22de06", |
00000131 => x"d84ada26", |
00000132 => x"d452d64e", |
00000133 => x"00efd256", |
00000134 => x"00631230", |
00000135 => x"00ef0c05", |
00000136 => x"0c632fb0", |
00000137 => x"00ef0a05", |
00000138 => x"08630410", |
00000139 => x"65150a05", |
00000140 => x"45814601", |
00000141 => x"b0050513", |
00000142 => x"10b000ef", |
00000143 => x"45814501", |
00000144 => x"031000ef", |
00000145 => x"557d55fd", |
00000146 => x"063000ef", |
00000147 => x"05136505", |
00000148 => x"00efd9c5", |
00000149 => x"00ef16f0", |
00000150 => x"00ef0090", |
00000151 => x"650560a0", |
00000152 => x"db850513", |
00000153 => x"00ef4481", |
00000154 => x"059315b0", |
00000155 => x"450177e0", |
00000156 => x"842a232d", |
00000157 => x"77e00593", |
00000158 => x"23054505", |
00000159 => x"0593942a", |
00000160 => x"450977e0", |
00000161 => x"942a2b19", |
00000162 => x"77e00593", |
00000163 => x"2331450d", |
00000164 => x"0593942a", |
00000165 => x"451177e0", |
00000166 => x"942a2309", |
00000167 => x"77e00593", |
00000168 => x"29e54515", |
00000169 => x"0593942a", |
00000170 => x"451977e0", |
00000171 => x"942a21fd", |
00000172 => x"77e00593", |
00000173 => x"21d5451d", |
00000174 => x"0593942a", |
00000175 => x"452d77e0", |
00000176 => x"942a29e9", |
00000177 => x"77e00593", |
00000178 => x"29c1455d", |
00000179 => x"c005942a", |
00000180 => x"05136505", |
00000181 => x"00efdd05", |
00000182 => x"50f20eb0", |
00000183 => x"54d25462", |
00000184 => x"59b25942", |
00000185 => x"5a925a22", |
00000186 => x"61214501", |
00000187 => x"05938082", |
00000188 => x"450177e0", |
00000189 => x"22f000ef", |
00000190 => x"c509842a", |
00000191 => x"05136505", |
00000192 => x"bfd1de45", |
00000193 => x"30046073", |
00000194 => x"650554fd", |
00000195 => x"8291a423", |
00000196 => x"dfc50513", |
00000197 => x"a4236985", |
00000198 => x"00ef8291", |
00000199 => x"85130a70", |
00000200 => x"00efe0c9", |
00000201 => x"650509f0", |
00000202 => x"e2050513", |
00000203 => x"8291a423", |
00000204 => x"091000ef", |
00000205 => x"e0c98513", |
00000206 => x"089000ef", |
00000207 => x"05136505", |
00000208 => x"00efe305", |
00000209 => x"17b707f0", |
00000210 => x"87931bcd", |
00000211 => x"90732347", |
00000212 => x"47b7b007", |
00000213 => x"87930003", |
00000214 => x"90734557", |
00000215 => x"2773b807", |
00000216 => x"76c1b000", |
00000217 => x"06b78f75", |
00000218 => x"12631bcd", |
00000219 => x"277332d7", |
00000220 => x"1e63b800", |
00000221 => x"650530f7", |
00000222 => x"e4050513", |
00000223 => x"045000ef", |
00000224 => x"65054485", |
00000225 => x"e4c50513", |
00000226 => x"039000ef", |
00000227 => x"112247b7", |
00000228 => x"49978793", |
00000229 => x"b0279073", |
00000230 => x"000907b7", |
00000231 => x"907307c5", |
00000232 => x"2773b827", |
00000233 => x"76c1b020", |
00000234 => x"06b78f75", |
00000235 => x"18631122", |
00000236 => x"27732ed7", |
00000237 => x"1463b820", |
00000238 => x"65052ef7", |
00000239 => x"e4050513", |
00000240 => x"001000ef", |
00000241 => x"65050485", |
00000242 => x"e5c50513", |
00000243 => x"7f4000ef", |
00000244 => x"c01027f3", |
00000245 => x"2af3c83e", |
00000246 => x"79c1c810", |
00000247 => x"0137fa33", |
00000248 => x"00efca56", |
00000249 => x"f9b36aa0", |
00000250 => x"116300a9", |
00000251 => x"9f632d3a", |
00000252 => x"65052aba", |
00000253 => x"e4050513", |
00000254 => x"7c8000ef", |
00000255 => x"65050485", |
00000256 => x"051359fd", |
00000257 => x"a423e6c5", |
00000258 => x"00ef8331", |
00000259 => x"000f7b60", |
00000260 => x"100f0ff0", |
00000261 => x"a7830000", |
00000262 => x"80638281", |
00000263 => x"65052b37", |
00000264 => x"e4450513", |
00000265 => x"79c000ef", |
00000266 => x"65050405", |
00000267 => x"051357fd", |
00000268 => x"a423e7c5", |
00000269 => x"00ef82f1", |
00000270 => x"27f378a0", |
00000271 => x"8b913010", |
00000272 => x"28079b63", |
00000273 => x"97824789", |
00000274 => x"8281a783", |
00000275 => x"26079e63", |
00000276 => x"05136505", |
00000277 => x"00efe405", |
00000278 => x"048576a0", |
00000279 => x"65054995", |
00000280 => x"051357fd", |
00000281 => x"a423eb85", |
00000282 => x"00ef82f1", |
00000283 => x"07937560", |
00000284 => x"9782f000", |
00000285 => x"8281a703", |
00000286 => x"15634785", |
00000287 => x"650526f7", |
00000288 => x"e4050513", |
00000289 => x"73c000ef", |
00000290 => x"65050485", |
00000291 => x"051357fd", |
00000292 => x"a423ec85", |
00000293 => x"00ef82f1", |
00000294 => x"07b772a0", |
00000295 => x"87938000", |
00000296 => x"80e70807", |
00000297 => x"a7030007", |
00000298 => x"47898281", |
00000299 => x"24f71363", |
00000300 => x"05136505", |
00000301 => x"00efe405", |
00000302 => x"048570a0", |
00000303 => x"57fd6505", |
00000304 => x"ed850513", |
00000305 => x"82f1a423", |
00000306 => x"6f8000ef", |
00000307 => x"a7039002", |
00000308 => x"478d8281", |
00000309 => x"22f71663", |
00000310 => x"05136505", |
00000311 => x"00efe405", |
00000312 => x"04856e20", |
00000313 => x"57fd6505", |
00000314 => x"ee850513", |
00000315 => x"82f1a423", |
00000316 => x"6d0000ef", |
00000317 => x"00202003", |
00000318 => x"8281a703", |
00000319 => x"18634791", |
00000320 => x"650520f7", |
00000321 => x"e4050513", |
00000322 => x"6b8000ef", |
00000323 => x"65050485", |
00000324 => x"051357fd", |
00000325 => x"a423ef85", |
00000326 => x"00ef82f1", |
00000327 => x"27836a60", |
00000328 => x"c63ef000", |
00000329 => x"8281a703", |
00000330 => x"19634795", |
00000331 => x"65051ef7", |
00000332 => x"e4050513", |
00000333 => x"68c000ef", |
00000334 => x"65050485", |
00000335 => x"051357fd", |
00000336 => x"a423f085", |
00000337 => x"00ef82f1", |
00000338 => x"212367a0", |
00000339 => x"a7030000", |
00000340 => x"47998281", |
00000341 => x"1cf71b63", |
00000342 => x"05136505", |
00000343 => x"00efe405", |
00000344 => x"04856620", |
00000345 => x"57fd6505", |
00000346 => x"f1850513", |
00000347 => x"82f1a423", |
00000348 => x"650000ef", |
00000349 => x"f0002023", |
00000350 => x"8281a703", |
00000351 => x"1d63479d", |
00000352 => x"65051af7", |
00000353 => x"e4050513", |
00000354 => x"638000ef", |
00000355 => x"65050485", |
00000356 => x"051357fd", |
00000357 => x"a423f285", |
00000358 => x"00ef82f1", |
00000359 => x"00736260", |
00000360 => x"a7030000", |
00000361 => x"47ad8281", |
00000362 => x"18f71f63", |
00000363 => x"05136505", |
00000364 => x"00efe405", |
00000365 => x"048560e0", |
00000366 => x"57fd6505", |
00000367 => x"f3850513", |
00000368 => x"82f1a423", |
00000369 => x"5fc000ef", |
00000370 => x"45814501", |
00000371 => x"4de000ef", |
00000372 => x"00010001", |
00000373 => x"00010001", |
00000374 => x"8281a703", |
00000375 => x"800007b7", |
00000376 => x"1863079d", |
00000377 => x"650516f7", |
00000378 => x"e4050513", |
00000379 => x"5d4000ef", |
00000380 => x"55fd0485", |
00000381 => x"00ef557d", |
00000382 => x"65054b40", |
00000383 => x"051357fd", |
00000384 => x"a423f485", |
00000385 => x"00ef82f1", |
00000386 => x"45015ba0", |
00000387 => x"76e000ef", |
00000388 => x"00010001", |
00000389 => x"00010001", |
00000390 => x"8281a703", |
00000391 => x"800007b7", |
00000392 => x"1e6307ad", |
00000393 => x"650512f7", |
00000394 => x"e4050513", |
00000395 => x"594000ef", |
00000396 => x"65050485", |
00000397 => x"051357fd", |
00000398 => x"a423f585", |
00000399 => x"00ef82f1", |
00000400 => x"21a95820", |
00000401 => x"051387aa", |
00000402 => x"37b33e85", |
00000403 => x"95be00f5", |
00000404 => x"29a109ad", |
00000405 => x"10500073", |
00000406 => x"8281a703", |
00000407 => x"800007b7", |
00000408 => x"0463079d", |
00000409 => x"650510f7", |
00000410 => x"e4450513", |
00000411 => x"554000ef", |
00000412 => x"65050405", |
00000413 => x"862686a2", |
00000414 => x"051385ce", |
00000415 => x"00eff685", |
00000416 => x"1a635420", |
00000417 => x"65050e04", |
00000418 => x"f8c50513", |
00000419 => x"6505b1a9", |
00000420 => x"e4450513", |
00000421 => x"52c000ef", |
00000422 => x"44054481", |
00000423 => x"6505b1dd", |
00000424 => x"e4450513", |
00000425 => x"51c000ef", |
00000426 => x"bb310405", |
00000427 => x"05136505", |
00000428 => x"00efe445", |
00000429 => x"040550e0", |
00000430 => x"6505b399", |
00000431 => x"e4050513", |
00000432 => x"500000ef", |
00000433 => x"b3950485", |
00000434 => x"05136505", |
00000435 => x"00efe445", |
00000436 => x"04054f20", |
00000437 => x"6505b361", |
00000438 => x"e8c50513", |
00000439 => x"4e4000ef", |
00000440 => x"bbb54991", |
00000441 => x"05136505", |
00000442 => x"00efe445", |
00000443 => x"04054d60", |
00000444 => x"6505bb69", |
00000445 => x"e4450513", |
00000446 => x"4c8000ef", |
00000447 => x"bb7d0405", |
00000448 => x"05136505", |
00000449 => x"00efe445", |
00000450 => x"04054ba0", |
00000451 => x"6505bbe1", |
00000452 => x"e4450513", |
00000453 => x"4ac000ef", |
00000454 => x"bbd50405", |
00000455 => x"05136505", |
00000456 => x"00efe445", |
00000457 => x"040549e0", |
00000458 => x"6505bd09", |
00000459 => x"e4450513", |
00000460 => x"490000ef", |
00000461 => x"b53d0405", |
00000462 => x"05136505", |
00000463 => x"00efe445", |
00000464 => x"04054820", |
00000465 => x"6505b5a9", |
00000466 => x"e4450513", |
00000467 => x"04052995", |
00000468 => x"6505b5a5", |
00000469 => x"e4450513", |
00000470 => x"040521a5", |
00000471 => x"6505bd59", |
00000472 => x"e4450513", |
00000473 => x"040529b1", |
00000474 => x"6505b5e9", |
00000475 => x"e4050513", |
00000476 => x"04852981", |
00000477 => x"6505bdfd", |
00000478 => x"f9850513", |
00000479 => x"2773bea9", |
00000480 => x"a4233420", |
00000481 => x"808282e1", |
00000482 => x"6505c509", |
00000483 => x"fa850513", |
00000484 => x"6505a905", |
00000485 => x"fb050513", |
00000486 => x"1141bfe5", |
00000487 => x"c226c422", |
00000488 => x"479dc606", |
00000489 => x"84ae842a", |
00000490 => x"02a7f363", |
00000491 => x"006347ad", |
00000492 => x"47cd02f5", |
00000493 => x"00f50b63", |
00000494 => x"056347dd", |
00000495 => x"47ed02f5", |
00000496 => x"1c634505", |
00000497 => x"452d00f4", |
00000498 => x"450da011", |
00000499 => x"25032329", |
00000500 => x"040aff40", |
00000501 => x"c004942a", |
00000502 => x"40b24501", |
00000503 => x"44924422", |
00000504 => x"80820141", |
00000505 => x"b7dd451d", |
00000506 => x"ce061101", |
00000507 => x"ca26cc22", |
00000508 => x"c64ec84a", |
00000509 => x"c256c452", |
00000510 => x"2973c05a", |
00000511 => x"4b01f130", |
00000512 => x"4a2559e1", |
00000513 => x"44914a8d", |
00000514 => x"033b0433", |
00000515 => x"04614501", |
00000516 => x"00895433", |
00000517 => x"0ff47413", |
00000518 => x"028a6f63", |
00000519 => x"0513c511", |
00000520 => x"75130305", |
00000521 => x"2ea50ff5", |
00000522 => x"03040513", |
00000523 => x"0ff57513", |
00000524 => x"056326bd", |
00000525 => x"0513015b", |
00000526 => x"269502e0", |
00000527 => x"15e30b05", |
00000528 => x"40f2fc9b", |
00000529 => x"44d24462", |
00000530 => x"49b24942", |
00000531 => x"4a924a22", |
00000532 => x"61054b02", |
00000533 => x"14598082", |
00000534 => x"74130505", |
00000535 => x"75130ff4", |
00000536 => x"bf5d0ff5", |
00000537 => x"11016505", |
00000538 => x"fb850513", |
00000539 => x"cc22ce06", |
00000540 => x"c84aca26", |
00000541 => x"650526b1", |
00000542 => x"fec50513", |
00000543 => x"25f32691", |
00000544 => x"6505f140", |
00000545 => x"00c50513", |
00000546 => x"25832e25", |
00000547 => x"6505fe40", |
00000548 => x"02450513", |
00000549 => x"65052635", |
00000550 => x"03c50513", |
00000551 => x"37a92615", |
00000552 => x"f13025f3", |
00000553 => x"05136505", |
00000554 => x"2e190505", |
00000555 => x"05136505", |
00000556 => x"263905c5", |
00000557 => x"301027f3", |
00000558 => x"906383f9", |
00000559 => x"65051807", |
00000560 => x"07050513", |
00000561 => x"65052cf5", |
00000562 => x"09050513", |
00000563 => x"25f32cd5", |
00000564 => x"44013010", |
00000565 => x"44e94905", |
00000566 => x"008917b3", |
00000567 => x"cb998fed", |
00000568 => x"04140513", |
00000569 => x"0ff57513", |
00000570 => x"2c55c62e", |
00000571 => x"02000513", |
00000572 => x"45b2247d", |
00000573 => x"11e30405", |
00000574 => x"6505fe94", |
00000575 => x"0a450513", |
00000576 => x"258324c1", |
00000577 => x"6505fe00", |
00000578 => x"0ac50513", |
00000579 => x"65052c55", |
00000580 => x"0c850513", |
00000581 => x"25832475", |
00000582 => x"2603ff80", |
00000583 => x"6505ff00", |
00000584 => x"0e850513", |
00000585 => x"65052c71", |
00000586 => x"11050513", |
00000587 => x"25032c51", |
00000588 => x"8911fe80", |
00000589 => x"65053d91", |
00000590 => x"12850513", |
00000591 => x"25032451", |
00000592 => x"8921fe80", |
00000593 => x"25833591", |
00000594 => x"2603ffc0", |
00000595 => x"6505ff40", |
00000596 => x"14050513", |
00000597 => x"650524b5", |
00000598 => x"16850513", |
00000599 => x"25032495", |
00000600 => x"8941fe80", |
00000601 => x"65053515", |
00000602 => x"18050513", |
00000603 => x"25032c91", |
00000604 => x"8905fe80", |
00000605 => x"65053d11", |
00000606 => x"19850513", |
00000607 => x"25032491", |
00000608 => x"8909fe80", |
00000609 => x"65053511", |
00000610 => x"1b050513", |
00000611 => x"65052c15", |
00000612 => x"fe802403", |
00000613 => x"1c450513", |
00000614 => x"65412425", |
00000615 => x"33ed8d61", |
00000616 => x"05136505", |
00000617 => x"2c291d05", |
00000618 => x"00020537", |
00000619 => x"3be98d61", |
00000620 => x"05136505", |
00000621 => x"24291dc5", |
00000622 => x"00040537", |
00000623 => x"33e98d61", |
00000624 => x"05136505", |
00000625 => x"2aed1e85", |
00000626 => x"00080537", |
00000627 => x"3b6d8d61", |
00000628 => x"05136505", |
00000629 => x"22ed1f45", |
00000630 => x"00100537", |
00000631 => x"336d8d61", |
00000632 => x"05136505", |
00000633 => x"2ae92005", |
00000634 => x"00200537", |
00000635 => x"3b698d61", |
00000636 => x"05136505", |
00000637 => x"22e920c5", |
00000638 => x"00400537", |
00000639 => x"33698d61", |
00000640 => x"05136505", |
00000641 => x"2a6d2185", |
00000642 => x"00800537", |
00000643 => x"3bad8d61", |
00000644 => x"05136505", |
00000645 => x"226d2245", |
00000646 => x"01000537", |
00000647 => x"33ad8d61", |
00000648 => x"05136505", |
00000649 => x"2a692305", |
00000650 => x"02000537", |
00000651 => x"44628d61", |
00000652 => x"44d240f2", |
00000653 => x"61054942", |
00000654 => x"4705bb81", |
00000655 => x"00e78963", |
00000656 => x"9a634709", |
00000657 => x"650500e7", |
00000658 => x"08850513", |
00000659 => x"6505bda5", |
00000660 => x"07850513", |
00000661 => x"6505bd85", |
00000662 => x"08050513", |
00000663 => x"6505b5a5", |
00000664 => x"23c50513", |
00000665 => x"2503a281", |
00000666 => x"8145fe80", |
00000667 => x"80828905", |
00000668 => x"c02a1141", |
00000669 => x"0793c22e", |
00000670 => x"a023f900", |
00000671 => x"47120007", |
00000672 => x"f8e02a23", |
00000673 => x"c3984702", |
00000674 => x"80820141", |
00000675 => x"27831141", |
00000676 => x"2703f940", |
00000677 => x"2683f900", |
00000678 => x"9ae3f940", |
00000679 => x"c03afed7", |
00000680 => x"4502c23e", |
00000681 => x"01414592", |
00000682 => x"06938082", |
00000683 => x"567df980", |
00000684 => x"c288c290", |
00000685 => x"8082c2cc", |
00000686 => x"68051141", |
00000687 => x"00058523", |
00000688 => x"00544781", |
00000689 => x"2b080813", |
00000690 => x"76334729", |
00000691 => x"88b302e5", |
00000692 => x"078500f6", |
00000693 => x"46039642", |
00000694 => x"55330006", |
00000695 => x"802302e5", |
00000696 => x"94e300c8", |
00000697 => x"8636fee7", |
00000698 => x"05134725", |
00000699 => x"48030300", |
00000700 => x"87ba0096", |
00000701 => x"0742177d", |
00000702 => x"17638341", |
00000703 => x"04a300a8", |
00000704 => x"167d0006", |
00000705 => x"4781f76d", |
00000706 => x"470197b6", |
00000707 => x"0007c603", |
00000708 => x"0513ca09", |
00000709 => x"972e0017", |
00000710 => x"00c70023", |
00000711 => x"01051713", |
00000712 => x"86138341", |
00000713 => x"9763fff7", |
00000714 => x"95ba00f6", |
00000715 => x"00058023", |
00000716 => x"80820141", |
00000717 => x"bfd987b2", |
00000718 => x"fe802503", |
00000719 => x"89058149", |
00000720 => x"20238082", |
00000721 => x"2683fa00", |
00000722 => x"0506fe00", |
00000723 => x"f5634701", |
00000724 => x"668502a6", |
00000725 => x"16f94781", |
00000726 => x"02e6e763", |
00000727 => x"89858a05", |
00000728 => x"067a07e2", |
00000729 => x"05f68fd1", |
00000730 => x"8fd98fcd", |
00000731 => x"10000737", |
00000732 => x"20238fd9", |
00000733 => x"8082faf0", |
00000734 => x"00170793", |
00000735 => x"01079713", |
00000736 => x"83418e89", |
00000737 => x"8513b7e9", |
00000738 => x"7513ffe7", |
00000739 => x"e5110fd5", |
00000740 => x"0785830d", |
00000741 => x"0ff7f793", |
00000742 => x"8305b7c1", |
00000743 => x"2423bfdd", |
00000744 => x"8082fca0", |
00000745 => x"46b54729", |
00000746 => x"00054783", |
00000747 => x"e3910505", |
00000748 => x"94638082", |
00000749 => x"242300e7", |
00000750 => x"2423fcd0", |
00000751 => x"b7edfcf0", |
00000752 => x"d422715d", |
00000753 => x"6405c2be", |
00000754 => x"d226185c", |
00000755 => x"cc52ce4e", |
00000756 => x"c85aca56", |
00000757 => x"d04ad606", |
00000758 => x"dc32da2e", |
00000759 => x"c0bade36", |
00000760 => x"c6c6c4c2", |
00000761 => x"0993c03e", |
00000762 => x"4a290250", |
00000763 => x"04934ab5", |
00000764 => x"0b130730", |
00000765 => x"04130750", |
00000766 => x"47832bc4", |
00000767 => x"c39d0005", |
00000768 => x"0d379463", |
00000769 => x"00154783", |
00000770 => x"00250913", |
00000771 => x"06978563", |
00000772 => x"02f4e463", |
00000773 => x"06300713", |
00000774 => x"06e78763", |
00000775 => x"06900713", |
00000776 => x"06e78c63", |
00000777 => x"542250b2", |
00000778 => x"59025492", |
00000779 => x"4a6249f2", |
00000780 => x"4b424ad2", |
00000781 => x"80826161", |
00000782 => x"09678163", |
00000783 => x"07800713", |
00000784 => x"fee792e3", |
00000785 => x"00544782", |
00000786 => x"438c8536", |
00000787 => x"00478713", |
00000788 => x"0613c03a", |
00000789 => x"47010200", |
00000790 => x"00e5d7b3", |
00000791 => x"97a28bbd", |
00000792 => x"0007c783", |
00000793 => x"16fd0711", |
00000794 => x"00f68423", |
00000795 => x"fec716e3", |
00000796 => x"00010623", |
00000797 => x"4782a031", |
00000798 => x"87134388", |
00000799 => x"c03a0047", |
00000800 => x"854a3715", |
00000801 => x"4782bf9d", |
00000802 => x"00478713", |
00000803 => x"0007c783", |
00000804 => x"2423c03a", |
00000805 => x"b7f5fcf0", |
00000806 => x"43884782", |
00000807 => x"00478713", |
00000808 => x"5863c03a", |
00000809 => x"07930005", |
00000810 => x"053302d0", |
00000811 => x"242340a0", |
00000812 => x"004cfcf0", |
00000813 => x"00483511", |
00000814 => x"4782b7e1", |
00000815 => x"8713004c", |
00000816 => x"43880047", |
00000817 => x"b7fdc03a", |
00000818 => x"01479463", |
00000819 => x"fd502423", |
00000820 => x"00150913", |
00000821 => x"7693bf7d", |
00000822 => x"470d0fb5", |
00000823 => x"866387aa", |
00000824 => x"472d00e6", |
00000825 => x"98634505", |
00000826 => x"450500e7", |
00000827 => x"00f517b3", |
00000828 => x"3047a073", |
00000829 => x"80824501", |
00000830 => x"f8800713", |
00000831 => x"e693431c", |
00000832 => x"c3140087", |
00000833 => x"07378b8d", |
00000834 => x"078a8000", |
00000835 => x"08870713", |
00000836 => x"a30397ba", |
00000837 => x"83020007", |
00000838 => x"fe802503", |
00000839 => x"8905815d", |
00000840 => x"479d8082", |
00000841 => x"00a7fa63", |
00000842 => x"80824505", |
00000843 => x"40b24505", |
00000844 => x"44924422", |
00000845 => x"80820141", |
00000846 => x"c2261141", |
00000847 => x"658584ae", |
00000848 => x"8593c422", |
00000849 => x"842acf85", |
00000850 => x"c606456d", |
00000851 => x"a4fff0ef", |
00000852 => x"07b7fd71", |
00000853 => x"17138000", |
00000854 => x"87930024", |
00000855 => x"97ba0887", |
00000856 => x"2703c384", |
00000857 => x"0421f880", |
00000858 => x"97b34785", |
00000859 => x"8fd90087", |
00000860 => x"0107e793", |
00000861 => x"f8f02423", |
00000862 => x"479dbf5d", |
00000863 => x"00a7ed63", |
00000864 => x"f8802783", |
00000865 => x"8d5d0542", |
00000866 => x"000807b7", |
00000867 => x"24238d5d", |
00000868 => x"4501f8a0", |
00000869 => x"45058082", |
00000870 => x"00008082", |
00000871 => x"2d2d0a0a", |
00000872 => x"2d2d2d2d", |
00000873 => x"55504320", |
00000874 => x"53455420", |
00000875 => x"2d2d2054", |
00000876 => x"2d2d2d2d", |
00000877 => x"00000a0a", |
00000878 => x"74530a0a", |
00000879 => x"69747261", |
00000880 => x"7420676e", |
00000881 => x"73747365", |
00000882 => x"0a2e2e2e", |
00000883 => x"0000000a", |
00000884 => x"20455452", |
00000885 => x"74736e69", |
00000886 => x"206c6c61", |
00000887 => x"6f727265", |
00000888 => x"000a2172", |
00000889 => x"43494c43", |
00000890 => x"736e6920", |
00000891 => x"6c6c6174", |
00000892 => x"72726520", |
00000893 => x"0a21726f", |
00000894 => x"00000000", |
00000895 => x"4d454d49", |
00000896 => x"5345545f", |
00000897 => x"20203a54", |
00000898 => x"00000020", |
00000899 => x"70696b73", |
00000900 => x"20646570", |
00000901 => x"73696428", |
00000902 => x"656c6261", |
00000903 => x"000a2964", |
00000904 => x"4d454d44", |
00000905 => x"5345545f", |
00000906 => x"20203a54", |
00000907 => x"00000020", |
00000908 => x"4359434d", |
00000909 => x"485b454c", |
00000910 => x"20203a5d", |
00000911 => x"00000020", |
00000912 => x"000a6b6f", |
00000913 => x"6c696166", |
00000914 => x"0000000a", |
00000915 => x"534e494d", |
00000916 => x"54455254", |
00000917 => x"3a5d485b", |
00000918 => x"00000020", |
00000919 => x"454d4954", |
00000920 => x"3a5d485b", |
00000921 => x"20202020", |
00000922 => x"00000020", |
00000923 => x"434e4546", |
00000924 => x"492e2845", |
00000925 => x"20203a29", |
00000926 => x"00000020", |
00000927 => x"20435845", |
00000928 => x"4c415f49", |
00000929 => x"3a4e4749", |
00000930 => x"00000020", |
00000931 => x"70696b73", |
00000932 => x"20646570", |
00000933 => x"746f6e28", |
00000934 => x"736f7020", |
00000935 => x"6c626973", |
00000936 => x"68772065", |
00000937 => x"43206e65", |
00000938 => x"5458452d", |
00000939 => x"616e6520", |
00000940 => x"64656c62", |
00000941 => x"00000a29", |
00000942 => x"20435845", |
00000943 => x"43415f49", |
00000944 => x"20203a43", |
00000945 => x"00000020", |
00000946 => x"20435845", |
00000947 => x"4c495f49", |
00000948 => x"3a47454c", |
00000949 => x"00000020", |
00000950 => x"20435845", |
00000951 => x"41455242", |
00000952 => x"20203a4b", |
00000953 => x"00000020", |
00000954 => x"20435845", |
00000955 => x"4c415f4c", |
00000956 => x"3a4e4749", |
00000957 => x"00000020", |
00000958 => x"20435845", |
00000959 => x"43415f4c", |
00000960 => x"20203a43", |
00000961 => x"00000020", |
00000962 => x"20435845", |
00000963 => x"4c415f53", |
00000964 => x"3a4e4749", |
00000965 => x"00000020", |
00000966 => x"20435845", |
00000967 => x"43415f53", |
00000968 => x"20203a43", |
00000969 => x"00000020", |
00000970 => x"20435845", |
00000971 => x"43564e45", |
00000972 => x"3a4c4c41", |
00000973 => x"00000020", |
00000974 => x"20515249", |
00000975 => x"3a49544d", |
00000976 => x"20202020", |
00000977 => x"00000020", |
00000978 => x"20515249", |
00000979 => x"3a49454d", |
00000980 => x"20202020", |
00000981 => x"00000020", |
00000982 => x"3a494657", |
00000983 => x"20202020", |
00000984 => x"20202020", |
00000985 => x"00000020", |
00000986 => x"65540a0a", |
00000987 => x"3a737473", |
00000988 => x"0a692520", |
00000989 => x"203a4b4f", |
00000990 => x"25202020", |
00000991 => x"41460a69", |
00000992 => x"203a4c49", |
00000993 => x"0a692520", |
00000994 => x"0000000a", |
00000995 => x"54534554", |
00000996 => x"214b4f20", |
00000997 => x"0000000a", |
00000998 => x"54534554", |
00000999 => x"49414620", |
00001000 => x"2144454c", |
00001001 => x"0000000a", |
00001002 => x"65757254", |
00001003 => x"0000000a", |
00001004 => x"736c6146", |
00001005 => x"00000a65", |
00001006 => x"3c3c0a0a", |
00001007 => x"4f454e20", |
00001008 => x"32335652", |
00001009 => x"72614820", |
00001010 => x"72617764", |
00001011 => x"6f432065", |
00001012 => x"6769666e", |
00001013 => x"74617275", |
00001014 => x"206e6f69", |
00001015 => x"7265764f", |
00001016 => x"77656976", |
00001017 => x"0a3e3e20", |
00001018 => x"00000000", |
00001019 => x"202d2d0a", |
00001020 => x"746e6543", |
00001021 => x"206c6172", |
00001022 => x"636f7250", |
00001023 => x"69737365", |
00001024 => x"5520676e", |
00001025 => x"2074696e", |
00001026 => x"000a2d2d", |
00001027 => x"74726148", |
00001028 => x"3a444920", |
00001029 => x"20202020", |
00001030 => x"20202020", |
00001031 => x"78302020", |
00001032 => x"000a7825", |
00001033 => x"72657355", |
00001034 => x"646f6320", |
00001035 => x"20203a65", |
00001036 => x"20202020", |
00001037 => x"78302020", |
00001038 => x"000a7825", |
00001039 => x"64726148", |
00001040 => x"65726177", |
00001041 => x"72657620", |
00001042 => x"6e6f6973", |
00001043 => x"0000203a", |
00001044 => x"78302820", |
00001045 => x"0a297825", |
00001046 => x"00000000", |
00001047 => x"68637241", |
00001048 => x"63657469", |
00001049 => x"65727574", |
00001050 => x"2020203a", |
00001051 => x"00002020", |
00001052 => x"6e6b6e75", |
00001053 => x"006e776f", |
00001054 => x"32335652", |
00001055 => x"00000000", |
00001056 => x"32315652", |
00001057 => x"00000038", |
00001058 => x"34365652", |
00001059 => x"00000000", |
00001060 => x"5550430a", |
00001061 => x"74786520", |
00001062 => x"69736e65", |
00001063 => x"3a736e6f", |
00001064 => x"00202020", |
00001065 => x"25783028", |
00001066 => x"000a2978", |
00001067 => x"636f6c43", |
00001068 => x"7073206b", |
00001069 => x"3a646565", |
00001070 => x"20202020", |
00001071 => x"75252020", |
00001072 => x"0a7a4820", |
00001073 => x"00000000", |
00001074 => x"202d2d0a", |
00001075 => x"6f6d654d", |
00001076 => x"43207972", |
00001077 => x"69666e6f", |
00001078 => x"61727567", |
00001079 => x"6e6f6974", |
00001080 => x"0a2d2d20", |
00001081 => x"00000000", |
00001082 => x"74736e49", |
00001083 => x"74637572", |
00001084 => x"206e6f69", |
00001085 => x"6f6d656d", |
00001086 => x"203a7972", |
00001087 => x"75252020", |
00001088 => x"74796220", |
00001089 => x"40207365", |
00001090 => x"25783020", |
00001091 => x"00000a78", |
00001092 => x"65746e49", |
00001093 => x"6c616e72", |
00001094 => x"454d4920", |
00001095 => x"20203a4d", |
00001096 => x"20202020", |
00001097 => x"00002020", |
00001098 => x"65746e49", |
00001099 => x"6c616e72", |
00001100 => x"454d4920", |
00001101 => x"7361204d", |
00001102 => x"4d4f5220", |
00001103 => x"0000203a", |
00001104 => x"61746144", |
00001105 => x"6d656d20", |
00001106 => x"3a79726f", |
00001107 => x"20202020", |
00001108 => x"20202020", |
00001109 => x"75252020", |
00001110 => x"74796220", |
00001111 => x"40207365", |
00001112 => x"25783020", |
00001113 => x"00000a78", |
00001114 => x"65746e49", |
00001115 => x"6c616e72", |
00001116 => x"454d4420", |
00001117 => x"20203a4d", |
00001118 => x"20202020", |
00001119 => x"00002020", |
00001120 => x"746f6f42", |
00001121 => x"64616f6c", |
00001122 => x"203a7265", |
00001123 => x"20202020", |
00001124 => x"20202020", |
00001125 => x"00002020", |
00001126 => x"65747845", |
00001127 => x"6c616e72", |
00001128 => x"746e6920", |
00001129 => x"61667265", |
00001130 => x"203a6563", |
00001131 => x"00002020", |
00001132 => x"202d2d0a", |
00001133 => x"69726550", |
00001134 => x"72656870", |
00001135 => x"20736c61", |
00001136 => x"000a2d2d", |
00001137 => x"4f495047", |
00001138 => x"2020203a", |
00001139 => x"00000020", |
00001140 => x"4d49544d", |
00001141 => x"20203a45", |
00001142 => x"00000020", |
00001143 => x"54524155", |
00001144 => x"2020203a", |
00001145 => x"00000020", |
00001146 => x"3a495053", |
00001147 => x"20202020", |
00001148 => x"00000020", |
00001149 => x"3a495754", |
00001150 => x"20202020", |
00001151 => x"00000020", |
00001152 => x"3a4d5750", |
00001153 => x"20202020", |
00001154 => x"00000020", |
00001155 => x"3a544457", |
00001156 => x"20202020", |
00001157 => x"00000020", |
00001158 => x"43494c43", |
00001159 => x"2020203a", |
00001160 => x"00000020", |
00001161 => x"474e5254", |
00001162 => x"2020203a", |
00001163 => x"00000020", |
00001164 => x"4e564544", |
00001165 => x"3a4c4c55", |
00001166 => x"00000020", |
00001167 => x"68540a0a", |
00001168 => x"454e2065", |
00001169 => x"3356524f", |
00001170 => x"72502032", |
00001171 => x"7365636f", |
00001172 => x"20726f73", |
00001173 => x"6a6f7250", |
00001174 => x"0a746365", |
00001175 => x"53207962", |
00001176 => x"68706574", |
00001177 => x"4e206e61", |
00001178 => x"69746c6f", |
00001179 => x"680a676e", |
00001180 => x"73707474", |
00001181 => x"672f2f3a", |
00001182 => x"75687469", |
00001183 => x"6f632e62", |
00001184 => x"74732f6d", |
00001185 => x"746c6f6e", |
00001186 => x"2f676e69", |
00001187 => x"726f656e", |
00001188 => x"0a323376", |
00001189 => x"6564616d", |
00001190 => x"206e6920", |
00001191 => x"6e6e6148", |
00001192 => x"7265766f", |
00001193 => x"6547202c", |
00001194 => x"6e616d72", |
00001195 => x"000a0a79", |
00001196 => x"33323130", |
00001197 => x"37363534", |
00001198 => x"00003938", |
00001199 => x"33323130", |
00001200 => x"37363534", |
00001201 => x"62613938", |
00001202 => x"66656463", |
00001203 => x"dead007f", |
00001204 => x"00008067", |
00000035 => x"ffc10113", |
00000036 => x"00010413", |
00000037 => x"80000197", |
00000038 => x"76c18193", |
00000039 => x"00000597", |
00000040 => x"08058593", |
00000041 => x"30559073", |
00000042 => x"f8000593", |
00000043 => x"0005a023", |
00000044 => x"00458593", |
00000045 => x"feb01ce3", |
00000046 => x"80000597", |
00000047 => x"f4858593", |
00000048 => x"84018613", |
00000049 => x"00c5d863", |
00000050 => x"00058023", |
00000051 => x"00158593", |
00000052 => x"ff5ff06f", |
00000053 => x"00001597", |
00000054 => x"ed858593", |
00000055 => x"80000617", |
00000056 => x"f2460613", |
00000057 => x"80000697", |
00000058 => x"f1c68693", |
00000059 => x"00d65c63", |
00000060 => x"00058703", |
00000061 => x"00e60023", |
00000062 => x"00158593", |
00000063 => x"00160613", |
00000064 => x"fedff06f", |
00000065 => x"00000513", |
00000066 => x"00000593", |
00000067 => x"05c000ef", |
00000068 => x"30047073", |
00000069 => x"10500073", |
00000070 => x"0000006f", |
00000071 => x"ff810113", |
00000072 => x"00812023", |
00000073 => x"00912223", |
00000074 => x"34202473", |
00000075 => x"02044663", |
00000076 => x"34102473", |
00000077 => x"00041483", |
00000078 => x"0034f493", |
00000079 => x"00240413", |
00000080 => x"34141073", |
00000081 => x"00300413", |
00000082 => x"00941863", |
00000083 => x"34102473", |
00000084 => x"00240413", |
00000085 => x"34141073", |
00000086 => x"00012483", |
00000087 => x"00412403", |
00000088 => x"00810113", |
00000089 => x"30200073", |
00000090 => x"ff010113", |
00000091 => x"00112623", |
00000092 => x"00812423", |
00000093 => x"0dd000ef", |
00000094 => x"04050663", |
00000095 => x"4dc000ef", |
00000096 => x"00005537", |
00000097 => x"00000613", |
00000098 => x"00000593", |
00000099 => x"b0050513", |
00000100 => x"618000ef", |
00000101 => x"00001537", |
00000102 => x"bbc50513", |
00000103 => x"6a8000ef", |
00000104 => x"00000513", |
00000105 => x"0bd000ef", |
00000106 => x"00000413", |
00000107 => x"0ff47513", |
00000108 => x"0b1000ef", |
00000109 => x"0c800513", |
00000110 => x"0ed000ef", |
00000111 => x"00140413", |
00000112 => x"fedff06f", |
00000113 => x"00c12083", |
00000114 => x"00812403", |
00000115 => x"01010113", |
00000116 => x"00008067", |
00000117 => x"00000000", |
00000118 => x"00000000", |
00000119 => x"00000000", |
00000120 => x"fc010113", |
00000121 => x"02112e23", |
00000122 => x"02512c23", |
00000123 => x"02612a23", |
00000124 => x"02712823", |
00000125 => x"02a12623", |
00000126 => x"02b12423", |
00000127 => x"02c12223", |
00000128 => x"02d12023", |
00000129 => x"00e12e23", |
00000130 => x"00f12c23", |
00000131 => x"01012a23", |
00000132 => x"01112823", |
00000133 => x"01c12623", |
00000134 => x"01d12423", |
00000135 => x"01e12223", |
00000136 => x"01f12023", |
00000137 => x"34102773", |
00000138 => x"342027f3", |
00000139 => x"0807c863", |
00000140 => x"00071683", |
00000141 => x"00300593", |
00000142 => x"0036f693", |
00000143 => x"00270613", |
00000144 => x"00b69463", |
00000145 => x"00470613", |
00000146 => x"34161073", |
00000147 => x"00b00713", |
00000148 => x"04f77a63", |
00000149 => x"38000793", |
00000150 => x"000780e7", |
00000151 => x"03c12083", |
00000152 => x"03812283", |
00000153 => x"03412303", |
00000154 => x"03012383", |
00000155 => x"02c12503", |
00000156 => x"02812583", |
00000157 => x"02412603", |
00000158 => x"02012683", |
00000159 => x"01c12703", |
00000160 => x"01812783", |
00000161 => x"01412803", |
00000162 => x"01012883", |
00000163 => x"00c12e03", |
00000164 => x"00812e83", |
00000165 => x"00412f03", |
00000166 => x"00012f83", |
00000167 => x"04010113", |
00000168 => x"30200073", |
00000169 => x"00001737", |
00000170 => x"00279793", |
00000171 => x"bd870713", |
00000172 => x"00e787b3", |
00000173 => x"0007a783", |
00000174 => x"00078067", |
00000175 => x"80000737", |
00000176 => x"ffd74713", |
00000177 => x"00e787b3", |
00000178 => x"01000713", |
00000179 => x"f8f764e3", |
00000180 => x"00001737", |
00000181 => x"00279793", |
00000182 => x"c0870713", |
00000183 => x"00e787b3", |
00000184 => x"0007a783", |
00000185 => x"00078067", |
00000186 => x"800007b7", |
00000187 => x"0007a783", |
00000188 => x"f69ff06f", |
00000189 => x"800007b7", |
00000190 => x"0047a783", |
00000191 => x"f5dff06f", |
00000192 => x"800007b7", |
00000193 => x"0087a783", |
00000194 => x"f51ff06f", |
00000195 => x"800007b7", |
00000196 => x"00c7a783", |
00000197 => x"f45ff06f", |
00000198 => x"8101a783", |
00000199 => x"f3dff06f", |
00000200 => x"8141a783", |
00000201 => x"f35ff06f", |
00000202 => x"8181a783", |
00000203 => x"f2dff06f", |
00000204 => x"81c1a783", |
00000205 => x"f25ff06f", |
00000206 => x"8201a783", |
00000207 => x"f1dff06f", |
00000208 => x"8241a783", |
00000209 => x"f15ff06f", |
00000210 => x"8281a783", |
00000211 => x"f0dff06f", |
00000212 => x"82c1a783", |
00000213 => x"f05ff06f", |
00000214 => x"8301a783", |
00000215 => x"efdff06f", |
00000216 => x"8341a783", |
00000217 => x"ef5ff06f", |
00000218 => x"8381a783", |
00000219 => x"eedff06f", |
00000220 => x"83c1a783", |
00000221 => x"ee5ff06f", |
00000222 => x"00000000", |
00000223 => x"00000000", |
00000224 => x"00001537", |
00000225 => x"fe010113", |
00000226 => x"c4c50513", |
00000227 => x"00112e23", |
00000228 => x"00812c23", |
00000229 => x"00912a23", |
00000230 => x"01212823", |
00000231 => x"01312623", |
00000232 => x"4fc000ef", |
00000233 => x"c81025f3", |
00000234 => x"c0102673", |
00000235 => x"00001537", |
00000236 => x"c7450513", |
00000237 => x"4e8000ef", |
00000238 => x"342024f3", |
00000239 => x"34102473", |
00000240 => x"00041983", |
00000241 => x"0039f913", |
00000242 => x"0404de63", |
00000243 => x"00001537", |
00000244 => x"c8c50513", |
00000245 => x"4c8000ef", |
00000246 => x"00001537", |
00000247 => x"00040593", |
00000248 => x"ca450513", |
00000249 => x"4b8000ef", |
00000250 => x"00001537", |
00000251 => x"cc450513", |
00000252 => x"4ac000ef", |
00000253 => x"00b00793", |
00000254 => x"0697f463", |
00000255 => x"800007b7", |
00000256 => x"ffd7c793", |
00000257 => x"00f487b3", |
00000258 => x"01000713", |
00000259 => x"02f77e63", |
00000260 => x"00001537", |
00000261 => x"00048593", |
00000262 => x"e6c50513", |
00000263 => x"480000ef", |
00000264 => x"0640006f", |
00000265 => x"00001537", |
00000266 => x"c9850513", |
00000267 => x"470000ef", |
00000268 => x"00300793", |
00000269 => x"00f91663", |
00000270 => x"ffc40413", |
00000271 => x"f9dff06f", |
00000272 => x"ffe40413", |
00000273 => x"f95ff06f", |
00000274 => x"00001737", |
00000275 => x"00279793", |
00000276 => x"f1c70713", |
00000277 => x"00e787b3", |
00000278 => x"0007a783", |
00000279 => x"00078067", |
00000280 => x"00001737", |
00000281 => x"00249793", |
00000282 => x"f6070713", |
00000283 => x"00e787b3", |
00000284 => x"0007a783", |
00000285 => x"00078067", |
00000286 => x"00001537", |
00000287 => x"ccc50513", |
00000288 => x"41c000ef", |
00000289 => x"00001537", |
00000290 => x"00098593", |
00000291 => x"e7c50513", |
00000292 => x"40c000ef", |
00000293 => x"00300793", |
00000294 => x"00f90863", |
00000295 => x"00001537", |
00000296 => x"ea850513", |
00000297 => x"3f8000ef", |
00000298 => x"343025f3", |
00000299 => x"00001537", |
00000300 => x"ebc50513", |
00000301 => x"3e8000ef", |
00000302 => x"341025f3", |
00000303 => x"00001537", |
00000304 => x"ecc50513", |
00000305 => x"3d8000ef", |
00000306 => x"01812403", |
00000307 => x"01c12083", |
00000308 => x"01412483", |
00000309 => x"01012903", |
00000310 => x"00c12983", |
00000311 => x"00001537", |
00000312 => x"ef450513", |
00000313 => x"02010113", |
00000314 => x"3b40006f", |
00000315 => x"00001537", |
00000316 => x"cec50513", |
00000317 => x"f8dff06f", |
00000318 => x"00001537", |
00000319 => x"d0850513", |
00000320 => x"f81ff06f", |
00000321 => x"00001537", |
00000322 => x"d1c50513", |
00000323 => x"f75ff06f", |
00000324 => x"00001537", |
00000325 => x"d3050513", |
00000326 => x"f69ff06f", |
00000327 => x"00001537", |
00000328 => x"d4850513", |
00000329 => x"f5dff06f", |
00000330 => x"00001537", |
00000331 => x"d5c50513", |
00000332 => x"f51ff06f", |
00000333 => x"00001537", |
00000334 => x"d7850513", |
00000335 => x"f45ff06f", |
00000336 => x"00001537", |
00000337 => x"d8c50513", |
00000338 => x"f39ff06f", |
00000339 => x"00001537", |
00000340 => x"dac50513", |
00000341 => x"f2dff06f", |
00000342 => x"00001537", |
00000343 => x"dc850513", |
00000344 => x"f21ff06f", |
00000345 => x"00001537", |
00000346 => x"de050513", |
00000347 => x"f15ff06f", |
00000348 => x"00001537", |
00000349 => x"dfc50513", |
00000350 => x"f09ff06f", |
00000351 => x"00001537", |
00000352 => x"e1850513", |
00000353 => x"efdff06f", |
00000354 => x"00001537", |
00000355 => x"e3450513", |
00000356 => x"ef1ff06f", |
00000357 => x"00001537", |
00000358 => x"e5050513", |
00000359 => x"ee5ff06f", |
00000360 => x"00f00793", |
00000361 => x"0aa7e663", |
00000362 => x"ff010113", |
00000363 => x"00812423", |
00000364 => x"00112623", |
00000365 => x"00900793", |
00000366 => x"00050413", |
00000367 => x"02f51663", |
00000368 => x"00300513", |
00000369 => x"4a4000ef", |
00000370 => x"00c00793", |
00000371 => x"02f41663", |
00000372 => x"01000513", |
00000373 => x"494000ef", |
00000374 => x"00f00793", |
00000375 => x"02f41663", |
00000376 => x"01300513", |
00000377 => x"0200006f", |
00000378 => x"00a00793", |
00000379 => x"04f51463", |
00000380 => x"00700513", |
00000381 => x"474000ef", |
00000382 => x"00d00793", |
00000383 => x"01100513", |
00000384 => x"04f41063", |
00000385 => x"464000ef", |
00000386 => x"80000537", |
00000387 => x"00050513", |
00000388 => x"00241413", |
00000389 => x"00850433", |
00000390 => x"38000793", |
00000391 => x"00c12083", |
00000392 => x"00f42023", |
00000393 => x"00812403", |
00000394 => x"00000513", |
00000395 => x"01010113", |
00000396 => x"00008067", |
00000397 => x"00b00793", |
00000398 => x"f8f518e3", |
00000399 => x"42c000ef", |
00000400 => x"00e00793", |
00000401 => x"01200513", |
00000402 => x"f8f418e3", |
00000403 => x"fb9ff06f", |
00000404 => x"00100513", |
00000405 => x"00008067", |
00000406 => x"ff010113", |
00000407 => x"00112623", |
00000408 => x"00812423", |
00000409 => x"00912223", |
00000410 => x"1e000793", |
00000411 => x"30579073", |
00000412 => x"00000413", |
00000413 => x"01000493", |
00000414 => x"00040513", |
00000415 => x"00140413", |
00000416 => x"0ff47413", |
00000417 => x"f1dff0ef", |
00000418 => x"fe9418e3", |
00000419 => x"00c12083", |
00000420 => x"00812403", |
00000421 => x"00412483", |
00000422 => x"01010113", |
00000423 => x"00008067", |
00000424 => x"fd010113", |
00000425 => x"02812423", |
00000426 => x"02912223", |
00000427 => x"03212023", |
00000428 => x"01312e23", |
00000429 => x"01412c23", |
00000430 => x"02112623", |
00000431 => x"01512a23", |
00000432 => x"00001a37", |
00000433 => x"00050493", |
00000434 => x"00058413", |
00000435 => x"00058523", |
00000436 => x"00000993", |
00000437 => x"00410913", |
00000438 => x"f90a0a13", |
00000439 => x"00a00593", |
00000440 => x"00048513", |
00000441 => x"474000ef", |
00000442 => x"00aa0533", |
00000443 => x"00054783", |
00000444 => x"01390ab3", |
00000445 => x"00048513", |
00000446 => x"00fa8023", |
00000447 => x"00a00593", |
00000448 => x"410000ef", |
00000449 => x"00198993", |
00000450 => x"00a00793", |
00000451 => x"00050493", |
00000452 => x"fcf996e3", |
00000453 => x"00090693", |
00000454 => x"00900713", |
00000455 => x"03000613", |
00000456 => x"0096c583", |
00000457 => x"00070793", |
00000458 => x"fff70713", |
00000459 => x"01071713", |
00000460 => x"01075713", |
00000461 => x"00c59a63", |
00000462 => x"000684a3", |
00000463 => x"fff68693", |
00000464 => x"fe0710e3", |
00000465 => x"00000793", |
00000466 => x"00f907b3", |
00000467 => x"00000593", |
00000468 => x"0007c703", |
00000469 => x"00070c63", |
00000470 => x"00158693", |
00000471 => x"00b405b3", |
00000472 => x"00e58023", |
00000473 => x"01069593", |
00000474 => x"0105d593", |
00000475 => x"fff78713", |
00000476 => x"02f91863", |
00000477 => x"00b40433", |
00000478 => x"00040023", |
00000479 => x"02c12083", |
00000480 => x"02812403", |
00000481 => x"02412483", |
00000482 => x"02012903", |
00000483 => x"01c12983", |
00000484 => x"01812a03", |
00000485 => x"01412a83", |
00000486 => x"03010113", |
00000487 => x"00008067", |
00000488 => x"00070793", |
00000489 => x"fadff06f", |
00000490 => x"fa002023", |
00000491 => x"fe002683", |
00000492 => x"00151513", |
00000493 => x"00000713", |
00000494 => x"04a6f263", |
00000495 => x"000016b7", |
00000496 => x"00000793", |
00000497 => x"ffe68693", |
00000498 => x"04e6e463", |
00000499 => x"00167613", |
00000500 => x"0015f593", |
00000501 => x"01879793", |
00000502 => x"01e61613", |
00000503 => x"00c7e7b3", |
00000504 => x"01d59593", |
00000505 => x"00b7e7b3", |
00000506 => x"00e7e7b3", |
00000507 => x"10000737", |
00000508 => x"00e7e7b3", |
00000509 => x"faf02023", |
00000510 => x"00008067", |
00000511 => x"00170793", |
00000512 => x"01079713", |
00000513 => x"40a686b3", |
00000514 => x"01075713", |
00000515 => x"fadff06f", |
00000516 => x"ffe78513", |
00000517 => x"0fd57513", |
00000518 => x"00051a63", |
00000519 => x"00375713", |
00000520 => x"00178793", |
00000521 => x"0ff7f793", |
00000522 => x"fa1ff06f", |
00000523 => x"00175713", |
00000524 => x"ff1ff06f", |
00000525 => x"fa002783", |
00000526 => x"fe07cee3", |
00000527 => x"faa02223", |
00000528 => x"00008067", |
00000529 => x"ff010113", |
00000530 => x"00812423", |
00000531 => x"01212023", |
00000532 => x"00112623", |
00000533 => x"00912223", |
00000534 => x"00050413", |
00000535 => x"00a00913", |
00000536 => x"00044483", |
00000537 => x"00140413", |
00000538 => x"00049e63", |
00000539 => x"00c12083", |
00000540 => x"00812403", |
00000541 => x"00412483", |
00000542 => x"00012903", |
00000543 => x"01010113", |
00000544 => x"00008067", |
00000545 => x"01249663", |
00000546 => x"00d00513", |
00000547 => x"fa9ff0ef", |
00000548 => x"00048513", |
00000549 => x"fa1ff0ef", |
00000550 => x"fc9ff06f", |
00000551 => x"fa010113", |
00000552 => x"02912a23", |
00000553 => x"04f12a23", |
00000554 => x"000014b7", |
00000555 => x"04410793", |
00000556 => x"02812c23", |
00000557 => x"03212823", |
00000558 => x"03412423", |
00000559 => x"03512223", |
00000560 => x"03612023", |
00000561 => x"01712e23", |
00000562 => x"02112e23", |
00000563 => x"03312623", |
00000564 => x"01812c23", |
00000565 => x"00050413", |
00000566 => x"04b12223", |
00000567 => x"04c12423", |
00000568 => x"04d12623", |
00000569 => x"04e12823", |
00000570 => x"05012c23", |
00000571 => x"05112e23", |
00000572 => x"00f12023", |
00000573 => x"02500a13", |
00000574 => x"00a00a93", |
00000575 => x"07300913", |
00000576 => x"07500b13", |
00000577 => x"07800b93", |
00000578 => x"f9c48493", |
00000579 => x"00044c03", |
00000580 => x"020c0463", |
00000581 => x"134c1263", |
00000582 => x"00144783", |
00000583 => x"00240993", |
00000584 => x"09278c63", |
00000585 => x"04f96263", |
00000586 => x"06300713", |
00000587 => x"0ae78463", |
00000588 => x"06900713", |
00000589 => x"0ae78c63", |
00000590 => x"03c12083", |
00000591 => x"03812403", |
00000592 => x"03412483", |
00000593 => x"03012903", |
00000594 => x"02c12983", |
00000595 => x"02812a03", |
00000596 => x"02412a83", |
00000597 => x"02012b03", |
00000598 => x"01c12b83", |
00000599 => x"01812c03", |
00000600 => x"06010113", |
00000601 => x"00008067", |
00000602 => x"0b678c63", |
00000603 => x"fd7796e3", |
00000604 => x"00012783", |
00000605 => x"00410693", |
00000606 => x"00068513", |
00000607 => x"0007a583", |
00000608 => x"00478713", |
00000609 => x"00e12023", |
00000610 => x"02000613", |
00000611 => x"00000713", |
00000612 => x"00e5d7b3", |
00000613 => x"00f7f793", |
00000614 => x"00f487b3", |
00000615 => x"0007c783", |
00000616 => x"00470713", |
00000617 => x"fff68693", |
00000618 => x"00f68423", |
00000619 => x"fec712e3", |
00000620 => x"00010623", |
00000621 => x"0140006f", |
00000622 => x"00012783", |
00000623 => x"0007a503", |
00000624 => x"00478713", |
00000625 => x"00e12023", |
00000626 => x"e7dff0ef", |
00000627 => x"00098413", |
00000628 => x"f3dff06f", |
00000629 => x"00012783", |
00000630 => x"0007c503", |
00000631 => x"00478713", |
00000632 => x"00e12023", |
00000633 => x"e51ff0ef", |
00000634 => x"fe5ff06f", |
00000635 => x"00012783", |
00000636 => x"0007a403", |
00000637 => x"00478713", |
00000638 => x"00e12023", |
00000639 => x"00045863", |
00000640 => x"02d00513", |
00000641 => x"40800433", |
00000642 => x"e2dff0ef", |
00000643 => x"00410593", |
00000644 => x"00040513", |
00000645 => x"c8dff0ef", |
00000646 => x"00410513", |
00000647 => x"fadff06f", |
00000648 => x"00012783", |
00000649 => x"00410593", |
00000650 => x"00478713", |
00000651 => x"0007a503", |
00000652 => x"00e12023", |
00000653 => x"fe1ff06f", |
00000654 => x"015c1663", |
00000655 => x"00d00513", |
00000656 => x"df5ff0ef", |
00000657 => x"00140993", |
00000658 => x"000c0513", |
00000659 => x"f99ff06f", |
00000660 => x"fe802503", |
00000661 => x"01055513", |
00000662 => x"00157513", |
00000663 => x"00008067", |
00000664 => x"f8a02223", |
00000665 => x"00008067", |
00000666 => x"01300793", |
00000667 => x"00050713", |
00000668 => x"02a7e663", |
00000669 => x"000f17b7", |
00000670 => x"88878793", |
00000671 => x"00a7d7b3", |
00000672 => x"0017f793", |
00000673 => x"00100513", |
00000674 => x"00078c63", |
00000675 => x"00e51733", |
00000676 => x"30473073", |
00000677 => x"00000513", |
00000678 => x"00008067", |
00000679 => x"00100513", |
00000680 => x"00008067", |
00000681 => x"00050593", |
00000682 => x"fe002503", |
00000683 => x"ff010113", |
00000684 => x"00112623", |
00000685 => x"00f55513", |
00000686 => x"02c000ef", |
00000687 => x"00051863", |
00000688 => x"00c12083", |
00000689 => x"01010113", |
00000690 => x"00008067", |
00000691 => x"00000013", |
00000692 => x"00000013", |
00000693 => x"00000013", |
00000694 => x"00000013", |
00000695 => x"fff50513", |
00000696 => x"fddff06f", |
00000697 => x"00050613", |
00000698 => x"00000513", |
00000699 => x"0015f693", |
00000700 => x"00068463", |
00000701 => x"00c50533", |
00000702 => x"0015d593", |
00000703 => x"00161613", |
00000704 => x"fe0596e3", |
00000705 => x"00008067", |
00000706 => x"06054063", |
00000707 => x"0605c663", |
00000708 => x"00058613", |
00000709 => x"00050593", |
00000710 => x"fff00513", |
00000711 => x"02060c63", |
00000712 => x"00100693", |
00000713 => x"00b67a63", |
00000714 => x"00c05863", |
00000715 => x"00161613", |
00000716 => x"00169693", |
00000717 => x"feb66ae3", |
00000718 => x"00000513", |
00000719 => x"00c5e663", |
00000720 => x"40c585b3", |
00000721 => x"00d56533", |
00000722 => x"0016d693", |
00000723 => x"00165613", |
00000724 => x"fe0696e3", |
00000725 => x"00008067", |
00000726 => x"00008293", |
00000727 => x"fb5ff0ef", |
00000728 => x"00058513", |
00000729 => x"00028067", |
00000730 => x"40a00533", |
00000731 => x"00b04863", |
00000732 => x"40b005b3", |
00000733 => x"f9dff06f", |
00000734 => x"40b005b3", |
00000735 => x"00008293", |
00000736 => x"f91ff0ef", |
00000737 => x"40a00533", |
00000738 => x"00028067", |
00000739 => x"00008293", |
00000740 => x"0005ca63", |
00000741 => x"00054c63", |
00000742 => x"f79ff0ef", |
00000743 => x"00058513", |
00000744 => x"00028067", |
00000745 => x"40b005b3", |
00000746 => x"fe0558e3", |
00000747 => x"40a00533", |
00000748 => x"f61ff0ef", |
00000749 => x"40b00533", |
00000750 => x"00028067", |
00000751 => x"6e696c42", |
00000752 => x"676e696b", |
00000753 => x"44454c20", |
00000754 => x"6d656420", |
00000755 => x"7270206f", |
00000756 => x"6172676f", |
00000757 => x"00000a6d", |
00000758 => x"000002e8", |
00000759 => x"000002f4", |
00000760 => x"00000300", |
00000761 => x"0000030c", |
00000762 => x"00000318", |
00000763 => x"00000320", |
00000764 => x"00000328", |
00000765 => x"00000330", |
00000766 => x"00000254", |
00000767 => x"00000254", |
00000768 => x"00000254", |
00000769 => x"00000338", |
00000770 => x"00000340", |
00000771 => x"00000254", |
00000772 => x"00000254", |
00000773 => x"00000254", |
00000774 => x"00000348", |
00000775 => x"00000254", |
00000776 => x"00000254", |
00000777 => x"00000254", |
00000778 => x"00000350", |
00000779 => x"00000254", |
00000780 => x"00000254", |
00000781 => x"00000254", |
00000782 => x"00000254", |
00000783 => x"00000358", |
00000784 => x"00000360", |
00000785 => x"00000368", |
00000786 => x"00000370", |
00000787 => x"3c3c0a0a", |
00000788 => x"4f454e20", |
00000789 => x"32335652", |
00000790 => x"6e755220", |
00000791 => x"656d6974", |
00000792 => x"766e4520", |
00000793 => x"6e6f7269", |
00000794 => x"746e656d", |
00000795 => x"0a3e3e20", |
00000796 => x"00000000", |
00000797 => x"74737953", |
00000798 => x"74206d65", |
00000799 => x"3a656d69", |
00000800 => x"25783020", |
00000801 => x"78255f78", |
00000802 => x"0000000a", |
00000803 => x"45544e49", |
00000804 => x"50555252", |
00000805 => x"00000054", |
00000806 => x"45435845", |
00000807 => x"4f495450", |
00000808 => x"0000004e", |
00000809 => x"20746120", |
00000810 => x"74736e69", |
00000811 => x"74637572", |
00000812 => x"206e6f69", |
00000813 => x"72646461", |
00000814 => x"3a737365", |
00000815 => x"25783020", |
00000816 => x"00000a78", |
00000817 => x"73756143", |
00000818 => x"00203a65", |
00000819 => x"74736e49", |
00000820 => x"74637572", |
00000821 => x"206e6f69", |
00000822 => x"72646461", |
00000823 => x"20737365", |
00000824 => x"6173696d", |
00000825 => x"6e67696c", |
00000826 => x"00006465", |
00000827 => x"74736e49", |
00000828 => x"74637572", |
00000829 => x"206e6f69", |
00000830 => x"65636361", |
00000831 => x"66207373", |
00000832 => x"746c7561", |
00000833 => x"00000000", |
00000834 => x"656c6c49", |
00000835 => x"206c6167", |
00000836 => x"74736e69", |
00000837 => x"74637572", |
00000838 => x"006e6f69", |
00000839 => x"61657242", |
00000840 => x"696f706b", |
00000841 => x"2820746e", |
00000842 => x"45524245", |
00000843 => x"00294b41", |
00000844 => x"64616f4c", |
00000845 => x"64646120", |
00000846 => x"73736572", |
00000847 => x"73696d20", |
00000848 => x"67696c61", |
00000849 => x"0064656e", |
00000850 => x"64616f4c", |
00000851 => x"63636120", |
00000852 => x"20737365", |
00000853 => x"6c756166", |
00000854 => x"00000074", |
00000855 => x"726f7453", |
00000856 => x"64612065", |
00000857 => x"73657264", |
00000858 => x"696d2073", |
00000859 => x"696c6173", |
00000860 => x"64656e67", |
00000861 => x"00000000", |
00000862 => x"726f7453", |
00000863 => x"63612065", |
00000864 => x"73736563", |
00000865 => x"75616620", |
00000866 => x"0000746c", |
00000867 => x"69766e45", |
00000868 => x"6d6e6f72", |
00000869 => x"20746e65", |
00000870 => x"6c6c6163", |
00000871 => x"6f726620", |
00000872 => x"2d4d206d", |
00000873 => x"65646f6d", |
00000874 => x"00000000", |
00000875 => x"6863614d", |
00000876 => x"20656e69", |
00000877 => x"74666f73", |
00000878 => x"65726177", |
00000879 => x"746e6920", |
00000880 => x"75727265", |
00000881 => x"00007470", |
00000882 => x"6863614d", |
00000883 => x"20656e69", |
00000884 => x"656d6974", |
00000885 => x"6e692072", |
00000886 => x"72726574", |
00000887 => x"00747075", |
00000888 => x"6863614d", |
00000889 => x"20656e69", |
00000890 => x"65747865", |
00000891 => x"6c616e72", |
00000892 => x"746e6920", |
00000893 => x"75727265", |
00000894 => x"00007470", |
00000895 => x"74736146", |
00000896 => x"746e6920", |
00000897 => x"75727265", |
00000898 => x"63207470", |
00000899 => x"6e6e6168", |
00000900 => x"30206c65", |
00000901 => x"00000000", |
00000902 => x"74736146", |
00000903 => x"746e6920", |
00000904 => x"75727265", |
00000905 => x"63207470", |
00000906 => x"6e6e6168", |
00000907 => x"31206c65", |
00000908 => x"00000000", |
00000909 => x"74736146", |
00000910 => x"746e6920", |
00000911 => x"75727265", |
00000912 => x"63207470", |
00000913 => x"6e6e6168", |
00000914 => x"32206c65", |
00000915 => x"00000000", |
00000916 => x"74736146", |
00000917 => x"746e6920", |
00000918 => x"75727265", |
00000919 => x"63207470", |
00000920 => x"6e6e6168", |
00000921 => x"33206c65", |
00000922 => x"00000000", |
00000923 => x"6e6b6e55", |
00000924 => x"206e776f", |
00000925 => x"25783028", |
00000926 => x"00002978", |
00000927 => x"7561460a", |
00000928 => x"6e69746c", |
00000929 => x"6e692067", |
00000930 => x"75727473", |
00000931 => x"6f697463", |
00000932 => x"6c28206e", |
00000933 => x"6820776f", |
00000934 => x"20666c61", |
00000935 => x"64726f77", |
00000936 => x"30203a29", |
00000937 => x"00782578", |
00000938 => x"65642820", |
00000939 => x"706d6f63", |
00000940 => x"73736572", |
00000941 => x"0a296465", |
00000942 => x"00000000", |
00000943 => x"56544d0a", |
00000944 => x"203a4c41", |
00000945 => x"78257830", |
00000946 => x"0000000a", |
00000947 => x"69797254", |
00000948 => x"7420676e", |
00000949 => x"6572206f", |
00000950 => x"656d7573", |
00000951 => x"70706120", |
00000952 => x"6163696c", |
00000953 => x"6e6f6974", |
00000954 => x"30204020", |
00000955 => x"2e782578", |
00000956 => x"00002e2e", |
00000957 => x"2f3c3c0a", |
00000958 => x"524f454e", |
00000959 => x"20323356", |
00000960 => x"746e7552", |
00000961 => x"20656d69", |
00000962 => x"69766e45", |
00000963 => x"6d6e6f72", |
00000964 => x"20746e65", |
00000965 => x"0a0a3e3e", |
00000966 => x"00000000", |
00000967 => x"0000054c", |
00000968 => x"00000410", |
00000969 => x"00000410", |
00000970 => x"00000410", |
00000971 => x"00000558", |
00000972 => x"00000410", |
00000973 => x"00000410", |
00000974 => x"00000410", |
00000975 => x"00000564", |
00000976 => x"00000410", |
00000977 => x"00000410", |
00000978 => x"00000410", |
00000979 => x"00000410", |
00000980 => x"00000570", |
00000981 => x"0000057c", |
00000982 => x"00000588", |
00000983 => x"00000594", |
00000984 => x"00000478", |
00000985 => x"000004ec", |
00000986 => x"000004f8", |
00000987 => x"00000504", |
00000988 => x"00000510", |
00000989 => x"0000051c", |
00000990 => x"00000528", |
00000991 => x"00000534", |
00000992 => x"00000410", |
00000993 => x"00000410", |
00000994 => x"00000410", |
00000995 => x"00000540", |
00000996 => x"33323130", |
00000997 => x"37363534", |
00000998 => x"00003938", |
00000999 => x"33323130", |
00001000 => x"37363534", |
00001001 => x"62613938", |
00001002 => x"66656463", |
others => x"00000000" |
); |
|
/neorv32/trunk/rtl/core/neorv32_bootloader_image.vhd
27,1005 → 27,1010
00000016 => x"00000513", |
00000017 => x"00000713", |
00000018 => x"00000793", |
00000019 => x"030000ef", |
00000019 => x"054000ef", |
00000020 => x"0000006f", |
00000021 => x"ffc10113", |
00000021 => x"ff810113", |
00000022 => x"00812023", |
00000023 => x"34202473", |
00000024 => x"00044863", |
00000025 => x"34102473", |
00000026 => x"00440413", |
00000027 => x"34141073", |
00000028 => x"00012403", |
00000029 => x"00410113", |
00000030 => x"30200073", |
00000031 => x"fd010113", |
00000032 => x"02112623", |
00000033 => x"02812423", |
00000034 => x"02912223", |
00000035 => x"03212023", |
00000036 => x"01312e23", |
00000037 => x"01412c23", |
00000038 => x"01512a23", |
00000039 => x"01612823", |
00000040 => x"01712623", |
00000041 => x"01812423", |
00000042 => x"f8002823", |
00000043 => x"f8002a23", |
00000044 => x"1dd000ef", |
00000045 => x"509000ef", |
00000046 => x"4dd000ef", |
00000047 => x"445000ef", |
00000048 => x"295000ef", |
00000049 => x"4e5000ef", |
00000050 => x"fe002403", |
00000051 => x"026267b7", |
00000052 => x"9ff78793", |
00000053 => x"00000713", |
00000054 => x"00000693", |
00000055 => x"00000613", |
00000056 => x"00000593", |
00000057 => x"00200513", |
00000058 => x"0087f463", |
00000059 => x"00400513", |
00000060 => x"3c5000ef", |
00000061 => x"00005537", |
00000062 => x"00000613", |
00000063 => x"00000593", |
00000064 => x"b0050513", |
00000065 => x"2ad000ef", |
00000066 => x"265000ef", |
00000067 => x"00245793", |
00000068 => x"00a78533", |
00000069 => x"00f537b3", |
00000070 => x"00b785b3", |
00000071 => x"27d000ef", |
00000072 => x"ffff07b7", |
00000073 => x"42c78793", |
00000074 => x"30579073", |
00000075 => x"08000793", |
00000076 => x"30479073", |
00000077 => x"30046073", |
00000078 => x"00100513", |
00000079 => x"451000ef", |
00000080 => x"00000793", |
00000081 => x"34079073", |
00000082 => x"ffff1537", |
00000083 => x"f0050513", |
00000084 => x"30d000ef", |
00000085 => x"149000ef", |
00000086 => x"ffff1537", |
00000087 => x"f3850513", |
00000088 => x"2fd000ef", |
00000089 => x"fe002503", |
00000090 => x"254000ef", |
00000091 => x"ffff1537", |
00000092 => x"f4050513", |
00000093 => x"2e9000ef", |
00000094 => x"fe402503", |
00000095 => x"240000ef", |
00000096 => x"ffff1537", |
00000097 => x"f4c50513", |
00000098 => x"2d5000ef", |
00000099 => x"30102573", |
00000100 => x"22c000ef", |
00000101 => x"ffff1537", |
00000102 => x"f5450513", |
00000103 => x"2c1000ef", |
00000104 => x"fe802503", |
00000105 => x"ffff14b7", |
00000106 => x"00341413", |
00000107 => x"210000ef", |
00000108 => x"ffff1537", |
00000109 => x"f5c50513", |
00000110 => x"2a5000ef", |
00000111 => x"ff802503", |
00000112 => x"ffff1937", |
00000113 => x"1f8000ef", |
00000114 => x"f6448513", |
00000115 => x"291000ef", |
00000116 => x"ff002503", |
00000117 => x"1e8000ef", |
00000118 => x"ffff1537", |
00000119 => x"f7050513", |
00000120 => x"27d000ef", |
00000121 => x"ffc02503", |
00000122 => x"1d4000ef", |
00000123 => x"f6448513", |
00000124 => x"26d000ef", |
00000125 => x"ff402503", |
00000126 => x"1c4000ef", |
00000127 => x"ffff1537", |
00000128 => x"f7850513", |
00000129 => x"259000ef", |
00000130 => x"165000ef", |
00000131 => x"00a404b3", |
00000132 => x"0084b433", |
00000133 => x"00b40433", |
00000134 => x"fa402783", |
00000135 => x"0607d263", |
00000136 => x"ffff1537", |
00000137 => x"fa450513", |
00000138 => x"235000ef", |
00000139 => x"ffff1937", |
00000140 => x"0d4000ef", |
00000141 => x"ffff19b7", |
00000142 => x"07200a13", |
00000143 => x"06800a93", |
00000144 => x"07500b13", |
00000145 => x"07300b93", |
00000146 => x"ffff14b7", |
00000147 => x"ffff1c37", |
00000148 => x"fb090513", |
00000149 => x"209000ef", |
00000150 => x"1f5000ef", |
00000151 => x"00050413", |
00000152 => x"1dd000ef", |
00000153 => x"fa098513", |
00000154 => x"1f5000ef", |
00000155 => x"03441e63", |
00000156 => x"30047073", |
00000157 => x"ffff02b7", |
00000158 => x"00028067", |
00000159 => x"0000006f", |
00000160 => x"0ed000ef", |
00000161 => x"f885eae3", |
00000162 => x"00b41463", |
00000163 => x"f89566e3", |
00000164 => x"00100513", |
00000165 => x"43c000ef", |
00000166 => x"fa090513", |
00000167 => x"1c1000ef", |
00000168 => x"070000ef", |
00000169 => x"f75ff06f", |
00000170 => x"01541663", |
00000171 => x"058000ef", |
00000172 => x"fa1ff06f", |
00000173 => x"00000513", |
00000174 => x"01640e63", |
00000175 => x"01741663", |
00000176 => x"654000ef", |
00000177 => x"f8dff06f", |
00000178 => x"06c00793", |
00000179 => x"00f41863", |
00000180 => x"00100513", |
00000181 => x"3fc000ef", |
00000182 => x"f79ff06f", |
00000183 => x"06500793", |
00000184 => x"00f41663", |
00000185 => x"02c000ef", |
00000186 => x"f69ff06f", |
00000187 => x"03f00793", |
00000188 => x"fb8c0513", |
00000189 => x"00f40463", |
00000190 => x"fcc48513", |
00000191 => x"161000ef", |
00000192 => x"f51ff06f", |
00000193 => x"ffff1537", |
00000194 => x"dd050513", |
00000195 => x"1510006f", |
00000196 => x"340027f3", |
00000197 => x"00079863", |
00000198 => x"ffff1537", |
00000199 => x"e3450513", |
00000200 => x"13d0006f", |
00000201 => x"ff010113", |
00000202 => x"00112623", |
00000203 => x"30047073", |
00000204 => x"00000793", |
00000205 => x"30479073", |
00000023 => x"00912223", |
00000024 => x"34202473", |
00000025 => x"02044663", |
00000026 => x"34102473", |
00000027 => x"00041483", |
00000028 => x"0034f493", |
00000029 => x"00240413", |
00000030 => x"34141073", |
00000031 => x"00300413", |
00000032 => x"00941863", |
00000033 => x"34102473", |
00000034 => x"00240413", |
00000035 => x"34141073", |
00000036 => x"00012483", |
00000037 => x"00412403", |
00000038 => x"00810113", |
00000039 => x"30200073", |
00000040 => x"fd010113", |
00000041 => x"02112623", |
00000042 => x"02812423", |
00000043 => x"02912223", |
00000044 => x"03212023", |
00000045 => x"01312e23", |
00000046 => x"01412c23", |
00000047 => x"01512a23", |
00000048 => x"01612823", |
00000049 => x"01712623", |
00000050 => x"01812423", |
00000051 => x"f8002823", |
00000052 => x"f8002a23", |
00000053 => x"1e1000ef", |
00000054 => x"4cd000ef", |
00000055 => x"435000ef", |
00000056 => x"4ed000ef", |
00000057 => x"4d5000ef", |
00000058 => x"fe002403", |
00000059 => x"026267b7", |
00000060 => x"9ff78793", |
00000061 => x"00000713", |
00000062 => x"00000693", |
00000063 => x"00000613", |
00000064 => x"00000593", |
00000065 => x"00200513", |
00000066 => x"0087f463", |
00000067 => x"00400513", |
00000068 => x"3b5000ef", |
00000069 => x"00005537", |
00000070 => x"00000613", |
00000071 => x"00000593", |
00000072 => x"b0050513", |
00000073 => x"29d000ef", |
00000074 => x"255000ef", |
00000075 => x"00245793", |
00000076 => x"00a78533", |
00000077 => x"00f537b3", |
00000078 => x"00b785b3", |
00000079 => x"26d000ef", |
00000080 => x"ffff07b7", |
00000081 => x"44c78793", |
00000082 => x"30579073", |
00000083 => x"08000793", |
00000084 => x"30479073", |
00000085 => x"30046073", |
00000086 => x"00100513", |
00000087 => x"441000ef", |
00000088 => x"00000793", |
00000089 => x"34079073", |
00000090 => x"ffff1537", |
00000091 => x"f1450513", |
00000092 => x"2fd000ef", |
00000093 => x"151000ef", |
00000094 => x"ffff1537", |
00000095 => x"f4c50513", |
00000096 => x"2ed000ef", |
00000097 => x"fe002503", |
00000098 => x"254000ef", |
00000099 => x"ffff1537", |
00000100 => x"f5450513", |
00000101 => x"2d9000ef", |
00000102 => x"fe402503", |
00000103 => x"240000ef", |
00000104 => x"ffff1537", |
00000105 => x"f6050513", |
00000106 => x"2c5000ef", |
00000107 => x"30102573", |
00000108 => x"22c000ef", |
00000109 => x"ffff1537", |
00000110 => x"f6850513", |
00000111 => x"2b1000ef", |
00000112 => x"fe802503", |
00000113 => x"ffff14b7", |
00000114 => x"00341413", |
00000115 => x"210000ef", |
00000116 => x"ffff1537", |
00000117 => x"f7050513", |
00000118 => x"295000ef", |
00000119 => x"ff802503", |
00000120 => x"ffff1937", |
00000121 => x"1f8000ef", |
00000122 => x"f7848513", |
00000123 => x"281000ef", |
00000124 => x"ff002503", |
00000125 => x"1e8000ef", |
00000126 => x"ffff1537", |
00000127 => x"f8450513", |
00000128 => x"26d000ef", |
00000129 => x"ffc02503", |
00000130 => x"1d4000ef", |
00000131 => x"f7848513", |
00000132 => x"25d000ef", |
00000133 => x"ff402503", |
00000134 => x"1c4000ef", |
00000135 => x"ffff1537", |
00000136 => x"f8c50513", |
00000137 => x"249000ef", |
00000138 => x"155000ef", |
00000139 => x"00a404b3", |
00000140 => x"0084b433", |
00000141 => x"00b40433", |
00000142 => x"fa402783", |
00000143 => x"0607d263", |
00000144 => x"ffff1537", |
00000145 => x"fb850513", |
00000146 => x"225000ef", |
00000147 => x"ffff1937", |
00000148 => x"0d4000ef", |
00000149 => x"ffff19b7", |
00000150 => x"07200a13", |
00000151 => x"06800a93", |
00000152 => x"07500b13", |
00000153 => x"07300b93", |
00000154 => x"ffff14b7", |
00000155 => x"ffff1c37", |
00000156 => x"fc490513", |
00000157 => x"1f9000ef", |
00000158 => x"1e5000ef", |
00000159 => x"00050413", |
00000160 => x"1cd000ef", |
00000161 => x"fb498513", |
00000162 => x"1e5000ef", |
00000163 => x"03441e63", |
00000164 => x"30047073", |
00000165 => x"ffff02b7", |
00000166 => x"00028067", |
00000167 => x"0000006f", |
00000168 => x"0dd000ef", |
00000169 => x"f885eae3", |
00000170 => x"00b41463", |
00000171 => x"f89566e3", |
00000172 => x"00100513", |
00000173 => x"444000ef", |
00000174 => x"fb490513", |
00000175 => x"1b1000ef", |
00000176 => x"070000ef", |
00000177 => x"f75ff06f", |
00000178 => x"01541663", |
00000179 => x"058000ef", |
00000180 => x"fa1ff06f", |
00000181 => x"00000513", |
00000182 => x"01640e63", |
00000183 => x"01741663", |
00000184 => x"65c000ef", |
00000185 => x"f8dff06f", |
00000186 => x"06c00793", |
00000187 => x"00f41863", |
00000188 => x"00100513", |
00000189 => x"404000ef", |
00000190 => x"f79ff06f", |
00000191 => x"06500793", |
00000192 => x"00f41663", |
00000193 => x"02c000ef", |
00000194 => x"f69ff06f", |
00000195 => x"03f00793", |
00000196 => x"fccc0513", |
00000197 => x"00f40463", |
00000198 => x"fe048513", |
00000199 => x"151000ef", |
00000200 => x"f51ff06f", |
00000201 => x"ffff1537", |
00000202 => x"de450513", |
00000203 => x"1410006f", |
00000204 => x"340027f3", |
00000205 => x"00079863", |
00000206 => x"ffff1537", |
00000207 => x"e5050513", |
00000208 => x"11d000ef", |
00000209 => x"fa002783", |
00000210 => x"fe07cee3", |
00000211 => x"b0001073", |
00000212 => x"b8001073", |
00000213 => x"b0201073", |
00000214 => x"b8201073", |
00000215 => x"ff002783", |
00000216 => x"00078067", |
00000217 => x"ff9ff06f", |
00000218 => x"ff010113", |
00000219 => x"00812423", |
00000220 => x"00050413", |
00000221 => x"ffff1537", |
00000222 => x"e6050513", |
00000223 => x"00112623", |
00000224 => x"0dd000ef", |
00000225 => x"00500793", |
00000226 => x"0287e263", |
00000227 => x"03040513", |
00000228 => x"0ff57513", |
00000229 => x"0a9000ef", |
00000230 => x"30047073", |
00000231 => x"00100513", |
00000232 => x"1ed000ef", |
00000233 => x"10500073", |
00000234 => x"0000006f", |
00000235 => x"ffff1537", |
00000236 => x"e6850513", |
00000237 => x"0a9000ef", |
00000238 => x"fe1ff06f", |
00000239 => x"fe010113", |
00000240 => x"01212823", |
00000241 => x"00050913", |
00000242 => x"ffff1537", |
00000243 => x"00912a23", |
00000244 => x"e7050513", |
00000245 => x"ffff14b7", |
00000246 => x"00812c23", |
00000247 => x"01312623", |
00000248 => x"00112e23", |
00000249 => x"01c00413", |
00000250 => x"075000ef", |
00000251 => x"fd848493", |
00000252 => x"ffc00993", |
00000253 => x"008957b3", |
00000254 => x"00f7f793", |
00000255 => x"00f487b3", |
00000256 => x"0007c503", |
00000257 => x"ffc40413", |
00000258 => x"035000ef", |
00000259 => x"ff3414e3", |
00000260 => x"01c12083", |
00000261 => x"01812403", |
00000262 => x"01412483", |
00000263 => x"01012903", |
00000264 => x"00c12983", |
00000265 => x"02010113", |
00000266 => x"00008067", |
00000267 => x"fb010113", |
00000268 => x"04112623", |
00000269 => x"04512423", |
00000270 => x"04612223", |
00000271 => x"04712023", |
00000272 => x"02812e23", |
00000273 => x"02a12c23", |
00000274 => x"02b12a23", |
00000275 => x"02c12823", |
00000276 => x"02d12623", |
00000277 => x"02e12423", |
00000278 => x"02f12223", |
00000279 => x"03012023", |
00000280 => x"01112e23", |
00000281 => x"01c12c23", |
00000282 => x"01d12a23", |
00000283 => x"01e12823", |
00000284 => x"01f12623", |
00000285 => x"34202473", |
00000286 => x"800007b7", |
00000287 => x"00778793", |
00000288 => x"02f40a63", |
00000289 => x"ffff1537", |
00000290 => x"e7450513", |
00000291 => x"7d0000ef", |
00000292 => x"00040513", |
00000293 => x"f29ff0ef", |
00000294 => x"ffff1537", |
00000295 => x"e8450513", |
00000296 => x"7bc000ef", |
00000297 => x"34102573", |
00000298 => x"f15ff0ef", |
00000299 => x"00500513", |
00000300 => x"eb9ff0ef", |
00000301 => x"00000513", |
00000302 => x"0b5000ef", |
00000303 => x"6b0000ef", |
00000304 => x"fe002783", |
00000305 => x"0027d793", |
00000306 => x"00a78533", |
00000307 => x"00f537b3", |
00000308 => x"00b785b3", |
00000309 => x"6c4000ef", |
00000310 => x"03c12403", |
00000311 => x"04c12083", |
00000312 => x"04812283", |
00000313 => x"04412303", |
00000314 => x"04012383", |
00000315 => x"03812503", |
00000316 => x"03412583", |
00000317 => x"03012603", |
00000318 => x"02c12683", |
00000319 => x"02812703", |
00000320 => x"02412783", |
00000321 => x"02012803", |
00000322 => x"01c12883", |
00000323 => x"01812e03", |
00000324 => x"01412e83", |
00000325 => x"01012f03", |
00000326 => x"00c12f83", |
00000327 => x"05010113", |
00000328 => x"30200073", |
00000329 => x"ff010113", |
00000330 => x"00000513", |
00000331 => x"00112623", |
00000332 => x"00812423", |
00000333 => x"7e0000ef", |
00000334 => x"00500513", |
00000335 => x"01d000ef", |
00000336 => x"00000513", |
00000337 => x"015000ef", |
00000338 => x"00050413", |
00000339 => x"00000513", |
00000340 => x"7e4000ef", |
00000341 => x"00c12083", |
00000342 => x"0ff47513", |
00000343 => x"00812403", |
00000344 => x"01010113", |
00000345 => x"00008067", |
00000346 => x"ff010113", |
00000207 => x"e4850513", |
00000208 => x"12d0006f", |
00000209 => x"ff010113", |
00000210 => x"00112623", |
00000211 => x"30047073", |
00000212 => x"00000793", |
00000213 => x"30479073", |
00000214 => x"ffff1537", |
00000215 => x"e6450513", |
00000216 => x"10d000ef", |
00000217 => x"fa002783", |
00000218 => x"fe07cee3", |
00000219 => x"b0001073", |
00000220 => x"b8001073", |
00000221 => x"b0201073", |
00000222 => x"b8201073", |
00000223 => x"ff002783", |
00000224 => x"00078067", |
00000225 => x"0000006f", |
00000226 => x"ff010113", |
00000227 => x"00812423", |
00000228 => x"00050413", |
00000229 => x"ffff1537", |
00000230 => x"e7450513", |
00000231 => x"00112623", |
00000232 => x"0cd000ef", |
00000233 => x"00500793", |
00000234 => x"0287e263", |
00000235 => x"03040513", |
00000236 => x"0ff57513", |
00000237 => x"099000ef", |
00000238 => x"30047073", |
00000239 => x"00100513", |
00000240 => x"1dd000ef", |
00000241 => x"10500073", |
00000242 => x"0000006f", |
00000243 => x"ffff1537", |
00000244 => x"e7c50513", |
00000245 => x"099000ef", |
00000246 => x"fe1ff06f", |
00000247 => x"fe010113", |
00000248 => x"01212823", |
00000249 => x"00050913", |
00000250 => x"ffff1537", |
00000251 => x"00912a23", |
00000252 => x"e8450513", |
00000253 => x"ffff14b7", |
00000254 => x"00812c23", |
00000255 => x"01312623", |
00000256 => x"00112e23", |
00000257 => x"01c00413", |
00000258 => x"065000ef", |
00000259 => x"fec48493", |
00000260 => x"ffc00993", |
00000261 => x"008957b3", |
00000262 => x"00f7f793", |
00000263 => x"00f487b3", |
00000264 => x"0007c503", |
00000265 => x"ffc40413", |
00000266 => x"025000ef", |
00000267 => x"ff3414e3", |
00000268 => x"01c12083", |
00000269 => x"01812403", |
00000270 => x"01412483", |
00000271 => x"01012903", |
00000272 => x"00c12983", |
00000273 => x"02010113", |
00000274 => x"00008067", |
00000275 => x"fb010113", |
00000276 => x"04112623", |
00000277 => x"04512423", |
00000278 => x"04612223", |
00000279 => x"04712023", |
00000280 => x"02812e23", |
00000281 => x"02a12c23", |
00000282 => x"02b12a23", |
00000283 => x"02c12823", |
00000284 => x"02d12623", |
00000285 => x"02e12423", |
00000286 => x"02f12223", |
00000287 => x"03012023", |
00000288 => x"01112e23", |
00000289 => x"01c12c23", |
00000290 => x"01d12a23", |
00000291 => x"01e12823", |
00000292 => x"01f12623", |
00000293 => x"34202473", |
00000294 => x"800007b7", |
00000295 => x"00778793", |
00000296 => x"02f40a63", |
00000297 => x"ffff1537", |
00000298 => x"e8850513", |
00000299 => x"7c0000ef", |
00000300 => x"00040513", |
00000301 => x"f29ff0ef", |
00000302 => x"ffff1537", |
00000303 => x"e9850513", |
00000304 => x"7ac000ef", |
00000305 => x"34102573", |
00000306 => x"f15ff0ef", |
00000307 => x"00500513", |
00000308 => x"eb9ff0ef", |
00000309 => x"00000513", |
00000310 => x"0a5000ef", |
00000311 => x"6a0000ef", |
00000312 => x"fe002783", |
00000313 => x"0027d793", |
00000314 => x"00a78533", |
00000315 => x"00f537b3", |
00000316 => x"00b785b3", |
00000317 => x"6b4000ef", |
00000318 => x"03c12403", |
00000319 => x"04c12083", |
00000320 => x"04812283", |
00000321 => x"04412303", |
00000322 => x"04012383", |
00000323 => x"03812503", |
00000324 => x"03412583", |
00000325 => x"03012603", |
00000326 => x"02c12683", |
00000327 => x"02812703", |
00000328 => x"02412783", |
00000329 => x"02012803", |
00000330 => x"01c12883", |
00000331 => x"01812e03", |
00000332 => x"01412e83", |
00000333 => x"01012f03", |
00000334 => x"00c12f83", |
00000335 => x"05010113", |
00000336 => x"30200073", |
00000337 => x"ff010113", |
00000338 => x"00000513", |
00000339 => x"00112623", |
00000340 => x"00812423", |
00000341 => x"7d0000ef", |
00000342 => x"00500513", |
00000343 => x"00d000ef", |
00000344 => x"00000513", |
00000345 => x"005000ef", |
00000346 => x"00050413", |
00000347 => x"00000513", |
00000348 => x"00112623", |
00000349 => x"00812423", |
00000350 => x"79c000ef", |
00000351 => x"09e00513", |
00000352 => x"7d8000ef", |
00000353 => x"00000513", |
00000354 => x"7d0000ef", |
00000355 => x"00050413", |
00000356 => x"00000513", |
00000357 => x"7a0000ef", |
00000358 => x"00c12083", |
00000359 => x"0ff47513", |
00000360 => x"00812403", |
00000361 => x"01010113", |
00000362 => x"00008067", |
00000363 => x"ff010113", |
00000348 => x"7d4000ef", |
00000349 => x"00c12083", |
00000350 => x"0ff47513", |
00000351 => x"00812403", |
00000352 => x"01010113", |
00000353 => x"00008067", |
00000354 => x"ff010113", |
00000355 => x"00000513", |
00000356 => x"00112623", |
00000357 => x"00812423", |
00000358 => x"78c000ef", |
00000359 => x"09e00513", |
00000360 => x"7c8000ef", |
00000361 => x"00000513", |
00000362 => x"7c0000ef", |
00000363 => x"00050413", |
00000364 => x"00000513", |
00000365 => x"00112623", |
00000366 => x"75c000ef", |
00000367 => x"00600513", |
00000368 => x"798000ef", |
00000369 => x"00c12083", |
00000370 => x"00000513", |
00000371 => x"01010113", |
00000372 => x"7640006f", |
00000373 => x"ff010113", |
00000374 => x"00812423", |
00000375 => x"00050413", |
00000376 => x"01055513", |
00000377 => x"0ff57513", |
00000378 => x"00112623", |
00000379 => x"76c000ef", |
00000380 => x"00845513", |
00000381 => x"0ff57513", |
00000382 => x"760000ef", |
00000383 => x"0ff47513", |
00000384 => x"00812403", |
00000385 => x"00c12083", |
00000386 => x"01010113", |
00000387 => x"74c0006f", |
00000388 => x"ff010113", |
00000389 => x"00812423", |
00000390 => x"00050413", |
00000391 => x"00000513", |
00000392 => x"00112623", |
00000393 => x"6f0000ef", |
00000394 => x"00300513", |
00000395 => x"72c000ef", |
00000396 => x"00040513", |
00000397 => x"fa1ff0ef", |
00000398 => x"00000513", |
00000399 => x"71c000ef", |
00000400 => x"00050413", |
00000401 => x"00000513", |
00000402 => x"6ec000ef", |
00000403 => x"00c12083", |
00000404 => x"0ff47513", |
00000405 => x"00812403", |
00000406 => x"01010113", |
00000407 => x"00008067", |
00000408 => x"fd010113", |
00000409 => x"02812423", |
00000410 => x"02912223", |
00000411 => x"03212023", |
00000412 => x"01312e23", |
00000413 => x"02112623", |
00000414 => x"00050493", |
00000415 => x"00300413", |
00000416 => x"00358913", |
00000417 => x"fff00993", |
00000418 => x"02049e63", |
00000419 => x"5c0000ef", |
00000420 => x"00c10793", |
00000421 => x"008787b3", |
00000422 => x"00a78023", |
00000423 => x"fff40413", |
00000424 => x"ff3414e3", |
00000425 => x"02c12083", |
00000426 => x"02812403", |
00000427 => x"00c12503", |
00000428 => x"02412483", |
00000429 => x"02012903", |
00000430 => x"01c12983", |
00000431 => x"03010113", |
00000432 => x"00008067", |
00000433 => x"40890533", |
00000434 => x"f49ff0ef", |
00000435 => x"fc5ff06f", |
00000436 => x"fd010113", |
00000437 => x"02812423", |
00000438 => x"fe802403", |
00000439 => x"02112623", |
00000440 => x"02912223", |
00000441 => x"03212023", |
00000442 => x"01312e23", |
00000443 => x"01412c23", |
00000444 => x"01512a23", |
00000445 => x"01612823", |
00000446 => x"01712623", |
00000447 => x"00847413", |
00000448 => x"00040663", |
00000449 => x"00400513", |
00000450 => x"c61ff0ef", |
00000451 => x"00050493", |
00000452 => x"02051863", |
00000453 => x"ffff1537", |
00000454 => x"e8c50513", |
00000455 => x"540000ef", |
00000456 => x"008005b7", |
00000457 => x"00048513", |
00000458 => x"f39ff0ef", |
00000459 => x"4788d7b7", |
00000460 => x"afe78793", |
00000461 => x"02f50463", |
00000462 => x"00000513", |
00000463 => x"fcdff06f", |
00000464 => x"ffff1537", |
00000465 => x"eac50513", |
00000466 => x"514000ef", |
00000467 => x"e1dff0ef", |
00000468 => x"fc0518e3", |
00000469 => x"00300513", |
00000470 => x"fb1ff06f", |
00000471 => x"00800a37", |
00000472 => x"004a0593", |
00000473 => x"00048513", |
00000474 => x"ef9ff0ef", |
00000475 => x"00050913", |
00000476 => x"008a0593", |
00000477 => x"00048513", |
00000478 => x"ee9ff0ef", |
00000479 => x"ff802783", |
00000480 => x"00050a93", |
00000481 => x"00100513", |
00000482 => x"f927e0e3", |
00000483 => x"ff002b83", |
00000484 => x"ffc97b13", |
00000485 => x"00000993", |
00000486 => x"00ca0a13", |
00000487 => x"014985b3", |
00000488 => x"053b1663", |
00000489 => x"01540433", |
00000490 => x"00200513", |
00000491 => x"f4041ee3", |
00000492 => x"ffff1537", |
00000493 => x"eb850513", |
00000494 => x"4a4000ef", |
00000495 => x"34091073", |
00000496 => x"02c12083", |
00000497 => x"02812403", |
00000498 => x"02412483", |
00000499 => x"02012903", |
00000500 => x"01c12983", |
00000501 => x"01812a03", |
00000502 => x"01412a83", |
00000503 => x"01012b03", |
00000504 => x"00c12b83", |
00000505 => x"03010113", |
00000506 => x"00008067", |
00000507 => x"00048513", |
00000508 => x"e71ff0ef", |
00000509 => x"013b87b3", |
00000510 => x"00a40433", |
00000511 => x"00a7a023", |
00000512 => x"00498993", |
00000513 => x"f99ff06f", |
00000514 => x"ff010113", |
00000515 => x"00112623", |
00000516 => x"00812423", |
00000517 => x"00912223", |
00000518 => x"00058413", |
00000519 => x"00050493", |
00000520 => x"d8dff0ef", |
00000521 => x"00000513", |
00000522 => x"4ec000ef", |
00000523 => x"00200513", |
00000524 => x"528000ef", |
00000525 => x"00048513", |
00000526 => x"d9dff0ef", |
00000527 => x"00040513", |
00000528 => x"518000ef", |
00000529 => x"00000513", |
00000530 => x"4ec000ef", |
00000531 => x"cd9ff0ef", |
00000532 => x"00157513", |
00000533 => x"fe051ce3", |
00000534 => x"00c12083", |
00000535 => x"00812403", |
00000536 => x"00412483", |
00000537 => x"01010113", |
00000538 => x"00008067", |
00000539 => x"fe010113", |
00000540 => x"00812c23", |
00000541 => x"00912a23", |
00000542 => x"01212823", |
00000543 => x"00112e23", |
00000544 => x"00b12623", |
00000545 => x"00300413", |
00000546 => x"00350493", |
00000547 => x"fff00913", |
00000548 => x"00c10793", |
00000549 => x"008787b3", |
00000550 => x"0007c583", |
00000551 => x"40848533", |
00000552 => x"fff40413", |
00000553 => x"f65ff0ef", |
00000554 => x"ff2414e3", |
00000555 => x"01c12083", |
00000556 => x"01812403", |
00000557 => x"01412483", |
00000558 => x"01012903", |
00000559 => x"02010113", |
00000560 => x"00008067", |
00000561 => x"ff010113", |
00000562 => x"00112623", |
00000563 => x"00812423", |
00000564 => x"00050413", |
00000565 => x"cd9ff0ef", |
00000566 => x"00000513", |
00000567 => x"438000ef", |
00000568 => x"0d800513", |
00000569 => x"474000ef", |
00000570 => x"00040513", |
00000571 => x"ce9ff0ef", |
00000572 => x"00000513", |
00000573 => x"440000ef", |
00000574 => x"c2dff0ef", |
00000575 => x"00157513", |
00000576 => x"fe051ce3", |
00000577 => x"00c12083", |
00000578 => x"00812403", |
00000579 => x"01010113", |
00000580 => x"00008067", |
00000581 => x"fe010113", |
00000582 => x"00112e23", |
00000583 => x"00812c23", |
00000584 => x"00912a23", |
00000585 => x"01212823", |
00000586 => x"01312623", |
00000587 => x"01412423", |
00000588 => x"01512223", |
00000589 => x"34002473", |
00000590 => x"02041863", |
00000591 => x"ffff1537", |
00000592 => x"e3450513", |
00000593 => x"01812403", |
00000594 => x"01c12083", |
00000595 => x"01412483", |
00000596 => x"01012903", |
00000597 => x"00c12983", |
00000598 => x"00812a03", |
00000599 => x"00412a83", |
00000600 => x"02010113", |
00000601 => x"2f80006f", |
00000602 => x"ffff1537", |
00000603 => x"ebc50513", |
00000604 => x"2ec000ef", |
00000605 => x"00040513", |
00000606 => x"a45ff0ef", |
00000607 => x"ffff1537", |
00000608 => x"ec850513", |
00000609 => x"2d8000ef", |
00000610 => x"00800537", |
00000611 => x"a31ff0ef", |
00000365 => x"790000ef", |
00000366 => x"00c12083", |
00000367 => x"0ff47513", |
00000368 => x"00812403", |
00000369 => x"01010113", |
00000370 => x"00008067", |
00000371 => x"ff010113", |
00000372 => x"00000513", |
00000373 => x"00112623", |
00000374 => x"74c000ef", |
00000375 => x"00600513", |
00000376 => x"788000ef", |
00000377 => x"00c12083", |
00000378 => x"00000513", |
00000379 => x"01010113", |
00000380 => x"7540006f", |
00000381 => x"ff010113", |
00000382 => x"00812423", |
00000383 => x"00050413", |
00000384 => x"01055513", |
00000385 => x"0ff57513", |
00000386 => x"00112623", |
00000387 => x"75c000ef", |
00000388 => x"00845513", |
00000389 => x"0ff57513", |
00000390 => x"750000ef", |
00000391 => x"0ff47513", |
00000392 => x"00812403", |
00000393 => x"00c12083", |
00000394 => x"01010113", |
00000395 => x"73c0006f", |
00000396 => x"ff010113", |
00000397 => x"00812423", |
00000398 => x"00050413", |
00000399 => x"00000513", |
00000400 => x"00112623", |
00000401 => x"6e0000ef", |
00000402 => x"00300513", |
00000403 => x"71c000ef", |
00000404 => x"00040513", |
00000405 => x"fa1ff0ef", |
00000406 => x"00000513", |
00000407 => x"70c000ef", |
00000408 => x"00050413", |
00000409 => x"00000513", |
00000410 => x"6dc000ef", |
00000411 => x"00c12083", |
00000412 => x"0ff47513", |
00000413 => x"00812403", |
00000414 => x"01010113", |
00000415 => x"00008067", |
00000416 => x"fd010113", |
00000417 => x"02812423", |
00000418 => x"02912223", |
00000419 => x"03212023", |
00000420 => x"01312e23", |
00000421 => x"01412c23", |
00000422 => x"02112623", |
00000423 => x"00050913", |
00000424 => x"00058993", |
00000425 => x"00c10493", |
00000426 => x"00000413", |
00000427 => x"00400a13", |
00000428 => x"02091e63", |
00000429 => x"5a8000ef", |
00000430 => x"00a481a3", |
00000431 => x"00140413", |
00000432 => x"fff48493", |
00000433 => x"ff4416e3", |
00000434 => x"02c12083", |
00000435 => x"02812403", |
00000436 => x"00c12503", |
00000437 => x"02412483", |
00000438 => x"02012903", |
00000439 => x"01c12983", |
00000440 => x"01812a03", |
00000441 => x"03010113", |
00000442 => x"00008067", |
00000443 => x"00898533", |
00000444 => x"f41ff0ef", |
00000445 => x"fc5ff06f", |
00000446 => x"fd010113", |
00000447 => x"02812423", |
00000448 => x"fe802403", |
00000449 => x"02112623", |
00000450 => x"02912223", |
00000451 => x"03212023", |
00000452 => x"01312e23", |
00000453 => x"01412c23", |
00000454 => x"01512a23", |
00000455 => x"01612823", |
00000456 => x"01712623", |
00000457 => x"00847413", |
00000458 => x"00040663", |
00000459 => x"00400513", |
00000460 => x"c59ff0ef", |
00000461 => x"00050493", |
00000462 => x"02051863", |
00000463 => x"ffff1537", |
00000464 => x"ea050513", |
00000465 => x"528000ef", |
00000466 => x"008005b7", |
00000467 => x"00048513", |
00000468 => x"f31ff0ef", |
00000469 => x"4788d7b7", |
00000470 => x"afe78793", |
00000471 => x"02f50463", |
00000472 => x"00000513", |
00000473 => x"fcdff06f", |
00000474 => x"ffff1537", |
00000475 => x"ec050513", |
00000476 => x"4fc000ef", |
00000477 => x"e15ff0ef", |
00000478 => x"fc0518e3", |
00000479 => x"00300513", |
00000480 => x"fb1ff06f", |
00000481 => x"00800a37", |
00000482 => x"004a0593", |
00000483 => x"00048513", |
00000484 => x"ef1ff0ef", |
00000485 => x"00050913", |
00000486 => x"008a0593", |
00000487 => x"00048513", |
00000488 => x"ee1ff0ef", |
00000489 => x"ff802783", |
00000490 => x"00050a93", |
00000491 => x"00100513", |
00000492 => x"f927e0e3", |
00000493 => x"ff002b83", |
00000494 => x"ffc97b13", |
00000495 => x"00000993", |
00000496 => x"00ca0a13", |
00000497 => x"014985b3", |
00000498 => x"053b1663", |
00000499 => x"01540433", |
00000500 => x"00200513", |
00000501 => x"f4041ee3", |
00000502 => x"ffff1537", |
00000503 => x"ecc50513", |
00000504 => x"48c000ef", |
00000505 => x"34091073", |
00000506 => x"02c12083", |
00000507 => x"02812403", |
00000508 => x"02412483", |
00000509 => x"02012903", |
00000510 => x"01c12983", |
00000511 => x"01812a03", |
00000512 => x"01412a83", |
00000513 => x"01012b03", |
00000514 => x"00c12b83", |
00000515 => x"03010113", |
00000516 => x"00008067", |
00000517 => x"00048513", |
00000518 => x"e69ff0ef", |
00000519 => x"013b87b3", |
00000520 => x"00a40433", |
00000521 => x"00a7a023", |
00000522 => x"00498993", |
00000523 => x"f99ff06f", |
00000524 => x"ff010113", |
00000525 => x"00112623", |
00000526 => x"00812423", |
00000527 => x"00912223", |
00000528 => x"00058413", |
00000529 => x"00050493", |
00000530 => x"d85ff0ef", |
00000531 => x"00000513", |
00000532 => x"4d4000ef", |
00000533 => x"00200513", |
00000534 => x"510000ef", |
00000535 => x"00048513", |
00000536 => x"d95ff0ef", |
00000537 => x"00040513", |
00000538 => x"500000ef", |
00000539 => x"00000513", |
00000540 => x"4d4000ef", |
00000541 => x"cd1ff0ef", |
00000542 => x"00157513", |
00000543 => x"fe051ce3", |
00000544 => x"00c12083", |
00000545 => x"00812403", |
00000546 => x"00412483", |
00000547 => x"01010113", |
00000548 => x"00008067", |
00000549 => x"fe010113", |
00000550 => x"00812c23", |
00000551 => x"00912a23", |
00000552 => x"01212823", |
00000553 => x"00112e23", |
00000554 => x"00b12623", |
00000555 => x"00300413", |
00000556 => x"00350493", |
00000557 => x"fff00913", |
00000558 => x"00c10793", |
00000559 => x"008787b3", |
00000560 => x"0007c583", |
00000561 => x"40848533", |
00000562 => x"fff40413", |
00000563 => x"f65ff0ef", |
00000564 => x"ff2414e3", |
00000565 => x"01c12083", |
00000566 => x"01812403", |
00000567 => x"01412483", |
00000568 => x"01012903", |
00000569 => x"02010113", |
00000570 => x"00008067", |
00000571 => x"ff010113", |
00000572 => x"00112623", |
00000573 => x"00812423", |
00000574 => x"00050413", |
00000575 => x"cd1ff0ef", |
00000576 => x"00000513", |
00000577 => x"420000ef", |
00000578 => x"0d800513", |
00000579 => x"45c000ef", |
00000580 => x"00040513", |
00000581 => x"ce1ff0ef", |
00000582 => x"00000513", |
00000583 => x"428000ef", |
00000584 => x"c25ff0ef", |
00000585 => x"00157513", |
00000586 => x"fe051ce3", |
00000587 => x"00c12083", |
00000588 => x"00812403", |
00000589 => x"01010113", |
00000590 => x"00008067", |
00000591 => x"fe010113", |
00000592 => x"00112e23", |
00000593 => x"00812c23", |
00000594 => x"00912a23", |
00000595 => x"01212823", |
00000596 => x"01312623", |
00000597 => x"01412423", |
00000598 => x"01512223", |
00000599 => x"34002473", |
00000600 => x"02041863", |
00000601 => x"ffff1537", |
00000602 => x"e4850513", |
00000603 => x"01812403", |
00000604 => x"01c12083", |
00000605 => x"01412483", |
00000606 => x"01012903", |
00000607 => x"00c12983", |
00000608 => x"00812a03", |
00000609 => x"00412a83", |
00000610 => x"02010113", |
00000611 => x"2e00006f", |
00000612 => x"ffff1537", |
00000613 => x"ee450513", |
00000614 => x"2c4000ef", |
00000615 => x"2b0000ef", |
00000616 => x"00050493", |
00000617 => x"298000ef", |
00000618 => x"07900793", |
00000619 => x"0af49e63", |
00000620 => x"bb9ff0ef", |
00000621 => x"00051663", |
00000622 => x"00300513", |
00000623 => x"9adff0ef", |
00000624 => x"ffff1537", |
00000625 => x"ef050513", |
00000626 => x"01045493", |
00000627 => x"290000ef", |
00000628 => x"00148493", |
00000629 => x"00800937", |
00000630 => x"fff00993", |
00000631 => x"00010a37", |
00000632 => x"fff48493", |
00000633 => x"07349063", |
00000634 => x"4788d5b7", |
00000635 => x"afe58593", |
00000636 => x"00800537", |
00000637 => x"e79ff0ef", |
00000638 => x"00800537", |
00000639 => x"00040593", |
00000640 => x"00450513", |
00000641 => x"e69ff0ef", |
00000642 => x"ff002a03", |
00000643 => x"008009b7", |
00000644 => x"ffc47413", |
00000645 => x"00000493", |
00000646 => x"00000913", |
00000647 => x"00c98a93", |
00000648 => x"01548533", |
00000649 => x"009a07b3", |
00000650 => x"02849663", |
00000651 => x"00898513", |
00000652 => x"412005b3", |
00000653 => x"e39ff0ef", |
00000654 => x"ffff1537", |
00000655 => x"eb850513", |
00000656 => x"f05ff06f", |
00000657 => x"00090513", |
00000658 => x"e7dff0ef", |
00000659 => x"01490933", |
00000660 => x"f91ff06f", |
00000661 => x"0007a583", |
00000662 => x"00448493", |
00000663 => x"00b90933", |
00000664 => x"e0dff0ef", |
00000665 => x"fbdff06f", |
00000666 => x"01c12083", |
00000667 => x"01812403", |
00000668 => x"01412483", |
00000669 => x"01012903", |
00000670 => x"00c12983", |
00000671 => x"00812a03", |
00000672 => x"00412a83", |
00000673 => x"02010113", |
00000674 => x"00008067", |
00000675 => x"000047b7", |
00000676 => x"70078793", |
00000677 => x"f8f02623", |
00000678 => x"00008067", |
00000679 => x"fe010113", |
00000680 => x"00112e23", |
00000681 => x"00812c23", |
00000682 => x"00912a23", |
00000683 => x"01212823", |
00000684 => x"01312623", |
00000685 => x"01412423", |
00000686 => x"01512223", |
00000687 => x"f1302973", |
00000688 => x"00000a93", |
00000689 => x"00900993", |
00000690 => x"00300a13", |
00000691 => x"00400493", |
00000692 => x"41500433", |
00000693 => x"00341413", |
00000694 => x"01840413", |
00000695 => x"00895433", |
00000696 => x"0ff47413", |
00000697 => x"00000513", |
00000698 => x"0489ec63", |
00000699 => x"00050863", |
00000700 => x"03050513", |
00000701 => x"0ff57513", |
00000702 => x"144000ef", |
00000703 => x"03040513", |
00000704 => x"0ff57513", |
00000705 => x"138000ef", |
00000706 => x"014a8663", |
00000707 => x"02e00513", |
00000708 => x"12c000ef", |
00000709 => x"001a8a93", |
00000710 => x"fa9a9ce3", |
00000711 => x"01c12083", |
00000712 => x"01812403", |
00000713 => x"01412483", |
00000714 => x"01012903", |
00000715 => x"00c12983", |
00000716 => x"00812a03", |
00000717 => x"00412a83", |
00000718 => x"02010113", |
00000719 => x"00008067", |
00000720 => x"ff640413", |
00000721 => x"00150513", |
00000722 => x"0ff47413", |
00000723 => x"0ff57513", |
00000724 => x"f99ff06f", |
00000725 => x"fc000713", |
00000726 => x"00072783", |
00000727 => x"00179793", |
00000728 => x"0017d793", |
00000729 => x"00f72023", |
00000730 => x"00008067", |
00000731 => x"ff010113", |
00000732 => x"f9402783", |
00000733 => x"f9002703", |
00000734 => x"f9402683", |
00000735 => x"fed79ae3", |
00000736 => x"00e12023", |
00000737 => x"00f12223", |
00000738 => x"00012503", |
00000739 => x"00412583", |
00000740 => x"01010113", |
00000741 => x"00008067", |
00000742 => x"f9800693", |
00000743 => x"fff00613", |
00000744 => x"00c6a023", |
00000745 => x"00a6a023", |
00000746 => x"00b6a223", |
00000747 => x"00008067", |
00000748 => x"fa002023", |
00000749 => x"fe002683", |
00000750 => x"00151513", |
00000751 => x"00000713", |
00000752 => x"04a6f263", |
00000753 => x"000016b7", |
00000754 => x"00000793", |
00000755 => x"ffe68693", |
00000756 => x"04e6e463", |
00000757 => x"00167613", |
00000758 => x"0015f593", |
00000759 => x"01879793", |
00000760 => x"01e61613", |
00000761 => x"00c7e7b3", |
00000762 => x"01d59593", |
00000763 => x"00b7e7b3", |
00000764 => x"00e7e7b3", |
00000765 => x"10000737", |
00000766 => x"00e7e7b3", |
00000767 => x"faf02023", |
00000768 => x"00008067", |
00000769 => x"00170793", |
00000770 => x"01079713", |
00000771 => x"40a686b3", |
00000772 => x"01075713", |
00000773 => x"fadff06f", |
00000774 => x"ffe78513", |
00000775 => x"0fd57513", |
00000776 => x"00051a63", |
00000777 => x"00375713", |
00000778 => x"00178793", |
00000779 => x"0ff7f793", |
00000780 => x"fa1ff06f", |
00000781 => x"00175713", |
00000782 => x"ff1ff06f", |
00000783 => x"fa002783", |
00000784 => x"fe07cee3", |
00000785 => x"faa02223", |
00000786 => x"00008067", |
00000787 => x"fa402503", |
00000788 => x"fe055ee3", |
00000789 => x"0ff57513", |
00000613 => x"ed050513", |
00000614 => x"2d4000ef", |
00000615 => x"00040513", |
00000616 => x"a3dff0ef", |
00000617 => x"ffff1537", |
00000618 => x"edc50513", |
00000619 => x"2c0000ef", |
00000620 => x"00800537", |
00000621 => x"a29ff0ef", |
00000622 => x"ffff1537", |
00000623 => x"ef850513", |
00000624 => x"2ac000ef", |
00000625 => x"298000ef", |
00000626 => x"00050493", |
00000627 => x"280000ef", |
00000628 => x"07900793", |
00000629 => x"0af49e63", |
00000630 => x"bb1ff0ef", |
00000631 => x"00051663", |
00000632 => x"00300513", |
00000633 => x"9a5ff0ef", |
00000634 => x"ffff1537", |
00000635 => x"f0450513", |
00000636 => x"01045493", |
00000637 => x"278000ef", |
00000638 => x"00148493", |
00000639 => x"00800937", |
00000640 => x"fff00993", |
00000641 => x"00010a37", |
00000642 => x"fff48493", |
00000643 => x"07349063", |
00000644 => x"4788d5b7", |
00000645 => x"afe58593", |
00000646 => x"00800537", |
00000647 => x"e79ff0ef", |
00000648 => x"00800537", |
00000649 => x"00040593", |
00000650 => x"00450513", |
00000651 => x"e69ff0ef", |
00000652 => x"ff002a03", |
00000653 => x"008009b7", |
00000654 => x"ffc47413", |
00000655 => x"00000493", |
00000656 => x"00000913", |
00000657 => x"00c98a93", |
00000658 => x"01548533", |
00000659 => x"009a07b3", |
00000660 => x"02849663", |
00000661 => x"00898513", |
00000662 => x"412005b3", |
00000663 => x"e39ff0ef", |
00000664 => x"ffff1537", |
00000665 => x"ecc50513", |
00000666 => x"f05ff06f", |
00000667 => x"00090513", |
00000668 => x"e7dff0ef", |
00000669 => x"01490933", |
00000670 => x"f91ff06f", |
00000671 => x"0007a583", |
00000672 => x"00448493", |
00000673 => x"00b90933", |
00000674 => x"e0dff0ef", |
00000675 => x"fbdff06f", |
00000676 => x"01c12083", |
00000677 => x"01812403", |
00000678 => x"01412483", |
00000679 => x"01012903", |
00000680 => x"00c12983", |
00000681 => x"00812a03", |
00000682 => x"00412a83", |
00000683 => x"02010113", |
00000684 => x"00008067", |
00000685 => x"000047b7", |
00000686 => x"70078793", |
00000687 => x"f8f02623", |
00000688 => x"00008067", |
00000689 => x"fe010113", |
00000690 => x"00112e23", |
00000691 => x"00812c23", |
00000692 => x"00912a23", |
00000693 => x"01212823", |
00000694 => x"01312623", |
00000695 => x"01412423", |
00000696 => x"01512223", |
00000697 => x"f1302973", |
00000698 => x"00000a93", |
00000699 => x"00900993", |
00000700 => x"00300a13", |
00000701 => x"00400493", |
00000702 => x"41500433", |
00000703 => x"00341413", |
00000704 => x"01840413", |
00000705 => x"00895433", |
00000706 => x"0ff47413", |
00000707 => x"00000513", |
00000708 => x"0489ec63", |
00000709 => x"00050863", |
00000710 => x"03050513", |
00000711 => x"0ff57513", |
00000712 => x"12c000ef", |
00000713 => x"03040513", |
00000714 => x"0ff57513", |
00000715 => x"120000ef", |
00000716 => x"014a8663", |
00000717 => x"02e00513", |
00000718 => x"114000ef", |
00000719 => x"001a8a93", |
00000720 => x"fa9a9ce3", |
00000721 => x"01c12083", |
00000722 => x"01812403", |
00000723 => x"01412483", |
00000724 => x"01012903", |
00000725 => x"00c12983", |
00000726 => x"00812a03", |
00000727 => x"00412a83", |
00000728 => x"02010113", |
00000729 => x"00008067", |
00000730 => x"ff640413", |
00000731 => x"00150513", |
00000732 => x"0ff47413", |
00000733 => x"0ff57513", |
00000734 => x"f99ff06f", |
00000735 => x"ff010113", |
00000736 => x"f9402783", |
00000737 => x"f9002703", |
00000738 => x"f9402683", |
00000739 => x"fed79ae3", |
00000740 => x"00e12023", |
00000741 => x"00f12223", |
00000742 => x"00012503", |
00000743 => x"00412583", |
00000744 => x"01010113", |
00000745 => x"00008067", |
00000746 => x"f9800693", |
00000747 => x"fff00613", |
00000748 => x"00c6a023", |
00000749 => x"00a6a023", |
00000750 => x"00b6a223", |
00000751 => x"00008067", |
00000752 => x"fa002023", |
00000753 => x"fe002683", |
00000754 => x"00151513", |
00000755 => x"00000713", |
00000756 => x"04a6f263", |
00000757 => x"000016b7", |
00000758 => x"00000793", |
00000759 => x"ffe68693", |
00000760 => x"04e6e463", |
00000761 => x"00167613", |
00000762 => x"0015f593", |
00000763 => x"01879793", |
00000764 => x"01e61613", |
00000765 => x"00c7e7b3", |
00000766 => x"01d59593", |
00000767 => x"00b7e7b3", |
00000768 => x"00e7e7b3", |
00000769 => x"10000737", |
00000770 => x"00e7e7b3", |
00000771 => x"faf02023", |
00000772 => x"00008067", |
00000773 => x"00170793", |
00000774 => x"01079713", |
00000775 => x"40a686b3", |
00000776 => x"01075713", |
00000777 => x"fadff06f", |
00000778 => x"ffe78513", |
00000779 => x"0fd57513", |
00000780 => x"00051a63", |
00000781 => x"00375713", |
00000782 => x"00178793", |
00000783 => x"0ff7f793", |
00000784 => x"fa1ff06f", |
00000785 => x"00175713", |
00000786 => x"ff1ff06f", |
00000787 => x"fa002783", |
00000788 => x"fe07cee3", |
00000789 => x"faa02223", |
00000790 => x"00008067", |
00000791 => x"ff010113", |
00000792 => x"00812423", |
00000793 => x"01212023", |
00000794 => x"00112623", |
00000795 => x"00912223", |
00000796 => x"00050413", |
00000797 => x"00a00913", |
00000798 => x"00044483", |
00000799 => x"00140413", |
00000800 => x"00049e63", |
00000801 => x"00c12083", |
00000802 => x"00812403", |
00000803 => x"00412483", |
00000804 => x"00012903", |
00000805 => x"01010113", |
00000806 => x"00008067", |
00000807 => x"01249663", |
00000808 => x"00d00513", |
00000809 => x"f99ff0ef", |
00000810 => x"00048513", |
00000811 => x"f91ff0ef", |
00000812 => x"fc9ff06f", |
00000813 => x"00757513", |
00000814 => x"00177793", |
00000815 => x"01079793", |
00000816 => x"0036f693", |
00000817 => x"00a51513", |
00000818 => x"00f56533", |
00000819 => x"00167613", |
00000820 => x"00e69793", |
00000821 => x"0015f593", |
00000822 => x"00f567b3", |
00000823 => x"00d61613", |
00000824 => x"00c7e7b3", |
00000825 => x"00959593", |
00000826 => x"fa800813", |
00000827 => x"00b7e7b3", |
00000828 => x"00082023", |
00000829 => x"1007e793", |
00000830 => x"00f82023", |
00000831 => x"00008067", |
00000832 => x"fa800713", |
00000833 => x"00072783", |
00000834 => x"eff7f793", |
00000835 => x"00f72023", |
00000836 => x"00008067", |
00000837 => x"fa800713", |
00000838 => x"00072683", |
00000839 => x"00757793", |
00000840 => x"00100513", |
00000841 => x"00f51533", |
00000842 => x"00d56533", |
00000843 => x"00a72023", |
00000844 => x"00008067", |
00000845 => x"fa800713", |
00000846 => x"00072683", |
00000847 => x"00757513", |
00000848 => x"00100793", |
00000849 => x"00a797b3", |
00000850 => x"fff7c793", |
00000851 => x"00d7f7b3", |
00000852 => x"00f72023", |
00000853 => x"00008067", |
00000854 => x"faa02623", |
00000855 => x"fa802783", |
00000856 => x"fe07cee3", |
00000857 => x"fac02503", |
00000858 => x"00008067", |
00000859 => x"f8400713", |
00000860 => x"00072683", |
00000861 => x"00f57793", |
00000862 => x"00100513", |
00000863 => x"00f51533", |
00000864 => x"00d54533", |
00000865 => x"00a72023", |
00000866 => x"00008067", |
00000867 => x"f8a02223", |
00000868 => x"00008067", |
00000869 => x"fb800713", |
00000870 => x"00072783", |
00000871 => x"ffe7f793", |
00000872 => x"00f72023", |
00000873 => x"00008067", |
00000874 => x"fb000713", |
00000875 => x"00072783", |
00000876 => x"ff77f793", |
00000877 => x"00f72023", |
00000878 => x"00008067", |
00000879 => x"f8800713", |
00000880 => x"00072783", |
00000881 => x"fef7f793", |
00000882 => x"00f72023", |
00000883 => x"00008067", |
00000884 => x"69617641", |
00000885 => x"6c62616c", |
00000886 => x"4d432065", |
00000887 => x"0a3a7344", |
00000888 => x"203a6820", |
00000889 => x"706c6548", |
00000890 => x"3a72200a", |
00000891 => x"73655220", |
00000892 => x"74726174", |
00000893 => x"3a75200a", |
00000894 => x"6c705520", |
00000895 => x"0a64616f", |
00000896 => x"203a7320", |
00000897 => x"726f7453", |
00000898 => x"6f742065", |
00000899 => x"616c6620", |
00000900 => x"200a6873", |
00000901 => x"4c203a6c", |
00000902 => x"2064616f", |
00000903 => x"6d6f7266", |
00000791 => x"fa402503", |
00000792 => x"fe055ee3", |
00000793 => x"0ff57513", |
00000794 => x"00008067", |
00000795 => x"ff010113", |
00000796 => x"00812423", |
00000797 => x"01212023", |
00000798 => x"00112623", |
00000799 => x"00912223", |
00000800 => x"00050413", |
00000801 => x"00a00913", |
00000802 => x"00044483", |
00000803 => x"00140413", |
00000804 => x"00049e63", |
00000805 => x"00c12083", |
00000806 => x"00812403", |
00000807 => x"00412483", |
00000808 => x"00012903", |
00000809 => x"01010113", |
00000810 => x"00008067", |
00000811 => x"01249663", |
00000812 => x"00d00513", |
00000813 => x"f99ff0ef", |
00000814 => x"00048513", |
00000815 => x"f91ff0ef", |
00000816 => x"fc9ff06f", |
00000817 => x"00757513", |
00000818 => x"00177793", |
00000819 => x"01079793", |
00000820 => x"0036f693", |
00000821 => x"00a51513", |
00000822 => x"00f56533", |
00000823 => x"00167613", |
00000824 => x"00e69793", |
00000825 => x"0015f593", |
00000826 => x"00f567b3", |
00000827 => x"00d61613", |
00000828 => x"00c7e7b3", |
00000829 => x"00959593", |
00000830 => x"fa800813", |
00000831 => x"00b7e7b3", |
00000832 => x"00082023", |
00000833 => x"1007e793", |
00000834 => x"00f82023", |
00000835 => x"00008067", |
00000836 => x"fa800713", |
00000837 => x"00072783", |
00000838 => x"eff7f793", |
00000839 => x"00f72023", |
00000840 => x"00008067", |
00000841 => x"fa800713", |
00000842 => x"00072683", |
00000843 => x"00757793", |
00000844 => x"00100513", |
00000845 => x"00f51533", |
00000846 => x"00d56533", |
00000847 => x"00a72023", |
00000848 => x"00008067", |
00000849 => x"fa800713", |
00000850 => x"00072683", |
00000851 => x"00757513", |
00000852 => x"00100793", |
00000853 => x"00a797b3", |
00000854 => x"fff7c793", |
00000855 => x"00d7f7b3", |
00000856 => x"00f72023", |
00000857 => x"00008067", |
00000858 => x"faa02623", |
00000859 => x"fa802783", |
00000860 => x"fe07cee3", |
00000861 => x"fac02503", |
00000862 => x"00008067", |
00000863 => x"f8400713", |
00000864 => x"00072683", |
00000865 => x"00f57793", |
00000866 => x"00100513", |
00000867 => x"00f51533", |
00000868 => x"00d54533", |
00000869 => x"00a72023", |
00000870 => x"00008067", |
00000871 => x"f8a02223", |
00000872 => x"00008067", |
00000873 => x"fb800713", |
00000874 => x"00072783", |
00000875 => x"ffe7f793", |
00000876 => x"00f72023", |
00000877 => x"00008067", |
00000878 => x"fb000713", |
00000879 => x"00072783", |
00000880 => x"ff77f793", |
00000881 => x"00f72023", |
00000882 => x"00008067", |
00000883 => x"fc000713", |
00000884 => x"00072783", |
00000885 => x"00179793", |
00000886 => x"0017d793", |
00000887 => x"00f72023", |
00000888 => x"00008067", |
00000889 => x"69617641", |
00000890 => x"6c62616c", |
00000891 => x"4d432065", |
00000892 => x"0a3a7344", |
00000893 => x"203a6820", |
00000894 => x"706c6548", |
00000895 => x"3a72200a", |
00000896 => x"73655220", |
00000897 => x"74726174", |
00000898 => x"3a75200a", |
00000899 => x"6c705520", |
00000900 => x"0a64616f", |
00000901 => x"203a7320", |
00000902 => x"726f7453", |
00000903 => x"6f742065", |
00000904 => x"616c6620", |
00000905 => x"200a6873", |
00000906 => x"45203a65", |
00000907 => x"75636578", |
00000908 => x"00006574", |
00000909 => x"65206f4e", |
00000910 => x"75636578", |
00000911 => x"6c626174", |
00000912 => x"76612065", |
00000913 => x"616c6961", |
00000914 => x"2e656c62", |
00000915 => x"00000000", |
00000916 => x"746f6f42", |
00000917 => x"2e676e69", |
00000918 => x"0a0a2e2e", |
00000919 => x"00000000", |
00000920 => x"52450a07", |
00000921 => x"00005f52", |
00000922 => x"6e6b6e75", |
00000923 => x"006e776f", |
00000924 => x"00007830", |
00000925 => x"58450a0a", |
00000926 => x"54504543", |
00000927 => x"3a4e4f49", |
00000928 => x"00000020", |
00000929 => x"30204020", |
00000930 => x"00000078", |
00000931 => x"69617741", |
00000932 => x"676e6974", |
00000933 => x"6f656e20", |
00000934 => x"32337672", |
00000935 => x"6578655f", |
00000936 => x"6e69622e", |
00000937 => x"202e2e2e", |
00000938 => x"00000000", |
00000939 => x"64616f4c", |
00000940 => x"2e676e69", |
00000941 => x"00202e2e", |
00000942 => x"00004b4f", |
00000943 => x"74697257", |
00000944 => x"78302065", |
00000945 => x"00000000", |
00000946 => x"74796220", |
00000947 => x"74207365", |
00000948 => x"5053206f", |
00000949 => x"6c662049", |
00000950 => x"20687361", |
00000951 => x"78302040", |
00000952 => x"00000000", |
00000953 => x"7928203f", |
00000954 => x"20296e2f", |
00000955 => x"00000000", |
00000956 => x"616c460a", |
00000957 => x"6e696873", |
00000958 => x"2e2e2e67", |
00000959 => x"00000020", |
00000960 => x"0a0a0a0a", |
00000961 => x"4e203c3c", |
00000962 => x"56524f45", |
00000963 => x"42203233", |
00000964 => x"6c746f6f", |
00000965 => x"6564616f", |
00000966 => x"3e3e2072", |
00000967 => x"4c420a0a", |
00000968 => x"203a5644", |
00000969 => x"206c754a", |
00000970 => x"32203132", |
00000971 => x"0a303230", |
00000972 => x"3a565748", |
00000973 => x"00002020", |
00000974 => x"4b4c430a", |
00000975 => x"0020203a", |
00000976 => x"0a7a4820", |
00000977 => x"52455355", |
00000978 => x"0000203a", |
00000979 => x"53494d0a", |
00000980 => x"00203a41", |
00000981 => x"4e4f430a", |
00000982 => x"00203a46", |
00000983 => x"454d490a", |
00000984 => x"00203a4d", |
00000985 => x"74796220", |
00000986 => x"40207365", |
00000987 => x"00000020", |
00000988 => x"454d440a", |
00000906 => x"4c203a6c", |
00000907 => x"2064616f", |
00000908 => x"6d6f7266", |
00000909 => x"616c6620", |
00000910 => x"200a6873", |
00000911 => x"45203a65", |
00000912 => x"75636578", |
00000913 => x"00006574", |
00000914 => x"65206f4e", |
00000915 => x"75636578", |
00000916 => x"6c626174", |
00000917 => x"76612065", |
00000918 => x"616c6961", |
00000919 => x"2e656c62", |
00000920 => x"00000000", |
00000921 => x"746f6f42", |
00000922 => x"2e676e69", |
00000923 => x"0a0a2e2e", |
00000924 => x"00000000", |
00000925 => x"52450a07", |
00000926 => x"00005f52", |
00000927 => x"6e6b6e75", |
00000928 => x"006e776f", |
00000929 => x"00007830", |
00000930 => x"58450a0a", |
00000931 => x"54504543", |
00000932 => x"3a4e4f49", |
00000933 => x"00000020", |
00000934 => x"30204020", |
00000935 => x"00000078", |
00000936 => x"69617741", |
00000937 => x"676e6974", |
00000938 => x"6f656e20", |
00000939 => x"32337672", |
00000940 => x"6578655f", |
00000941 => x"6e69622e", |
00000942 => x"202e2e2e", |
00000943 => x"00000000", |
00000944 => x"64616f4c", |
00000945 => x"2e676e69", |
00000946 => x"00202e2e", |
00000947 => x"00004b4f", |
00000948 => x"74697257", |
00000949 => x"78302065", |
00000950 => x"00000000", |
00000951 => x"74796220", |
00000952 => x"74207365", |
00000953 => x"5053206f", |
00000954 => x"6c662049", |
00000955 => x"20687361", |
00000956 => x"78302040", |
00000957 => x"00000000", |
00000958 => x"7928203f", |
00000959 => x"20296e2f", |
00000960 => x"00000000", |
00000961 => x"616c460a", |
00000962 => x"6e696873", |
00000963 => x"2e2e2e67", |
00000964 => x"00000020", |
00000965 => x"0a0a0a0a", |
00000966 => x"4e203c3c", |
00000967 => x"56524f45", |
00000968 => x"42203233", |
00000969 => x"6c746f6f", |
00000970 => x"6564616f", |
00000971 => x"3e3e2072", |
00000972 => x"4c420a0a", |
00000973 => x"203a5644", |
00000974 => x"206c754a", |
00000975 => x"32203532", |
00000976 => x"0a303230", |
00000977 => x"3a565748", |
00000978 => x"00002020", |
00000979 => x"4b4c430a", |
00000980 => x"0020203a", |
00000981 => x"0a7a4820", |
00000982 => x"52455355", |
00000983 => x"0000203a", |
00000984 => x"53494d0a", |
00000985 => x"00203a41", |
00000986 => x"4e4f430a", |
00000987 => x"00203a46", |
00000988 => x"454d490a", |
00000989 => x"00203a4d", |
00000990 => x"75410a0a", |
00000991 => x"6f626f74", |
00000992 => x"6920746f", |
00000993 => x"7338206e", |
00000994 => x"7250202e", |
00000995 => x"20737365", |
00000996 => x"2079656b", |
00000997 => x"61206f74", |
00000998 => x"74726f62", |
00000999 => x"00000a2e", |
00001000 => x"0000000a", |
00001001 => x"726f6241", |
00001002 => x"2e646574", |
00001003 => x"00000a0a", |
00001004 => x"444d430a", |
00001005 => x"00203e3a", |
00001006 => x"53207962", |
00001007 => x"68706574", |
00001008 => x"4e206e61", |
00001009 => x"69746c6f", |
00001010 => x"0000676e", |
00001011 => x"61766e49", |
00001012 => x"2064696c", |
00001013 => x"00444d43", |
00001014 => x"33323130", |
00001015 => x"37363534", |
00001016 => x"42413938", |
00001017 => x"46454443", |
00000990 => x"74796220", |
00000991 => x"40207365", |
00000992 => x"00000020", |
00000993 => x"454d440a", |
00000994 => x"00203a4d", |
00000995 => x"75410a0a", |
00000996 => x"6f626f74", |
00000997 => x"6920746f", |
00000998 => x"7338206e", |
00000999 => x"7250202e", |
00001000 => x"20737365", |
00001001 => x"2079656b", |
00001002 => x"61206f74", |
00001003 => x"74726f62", |
00001004 => x"00000a2e", |
00001005 => x"0000000a", |
00001006 => x"726f6241", |
00001007 => x"2e646574", |
00001008 => x"00000a0a", |
00001009 => x"444d430a", |
00001010 => x"00203e3a", |
00001011 => x"53207962", |
00001012 => x"68706574", |
00001013 => x"4e206e61", |
00001014 => x"69746c6f", |
00001015 => x"0000676e", |
00001016 => x"61766e49", |
00001017 => x"2064696c", |
00001018 => x"00444d43", |
00001019 => x"33323130", |
00001020 => x"37363534", |
00001021 => x"42413938", |
00001022 => x"46454443", |
others => x"00000000" |
); |
|
/neorv32/trunk/rtl/core/neorv32_cpu.vhd
52,8 → 52,8
generic ( |
-- General -- |
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])? |
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id |
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address |
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id |
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
60,41 → 60,43
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.? |
-- Memory configuration: External memory interface -- |
MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout |
-- Bus Interface -- |
BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout |
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
clk_i : in std_ulogic := '0'; -- global clock, rising edge |
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async |
-- instruction bus interface -- |
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data |
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
i_bus_we_o : out std_ulogic; -- write enable |
i_bus_re_o : out std_ulogic; -- read enable |
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
i_bus_err_i : in std_ulogic; -- bus transfer error |
i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge |
i_bus_err_i : in std_ulogic := '0'; -- bus transfer error |
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation |
-- data bus interface -- |
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data |
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
d_bus_we_o : out std_ulogic; -- write enable |
d_bus_re_o : out std_ulogic; -- read enable |
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
d_bus_err_i : in std_ulogic; -- bus transfer error |
d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge |
d_bus_err_i : in std_ulogic := '0'; -- bus transfer error |
d_bus_fence_o : out std_ulogic; -- executed FENCE operation |
-- system time input from MTIME -- |
time_i : in std_ulogic_vector(63 downto 0); -- current system time |
-- external interrupts -- |
msw_irq_i : in std_ulogic; -- software interrupt |
clic_irq_i : in std_ulogic; -- CLIC interrupt request |
mtime_irq_i : in std_ulogic -- machine timer interrupt |
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time |
-- interrupts (risc-v compliant) -- |
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt |
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt |
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt |
-- fast interrupts (custom) -- |
firq_i : in std_ulogic_vector(3 downto 0) := (others => '0') |
); |
end neorv32_cpu; |
|
166,10 → 168,12
-- csr interface -- |
csr_wdata_i => alu_res, -- CSR write data |
csr_rdata_o => csr_rdata, -- CSR read data |
-- external interrupt -- |
msw_irq_i => msw_irq_i, -- software interrupt |
clic_irq_i => clic_irq_i, -- CLIC interrupt request |
-- interrupts (risc-v compliant) -- |
msw_irq_i => msw_irq_i, -- machine software interrupt |
mext_irq_i => mext_irq_i, -- machine external interrupt |
mtime_irq_i => mtime_irq_i, -- machine timer interrupt |
-- fast interrupts (custom) -- |
firq_i => firq_i, |
-- system time input from MTIME -- |
time_i => time_i, -- current system time |
-- bus access exceptions -- |
272,7 → 276,7
neorv32_cpu_bus_inst: neorv32_cpu_bus |
generic map ( |
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? |
MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout |
BUS_TIMEOUT => BUS_TIMEOUT -- cycles after which a valid bus access will timeout |
) |
port map ( |
-- global control -- |
/neorv32/trunk/rtl/core/neorv32_cpu_bus.vhd
44,7 → 44,7
entity neorv32_cpu_bus is |
generic ( |
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension? |
MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout |
BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout |
); |
port ( |
-- global control -- |
113,7 → 113,7
wr_req : std_ulogic; -- write access in progress |
err_align : std_ulogic; -- alignment error |
err_bus : std_ulogic; -- bus access error |
timeout : std_ulogic_vector(index_size_f(MEM_EXT_TIMEOUT)-1 downto 0); |
timeout : std_ulogic_vector(index_size_f(BUS_TIMEOUT)-1 downto 0); |
end record; |
signal i_arbiter, d_arbiter : bus_arbiter_t; |
|
271,7 → 271,7
i_arbiter.rd_req <= ctrl_i(ctrl_bus_if_c); |
i_arbiter.err_align <= i_misaligned; |
i_arbiter.err_bus <= '0'; |
i_arbiter.timeout <= std_ulogic_vector(to_unsigned(MEM_EXT_TIMEOUT, index_size_f(MEM_EXT_TIMEOUT))); |
i_arbiter.timeout <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT))); |
else -- in progress |
i_arbiter.timeout <= std_ulogic_vector(unsigned(i_arbiter.timeout) - 1); |
i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned) and (not ctrl_i(ctrl_bus_ierr_ack_c)); |
326,7 → 326,7
d_arbiter.rd_req <= ctrl_i(ctrl_bus_rd_c); |
d_arbiter.err_align <= d_misaligned; |
d_arbiter.err_bus <= '0'; |
d_arbiter.timeout <= std_ulogic_vector(to_unsigned(MEM_EXT_TIMEOUT, index_size_f(MEM_EXT_TIMEOUT))); |
d_arbiter.timeout <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT))); |
else -- in progress |
d_arbiter.timeout <= std_ulogic_vector(unsigned(d_arbiter.timeout) - 1); |
d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c)); |
/neorv32/trunk/rtl/core/neorv32_cpu_control.vhd
77,10 → 77,12
-- csr data interface -- |
csr_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR write data |
csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data |
-- external interrupt -- |
msw_irq_i : in std_ulogic; -- software interrupt |
clic_irq_i : in std_ulogic; -- CLIC interrupt request |
-- interrupts (risc-v compliant) -- |
msw_irq_i : in std_ulogic; -- machine software interrupt |
mext_irq_i : in std_ulogic; -- machine external interrupt |
mtime_irq_i : in std_ulogic; -- machine timer interrupt |
-- fast interrupts (custom) -- |
firq_i : in std_ulogic_vector(3 downto 0); |
-- system time input from MTIME -- |
time_i : in std_ulogic_vector(63 downto 0); -- current system time |
-- bus access exceptions -- |
168,8 → 170,8
exc_ack : std_ulogic; -- acknowledge all exceptions |
irq_ack : std_ulogic_vector(interrupt_width_c-1 downto 0); -- acknowledge specific interrupt |
irq_ack_nxt : std_ulogic_vector(interrupt_width_c-1 downto 0); |
cause : std_ulogic_vector(4 downto 0); -- trap ID (for "mcause"), only for hw |
cause_nxt : std_ulogic_vector(4 downto 0); |
cause : std_ulogic_vector(5 downto 0); -- trap ID (for "mcause"), only for hw |
cause_nxt : std_ulogic_vector(5 downto 0); |
-- |
env_start : std_ulogic; -- start trap handler env |
env_start_ack : std_ulogic; -- start of trap handler acknowledged |
199,9 → 201,10
mstatus_mpie : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/-) |
mie_msie : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W) |
mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W) |
mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W) |
mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W |
mie_firqe : std_ulogic_vector(3 downto 0); -- mie.firq*e: fast interrupt enabled (R/W) |
mepc : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W) |
mcause : std_ulogic_vector(data_width_c-1 downto 0); -- mcause: machine trap cause (R/W) |
mcause : std_ulogic_vector(data_width_c-1 downto 0); -- mcause: machine trap cause (R/-) |
mtvec : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W), bit 1:0 == 00 |
mtval : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or isntruction (R/W) |
mscratch : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W) |
633,17 → 636,14
trap_ctrl.instr_ma <= ipb.rdata(33); -- misaligned instruction fetch address |
trap_ctrl.instr_be <= ipb.rdata(34); -- bus access fault druing instrucion fetch |
illegal_compressed <= ipb.rdata(35); -- invalid decompressed instruction |
if (trap_ctrl.env_start = '1') or ((ipb.rdata(33) or ipb.rdata(34) or ipb.rdata(35)) = '1') then -- exception/interrupt? |
execute_engine.is_ci_nxt <= ipb.rdata(32); -- flag to indicate this is a compressed instruction beeing executed |
execute_engine.i_reg_nxt <= ipb.rdata(31 downto 0); |
execute_engine.pc_nxt <= ipb.raddr; -- the PC according to the current instruction |
-- ipb.rdata(35) is not immediately checked here! |
if (execute_engine.sleep = '1') or (trap_ctrl.env_start = '1') or ((ipb.rdata(33) or ipb.rdata(34)) = '1') then |
execute_engine.state_nxt <= TRAP; |
else |
execute_engine.is_ci_nxt <= ipb.rdata(32); -- flag to indicate this is a compressed instruction beeing executed |
execute_engine.i_reg_nxt <= ipb.rdata(31 downto 0); |
execute_engine.pc_nxt <= ipb.raddr; -- the PC according to the current instruction |
if (execute_engine.sleep = '1') then |
execute_engine.state_nxt <= TRAP; |
else |
execute_engine.state_nxt <= EXECUTE; |
end if; |
execute_engine.state_nxt <= EXECUTE; |
end if; |
end if; |
|
1074,10 → 1074,15
trap_ctrl.exc_buf(exception_m_envcall_c) <= (trap_ctrl.exc_buf(exception_m_envcall_c) or trap_ctrl.env_call) and (not trap_ctrl.exc_ack); |
trap_ctrl.exc_buf(exception_break_c) <= (trap_ctrl.exc_buf(exception_break_c) or trap_ctrl.break_point) and (not trap_ctrl.exc_ack); |
trap_ctrl.exc_buf(exception_iillegal_c) <= (trap_ctrl.exc_buf(exception_iillegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.exc_ack); |
-- interrupt buffer: machine software/external/timer interrupt |
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and (trap_ctrl.irq_buf(interrupt_msw_irq_c) or msw_irq_i) and (not trap_ctrl.irq_ack(interrupt_msw_irq_c)); |
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and (trap_ctrl.irq_buf(interrupt_mext_irq_c) or clic_irq_i) and (not trap_ctrl.irq_ack(interrupt_mext_irq_c)); |
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and (trap_ctrl.irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not trap_ctrl.irq_ack(interrupt_mtime_irq_c)); |
-- interrupt buffer (RISC-V compliant): machine software/external/timer interrupt |
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and (trap_ctrl.irq_buf(interrupt_msw_irq_c) or msw_irq_i) and (not trap_ctrl.irq_ack(interrupt_msw_irq_c)); |
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and (trap_ctrl.irq_buf(interrupt_mext_irq_c) or mext_irq_i) and (not trap_ctrl.irq_ack(interrupt_mext_irq_c)); |
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and (trap_ctrl.irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not trap_ctrl.irq_ack(interrupt_mtime_irq_c)); |
-- interrupt buffer (custom): fast interrupts |
trap_ctrl.irq_buf(interrupt_firq_0_c) <= csr.mie_firqe(0) and (trap_ctrl.irq_buf(interrupt_firq_0_c) or firq_i(0)) and (not trap_ctrl.irq_ack(interrupt_firq_0_c)); |
trap_ctrl.irq_buf(interrupt_firq_1_c) <= csr.mie_firqe(1) and (trap_ctrl.irq_buf(interrupt_firq_1_c) or firq_i(1)) and (not trap_ctrl.irq_ack(interrupt_firq_1_c)); |
trap_ctrl.irq_buf(interrupt_firq_2_c) <= csr.mie_firqe(2) and (trap_ctrl.irq_buf(interrupt_firq_2_c) or firq_i(2)) and (not trap_ctrl.irq_ack(interrupt_firq_2_c)); |
trap_ctrl.irq_buf(interrupt_firq_3_c) <= csr.mie_firqe(3) and (trap_ctrl.irq_buf(interrupt_firq_3_c) or firq_i(3)) and (not trap_ctrl.irq_ack(interrupt_firq_3_c)); |
|
-- trap control -- |
if (trap_ctrl.env_start = '0') then -- no started trap handler |
1131,6 → 1136,27
trap_ctrl.irq_ack_nxt(interrupt_msw_irq_c) <= '1'; |
|
|
-- interrupt: 1.16 fast interrupt channel 0 -- |
elsif (trap_ctrl.irq_buf(interrupt_firq_0_c) = '1') then |
trap_ctrl.cause_nxt <= trap_firq0_c; |
trap_ctrl.irq_ack_nxt(interrupt_firq_0_c) <= '1'; |
|
-- interrupt: 1.17 fast interrupt channel 1 -- |
elsif (trap_ctrl.irq_buf(interrupt_firq_1_c) = '1') then |
trap_ctrl.cause_nxt <= trap_firq1_c; |
trap_ctrl.irq_ack_nxt(interrupt_firq_1_c) <= '1'; |
|
-- interrupt: 1.18 fast interrupt channel 2 -- |
elsif (trap_ctrl.irq_buf(interrupt_firq_2_c) = '1') then |
trap_ctrl.cause_nxt <= trap_firq2_c; |
trap_ctrl.irq_ack_nxt(interrupt_firq_2_c) <= '1'; |
|
-- interrupt: 1.19 fast interrupt channel 3 -- |
elsif (trap_ctrl.irq_buf(interrupt_firq_3_c) = '1') then |
trap_ctrl.cause_nxt <= trap_firq3_c; |
trap_ctrl.irq_ack_nxt(interrupt_firq_3_c) <= '1'; |
|
|
-- the following traps are caused by synchronous exceptions |
-- here we do not need a specific acknowledge mask since only one exception (the one |
-- with highest priority) can trigger at once |
1150,7 → 1176,7
|
-- trap/fault: 0.11 environment call from M-mode -- |
elsif (trap_ctrl.exc_buf(exception_m_envcall_c) = '1') then |
trap_ctrl.cause_nxt <= trap_env_c; |
trap_ctrl.cause_nxt <= trap_menv_c; |
|
-- trap/fault: 0.3 breakpoint -- |
elsif (trap_ctrl.exc_buf(exception_break_c) = '1') then |
1198,6 → 1224,7
csr.mie_msie <= '0'; |
csr.mie_meie <= '0'; |
csr.mie_mtie <= '0'; |
csr.mie_firqe <= (others => '0'); |
csr.mtvec <= (others => '0'); |
csr.mscratch <= (others => '0'); |
csr.mepc <= (others => '0'); |
1221,9 → 1248,14
csr.mstatus_mie <= csr_wdata_i(03); |
csr.mstatus_mpie <= csr_wdata_i(07); |
when x"4" => -- R/W: mie - machine interrupt-enable register |
csr.mie_msie <= csr_wdata_i(03); -- SW IRQ enable |
csr.mie_mtie <= csr_wdata_i(07); -- TIMER IRQ enable |
csr.mie_meie <= csr_wdata_i(11); -- EXT IRQ enable |
csr.mie_msie <= csr_wdata_i(03); -- machine SW IRQ enable |
csr.mie_mtie <= csr_wdata_i(07); -- machine TIMER IRQ enable |
csr.mie_meie <= csr_wdata_i(11); -- machine EXT IRQ enable |
-- |
csr.mie_firqe(0) <= csr_wdata_i(16); -- fast interrupt channel 0 |
csr.mie_firqe(1) <= csr_wdata_i(17); -- fast interrupt channel 1 |
csr.mie_firqe(2) <= csr_wdata_i(18); -- fast interrupt channel 2 |
csr.mie_firqe(3) <= csr_wdata_i(19); -- fast interrupt channel 3 |
when x"5" => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions) |
csr.mtvec <= csr_wdata_i(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0 |
when others => |
1237,8 → 1269,6
csr.mscratch <= csr_wdata_i; |
when x"1" => -- R/W: mepc - machine exception program counter |
csr.mepc <= csr_wdata_i(data_width_c-1 downto 1) & '0'; |
when x"2" => -- R/W: mcause - machine trap cause |
csr.mcause <= csr_wdata_i; |
when x"3" => -- R/W: mtval - machine bad address or instruction |
csr.mtval <= csr_wdata_i; |
when others => |
1250,20 → 1280,20
-- automatic update by hardware -- |
else |
|
-- machine exception PC & trap value register -- |
-- machine exception PC & machine trap value register -- |
if (trap_ctrl.env_start_ack = '1') then -- trap handler starting? |
csr.mcause <= trap_ctrl.cause(4) & "000" & x"000000" & trap_ctrl.cause(3 downto 0); |
if (trap_ctrl.cause(4) = '1') then -- for INTERRUPTS only (is mcause(31)) |
csr.mcause <= trap_ctrl.cause(trap_ctrl.cause'left) & "000" & x"00000" & "000" & trap_ctrl.cause(4 downto 0); |
if (trap_ctrl.cause(trap_ctrl.cause'left) = '1') then -- for INTERRUPTS only (is mcause(31)) |
csr.mepc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction |
csr.mtval <= (others => '0'); -- mtval is zero for interrupts |
else -- for EXCEPTIONS (according to their priority) |
csr.mepc <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction |
if (trap_ctrl.cause(3 downto 0) = trap_iba_c(3 downto 0)) or -- instr access error OR |
(trap_ctrl.cause(3 downto 0) = trap_ima_c(3 downto 0)) or -- misaligned instruction OR |
(trap_ctrl.cause(3 downto 0) = trap_brk_c(3 downto 0)) or -- breakpoint OR |
(trap_ctrl.cause(3 downto 0) = trap_env_c(3 downto 0)) then -- env call OR |
if (trap_ctrl.cause(4 downto 0) = trap_iba_c(4 downto 0)) or -- instr access error OR |
(trap_ctrl.cause(4 downto 0) = trap_ima_c(4 downto 0)) or -- misaligned instruction OR |
(trap_ctrl.cause(4 downto 0) = trap_brk_c(4 downto 0)) or -- breakpoint OR |
(trap_ctrl.cause(4 downto 0) = trap_menv_c(4 downto 0)) then -- env call OR |
csr.mtval <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- address of faulting instruction |
elsif (trap_ctrl.cause(3 downto 0) = trap_iil_c(3 downto 0)) then -- illegal instruction |
elsif (trap_ctrl.cause(4 downto 0) = trap_iil_c(4 downto 0)) then -- illegal instruction |
csr.mtval <= execute_engine.i_reg; -- faulting instruction itself |
else -- load/store misalignments/access errors |
csr.mtval <= mar_i; -- faulting data access address |
1307,13 → 1337,19
csr_rdata_o(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension |
csr_rdata_o(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E) |
csr_rdata_o(12) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_M); -- M CPU extension |
csr_rdata_o(23) <= '1'; -- X CPU extension (non-std extensions) |
csr_rdata_o(25) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr) and bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Z CPU extension |
csr_rdata_o(30) <= '1'; -- 32-bit architecture (MXL lo) |
csr_rdata_o(31) <= '0'; -- 32-bit architecture (MXL hi) |
when x"304" => -- R/W: mie - machine interrupt-enable register |
csr_rdata_o(03) <= csr.mie_msie; -- software IRQ enable |
csr_rdata_o(07) <= csr.mie_mtie; -- timer IRQ enable |
csr_rdata_o(11) <= csr.mie_meie; -- external IRQ enable |
csr_rdata_o(03) <= csr.mie_msie; -- machine software IRQ enable |
csr_rdata_o(07) <= csr.mie_mtie; -- machine timer IRQ enable |
csr_rdata_o(11) <= csr.mie_meie; -- machine external IRQ enable |
-- |
csr_rdata_o(16) <= csr.mie_firqe(0); -- fast interrupt channel 0 |
csr_rdata_o(17) <= csr.mie_firqe(1); -- fast interrupt channel 1 |
csr_rdata_o(18) <= csr.mie_firqe(2); -- fast interrupt channel 2 |
csr_rdata_o(19) <= csr.mie_firqe(3); -- fast interrupt channel 3 |
when x"305" => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions) |
csr_rdata_o <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0 |
|
1322,7 → 1358,7
csr_rdata_o <= csr.mscratch; |
when x"341" => -- R/W: mepc - machine exception program counter |
csr_rdata_o <= csr.mepc(data_width_c-1 downto 1) & '0'; |
when x"342" => -- R/W: mcause - machine trap cause |
when x"342" => -- R/-: mcause - machine trap cause |
csr_rdata_o <= csr.mcause; |
when x"343" => -- R/W: mtval - machine bad address or instruction |
csr_rdata_o <= csr.mtval; |
1330,6 → 1366,11
csr_rdata_o(03) <= trap_ctrl.irq_buf(interrupt_msw_irq_c); |
csr_rdata_o(07) <= trap_ctrl.irq_buf(interrupt_mtime_irq_c); |
csr_rdata_o(11) <= trap_ctrl.irq_buf(interrupt_mext_irq_c); |
-- |
csr_rdata_o(16) <= trap_ctrl.irq_buf(interrupt_firq_0_c); |
csr_rdata_o(17) <= trap_ctrl.irq_buf(interrupt_firq_1_c); |
csr_rdata_o(18) <= trap_ctrl.irq_buf(interrupt_firq_2_c); |
csr_rdata_o(19) <= trap_ctrl.irq_buf(interrupt_firq_3_c); |
|
-- counter and timers -- |
when x"c00" | x"b00" => -- R/(W): cycle/mcycle: Cycle counter LOW |
/neorv32/trunk/rtl/core/neorv32_package.vhd
41,7 → 41,7
-- Architecture Constants ----------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant data_width_c : natural := 32; -- data width - FIXED! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01020006"; -- no touchy! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01030000"; -- no touchy! |
|
-- Helper Functions ----------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
76,10 → 76,9
constant gpio_in_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(gpio_base_c) + x"00000000"); |
constant gpio_out_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(gpio_base_c) + x"00000004"); |
|
-- Core-Local Interrupt Controller (CLIC) -- |
constant clic_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88"; -- base address, fixed! |
constant clic_size_c : natural := 1*4; -- bytes, fixed! |
constant clic_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(clic_base_c) + x"00000000"); |
-- RESERVED -- |
--constant ???_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88"; -- base address, fixed! |
--constant ???_size_c : natural := 1*4; -- bytes, fixed! |
|
-- Watch Dog Timer (WDT) -- |
constant wdt_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C"; -- base address, fixed! |
317,18 → 316,25
|
-- Trap ID Codes -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant trap_ima_c : std_ulogic_vector(4 downto 0) := "00000"; -- 0.0: instruction misaligned |
constant trap_iba_c : std_ulogic_vector(4 downto 0) := "00001"; -- 0.1: instruction access fault |
constant trap_iil_c : std_ulogic_vector(4 downto 0) := "00010"; -- 0.2: illegal instruction |
constant trap_brk_c : std_ulogic_vector(4 downto 0) := "00011"; -- 0.3: breakpoint |
constant trap_lma_c : std_ulogic_vector(4 downto 0) := "00100"; -- 0.4: load address misaligned |
constant trap_lbe_c : std_ulogic_vector(4 downto 0) := "00101"; -- 0.5: load access fault |
constant trap_sma_c : std_ulogic_vector(4 downto 0) := "00110"; -- 0.6: store address misaligned |
constant trap_sbe_c : std_ulogic_vector(4 downto 0) := "00111"; -- 0.7: store access fault |
constant trap_env_c : std_ulogic_vector(4 downto 0) := "01011"; -- 0.11: environment call from m-mode |
constant trap_msi_c : std_ulogic_vector(4 downto 0) := "10011"; -- 1.3: machine software interrupt |
constant trap_mti_c : std_ulogic_vector(4 downto 0) := "10111"; -- 1.7: machine timer interrupt |
constant trap_mei_c : std_ulogic_vector(4 downto 0) := "11011"; -- 1.11: machine external interrupt |
-- risc-v compliant -- |
constant trap_ima_c : std_ulogic_vector(5 downto 0) := "000000"; -- 0.0: instruction misaligned |
constant trap_iba_c : std_ulogic_vector(5 downto 0) := "000001"; -- 0.1: instruction access fault |
constant trap_iil_c : std_ulogic_vector(5 downto 0) := "000010"; -- 0.2: illegal instruction |
constant trap_brk_c : std_ulogic_vector(5 downto 0) := "000011"; -- 0.3: breakpoint |
constant trap_lma_c : std_ulogic_vector(5 downto 0) := "000100"; -- 0.4: load address misaligned |
constant trap_lbe_c : std_ulogic_vector(5 downto 0) := "000101"; -- 0.5: load access fault |
constant trap_sma_c : std_ulogic_vector(5 downto 0) := "000110"; -- 0.6: store address misaligned |
constant trap_sbe_c : std_ulogic_vector(5 downto 0) := "000111"; -- 0.7: store access fault |
constant trap_menv_c : std_ulogic_vector(5 downto 0) := "001011"; -- 0.11: environment call from m-mode |
-- |
constant trap_msi_c : std_ulogic_vector(5 downto 0) := "100011"; -- 1.3: machine software interrupt |
constant trap_mti_c : std_ulogic_vector(5 downto 0) := "100111"; -- 1.7: machine timer interrupt |
constant trap_mei_c : std_ulogic_vector(5 downto 0) := "101011"; -- 1.11: machine external interrupt |
-- custom -- |
constant trap_firq0_c : std_ulogic_vector(5 downto 0) := "110000"; -- 1.16: fast interrupt 0 |
constant trap_firq1_c : std_ulogic_vector(5 downto 0) := "110001"; -- 1.17: fast interrupt 1 |
constant trap_firq2_c : std_ulogic_vector(5 downto 0) := "110010"; -- 1.18: fast interrupt 2 |
constant trap_firq3_c : std_ulogic_vector(5 downto 0) := "110011"; -- 1.19: fast interrupt 3 |
|
-- CPU Control Exception System ----------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
342,12 → 348,18
constant exception_lalign_c : natural := 6; -- load address misaligned |
constant exception_saccess_c : natural := 7; -- store access fault |
constant exception_laccess_c : natural := 8; -- load access fault |
-- |
constant exception_width_c : natural := 9; -- length of this list in bits |
-- interrupt source bits -- |
constant interrupt_msw_irq_c : natural := 0; -- machine software interrupt |
constant interrupt_mtime_irq_c : natural := 1; -- machine timer interrupt |
constant interrupt_mext_irq_c : natural := 2; -- machine external interrupt |
constant interrupt_width_c : natural := 3; -- length of this list in bits |
constant interrupt_firq_0_c : natural := 3; -- fast interrupt channel 0 |
constant interrupt_firq_1_c : natural := 4; -- fast interrupt channel 1 |
constant interrupt_firq_2_c : natural := 5; -- fast interrupt channel 2 |
constant interrupt_firq_3_c : natural := 6; -- fast interrupt channel 3 |
-- |
constant interrupt_width_c : natural := 7; -- length of this list in bits |
|
-- Clock Generator ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
398,7 → 410,6
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)? |
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)? |
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)? |
); |
428,7 → 439,7
-- SPI -- |
spi_sck_o : out std_ulogic; -- SPI serial clock |
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in |
spi_sdi_i : in std_ulogic; -- controller data in, peripheral data out |
spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out |
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS |
-- TWI -- |
twi_sda_io : inout std_logic := 'H'; -- twi serial data line |
436,8 → 447,8
-- PWM -- |
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels |
-- Interrupts -- |
ext_irq_i : in std_ulogic_vector(01 downto 0) := (others => '0'); -- external interrupt request |
ext_ack_o : out std_ulogic_vector(01 downto 0) -- external interrupt request acknowledge |
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt |
mext_irq_i : in std_ulogic := '0' -- machine external interrupt |
); |
end component; |
|
447,8 → 458,8
generic ( |
-- General -- |
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])? |
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id |
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address |
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id |
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
455,41 → 466,43
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.? |
-- Memory configuration: External memory interface -- |
MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout |
-- Bus Interface -- |
BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout |
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
clk_i : in std_ulogic := '0'; -- global clock, rising edge |
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async |
-- instruction bus interface -- |
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data |
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
i_bus_we_o : out std_ulogic; -- write enable |
i_bus_re_o : out std_ulogic; -- read enable |
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
i_bus_err_i : in std_ulogic; -- bus transfer error |
i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge |
i_bus_err_i : in std_ulogic := '0'; -- bus transfer error |
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation |
-- data bus interface -- |
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data |
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
d_bus_we_o : out std_ulogic; -- write enable |
d_bus_re_o : out std_ulogic; -- read enable |
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
d_bus_err_i : in std_ulogic; -- bus transfer error |
d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge |
d_bus_err_i : in std_ulogic := '0'; -- bus transfer error |
d_bus_fence_o : out std_ulogic; -- executed FENCE operation |
-- system time input from MTIME -- |
time_i : in std_ulogic_vector(63 downto 0); -- current system time |
-- external interrupts -- |
msw_irq_i : in std_ulogic; -- software interrupt |
clic_irq_i : in std_ulogic; -- CLIC interrupt request |
mtime_irq_i : in std_ulogic -- machine timer interrupt |
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time |
-- interrupts (risc-v compliant) -- |
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt |
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt |
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt |
-- fast interrupts (custom) -- |
firq_i : in std_ulogic_vector(3 downto 0) := (others => '0') |
); |
end component; |
|
529,10 → 542,12
-- csr interface -- |
csr_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR write data |
csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data |
-- external interrupt -- |
msw_irq_i : in std_ulogic; -- software interrupt |
clic_irq_i : in std_ulogic; -- CLIC interrupt request |
-- interrupts (risc-v compliant) -- |
msw_irq_i : in std_ulogic; -- machine software interrupt |
mext_irq_i : in std_ulogic; -- machine external interrupt |
mtime_irq_i : in std_ulogic; -- machine timer interrupt |
-- fast interrupts (custom) -- |
firq_i : in std_ulogic_vector(3 downto 0); |
-- system time input from MTIME -- |
time_i : in std_ulogic_vector(63 downto 0); -- current system time |
-- bus access exceptions -- |
620,7 → 635,7
component neorv32_cpu_bus |
generic ( |
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension? |
MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout |
BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout |
); |
port ( |
-- global control -- |
821,27 → 836,6
); |
end component; |
|
-- Component: Core Local Interrupt Controller (CLIC) -------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
component neorv32_clic |
port ( |
-- host access -- |
clk_i : in std_ulogic; -- global clock line |
addr_i : in std_ulogic_vector(31 downto 0); -- address |
rden_i : in std_ulogic; -- read enable |
wren_i : in std_ulogic; -- write enable |
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable |
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
ack_o : out std_ulogic; -- transfer acknowledge |
-- cpu interrupt -- |
cpu_irq_o : out std_ulogic; -- trigger CPU's external IRQ |
-- external interrupt lines -- |
ext_irq_i : in std_ulogic_vector(07 downto 0); -- IRQ, triggering on HIGH level |
ext_ack_o : out std_ulogic_vector(07 downto 0) -- acknowledge |
); |
end component; |
|
-- Component: Watchdog Timer (WDT) -------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
component neorv32_wdt |
1064,7 → 1058,6
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)? |
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)? |
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)? |
); |
/neorv32/trunk/rtl/core/neorv32_sysinfo.vhd
69,7 → 69,6
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)? |
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)? |
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)? |
); |
125,6 → 124,7
sysinfo_mem(2)(02) <= bool_to_ulogic_f(MEM_INT_IMEM_USE); -- implement processor-internal instruction memory? |
sysinfo_mem(2)(03) <= bool_to_ulogic_f(MEM_INT_IMEM_ROM); -- implement processor-internal instruction memory as ROM? |
sysinfo_mem(2)(04) <= bool_to_ulogic_f(MEM_INT_DMEM_USE); -- implement processor-internal data memory? |
sysinfo_mem(2)(15 downto 05) <= (others => '0'); -- reserved |
-- IO |
sysinfo_mem(2)(16) <= bool_to_ulogic_f(IO_GPIO_USE); -- implement general purpose input/output port unit (GPIO)? |
sysinfo_mem(2)(17) <= bool_to_ulogic_f(IO_MTIME_USE); -- implement machine system timer (MTIME)? |
133,9 → 133,10
sysinfo_mem(2)(20) <= bool_to_ulogic_f(IO_TWI_USE); -- implement two-wire interface (TWI)? |
sysinfo_mem(2)(21) <= bool_to_ulogic_f(IO_PWM_USE); -- implement pulse-width modulation unit (PWM)? |
sysinfo_mem(2)(22) <= bool_to_ulogic_f(IO_WDT_USE); -- implement watch dog timer (WDT)? |
sysinfo_mem(2)(23) <= bool_to_ulogic_f(IO_CLIC_USE); -- implement core local interrupt controller (CLIC)? |
sysinfo_mem(2)(23) <= '0'; |
sysinfo_mem(2)(24) <= bool_to_ulogic_f(IO_TRNG_USE); -- implement true random number generator (TRNG)? |
sysinfo_mem(2)(25) <= bool_to_ulogic_f(IO_DEVNULL_USE); -- implement dummy device (DEVNULL)? |
sysinfo_mem(2)(31 downto 26) <= (others => '0'); -- reserved |
|
-- SYSINFO(3): reserved -- |
sysinfo_mem(3) <= (others => '0'); -- reserved - maybe for technology-specific configuration options? |
/neorv32/trunk/rtl/core/neorv32_top.vhd
80,7 → 80,6
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)? |
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)? |
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)? |
); |
110,16 → 109,16
-- SPI (available if IO_SPI_USE = true) -- |
spi_sck_o : out std_ulogic; -- SPI serial clock |
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in |
spi_sdi_i : in std_ulogic; -- controller data in, peripheral data out |
spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out |
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS |
-- TWI (available if IO_TWI_USE = true) -- |
twi_sda_io : inout std_logic := 'H'; -- twi serial data line |
twi_scl_io : inout std_logic := 'H'; -- twi serial clock line |
-- PWM (available if IO_PWM_USE = true) -- |
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels |
-- Interrupts (available if IO_CLIC_USE = true) -- |
ext_irq_i : in std_ulogic_vector(01 downto 0) := (others => '0'); -- external interrupt request |
ext_ack_o : out std_ulogic_vector(01 downto 0) -- external interrupt request acknowledge |
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels |
-- Interrupts -- |
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt |
mext_irq_i : in std_ulogic := '0' -- machine external interrupt |
); |
end neorv32_top; |
|
191,8 → 190,6
signal pwm_ack : std_ulogic; |
signal wdt_rdata : std_ulogic_vector(data_width_c-1 downto 0); |
signal wdt_ack : std_ulogic; |
signal clic_rdata : std_ulogic_vector(data_width_c-1 downto 0); |
signal clic_ack : std_ulogic; |
signal trng_rdata : std_ulogic_vector(data_width_c-1 downto 0); |
signal trng_ack : std_ulogic; |
signal devnull_rdata : std_ulogic_vector(data_width_c-1 downto 0); |
202,9 → 199,7
|
-- IRQs -- |
signal mtime_irq : std_ulogic; |
signal clic_irq : std_ulogic; |
signal clic_xirq : std_ulogic_vector(7 downto 0); |
signal clic_xack : std_ulogic_vector(7 downto 0); |
signal fast_irq : std_ulogic_vector(3 downto 0); |
signal gpio_irq : std_ulogic; |
signal wdt_irq : std_ulogic; |
signal uart_irq : std_ulogic; |
256,10 → 251,6
if (CPU_EXTENSION_RISCV_Zicsr = false) then |
assert false report "NEORV32 CONFIG WARNING! No exception/interrupt/machine features available when CPU_EXTENSION_RISCV_Zicsr = false." severity warning; |
end if; |
-- core local interrupt controller -- |
if (CPU_EXTENSION_RISCV_Zicsr = false) and (IO_CLIC_USE = true) then |
assert false report "NEORV32 CONFIG ERROR! Core local interrupt controller (CLIC) cannot be used without >Zicsr< CPU extension." severity error; |
end if; |
|
-- memory layout notifier -- |
if (MEM_ISPACE_BASE /= x"00000000") then |
339,8 → 330,8
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension? |
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.? |
-- Memory configuration: External memory interface -- |
MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout |
-- Bus Interface -- |
BUS_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout |
) |
port map ( |
-- global control -- |
370,13 → 361,25
d_bus_fence_o => cpu_d.fence, -- executed FENCE operation |
-- system time input from MTIME -- |
time_i => mtime_time, -- current system time |
-- external interrupts -- |
msw_irq_i => '0', -- software interrupt |
clic_irq_i => clic_irq, -- CLIC interrupt request |
mtime_irq_i => mtime_irq -- machine timer interrupt |
-- interrupts (risc-v compliant) -- |
msw_irq_i => msw_irq_i, -- machine software interrupt |
mext_irq_i => mext_irq_i, -- machine external interrupt request |
mtime_irq_i => mtime_irq, -- machine timer interrupt |
-- fast interrupts (custom) -- |
firq_i => fast_irq |
); |
|
-- advanced memory control -- |
fence_o <= cpu_d.fence; -- indicates an executed FENCE operation |
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation |
|
-- fast interrupts -- |
fast_irq(0) <= wdt_irq; -- highest priority |
fast_irq(1) <= gpio_irq; |
fast_irq(2) <= uart_irq; |
fast_irq(3) <= spi_irq or twi_irq; -- lowest priority, can be triggered by SPI or TWI |
|
|
-- CPU Crossbar Switch -------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
neorv32_busswitch_inst: neorv32_busswitch |
420,19 → 423,15
p_bus_err_i => p_bus.err -- bus transfer error |
); |
|
-- advanced memory control -- |
fence_o <= cpu_d.fence; -- indicates an executed FENCE operation |
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation |
|
-- process bus: CPU data input -- |
-- processor bus: CPU data input -- |
p_bus.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or uart_rdata or |
spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or clic_rdata or trng_rdata or devnull_rdata or sysinfo_rdata); |
spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or trng_rdata or devnull_rdata or sysinfo_rdata); |
|
-- process bus: CPU data ACK input -- |
-- processor bus: CPU data ACK input -- |
p_bus.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or uart_ack or |
spi_ack or twi_ack or pwm_ack or wdt_ack or clic_ack or trng_ack or devnull_ack or sysinfo_ack); |
spi_ack or twi_ack or pwm_ack or wdt_ack or trng_ack or devnull_ack or sysinfo_ack); |
|
-- process bus: CPU data bus error input -- |
-- processor bus: CPU data bus error input -- |
p_bus.err <= wishbone_err; |
|
|
615,52 → 614,6
end generate; |
|
|
-- Core-Local Interrupt Controller (CLIC) ------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
neorv32_clic_inst_true: |
if (IO_CLIC_USE = true) generate |
neorv32_clic_inst: neorv32_clic |
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => p_bus.ben, -- byte write enable |
addr_i => p_bus.addr, -- address |
data_i => p_bus.wdata, -- data in |
data_o => clic_rdata, -- data out |
ack_o => clic_ack, -- transfer acknowledge |
-- cpu interrupt -- |
cpu_irq_o => clic_irq, -- trigger CPU's external IRQ |
-- external interrupt lines -- |
ext_irq_i => clic_xirq, -- IRQ, triggering on HIGH level |
ext_ack_o => clic_xack -- acknowledge |
); |
end generate; |
|
-- CLIC interrupt channels and priority -- |
clic_xirq(0) <= wdt_irq; -- highest priority |
clic_xirq(1) <= '0'; -- reserved |
clic_xirq(2) <= gpio_irq; |
clic_xirq(3) <= uart_irq; |
clic_xirq(4) <= spi_irq; |
clic_xirq(5) <= twi_irq; |
clic_xirq(6) <= ext_irq_i(0); |
clic_xirq(7) <= ext_irq_i(1); -- lowest priority |
|
-- external interrupt request acknowledge -- |
ext_ack_o(0) <= clic_xack(6); |
ext_ack_o(1) <= clic_xack(7); |
|
neorv32_clic_inst_false: |
if (IO_CLIC_USE = false) generate |
clic_rdata <= (others => '0'); |
clic_ack <= '0'; |
clic_irq <= '0'; |
clic_xack <= (others => '0'); |
end generate; |
|
|
-- Watch Dog Timer (WDT) ------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
neorv32_wdt_inst_true: |
952,7 → 905,6
IO_TWI_USE => IO_TWI_USE, -- implement two-wire interface (TWI)? |
IO_PWM_USE => IO_PWM_USE, -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE => IO_WDT_USE, -- implement watch dog timer (WDT)? |
IO_CLIC_USE => IO_CLIC_USE, -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE => IO_TRNG_USE, -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE => IO_DEVNULL_USE -- implement dummy device (DEVNULL)? |
) |
/neorv32/trunk/rtl/fpga_specific/lattice_ice40up/neorv32_dmem.ice40up_spram.vhd
90,7 → 90,7
|
-- Access Control ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
acc_en <= '1' when (addr_i >= DMEM_BASE) and (addr_i < std_ulogic_vector(unsigned(DMEM_BASE) + DMEM_SIZE)) else '0'; |
acc_en <= '1' when (unsigned(addr_i) >= unsigned(DMEM_BASE)) and (unsigned(addr_i) < unsigned(DMEM_BASE) + DMEM_SIZE) else '0'; |
mem_cs <= acc_en and (rden_i or wren_i); |
|
|
/neorv32/trunk/rtl/fpga_specific/lattice_ice40up/neorv32_imem.ice40up_spram.vhd
93,7 → 93,7
|
-- Access Control ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
acc_en <= '1' when (addr_i >= IMEM_BASE) and (addr_i < std_ulogic_vector(unsigned(IMEM_BASE) + IMEM_SIZE)) else '0'; |
acc_en <= '1' when (unsigned(addr_i) >= unsigned(IMEM_BASE)) and (unsigned(addr_i) < unsigned(IMEM_BASE) + IMEM_SIZE) else '0'; |
mem_cs <= acc_en and (rden_i or wren_i); |
|
|
/neorv32/trunk/rtl/top_templates/neorv32_test_setup.vhd
102,7 → 102,6
IO_TWI_USE => false, -- implement two-wire interface (TWI)? |
IO_PWM_USE => false, -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE => true, -- implement watch dog timer (WDT)? |
IO_CLIC_USE => true, -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE => false, -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE => true -- implement dummy device (DEVNULL)? |
) |
140,8 → 139,8
-- PWM -- |
pwm_o => open, -- pwm channels |
-- Interrupts -- |
ext_irq_i => (others => '0'), -- external interrupt request |
ext_ack_o => open -- external interrupt request acknowledge |
msw_irq_i => '0', -- machine software interrupt |
mext_irq_i => '0' -- machine external interrupt |
); |
|
-- output -- |
/neorv32/trunk/sim/ghdl/ghdl_sim.sh
37,7 → 37,6
# |
ghdl -a --work=neorv32 $srcdir_core/neorv32_boot_rom.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_busswitch.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_clic.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu_alu.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu_bus.vhd |
/neorv32/trunk/sim/vivado/neorv32_tb_behav.wcfg
12,15 → 12,15
</db_ref> |
</db_ref_list> |
<zoom_setting> |
<ZoomStartTime time="125360934fs"></ZoomStartTime> |
<ZoomEndTime time="125396735fs"></ZoomEndTime> |
<Cursor1Time time="125479534fs"></Cursor1Time> |
<ZoomStartTime time="1345742867fs"></ZoomStartTime> |
<ZoomEndTime time="1345761168fs"></ZoomEndTime> |
<Cursor1Time time="1345799367fs"></Cursor1Time> |
</zoom_setting> |
<column_width_setting> |
<NameColumnWidth column_width="178"></NameColumnWidth> |
<ValueColumnWidth column_width="120"></ValueColumnWidth> |
<ValueColumnWidth column_width="116"></ValueColumnWidth> |
</column_width_setting> |
<WVObjectSize size="144" /> |
<WVObjectSize size="142" /> |
<wvobject type="divider" fp_name="divider273"> |
<obj_property name="label">CPU: Control.FETCH</obj_property> |
<obj_property name="DisplayName">label</obj_property> |
61,70 → 61,6
<obj_property name="ElementShortName">fetch_engine</obj_property> |
<obj_property name="ObjectShortName">fetch_engine</obj_property> |
<obj_property name="isExpanded"></obj_property> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.state" type="other"> |
<obj_property name="ElementShortName">.state</obj_property> |
<obj_property name="ObjectShortName">.state</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.state_nxt" type="other"> |
<obj_property name="ElementShortName">.state_nxt</obj_property> |
<obj_property name="ObjectShortName">.state_nxt</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf" type="array"> |
<obj_property name="ElementShortName">.i_buf[33:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf[33:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf_nxt" type="array"> |
<obj_property name="ElementShortName">.i_buf_nxt[33:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf_nxt[33:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf2" type="array"> |
<obj_property name="ElementShortName">.i_buf2[33:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf2[33:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf2_nxt" type="array"> |
<obj_property name="ElementShortName">.i_buf2_nxt[33:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf2_nxt[33:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.ci_input" type="array"> |
<obj_property name="ElementShortName">.ci_input[15:0]</obj_property> |
<obj_property name="ObjectShortName">.ci_input[15:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf_state" type="array"> |
<obj_property name="ElementShortName">.i_buf_state[1:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf_state[1:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf_state_nxt" type="array"> |
<obj_property name="ElementShortName">.i_buf_state_nxt[1:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf_state_nxt[1:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.pc_real" type="array"> |
<obj_property name="ElementShortName">.pc_real[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_real[31:0]</obj_property> |
<obj_property name="CustomSignalColor">#FFFFFF</obj_property> |
<obj_property name="UseCustomSignalColor">true</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.pc_real_add" type="array"> |
<obj_property name="ElementShortName">.pc_real_add[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_real_add[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.pc_fetch" type="array"> |
<obj_property name="ElementShortName">.pc_fetch[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_fetch[31:0]</obj_property> |
<obj_property name="CustomSignalColor">#FFFFFF</obj_property> |
<obj_property name="UseCustomSignalColor">true</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.pc_fetch_add" type="array"> |
<obj_property name="ElementShortName">.pc_fetch_add[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_fetch_add[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.reset" type="logic"> |
<obj_property name="ElementShortName">.reset</obj_property> |
<obj_property name="ObjectShortName">.reset</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.bus_err_ack" type="logic"> |
<obj_property name="ElementShortName">.bus_err_ack</obj_property> |
<obj_property name="ObjectShortName">.bus_err_ack</obj_property> |
</wvobject> |
</wvobject> |
<wvobject type="divider" fp_name="divider273"> |
<obj_property name="label">CPU: Control.IPB</obj_property> |
167,10 → 103,6
<obj_property name="ElementShortName">csr_rdata_o[31:0]</obj_property> |
<obj_property name="ObjectShortName">csr_rdata_o[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/clic_irq_i" type="logic"> |
<obj_property name="ElementShortName">clic_irq_i</obj_property> |
<obj_property name="ObjectShortName">clic_irq_i</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/mtime_irq_i" type="logic"> |
<obj_property name="ElementShortName">mtime_irq_i</obj_property> |
<obj_property name="ObjectShortName">mtime_irq_i</obj_property> |
239,6 → 171,70
<obj_property name="ElementShortName">execute_engine</obj_property> |
<obj_property name="ObjectShortName">execute_engine</obj_property> |
<obj_property name="isExpanded"></obj_property> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.state" type="other"> |
<obj_property name="ElementShortName">.state</obj_property> |
<obj_property name="ObjectShortName">.state</obj_property> |
<obj_property name="CustomSignalColor">#FFA500</obj_property> |
<obj_property name="UseCustomSignalColor">true</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.state_nxt" type="other"> |
<obj_property name="ElementShortName">.state_nxt</obj_property> |
<obj_property name="ObjectShortName">.state_nxt</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.i_reg" type="array"> |
<obj_property name="ElementShortName">.i_reg[31:0]</obj_property> |
<obj_property name="ObjectShortName">.i_reg[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.i_reg_nxt" type="array"> |
<obj_property name="ElementShortName">.i_reg_nxt[31:0]</obj_property> |
<obj_property name="ObjectShortName">.i_reg_nxt[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.is_ci" type="logic"> |
<obj_property name="ElementShortName">.is_ci</obj_property> |
<obj_property name="ObjectShortName">.is_ci</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.is_ci_nxt" type="logic"> |
<obj_property name="ElementShortName">.is_ci_nxt</obj_property> |
<obj_property name="ObjectShortName">.is_ci_nxt</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.is_jump" type="logic"> |
<obj_property name="ElementShortName">.is_jump</obj_property> |
<obj_property name="ObjectShortName">.is_jump</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.is_jump_nxt" type="logic"> |
<obj_property name="ElementShortName">.is_jump_nxt</obj_property> |
<obj_property name="ObjectShortName">.is_jump_nxt</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.branch_taken" type="logic"> |
<obj_property name="ElementShortName">.branch_taken</obj_property> |
<obj_property name="ObjectShortName">.branch_taken</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.pc" type="array"> |
<obj_property name="ElementShortName">.pc[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc[31:0]</obj_property> |
<obj_property name="CustomSignalColor">#FFFFFF</obj_property> |
<obj_property name="UseCustomSignalColor">true</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.pc_nxt" type="array"> |
<obj_property name="ElementShortName">.pc_nxt[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_nxt[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.next_pc" type="array"> |
<obj_property name="ElementShortName">.next_pc[31:0]</obj_property> |
<obj_property name="ObjectShortName">.next_pc[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.last_pc" type="array"> |
<obj_property name="ElementShortName">.last_pc[31:0]</obj_property> |
<obj_property name="ObjectShortName">.last_pc[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.sleep" type="logic"> |
<obj_property name="ElementShortName">.sleep</obj_property> |
<obj_property name="ObjectShortName">.sleep</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.sleep_nxt" type="logic"> |
<obj_property name="ElementShortName">.sleep_nxt</obj_property> |
<obj_property name="ObjectShortName">.sleep_nxt</obj_property> |
</wvobject> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/CPU_EXTENSION_RISCV_C" type="other"> |
<obj_property name="ElementShortName">CPU_EXTENSION_RISCV_C</obj_property> |
482,10 → 478,6
<obj_property name="ElementShortName">be_store_o</obj_property> |
<obj_property name="ObjectShortName">be_store_o</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/MEM_EXT_TIMEOUT" type="other"> |
<obj_property name="ElementShortName">MEM_EXT_TIMEOUT</obj_property> |
<obj_property name="ObjectShortName">MEM_EXT_TIMEOUT</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/i_arbiter" type="array"> |
<obj_property name="ElementShortName">i_arbiter</obj_property> |
<obj_property name="ObjectShortName">i_arbiter</obj_property> |
/neorv32/trunk/sim/neorv32_tb.vhd
159,7 → 159,6
IO_TWI_USE => true, -- implement two-wire interface (TWI)? |
IO_PWM_USE => true, -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE => true, -- implement watch dog timer (WDT)? |
IO_CLIC_USE => true, -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE => false, -- CANNOT BE SIMULATED! |
IO_DEVNULL_USE => true -- implement dummy device (DEVNULL)? |
) |
197,8 → 196,7
-- PWM -- |
pwm_o => open, -- pwm channels |
-- Interrupts -- |
ext_irq_i => (others => '0'), -- external interrupt request |
ext_ack_o => open -- external interrupt request acknowledge |
mext_irq_i => '0' -- machine external interrupt |
); |
|
-- TWI termination -- |
/neorv32/trunk/sw/bootloader/bootloader.c
176,7 → 176,6
|
// deactivate unused IO devices |
neorv32_wdt_disable(); |
neorv32_clic_disable(); |
neorv32_pwm_disable(); |
neorv32_spi_disable(); |
neorv32_trng_disable(); |
338,16 → 337,15
while ((UART_CT & (1<<UART_CT_TX_BUSY)) != 0); |
|
// reset performance counters (to benchmark actual application) |
asm volatile ("csrrw zero, mcycle, zero"); // will also clear 'cycle' |
asm volatile ("csrrw zero, mcycleh, zero"); // will also clear 'cycleh' |
asm volatile ("csrrw zero, minstret, zero"); // will also clear 'instret' |
asm volatile ("csrrw zero, minstreth, zero"); // will also clear 'instreth' |
asm volatile ("csrw mcycle, zero"); // will also clear 'cycle' |
asm volatile ("csrw mcycleh, zero"); // will also clear 'cycleh' |
asm volatile ("csrw minstret, zero"); // will also clear 'instret' |
asm volatile ("csrw minstreth, zero"); // will also clear 'instreth' |
|
// start app at instruction space base address |
while (1) { |
register uint32_t app_base = SYSINFO_ISPACE_BASE; |
asm volatile ("jalr zero, %0" : : "r" (app_base)); |
} |
register uint32_t app_base = SYSINFO_ISPACE_BASE; |
asm volatile ("jalr zero, %0" : : "r" (app_base)); |
while (1); |
} |
|
|
359,7 → 357,7
|
// make sure this was caused by MTIME IRQ |
uint32_t cause = neorv32_cpu_csr_read(CSR_MCAUSE); |
if (cause != EXCCODE_MTI) { // raw exception code for MTI |
if (cause != TRAP_CODE_MTI) { // raw exception code for MTI |
neorv32_uart_print("\n\nEXCEPTION: "); |
print_hex_word(cause); |
neorv32_uart_print(" @ 0x"); |
/neorv32/trunk/sw/common/bootloader_crt0.S
41,8 → 41,8
|
|
// SYSINFO |
.set SYSINFO_DSPACE_BASE, 0xFFFFFFF4 |
.set SYSINFO_DSPACE_SIZE, 0xFFFFFFFC |
.equ SYSINFO_DSPACE_BASE, 0xFFFFFFF4 |
.equ SYSINFO_DSPACE_SIZE, 0xFFFFFFFC |
|
|
_start: |
102,25 → 102,42
|
// ********************************************************* |
// dummy trap handler (for exceptions & IRQs) |
// bootloader has to be compiled without any CPU extensions |
// - especially without C extension! |
// tries to move on to next instruction |
// ********************************************************* |
.global __crt0_dummy_trap_handler |
.balign 4 |
__crt0_dummy_trap_handler: |
|
addi sp, sp, -4 |
addi sp, sp, -8 |
sw x8, 0(sp) |
sw x9, 4(sp) |
|
csrr x8, mcause |
blt x8, zero, __crt0_dummy_trap_handler_irq // skip mepc modification if interrupt |
|
__crt0_dummy_trap_handler_compute_return: |
csrr x8, mepc |
addi x8, x8, +4 // move on to next instruction if exception |
|
// is compressed instruction? |
lh x9, 0(x8) // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception |
andi x9, x9, 3 // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions) |
|
addi x8, x8, +2 // only this for compressed instructions |
csrw mepc, x8 // set return address when compressed instruction |
|
addi x8, zero, 3 |
bne x8, x9, __crt0_dummy_trap_handler_irq // jump if compressed instruction |
|
// is uncompressed instruction |
csrr x8, mepc |
addi x8, x8, +2 // add another 2 (making +4) for uncompressed instructions |
csrw mepc, x8 |
|
__crt0_dummy_trap_handler_irq: |
|
lw x8, 0(sp) |
addi sp, sp, +4 |
lw x9, 0(sp) |
lw x8, 4(sp) |
addi sp, sp, +8 |
|
mret |
|
/neorv32/trunk/sw/common/crt0.S
43,11 → 43,11
|
|
// IO region |
.set IO_BEGIN, 0xFFFFFF80 // start of processor-internal IO region |
.equ IO_BEGIN, 0xFFFFFF80 // start of processor-internal IO region |
|
// SYSINFO |
.set SYSINFO_DSPACE_BASE, 0xFFFFFFF4 |
.set SYSINFO_DSPACE_SIZE, 0xFFFFFFFC |
.equ SYSINFO_DSPACE_BASE, 0xFFFFFFF4 |
.equ SYSINFO_DSPACE_SIZE, 0xFFFFFFFC |
|
|
_start: |
58,9 → 58,8
// Clear register file |
// ********************************************************* |
__crt0_reg_file_clear: |
addi x0, x0, 0 // hardwired to zero |
//addi x0, x0, 0 // hardwired to zero |
addi x1, x0, 0 |
__crt0_reg_file_init: |
addi x2, x1, 0 |
addi x3, x2, 0 |
addi x4, x3, 0 |
78,7 → 77,7
|
// the following registers do not exist in rv32e |
// "__RISCV_EMBEDDED_CPU__" is automatically defined by the makefiles when |
// compiling for a rv32e architecture |
// compiling for a rv32e* architecture |
#ifndef __RISCV_EMBEDDED_CPU__ |
addi x16, x15, 0 |
addi x17, x16, 0 |
100,7 → 99,7
|
|
// ********************************************************* |
// TEST AREA / DANGER ZONE / IDEA-LAB |
// TEST AREA / DANGER ZONE |
// ********************************************************* |
__crt0_tests: |
nop |
128,23 → 127,13
|
|
// ********************************************************* |
// Init exception vector table (2x16 4-byte entries) with dummy handlers |
// Init trap handler base address |
// ********************************************************* |
__crt0_neorv32_rte_init: |
la x11, __crt0_neorv32_rte |
__crt0_neorv32_trap_init: |
la x11, __crt0_dummy_trap_handler |
csrw mtvec, x11 // set address of first-level exception handler |
|
lw x11, SYSINFO_DSPACE_BASE(zero) // data memory space base address |
la x12, __crt0_neorv32_rte_dummy_hanlder |
li x13, 2*16 // number of entries (16xEXC, 16xIRQ) |
|
__crt0_neorv32_rte_init_loop: |
sw x12, 0(x11) // set dummy handler |
add x11, x11, 4 |
add x13, x13, -1 |
bne zero, x13, __crt0_neorv32_rte_init_loop |
|
|
// ********************************************************* |
// Reset/deactivate IO/peripheral devices |
// Devices, that are not implemented, will cause a store access fault |
216,167 → 205,45
|
|
// ********************************************************* |
// NEORV32 runtime environment: First-level exception/interrupt handler |
// dummy trap handler (for exceptions & IRQs) |
// tries to move on to next instruction |
// ********************************************************* |
.align 4 |
__crt0_neorv32_rte: |
.global __crt0_dummy_trap_handler |
.balign 4 |
__crt0_dummy_trap_handler: |
|
// -------------------------------------------- |
// full context save |
// -------------------------------------------- |
#ifndef __RISCV_EMBEDDED_CPU__ |
addi sp, sp, -120 |
#else |
addi sp, sp, -56 |
#endif |
addi sp, sp, -8 |
sw x8, 0(sp) |
sw x9, 4(sp) |
|
sw ra,0(sp) |
sw gp,4(sp) |
sw tp,8(sp) |
sw t0,12(sp) |
sw t1,16(sp) |
sw t2,20(sp) |
sw s0,24(sp) |
sw s1,28(sp) |
sw a0,32(sp) |
sw a1,36(sp) |
sw a2,40(sp) |
sw a3,44(sp) |
sw a4,48(sp) |
sw a5,52(sp) |
#ifndef __RISCV_EMBEDDED_CPU__ |
sw a6,56(sp) |
sw a7,60(sp) |
sw s2,64(sp) |
sw s3,68(sp) |
sw s4,72(sp) |
sw s5,76(sp) |
sw s6,80(sp) |
sw s7,84(sp) |
sw s8,88(sp) |
sw s9,92(sp) |
sw s10,96(sp) |
sw s11,100(sp) |
sw t3,104(sp) |
sw t4,108(sp) |
sw t5,112(sp) |
sw t6,116(sp) |
#endif |
csrr x8, mcause |
blt x8, zero, __crt0_dummy_trap_handler_irq // skip mepc modification if interrupt |
|
__crt0_dummy_trap_handler_compute_return: |
csrr x8, mepc |
|
// -------------------------------------------- |
// get cause and prepare jump into vector table |
// -------------------------------------------- |
csrr t0, mcause // get cause code |
// is compressed instruction? |
lh x9, 0(x8) // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception |
andi x9, x9, 3 // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions) |
|
andi t1, t0, 0x0f // isolate cause ID |
slli t1, t1, 2 // make address offset |
lw ra, SYSINFO_DSPACE_BASE(zero) // data memory space base address |
add t1, t1, ra // get vetor table entry address (EXC vectors) |
addi x8, x8, +2 // only this for compressed instructions |
csrw mepc, x8 // set return address when compressed instruction |
|
csrr ra, mepc // get return address |
|
blt t0, zero, __crt0_neorv32_rte_is_irq // branch if this is an INTERRUPT |
|
|
// -------------------------------------------- |
// compute return address for EXCEPTIONS only |
// -------------------------------------------- |
__crt0_neorv32_rte_is_exc: |
|
// check if faulting instruction is compressed and adjust return address |
|
lh t0, 0(ra) // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception |
addi t2, zero, 3 // mask |
and t0, t0, t2 // isolate lowest 2 opcode bits (= 11 for uncompressed instructions) |
|
addi ra, ra, +2 // only this for compressed instructions |
bne t0, t2, __crt0_neorv32_rte_execute // jump if compressed instruction |
addi x8, zero, 3 |
bne x8, x9, __crt0_dummy_trap_handler_irq // jump if compressed instruction |
|
addi ra, ra, +2 // add another 2 (making +4) for uncompressed instructions |
j __crt0_neorv32_rte_execute |
// is uncompressed instruction |
csrr x8, mepc |
addi x8, x8, +2 // add another 2 (making +4) for uncompressed instructions |
csrw mepc, x8 |
|
__crt0_dummy_trap_handler_irq: |
|
// -------------------------------------------- |
// vector table offset for INTERRUPTS only |
// -------------------------------------------- |
__crt0_neorv32_rte_is_irq: |
addi t1, t1, 16*4 |
lw x9, 0(sp) |
lw x8, 4(sp) |
addi sp, sp, +8 |
|
|
// -------------------------------------------- |
// call handler from vector table |
// -------------------------------------------- |
__crt0_neorv32_rte_execute: |
lw t0, 0(t1) // get base address of second-level handler |
|
// push ra |
addi sp, sp, -4 |
sw ra, 0(sp) |
|
jalr ra, t0 // call second-level handler |
|
// pop ra |
lw ra, 0(sp) |
addi sp, sp, +4 |
|
csrw mepc, ra |
|
|
// -------------------------------------------- |
// full context restore |
// -------------------------------------------- |
lw ra,0(sp) |
lw gp,4(sp) |
lw tp,8(sp) |
lw t0,12(sp) |
lw t1,16(sp) |
lw t2,20(sp) |
lw s0,24(sp) |
lw s1,28(sp) |
lw a0,32(sp) |
lw a1,36(sp) |
lw a2,40(sp) |
lw a3,44(sp) |
lw a4,48(sp) |
lw a5,52(sp) |
#ifndef __RISCV_EMBEDDED_CPU__ |
lw a6,56(sp) |
lw a7,60(sp) |
lw s2,64(sp) |
lw s3,68(sp) |
lw s4,72(sp) |
lw s5,76(sp) |
lw s6,80(sp) |
lw s7,84(sp) |
lw s8,88(sp) |
lw s9,92(sp) |
lw s10,96(sp) |
lw s11,100(sp) |
lw t3,104(sp) |
lw t4,108(sp) |
lw t5,112(sp) |
lw t6,116(sp) |
#endif |
|
#ifndef __RISCV_EMBEDDED_CPU__ |
addi sp, sp, +120 |
#else |
addi sp, sp, +56 |
#endif |
|
|
// -------------------------------------------- |
// this is the ONLY place where MRET should be used! |
// -------------------------------------------- |
mret |
|
|
// ********************************************************* |
// Dummy exception handler: just move on to next instruction |
// ********************************************************* |
__crt0_neorv32_rte_dummy_hanlder: |
ret |
|
.cfi_endproc |
.end |
/neorv32/trunk/sw/common/neorv32.ld
53,9 → 53,8
/* ************************************************* */ |
MEMORY |
{ |
rom (rx) : ORIGIN = 0x00000000, LENGTH = 16*1024 |
ram (rwx) : ORIGIN = 0x80000000 + 2*16*4, LENGTH = 8*1024 |
/* DO NOT REMOVE THE " + 2*16*4"!! */ |
rom (rx) : ORIGIN = 0x00000000, LENGTH = 16*1024 |
ram (rwx) : ORIGIN = 0x80000000, LENGTH = 8*1024 |
} |
/* ************************************************* */ |
|
/neorv32/trunk/sw/example/blink_led/main.c
68,7 → 68,7
|
// capture all exceptions and give debug info via UART |
// this is not required, but keeps us safe |
neorv32_rte_enable_debug_mode(); |
neorv32_rte_setup(); |
|
|
// init UART at default baud rate, no rx interrupt, no tx interrupt |
/neorv32/trunk/sw/example/coremark/core_portme.c
124,7 → 124,7
neorv32_cpu_dint(); |
|
// capture all exceptions and give debug information |
neorv32_rte_enable_debug_mode(); |
neorv32_rte_setup(); |
|
// setup neorv32 UART |
neorv32_uart_setup(BAUD_RATE, 0, 0); |
/neorv32/trunk/sw/example/cpu_test/main.c
109,11 → 109,6
return 0; |
} |
|
// check if CLIC unit is implemented at all |
if (neorv32_clic_available() == 0) { |
return 0; |
} |
|
// check if MTIME unit is implemented at all |
if (neorv32_mtime_available() == 0) { |
return 0; |
141,43 → 136,37
// intro2 |
neorv32_uart_printf("\n\nStarting tests...\n\n"); |
|
// install exception handler functions |
// configure RTE |
neorv32_rte_setup(); // this will install a full-detailed debug handler for all traps |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
int install_err = 0; |
install_err += neorv32_rte_exception_install(EXCID_I_MISALIGNED, global_trap_handler); |
install_err += neorv32_rte_exception_install(EXCID_I_ACCESS, global_trap_handler); |
install_err += neorv32_rte_exception_install(EXCID_I_ILLEGAL, global_trap_handler); |
install_err += neorv32_rte_exception_install(EXCID_BREAKPOINT, global_trap_handler); |
install_err += neorv32_rte_exception_install(EXCID_L_MISALIGNED, global_trap_handler); |
install_err += neorv32_rte_exception_install(EXCID_L_ACCESS, global_trap_handler); |
install_err += neorv32_rte_exception_install(EXCID_S_MISALIGNED, global_trap_handler); |
install_err += neorv32_rte_exception_install(EXCID_S_ACCESS, global_trap_handler); |
install_err += neorv32_rte_exception_install(EXCID_MENV_CALL, global_trap_handler); |
install_err += neorv32_rte_exception_install(EXCID_MTI, global_trap_handler); |
//install_err += neorv32_rte_exception_install(EXCID_MEI, -); done by neorv32_clic_handler_install |
// here we are overriding the default debug handlers |
install_err += neorv32_rte_exception_install(RTE_TRAP_I_MISALIGNED, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_I_ACCESS, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_I_ILLEGAL, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_BREAKPOINT, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_L_MISALIGNED, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_L_ACCESS, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_S_MISALIGNED, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_S_ACCESS, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_MENV_CALL, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_MTI, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_MSI, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_MTI, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_0, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_1, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_2, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_3, global_trap_handler); |
|
if (install_err) { |
neorv32_uart_printf("RTE install error!\n"); |
neorv32_uart_printf("RTE install error (%i)!\n", install_err); |
return 0; |
} |
#endif |
|
|
// install interrupt handler for clic WDT channel |
install_err += neorv32_clic_handler_install(CLIC_CH_WDT, global_trap_handler); |
|
if (install_err) { |
neorv32_uart_printf("CLIC install error!\n"); |
return 0; |
} |
|
|
#if (DETAILED_EXCEPTION_DEBUG==1) |
// enable debug mode for uninitialized exception/interrupt vectors |
// and overwrite previous exception handler installations |
// -> any exception/interrupt will show a message from the neorv32 runtime environment |
neorv32_rte_enable_debug_mode(); |
#endif |
|
|
// enable global interrupts |
neorv32_cpu_eint(); |
|
197,7 → 186,7
|
while(1) { |
asm volatile ("lb zero, 0(%[input_j])" : : [input_j] "r" (dmem_probe_addr)); |
if (exception_handler_answer == EXCCODE_L_ACCESS) { |
if (exception_handler_answer == TRAP_CODE_L_ACCESS) { |
break; |
} |
dmem_probe_addr++; |
229,7 → 218,7
|
while(1) { |
asm volatile ("lb zero, 0(%[input_j])" : : [input_j] "r" (imem_probe_addr)); |
if (exception_handler_answer == EXCCODE_L_ACCESS) { |
if (exception_handler_answer == TRAP_CODE_L_ACCESS) { |
break; |
} |
imem_probe_addr++; |
291,13 → 280,13
neorv32_uart_printf("TIME[H]: "); |
cnt_test++; |
|
cpu_systime.uint32[0] = neorv32_cpu_csr_read(CSR_TIME); |
cpu_systime.uint32[1] = neorv32_cpu_csr_read(CSR_TIMEH); |
cpu_systime.uint64 &= 0xFFFFFFFFFFFF0000LL; |
cpu_systime.uint64 = neorv32_cpu_get_systime(); |
uint64_t mtime_systime = neorv32_mtime_get_time(); |
|
uint64_t mtime_systime = neorv32_mtime_get_time() & 0xFFFFFFFFFFFF0000LL; |
// compute difference |
mtime_systime = mtime_systime - cpu_systime.uint64; |
|
if (cpu_systime.uint64 == mtime_systime) { |
if (mtime_systime < 100) { // diff should be pretty small |
test_ok(); |
} |
else { |
334,7 → 323,7
neorv32_cpu_csr_read(0xfff); // CSR 0xfff not implemented |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == EXCCODE_I_ILLEGAL) { |
if (exception_handler_answer == TRAP_CODE_I_ILLEGAL) { |
test_ok(); |
} |
else { |
358,7 → 347,7
((void (*)(void))ADDR_UNALIGNED)(); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == EXCCODE_I_MISALIGNED) { |
if (exception_handler_answer == TRAP_CODE_I_MISALIGNED) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
384,7 → 373,7
((void (*)(void))ADDR_UNREACHABLE)(); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == EXCCODE_I_ACCESS) { |
if (exception_handler_answer == TRAP_CODE_I_ACCESS) { |
test_ok(); |
} |
else { |
401,8 → 390,8
cnt_test++; |
|
// create test program in RAM |
static const uint32_t dummy_sub_program[2] = { |
0xDEAD007F, // undefined 32-bit opcode -> illegal instruction exception |
static const uint32_t dummy_sub_program[2] __attribute__((aligned(8))) = { |
0xDEAD007F, // undefined 32-bit instruction (invalid opcode) -> illegal instruction exception |
0x00008067 // ret (32-bit) |
}; |
|
410,7 → 399,7
asm volatile ( "jalr ra, %0 " : "=r" (tmp_a) : "r" (tmp_a)); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == EXCCODE_I_ILLEGAL) { |
if (exception_handler_answer == TRAP_CODE_I_ILLEGAL) { |
test_ok(); |
} |
else { |
431,7 → 420,7
cnt_test++; |
|
// create test program in RAM |
static const uint32_t dummy_sub_program_ci[2] = { |
static const uint32_t dummy_sub_program_ci[2] __attribute__((aligned(8))) = { |
0x00000001, // 2nd: official_illegal_op | 1st: NOP -> illegal instruction exception |
0x00008067 // ret (32-bit) |
}; |
440,7 → 429,7
asm volatile ( "jalr ra, %0 " : "=r" (tmp_a) : "r" (tmp_a)); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == EXCCODE_I_ILLEGAL) { |
if (exception_handler_answer == TRAP_CODE_I_ILLEGAL) { |
test_ok(); |
} |
else { |
463,7 → 452,7
asm volatile("EBREAK"); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == EXCCODE_BREAKPOINT) { |
if (exception_handler_answer == TRAP_CODE_BREAKPOINT) { |
test_ok(); |
} |
else { |
483,7 → 472,7
asm volatile ("lw zero, %[input_i](zero)" : : [input_i] "i" (ADDR_UNALIGNED)); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == EXCCODE_L_MISALIGNED) { |
if (exception_handler_answer == TRAP_CODE_L_MISALIGNED) { |
test_ok(); |
} |
else { |
503,7 → 492,7
dummy_dst = MMR_UNREACHABLE; |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == EXCCODE_L_ACCESS) { |
if (exception_handler_answer == TRAP_CODE_L_ACCESS) { |
test_ok(); |
} |
else { |
523,7 → 512,7
asm volatile ("sw zero, %[input_i](zero)" : : [input_i] "i" (ADDR_UNALIGNED)); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == EXCCODE_S_MISALIGNED) { |
if (exception_handler_answer == TRAP_CODE_S_MISALIGNED) { |
test_ok(); |
} |
else { |
543,7 → 532,7
MMR_UNREACHABLE = 0; |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == EXCCODE_S_ACCESS) { |
if (exception_handler_answer == TRAP_CODE_S_ACCESS) { |
test_ok(); |
} |
else { |
562,7 → 551,7
asm volatile("ECALL"); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == EXCCODE_MENV_CALL) { |
if (exception_handler_answer == TRAP_CODE_MENV_CALL) { |
test_ok(); |
} |
else { |
576,79 → 565,103
// ---------------------------------------------------------- |
exception_handler_answer = 0xFFFFFFFF; |
neorv32_uart_printf("IRQ MTI: "); |
cnt_test++; |
|
// force MTIME IRQ |
neorv32_mtime_set_timecmp(0); |
if (neorv32_mtime_available()) { |
cnt_test++; |
|
// wait some time for the IRQ to arrive the CPU |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
// force MTIME IRQ |
neorv32_mtime_set_timecmp(0); |
|
// wait some time for the IRQ to arrive the CPU |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == EXCCODE_MTI) { |
test_ok(); |
if (exception_handler_answer == TRAP_CODE_MTI) { |
test_ok(); |
} |
else { |
test_fail(); |
} |
#endif |
|
// no more mtime interrupts |
neorv32_mtime_set_timecmp(-1); |
} |
else { |
test_fail(); |
neorv32_uart_printf("skipped (WDT not implemented)\n"); |
} |
#endif |
|
// no more mtime interrupts |
neorv32_mtime_set_timecmp(-1); |
|
|
// ---------------------------------------------------------- |
// Machine external interrupt (via CLIC) |
// Fast interrupt |
// ---------------------------------------------------------- |
exception_handler_answer = 0xFFFFFFFF; |
neorv32_uart_printf("IRQ MEI: "); |
cnt_test++; |
neorv32_uart_printf("FIRQ0 (WDT): "); |
|
// manually trigger CLIC channel (watchdog interrupt) |
neorv32_clic_trigger_irq(CLIC_CH_WDT); |
if (neorv32_wdt_available()) { |
cnt_test++; |
|
// wait some time for the IRQ to arrive the CPU |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
// configure WDT |
neorv32_wdt_setup(CLK_PRSC_2, 0); // lowest clock prescaler, trigger IRQ on timeout |
neorv32_wdt_reset(); // reset watchdog |
neorv32_wdt_force(); // force watchdog into action |
|
// wait some time for the IRQ to arrive the CPU |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == EXCCODE_MEI) { |
test_ok(); |
if (exception_handler_answer == TRAP_CODE_FIRQ_0) { |
test_ok(); |
} |
else { |
test_fail(); |
} |
#endif |
} |
else { |
test_fail(); |
neorv32_uart_printf("skipped (WDT not implemented)\n"); |
} |
#endif |
|
|
// ---------------------------------------------------------- |
// Test WFI ("sleep") instructions |
// Test WFI ("sleep") instructions, wakeup via MTIME |
// ---------------------------------------------------------- |
exception_handler_answer = 0xFFFFFFFF; |
neorv32_uart_printf("WFI: "); |
cnt_test++; |
|
// program timer to wake up |
neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + 1000); |
if (neorv32_mtime_available()) { |
cnt_test++; |
|
// put CPU into sleep mode |
asm volatile ("wfi"); |
// program timer to wake up |
neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + 1000); |
|
if (exception_handler_answer != EXCCODE_MTI) { |
test_fail(); |
// put CPU into sleep mode |
asm volatile ("wfi"); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer != TRAP_CODE_MTI) { |
test_fail(); |
} |
else { |
test_ok(); |
} |
#endif |
} |
else { |
test_ok(); |
neorv32_uart_printf("skipped (MTIME not implemented)\n"); |
} |
|
|
|
// error report |
// ---------------------------------------------------------- |
// Final test reports |
// ---------------------------------------------------------- |
neorv32_uart_printf("\n\nTests: %i\nOK: %i\nFAIL: %i\n\n", cnt_test, cnt_ok, cnt_fail); |
|
// final result |
/neorv32/trunk/sw/example/demo_pwm/main.c
70,7 → 70,7
|
// capture all exceptions and give debug info via UART |
// this is not required, but keeps us safe |
neorv32_rte_enable_debug_mode(); |
neorv32_rte_setup(); |
|
|
// init UART at default baud rate, no rx interrupt, no tx interrupt |
/neorv32/trunk/sw/example/demo_trng/main.c
76,7 → 76,7
|
// capture all exceptions and give debug info via UART |
// this is not required, but keeps us safe |
neorv32_rte_enable_debug_mode(); |
neorv32_rte_setup(); |
|
|
// init UART at default baud rate, no rx interrupt, no tx interrupt |
/neorv32/trunk/sw/example/demo_twi/main.c
40,6 → 40,7
**************************************************************************/ |
|
#include <neorv32.h> |
#include <string.h> |
|
|
/**********************************************************************//** |
79,7 → 80,7
|
// capture all exceptions and give debug info via UART |
// this is not required, but keeps us safe |
neorv32_rte_enable_debug_mode(); |
neorv32_rte_setup(); |
|
|
// init UART at default baud rate, no rx interrupt, no tx interrupt |
/neorv32/trunk/sw/example/demo_wdt/main.c
73,7 → 73,7
|
// capture all exceptions and give debug info via UART |
// this is not required, but keeps us safe |
neorv32_rte_enable_debug_mode(); |
neorv32_rte_setup(); |
|
|
// init UART at default baud rate, no rx interrupt, no tx interrupt |
/neorv32/trunk/sw/example/game_of_life/main.c
90,7 → 90,7
|
// capture all exceptions and give debug info via UART |
// this is not required, but keeps us safe |
neorv32_rte_enable_debug_mode(); |
neorv32_rte_setup(); |
|
|
// init UART at default baud rate, no rx interrupt, no tx interrupt |
/neorv32/trunk/sw/lib/include/neorv32_clic.h
File deleted
/neorv32/trunk/sw/lib/include/neorv32.h
64,7 → 64,7
|
CSR_MSCRATCH = 0x340, /**< 0x340 - mscratch (r/w): Machine scratch register */ |
CSR_MEPC = 0x341, /**< 0x341 - mepc (r/w): Machine exception program counter */ |
CSR_MCAUSE = 0x342, /**< 0x342 - mcause (r/w): Machine trap cause */ |
CSR_MCAUSE = 0x342, /**< 0x342 - mcause (r/-): Machine trap cause */ |
CSR_MTVAL = 0x343, /**< 0x343 - mtval (r/w): Machine bad address or instruction */ |
CSR_MIP = 0x344, /**< 0x344 - mip (r/w): Machine interrupt pending register */ |
|
101,9 → 101,14
* CPU <b>mie</b> CSR (r/w): Machine interrupt enable (RISC-V spec.) |
**************************************************************************/ |
enum NEORV32_CPU_MIE_enum { |
CPU_MIE_MSIE = 3, /**< CPU mie CSR (3): Machine software interrupt enable (r/w) */ |
CPU_MIE_MTIE = 7, /**< CPU mie CSR (7): Machine timer interrupt (MTIME) enable bit (r/w) */ |
CPU_MIE_MEIE = 11 /**< CPU mie CSR (11): Machine external interrupt (via CLIC) enable bit (r/w) */ |
CPU_MIE_MSIE = 3, /**< CPU mie CSR (3): Machine software interrupt enable (r/w) */ |
CPU_MIE_MTIE = 7, /**< CPU mie CSR (7): Machine timer interrupt enable bit (r/w) */ |
CPU_MIE_MEIE = 11, /**< CPU mie CSR (11): Machine external interrupt enable bit (r/w) */ |
|
CPU_MIE_FIRQ0E = 16, /**< CPU mie CSR (16): Fast interrupt channel 0 enable bit (r/w) */ |
CPU_MIE_FIRQ1E = 17, /**< CPU mie CSR (17): Fast interrupt channel 1 enable bit (r/w) */ |
CPU_MIE_FIRQ2E = 18, /**< CPU mie CSR (18): Fast interrupt channel 2 enable bit (r/w) */ |
CPU_MIE_FIRQ3E = 19 /**< CPU mie CSR (19): Fast interrupt channel 3 enable bit (r/w) */ |
}; |
|
|
111,9 → 116,14
* CPU <b>mip</b> CSR (r/-): Machine interrupt pending (RISC-V spec.) |
**************************************************************************/ |
enum NEORV32_CPU_MIP_enum { |
CPU_MIP_MSIP = 3, /**< CPU mip CSR (3): Machine software interrupt pending (r/-) */ |
CPU_MIP_MTIP = 7, /**< CPU mip CSR (7): Machine timer interrupt (MTIME) pending (r/-) */ |
CPU_MIP_MEIP = 11 /**< CPU mip CSR (11): Machine external interrupt (via CLIC) pending (r/-) */ |
CPU_MIP_MSIP = 3, /**< CPU mip CSR (3): Machine software interrupt pending (r/-) */ |
CPU_MIP_MTIP = 7, /**< CPU mip CSR (7): Machine timer interrupt pending (r/-) */ |
CPU_MIP_MEIP = 11, /**< CPU mip CSR (11): Machine external interrupt pending (r/-) */ |
|
CPU_MIP_FIRQ0P = 16, /**< CPU mip CSR (16): Fast interrupt channel 0 pending (r/-) */ |
CPU_MIP_FIRQ1P = 17, /**< CPU mip CSR (17): Fast interrupt channel 1 pending (r/-) */ |
CPU_MIP_FIRQ2P = 18, /**< CPU mip CSR (18): Fast interrupt channel 2 pending (r/-) */ |
CPU_MIP_FIRQ3P = 19 /**< CPU mip CSR (19): Fast interrupt channel 3 pending (r/-) */ |
}; |
|
|
133,40 → 143,25
|
|
/**********************************************************************//** |
* Exception IDs. |
* Trap codes from mcause CSR. |
**************************************************************************/ |
enum NEORV32_EXCEPTION_IDS_enum { |
EXCID_I_MISALIGNED = 0, /**< 0: Instruction address misaligned */ |
EXCID_I_ACCESS = 1, /**< 1: Instruction (bus) access fault */ |
EXCID_I_ILLEGAL = 2, /**< 2: Illegal instruction */ |
EXCID_BREAKPOINT = 3, /**< 3: Breakpoint (EBREAK instruction) */ |
EXCID_L_MISALIGNED = 4, /**< 4: Load address misaligned */ |
EXCID_L_ACCESS = 5, /**< 5: Load (bus) access fault */ |
EXCID_S_MISALIGNED = 6, /**< 6: Store address misaligned */ |
EXCID_S_ACCESS = 7, /**< 7: Store (bus) access fault */ |
EXCID_MENV_CALL = 11, /**< 11: Environment call from machine mode (ECALL instruction) */ |
EXCID_MSI = 19, /**< 16 + 3: Machine software interrupt */ |
EXCID_MTI = 23, /**< 16 + 7: Machine timer interrupt (via MTIME) */ |
EXCID_MEI = 27 /**< 16 + 11: Machine external interrupt (via CLIC) */ |
}; |
|
|
/**********************************************************************//** |
* Exception codes from mcause CSR. |
**************************************************************************/ |
enum NEORV32_EXCEPTION_CODES_enum { |
EXCCODE_I_MISALIGNED = 0x00000000, /**< 0: Instruction address misaligned */ |
EXCCODE_I_ACCESS = 0x00000001, /**< 1: Instruction (bus) access fault */ |
EXCCODE_I_ILLEGAL = 0x00000002, /**< 2: Illegal instruction */ |
EXCCODE_BREAKPOINT = 0x00000003, /**< 3: Breakpoint (EBREAK instruction) */ |
EXCCODE_L_MISALIGNED = 0x00000004, /**< 4: Load address misaligned */ |
EXCCODE_L_ACCESS = 0x00000005, /**< 5: Load (bus) access fault */ |
EXCCODE_S_MISALIGNED = 0x00000006, /**< 6: Store address misaligned */ |
EXCCODE_S_ACCESS = 0x00000007, /**< 7: Store (bus) access fault */ |
EXCCODE_MENV_CALL = 0x0000000b, /**< 11: Environment call from machine mode (ECALL instruction) */ |
EXCCODE_MSI = 0x80000003, /**< 16 + 3: Machine software interrupt */ |
EXCCODE_MTI = 0x80000007, /**< 16 + 7: Machine timer interrupt (via MTIME) */ |
EXCCODE_MEI = 0x8000000b /**< 16 + 11: Machine external interrupt (via CLIC) */ |
TRAP_CODE_I_MISALIGNED = 0x00000000, /**< 0.0: Instruction address misaligned */ |
TRAP_CODE_I_ACCESS = 0x00000001, /**< 0.1: Instruction (bus) access fault */ |
TRAP_CODE_I_ILLEGAL = 0x00000002, /**< 0.2: Illegal instruction */ |
TRAP_CODE_BREAKPOINT = 0x00000003, /**< 0.3: Breakpoint (EBREAK instruction) */ |
TRAP_CODE_L_MISALIGNED = 0x00000004, /**< 0.4: Load address misaligned */ |
TRAP_CODE_L_ACCESS = 0x00000005, /**< 0.5: Load (bus) access fault */ |
TRAP_CODE_S_MISALIGNED = 0x00000006, /**< 0.6: Store address misaligned */ |
TRAP_CODE_S_ACCESS = 0x00000007, /**< 0.7: Store (bus) access fault */ |
TRAP_CODE_MENV_CALL = 0x0000000b, /**< 0.11: Environment call from machine mode (ECALL instruction) */ |
TRAP_CODE_MSI = 0x80000003, /**< 1.3: Machine software interrupt */ |
TRAP_CODE_MTI = 0x80000007, /**< 1.7: Machine timer interrupt */ |
TRAP_CODE_MEI = 0x8000000b, /**< 1.11: Machine external interrupt */ |
TRAP_CODE_FIRQ_0 = 0x80000010, /**< 1.16: Fast interrupt channel 0 */ |
TRAP_CODE_FIRQ_1 = 0x80000011, /**< 1.17: Fast interrupt channel 1 */ |
TRAP_CODE_FIRQ_2 = 0x80000012, /**< 1.18: Fast interrupt channel 2 */ |
TRAP_CODE_FIRQ_3 = 0x80000013 /**< 1.19: Fast interrupt channel 3 */ |
}; |
|
|
235,53 → 230,6
|
|
/**********************************************************************//** |
* @name IO Device: Core Local Interrupts Controller (CLIC) |
**************************************************************************/ |
/**@{*/ |
/** CLIC control register (r/w) */ |
#define CLIC_CT (*(IO_REG32 0xFFFFFF88UL)) |
|
/** CLIC control register bits */ |
enum NEORV32_CLIC_CT_enum { |
CLIC_CT_SRC0 = 0, /**< CLIC control register(0) (r/-): IRQ source bit 0 */ |
CLIC_CT_SRC1 = 1, /**< CLIC control register(1) (r/-): IRQ source bit 1 */ |
CLIC_CT_SRC2 = 2, /**< CLIC control register(2) (r/-): IRQ source bit 2 */ |
CLIC_CT_ACK = 3, /**< CLIC control register(3) (-/w): Acknowledge current IRQ when set, auto-clears when set */ |
CLIC_CT_EN = 4, /**< CLIC control register(4) (r/w): Unit enable */ |
|
CLIC_CT_IRQ0_EN = 8, /**< CLIC control register(8) (r/w): Enable IRQ channel 0 */ |
CLIC_CT_IRQ1_EN = 9, /**< CLIC control register(9) (r/w): Enable IRQ channel 1 */ |
CLIC_CT_IRQ2_EN = 10, /**< CLIC control register(10) (r/w): Enable IRQ channel 2 */ |
CLIC_CT_IRQ3_EN = 11, /**< CLIC control register(11) (r/w): Enable IRQ channel 3 */ |
CLIC_CT_IRQ4_EN = 12, /**< CLIC control register(12) (r/w): Enable IRQ channel 4 */ |
CLIC_CT_IRQ5_EN = 13, /**< CLIC control register(13) (r/w): Enable IRQ channel 5 */ |
CLIC_CT_IRQ6_EN = 14, /**< CLIC control register(14) (r/w): Enable IRQ channel 6 */ |
CLIC_CT_IRQ7_EN = 15, /**< CLIC control register(15) (r/w): Enable IRQ channel 7 */ |
|
CLIC_CT_SW_IRQ_SRC0 = 16, /**< CLIC control register(16) (-/w): SW IRQ trigger, IRQ select bit 0, auto-clears when set */ |
CLIC_CT_SW_IRQ_SRC1 = 17, /**< CLIC control register(17) (-/w): SW IRQ trigger, IRQ select bit 1, auto-clears when set */ |
CLIC_CT_SW_IRQ_SRC2 = 18, /**< CLIC control register(18) (-/w): SW IRQ trigger, IRQ select bit 2, auto-clears when set */ |
CLIC_CT_SW_IRQ_EN = 19 /**< CLIC control register(19) (-/w): SW IRQ trigger enable, auto-clears when set */ |
}; |
/**@}*/ |
|
|
/**********************************************************************//** |
* Core-local interrupt controller IRQ channel |
**************************************************************************/ |
enum NEORV32_CLIC_CHANNELS_enum { |
CLIC_CH_WDT = 0, /**< CLIC channel 0: Watchdog timer overflow interrupt */ |
CLIC_CH_RES = 1, /**< CLIC channel 1: reserved */ |
CLIC_CH_GPIO = 2, /**< CLIC channel 2: GPIO pin-change interrupt */ |
CLIC_CH_UART = 3, /**< CLIC channel 3: UART RX available or TX done interrupt */ |
CLIC_CH_SPI = 4, /**< CLIC channel 4: SPI transmission done interrupt */ |
CLIC_CH_TWI = 5, /**< CLIC channel 5: TWI transmission done interrupt */ |
CLIC_CH_EXT0 = 6, /**< CLIC channel 6: Processor-external interrupt request 0 */ |
CLIC_CH_EXT1 = 7 /**< CLIC channel 7: Processor-external interrupt request 1 */ |
}; |
|
|
/**********************************************************************//** |
* @name IO Device: Watchdog Timer (WDT) |
**************************************************************************/ |
/**@{*/ |
543,7 → 491,7
SYSINFO_FEATURES_IO_TWI = 20, /**< SYSINFO_FEATURES (20) (r/-): Two-wire interface implemented when 1 (via IO_TWI_USE generic) */ |
SYSINFO_FEATURES_IO_PWM = 21, /**< SYSINFO_FEATURES (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_USE generic) */ |
SYSINFO_FEATURES_IO_WDT = 22, /**< SYSINFO_FEATURES (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_USE generic) */ |
SYSINFO_FEATURES_IO_CLIC = 23, /**< SYSINFO_FEATURES (23) (r/-): Core-local interrupt controller implemented when 1 (via IO_CLIC_USE generic) */ |
|
SYSINFO_FEATURES_IO_TRNG = 24, /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_USE generic) */ |
SYSINFO_FEATURES_IO_DEVNULL = 25 /**< SYSINFO_FEATURES (24) (r/-): Dummy device implemented when 1 (via IO_DEVNULL_USE generic) */ |
}; |
559,7 → 507,6
#include "neorv32_rte.h" |
|
// io/peripheral devices |
#include "neorv32_clic.h" |
#include "neorv32_gpio.h" |
#include "neorv32_mtime.h" |
#include "neorv32_pwm.h" |
/neorv32/trunk/sw/lib/include/neorv32_rte.h
42,10 → 42,32
#ifndef neorv32_rte_h |
#define neorv32_rte_h |
|
/**********************************************************************//** |
* RTE trap IDs. |
**************************************************************************/ |
enum NEORV32_RTE_TRAP_enum { |
RTE_TRAP_I_MISALIGNED = 0, /**< Instruction address misaligned */ |
RTE_TRAP_I_ACCESS = 1, /**< Instruction (bus) access fault */ |
RTE_TRAP_I_ILLEGAL = 2, /**< Illegal instruction */ |
RTE_TRAP_BREAKPOINT = 3, /**< Breakpoint (EBREAK instruction) */ |
RTE_TRAP_L_MISALIGNED = 4, /**< Load address misaligned */ |
RTE_TRAP_L_ACCESS = 5, /**< Load (bus) access fault */ |
RTE_TRAP_S_MISALIGNED = 6, /**< Store address misaligned */ |
RTE_TRAP_S_ACCESS = 7, /**< Store (bus) access fault */ |
RTE_TRAP_MENV_CALL = 8, /**< Environment call from machine mode (ECALL instruction) */ |
RTE_TRAP_MSI = 9, /**< Machine software interrupt */ |
RTE_TRAP_MTI = 10, /**< Machine timer interrupt */ |
RTE_TRAP_MEI = 11, /**< Machine external interrupt */ |
RTE_TRAP_FIRQ_0 = 12, /**< Fast interrupt channel 0 */ |
RTE_TRAP_FIRQ_1 = 13, /**< Fast interrupt channel 1 */ |
RTE_TRAP_FIRQ_2 = 14, /**< Fast interrupt channel 2 */ |
RTE_TRAP_FIRQ_3 = 15 /**< Fast interrupt channel 3 */ |
}; |
|
// prototypes |
void neorv32_rte_enable_debug_mode(void); |
int neorv32_rte_exception_install(uint8_t exc_id, void (*handler)(void)); |
int neorv32_rte_exception_uninstall(uint8_t exc_id); |
void neorv32_rte_setup(void); |
int neorv32_rte_exception_install(uint8_t id, void (*handler)(void)); |
int neorv32_rte_exception_uninstall(uint8_t id); |
|
void neorv32_rte_print_hw_config(void); |
void neorv32_rte_print_hw_version(void); |
/neorv32/trunk/sw/lib/source/neorv32_clic.c
File deleted
/neorv32/trunk/sw/lib/source/neorv32_cpu.c
53,7 → 53,8
**************************************************************************/ |
int neorv32_cpu_irq_enable(uint8_t irq_sel) { |
|
if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE)) { |
if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE) && |
(irq_sel != CPU_MIE_FIRQ0E) && (irq_sel != CPU_MIE_FIRQ1E) && (irq_sel != CPU_MIE_FIRQ2E) && (irq_sel != CPU_MIE_FIRQ3E)) { |
return 1; |
} |
|
71,7 → 72,8
**************************************************************************/ |
int neorv32_cpu_irq_disable(uint8_t irq_sel) { |
|
if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE)) { |
if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE) && |
(irq_sel != CPU_MIE_FIRQ0E) && (irq_sel != CPU_MIE_FIRQ1E) && (irq_sel != CPU_MIE_FIRQ2E) && (irq_sel != CPU_MIE_FIRQ3E)) { |
return 1; |
} |
|
/neorv32/trunk/sw/lib/source/neorv32_rte.c
42,30 → 42,34
#include "neorv32.h" |
#include "neorv32_rte.h" |
|
// Privates |
static void __neorv32_rte_dummy_exc_handler(void) __attribute__((unused)); |
/**********************************************************************//** |
* The >private< trap vector look-up table of the NEORV32 RTE. |
**************************************************************************/ |
static uint32_t __neorv32_rte_vector_lut[16] __attribute__((unused)); // trap handler vector table |
|
// private functions |
static void __attribute__((__interrupt__)) __neorv32_rte_core(void) __attribute__((aligned(16))) __attribute__((unused)); |
static void __neorv32_rte_debug_exc_handler(void) __attribute__((unused)); |
static void __neorv32_rte_print_true_false(int state) __attribute__((unused)); |
|
|
/**********************************************************************//** |
* Setup NEORV32 runtime environment in debug mode. |
* Setup NEORV32 runtime environment. |
* |
* @note This function installs a debug handler for ALL exception and interrupt sources, which |
* gives detailed information about the exception/interrupt. Call this function before you |
* install custom handler functions via neorv32_rte_exception_install(uint8_t exc_id, void (*handler)(void)), |
* since this function will override all installed exception handlers. |
* |
* @warning This function should be used for debugging only, since it only shows the uninitialize exception/interrupt, but |
* does not resolve the cause. Hence, it cannot guarantee to resume normal application execution after showing the debug messages. |
* gives detailed information about the exception/interrupt. Actual handler can be installed afterwards |
* via neorv32_rte_exception_install(uint8_t id, void (*handler)(void)). |
**************************************************************************/ |
void neorv32_rte_enable_debug_mode(void) { |
void neorv32_rte_setup(void) { |
|
uint8_t id; |
// configure trap handler base address |
uint32_t mtvec_base = (uint32_t)(&__neorv32_rte_core); |
neorv32_cpu_csr_write(CSR_MTVEC, mtvec_base); |
|
// install debug handler for all sources |
for (id=0; id<32; id++) { |
neorv32_rte_exception_install(id, __neorv32_rte_debug_exc_handler); |
uint8_t id; |
for (id = 0; id < (sizeof(__neorv32_rte_vector_lut)/sizeof(__neorv32_rte_vector_lut[0])); id++) { |
neorv32_rte_exception_uninstall(id); // this will configure the debug handler |
} |
} |
|
74,29 → 78,33
* Install exception handler function to NEORV32 runtime environment. |
* |
* @note This function automatically activates the according CSR.mie bits when installing handlers for |
* the MTIME (MTI), CLIC (MEI) or machine software interrupt (MSI). The global interrupt enable bit mstatus.mie has |
* the MTIME (MTI), CLIC (MEI), machine software interrupt (MSI) or a fast IRQ. The global interrupt enable bit mstatus.mie has |
* to be set by the user via neorv32_cpu_eint(void). |
* |
* @param[in] exc_id Identifier (type) of the targeted exception. See #NEORV32_EXCEPTION_IDS_enum. |
* @param[in] handler The actual handler function for the specified exception (function must be of type "void function(void);"). |
* return 0 if success, 1 if error (invalid exc_id or targeted exception not supported). |
* @param[in] id Identifier (type) of the targeted exception. See #NEORV32_RTE_TRAP_enum. |
* @param[in] handler The actual handler function for the specified exception (function MUST be of type "void function(void);"). |
* return 0 if success, 1 if error (invalid id or targeted exception not supported). |
**************************************************************************/ |
int neorv32_rte_exception_install(uint8_t exc_id, void (*handler)(void)) { |
int neorv32_rte_exception_install(uint8_t id, void (*handler)(void)) { |
|
// id valid? |
if ((exc_id == EXCID_I_MISALIGNED) || (exc_id == EXCID_I_ACCESS) || (exc_id == EXCID_I_ILLEGAL) || |
(exc_id == EXCID_BREAKPOINT) || (exc_id == EXCID_L_MISALIGNED) || (exc_id == EXCID_L_ACCESS) || |
(exc_id == EXCID_S_MISALIGNED) || (exc_id == EXCID_S_ACCESS) || (exc_id == EXCID_MENV_CALL) || |
(exc_id == EXCID_MSI) || (exc_id == EXCID_MTI) || (exc_id == EXCID_MEI)) { |
if ((id == RTE_TRAP_I_MISALIGNED) || (id == RTE_TRAP_I_ACCESS) || (id == RTE_TRAP_I_ILLEGAL) || |
(id == RTE_TRAP_BREAKPOINT) || (id == RTE_TRAP_L_MISALIGNED) || (id == RTE_TRAP_L_ACCESS) || |
(id == RTE_TRAP_S_MISALIGNED) || (id == RTE_TRAP_S_ACCESS) || (id == RTE_TRAP_MENV_CALL) || |
(id == RTE_TRAP_MSI) || (id == RTE_TRAP_MTI) || (id == RTE_TRAP_MEI) || |
(id == RTE_TRAP_FIRQ_0) || (id == RTE_TRAP_FIRQ_1) || (id == RTE_TRAP_FIRQ_2) || (id == RTE_TRAP_FIRQ_3)) { |
|
if (exc_id == EXCID_MSI) { neorv32_cpu_irq_enable(CPU_MIE_MSIE); } // activate software interrupt |
if (exc_id == EXCID_MTI) { neorv32_cpu_irq_enable(CPU_MIE_MTIE); } // activate timer interrupt |
if (exc_id == EXCID_MEI) { neorv32_cpu_irq_enable(CPU_MIE_MEIE); } // activate external interrupt |
|
uint32_t vt_base = SYSINFO_DSPACE_BASE; // base address of vector table |
vt_base = vt_base + (((uint32_t)exc_id) << 2); |
(*(IO_REG32 (vt_base))) = (uint32_t)handler; |
if (id == RTE_TRAP_MSI) { neorv32_cpu_irq_enable(CPU_MIE_MSIE); } // activate software interrupt |
if (id == RTE_TRAP_MTI) { neorv32_cpu_irq_enable(CPU_MIE_MTIE); } // activate timer interrupt |
if (id == RTE_TRAP_MEI) { neorv32_cpu_irq_enable(CPU_MIE_MEIE); } // activate external interrupt |
if (id == RTE_TRAP_FIRQ_0) { neorv32_cpu_irq_enable(CPU_MIE_FIRQ0E); } // activate fast interrupt channel 0 |
if (id == RTE_TRAP_FIRQ_1) { neorv32_cpu_irq_enable(CPU_MIE_FIRQ1E); } // activate fast interrupt channel 1 |
if (id == RTE_TRAP_FIRQ_2) { neorv32_cpu_irq_enable(CPU_MIE_FIRQ2E); } // activate fast interrupt channel 2 |
if (id == RTE_TRAP_FIRQ_3) { neorv32_cpu_irq_enable(CPU_MIE_FIRQ3E); } // activate fast interrupt channel 3 |
|
__neorv32_rte_vector_lut[id] = (uint32_t)handler; // install handler |
|
return 0; |
} |
return 1; |
105,30 → 113,33
|
/**********************************************************************//** |
* Uninstall exception handler function from NEORV32 runtime environment, which was |
* previously installed via neorv32_rte_exception_install(uint8_t exc_id, void (*handler)(void)). |
* previously installed via neorv32_rte_exception_install(uint8_t id, void (*handler)(void)). |
* |
* @note This function automatically clears the according CSR.mie bits when uninstalling handlers for |
* the MTIME (MTI), CLIC (MEI) or machine software interrupt (MSI). The global interrupt enable bit mstatus.mie has |
* the MTIME (MTI), CLIC (MEI), machine software interrupt (MSI) or fast IRQs. The global interrupt enable bit mstatus.mie has |
* to be cleared by the user via neorv32_cpu_dint(void). |
* |
* @param[in] exc_id Identifier (type) of the targeted exception. See #NEORV32_EXCEPTION_IDS_enum. |
* return 0 if success, 1 if error (invalid exc_id or targeted exception not supported). |
* @param[in] id Identifier (type) of the targeted exception. See #NEORV32_RTE_TRAP_enum. |
* return 0 if success, 1 if error (invalid id or targeted exception not supported). |
**************************************************************************/ |
int neorv32_rte_exception_uninstall(uint8_t exc_id) { |
int neorv32_rte_exception_uninstall(uint8_t id) { |
|
// id valid? |
if ((exc_id == EXCID_I_MISALIGNED) || (exc_id == EXCID_I_ACCESS) || (exc_id == EXCID_I_ILLEGAL) || |
(exc_id == EXCID_BREAKPOINT) || (exc_id == EXCID_L_MISALIGNED) || (exc_id == EXCID_L_ACCESS) || |
(exc_id == EXCID_S_MISALIGNED) || (exc_id == EXCID_S_ACCESS) || (exc_id == EXCID_MENV_CALL) || |
(exc_id == EXCID_MSI) || (exc_id == EXCID_MTI) || (exc_id == EXCID_MEI)) { |
if ((id == RTE_TRAP_I_MISALIGNED) || (id == RTE_TRAP_I_ACCESS) || (id == RTE_TRAP_I_ILLEGAL) || |
(id == RTE_TRAP_BREAKPOINT) || (id == RTE_TRAP_L_MISALIGNED) || (id == RTE_TRAP_L_ACCESS) || |
(id == RTE_TRAP_S_MISALIGNED) || (id == RTE_TRAP_S_ACCESS) || (id == RTE_TRAP_MENV_CALL) || |
(id == RTE_TRAP_MSI) || (id == RTE_TRAP_MTI) || (id == RTE_TRAP_MEI) || |
(id == RTE_TRAP_FIRQ_0) || (id == RTE_TRAP_FIRQ_1) || (id == RTE_TRAP_FIRQ_2) || (id == RTE_TRAP_FIRQ_3)) { |
|
if (exc_id == EXCID_MSI) { neorv32_cpu_irq_disable(CPU_MIE_MSIE); } // deactivate software interrupt |
if (exc_id == EXCID_MTI) { neorv32_cpu_irq_disable(CPU_MIE_MTIE); } // deactivate timer interrupt |
if (exc_id == EXCID_MEI) { neorv32_cpu_irq_disable(CPU_MIE_MEIE); } // deactivate external interrupt |
if (id == RTE_TRAP_MSI) { neorv32_cpu_irq_disable(CPU_MIE_MSIE); } // deactivate software interrupt |
if (id == RTE_TRAP_MTI) { neorv32_cpu_irq_disable(CPU_MIE_MTIE); } // deactivate timer interrupt |
if (id == RTE_TRAP_MEI) { neorv32_cpu_irq_disable(CPU_MIE_MEIE); } // deactivate external interrupt |
if (id == RTE_TRAP_FIRQ_0) { neorv32_cpu_irq_disable(CPU_MIE_FIRQ0E); } // deactivate fast interrupt channel 0 |
if (id == RTE_TRAP_FIRQ_1) { neorv32_cpu_irq_disable(CPU_MIE_FIRQ1E); } // deactivate fast interrupt channel 1 |
if (id == RTE_TRAP_FIRQ_2) { neorv32_cpu_irq_disable(CPU_MIE_FIRQ2E); } // deactivate fast interrupt channel 2 |
if (id == RTE_TRAP_FIRQ_3) { neorv32_cpu_irq_disable(CPU_MIE_FIRQ3E); } // deactivate fast interrupt channel 3 |
|
uint32_t vt_base = SYSINFO_DSPACE_BASE; // base address of vector table |
vt_base = vt_base + (((uint32_t)exc_id) << 2); |
(*(IO_REG32 (vt_base))) = (uint32_t)(&__neorv32_rte_dummy_exc_handler); // use dummy handler in case the exception is triggered |
__neorv32_rte_vector_lut[id] = (uint32_t)(&__neorv32_rte_debug_exc_handler); // use dummy handler in case the exception is accidently triggered |
|
return 0; |
} |
137,18 → 148,66
|
|
/**********************************************************************//** |
* NEORV32 runtime environment: Dummy exception handler (does nothing). |
* @note This function is used by neorv32_rte_exception_uninstall(uint8_t exc_id) only. |
* This is the core of the NEORV32 RTE. |
* |
* @note This function must no be explicitly used by the user. |
* @warning When using the the RTE, this function is the ONLY function that can use the 'interrupt' attribute! |
**************************************************************************/ |
static void __neorv32_rte_dummy_exc_handler(void) { |
static void __attribute__((__interrupt__)) __attribute__((aligned(16))) __neorv32_rte_core(void) { |
|
asm volatile("nop"); |
register uint32_t rte_mepc = neorv32_cpu_csr_read(CSR_MEPC); |
register uint32_t rte_mcause = neorv32_cpu_csr_read(CSR_MCAUSE); |
|
// compute return address |
if ((rte_mcause & 0x80000000) == 0) { // modify pc only if exception |
|
// get low half word of faulting instruction |
register uint32_t rte_trap_inst; |
asm volatile ("lh %[result], 0(%[input_i])" : [result] "=r" (rte_trap_inst) : [input_i] "r" (rte_mepc)); |
|
if ((rte_trap_inst & 3) == 3) { // faulting instruction is uncompressed instruction |
rte_mepc += 4; |
} |
else { // faulting instruction is compressed instruction |
rte_mepc += 2; |
} |
|
// store new return address |
neorv32_cpu_csr_write(CSR_MEPC, rte_mepc); |
} |
|
// find according trap handler |
register uint32_t rte_handler = (uint32_t)(&__neorv32_rte_debug_exc_handler); |
switch (rte_mcause) { |
case TRAP_CODE_I_MISALIGNED: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_I_MISALIGNED]; break; |
case TRAP_CODE_I_ACCESS: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_I_ACCESS]; break; |
case TRAP_CODE_I_ILLEGAL: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_I_ILLEGAL]; break; |
case TRAP_CODE_BREAKPOINT: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_BREAKPOINT]; break; |
case TRAP_CODE_L_MISALIGNED: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_L_MISALIGNED]; break; |
case TRAP_CODE_L_ACCESS: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_L_ACCESS]; break; |
case TRAP_CODE_S_MISALIGNED: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_S_MISALIGNED]; break; |
case TRAP_CODE_S_ACCESS: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_S_ACCESS]; break; |
case TRAP_CODE_MENV_CALL: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MENV_CALL]; break; |
case TRAP_CODE_MSI: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MSI]; break; |
case TRAP_CODE_MTI: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MTI]; break; |
case TRAP_CODE_MEI: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MEI]; break; |
case TRAP_CODE_FIRQ_0: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_0]; break; |
case TRAP_CODE_FIRQ_1: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_1]; break; |
case TRAP_CODE_FIRQ_2: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_2]; break; |
case TRAP_CODE_FIRQ_3: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_3]; break; |
default: break; |
} |
|
// execute handler |
void (*handler_pnt)(void); |
handler_pnt = (void*)rte_handler; |
(*handler_pnt)(); |
} |
|
|
/**********************************************************************//** |
* NEORV32 runtime environment: Debug exception handler, printing various exception/interrupt information via UART. |
* @note This function is used by neorv32_rte_enable_debug_mode(void) only. |
* @note This function is used by neorv32_rte_exception_uninstall(void) only. |
**************************************************************************/ |
static void __neorv32_rte_debug_exc_handler(void) { |
|
179,29 → 238,34
|
neorv32_uart_printf("Cause: "); |
switch (trap_cause) { |
case 0x00000000: neorv32_uart_printf("Instruction address misaligned"); break; |
case 0x00000001: neorv32_uart_printf("Instruction access fault"); break; |
case 0x00000002: neorv32_uart_printf("Illegal instruction"); break; |
case 0x00000003: neorv32_uart_printf("Breakpoint (EBREAK)"); break; |
case 0x00000004: neorv32_uart_printf("Load address misaligned"); break; |
case 0x00000005: neorv32_uart_printf("Load access fault"); break; |
case 0x00000006: neorv32_uart_printf("Store address misaligned"); break; |
case 0x00000007: neorv32_uart_printf("Store access fault"); break; |
case 0x0000000B: neorv32_uart_printf("Environment call (ECALL)"); break; |
case 0x80000003: neorv32_uart_printf("Machine software interrupt"); break; |
case 0x80000007: neorv32_uart_printf("Machine timer interrupt (via MTIME)"); break; |
case 0x8000000B: neorv32_uart_printf("Machine external interrupt (via CLIC)"); break; |
default: neorv32_uart_printf("Unknown (0x%x)", trap_cause); break; |
case TRAP_CODE_I_MISALIGNED: neorv32_uart_printf("Instruction address misaligned"); break; |
case TRAP_CODE_I_ACCESS: neorv32_uart_printf("Instruction access fault"); break; |
case TRAP_CODE_I_ILLEGAL: neorv32_uart_printf("Illegal instruction"); break; |
case TRAP_CODE_BREAKPOINT: neorv32_uart_printf("Breakpoint (EBREAK)"); break; |
case TRAP_CODE_L_MISALIGNED: neorv32_uart_printf("Load address misaligned"); break; |
case TRAP_CODE_L_ACCESS: neorv32_uart_printf("Load access fault"); break; |
case TRAP_CODE_S_MISALIGNED: neorv32_uart_printf("Store address misaligned"); break; |
case TRAP_CODE_S_ACCESS: neorv32_uart_printf("Store access fault"); break; |
case TRAP_CODE_MENV_CALL: neorv32_uart_printf("Environment call from M-mode"); break; |
case TRAP_CODE_MSI: neorv32_uart_printf("Machine software interrupt"); break; |
case TRAP_CODE_MTI: neorv32_uart_printf("Machine timer interrupt"); break; |
case TRAP_CODE_MEI: neorv32_uart_printf("Machine external interrupt"); break; |
case TRAP_CODE_FIRQ_0: neorv32_uart_printf("Fast interrupt channel 0"); break; |
case TRAP_CODE_FIRQ_1: neorv32_uart_printf("Fast interrupt channel 1"); break; |
case TRAP_CODE_FIRQ_2: neorv32_uart_printf("Fast interrupt channel 2"); break; |
case TRAP_CODE_FIRQ_3: neorv32_uart_printf("Fast interrupt channel 3"); break; |
default: neorv32_uart_printf("Unknown (0x%x)", trap_cause); break; |
} |
|
// fault address |
neorv32_uart_printf("\nFaulting instruction (low): 0x%x\n", trap_inst); |
neorv32_uart_printf("MTVAL: 0x%x\n", neorv32_cpu_csr_read(CSR_MTVAL)); |
neorv32_uart_printf("\nFaulting instruction (low half word): 0x%x", trap_inst); |
|
if ((trap_inst & 3) != 3) { |
neorv32_uart_printf("(decompressed)\n"); |
neorv32_uart_printf(" (decompressed)\n"); |
} |
|
neorv32_uart_printf("\nMTVAL: 0x%x\n", neorv32_cpu_csr_read(CSR_MTVAL)); |
|
neorv32_uart_printf("Trying to resume application @ 0x%x...", neorv32_cpu_csr_read(CSR_MEPC)); |
|
neorv32_uart_printf("\n<</NEORV32 Runtime Environment >>\n\n"); |
313,9 → 377,6
neorv32_uart_printf("WDT: "); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_WDT)); |
|
neorv32_uart_printf("CLIC: "); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_CLIC)); |
|
neorv32_uart_printf("TRNG: "); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TRNG)); |
|
/neorv32/trunk/README.md
20,24 → 20,28
|
## Introduction |
|
The NEORV32 is a customizable full-scale mikrocontroller-like processor system based on a [RISC-V-compliant](https://github.com/stnolting/neorv32_riscv_compliance) |
`rv32i` CPU with optional `E`, `C`, `M`, `Zicsr` and `Zifencei` extensions. The CPU was built from scratch and is compliant to the **Unprivileged |
ISA Specification Version 2.2** and a subset of the **Privileged Architecture Specification Version 1.12-draft**. |
The **NEORV32 processor** is a customizable full-scale mikrocontroller-like processor system based on the RISC-V-compliant |
`rv32i` NEORV32 CPU with optional `M`, `E`, `C` and `Zicsr` and `Zifencei` extensions. The CPU was built from scratch and |
is compliant to the *Unprivileged ISA Specification Version 2.2* and a subset of the *Privileged Architecture |
Specification Version 1.12-draft*. |
|
The NEORV32 is intended as auxiliary processor within a larger SoC designs or as stand-alone custom microcontroller. |
Its top entity can be directly synthesized for any FPGA without modifications and provides a full-scale RISC-V based microcontroller. |
The **processor** is intended as auxiliary processor within a larger SoC designs or as stand-alone |
custom microcontroller. Its top entity can be directly synthesized for any FPGA without modifications and |
provides a full-scale RISC-V based microcontroller with common peripherals like GPIO, serial interfaces for |
UART, I²C and SPI, timers, external bus interface and embedded memories. All optional features beyond the |
base CPU can be enabled and configured via VHDL generics. |
|
The processor provides common peripherals and interfaces like input and output ports, serial interfaces for UART, I²C and SPI, |
interrupt controller, timers and embedded memories. External memories, peripherals and custom IP can be attached via a |
Wishbone-based external memory interface. All optional features beyond the base CPU can be enabled and configured via VHDL generics. |
Alternatively, you can use the **NEORV32 CPU** as stand-alone central processing unit and build your own microcontroller |
or processor system around it. |
|
This project comes with a complete software ecosystem that features core libraries for high-level usage of the |
provided functions and peripherals, application makefiles, a runtime environment and several example programs. All software source files |
provide a doxygen-based [documentary](https://stnolting.github.io/neorv32/files.html). |
This project comes with a complete software ecosystem that features core libraries for high-level |
usage of the provided functions and peripherals, application makefiles, a runtime environment and |
several example programs. All software source files provide a doxygen-based documentary. |
|
The project is intended to work "out of the box". Just synthesize the test setup from this project, upload |
it to your FPGA board of choice and start playing with the NEORV32. If you do not want to [compile the GCC toolchains](https://github.com/riscv/riscv-gnu-toolchain) |
by yourself, you can also download [pre-compiled toolchains](https://github.com/stnolting/riscv_gcc_prebuilt) for Linux. |
The project is intended to work "out of the box". Just synthesize the test setup from this project, |
upload it to your FPGA board of choice and start playing with the NEORV32. If you do not want to |
[compile the GCC toolchains](https://github.com/riscv/riscv-gnu-toolchain) by yourself, you can also |
download [pre-compiled toolchains](https://github.com/stnolting/riscv_gcc_prebuilt) for Linux. |
|
For more information take a look a the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf). |
|
60,19 → 64,24
|
| Project component | CI status | Note | |
|:--------------------------------------------------------------------------------|:----------|:---------| |
| [NEORV32 processor](https://github.com/stnolting/neorv32) | [](https://travis-ci.com/stnolting/neorv32) | [](https://stnolting.github.io/neorv32/files.html) | |
| [Pre-built toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) | [](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) | | |
| [RISC-V compliance test](https://github.com/stnolting/neorv32_riscv_compliance) | [](https://travis-ci.com/stnolting/neorv32_riscv_compliance) | | |
| [NEORV32 processor](https://github.com/stnolting/neorv32) | [](https://travis-ci.com/stnolting/neorv32) | [](https://stnolting.github.io/neorv32/files.html) | |
| [Pre-built toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) | [](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) | | |
| [RISC-V compliance test](https://github.com/stnolting/neorv32_riscv_compliance) | [](https://travis-ci.com/stnolting/neorv32_riscv_compliance) | | |
|
|
### Non RISC-V-Compliant Issues |
|
* No exception is triggered in `E` mode when using registers above `x15` (*needs fixing*) |
* No exception is triggered for the `E` CPU extension when using registers above `x15` (*needs fixing*) |
* `misa` CSR is read-only - no dynamic enabling/disabling of implemented CPU extensions during runtime |
* Machine software interrupt `msi` is implemented, but there is no mechanism available to trigger it |
* `mcause` CSR is read-only |
* The `[m]cycleh` and `[m]instreth` CSR counters are only 20-bit wide (in contrast to original 32-bit) |
|
|
### Custom CPU Extensions |
|
* Four *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause` |
|
|
### To-Do / Wish List |
|
- Add instructions how to use the NEORV32 CPU without the processor surroundings |
93,7 → 102,7
|
 |
|
- RISC-V-compliant `rv32i` or `rv32e` CPU with optional `C`, `E`, `M`, `Zicsr` and `rv32Zifencei` extensions |
- RISC-V-compliant `rv32i` CPU with optional `C`, `E`, `M`, `Zicsr` and `rv32Zifencei` extensions |
- GCC-based toolchain ([pre-compiled rv32i and rv32 etoolchains available](https://github.com/stnolting/riscv_gcc_prebuilt)) |
- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile) |
- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html) |
113,7 → 122,6
- _Optional_ watchdog timer (WDT) |
- _Optional_ PWM controller with 4 channels and 8-bit duty cycle resolution (PWM) |
- _Optional_ GARO-based true random number generator (TRNG) |
- _Optional_ core-local interrupt controller with 8 channels (CLIC) |
- _Optional_ dummy device (DEVNULL) (can be used for *fast* simulation console output) |
- System configuration information memory to check hardware configuration by software (SYSINFO) |
|
159,7 → 167,7
* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI` |
* System instructions: `MRET` `WFI` |
* Counter CSRs: `[m]cycle[h]` `[m]instret[h]` `time[h]` |
* Machine CSRs: `mstatus` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mvendorid` `marchid` `mimpid` `mhartid` |
* Machine CSRs: `mstatus` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause`(read-only!) `mtval` `mip` `mvendorid` `marchid` `mimpid` `mhartid` |
* Supported exceptions and interrupts: |
* Misaligned instruction address |
* Instruction access fault |
186,35 → 194,36
|
### CPU |
|
Results generated for hardware version: `1.2.0.0` |
Results generated for hardware version: `1.3.0.0` |
|
| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max | |
|:---------------------------------|:----------:|:--------:|:-----------:|:----:|:-------:| |
| `rv32i` | 1065 | 477 | 2048 | 0 | 112 MHz | |
| `rv32i` + `Zicsr` + `Zifencei` | 1914 | 837 | 2048 | 0 | 100 MHz | |
| `rv32im` + `Zicsr` + `Zifencei` | 2542 | 1085 | 2048 | 0 | 100 MHz | |
| `rv32imc` + `Zicsr` + `Zifencei` | 2806 | 1102 | 2048 | 0 | 100 MHz | |
| `rv32emc` + `Zicsr` + `Zifencei` | 2783 | 1102 | 1024 | 0 | 100 MHz | |
| `rv32i` | 1122 | 481 | 2048 | 0 | 110 MHz | |
| `rv32i` + `Zicsr` + `Zifencei` | 1891 | 819 | 2048 | 0 | 100 MHz | |
| `rv32im` + `Zicsr` + `Zifencei` | 2496 | 1067 | 2048 | 0 | 100 MHz | |
| `rv32imc` + `Zicsr` + `Zifencei` | 2734 | 1066 | 2048 | 0 | 100 MHz | |
| `rv32emc` + `Zicsr` + `Zifencei` | 2722 | 1066 | 1024 | 0 | 100 MHz | |
|
### Processor-Internal Peripherals and Memories |
|
Results generated for hardware version: `1.2.0.0` |
Results generated for hardware version: `1.3.0.0` |
|
| Module | Description | LEs | FFs | Memory bits | DSPs | |
|:---------|:------------------------------------------------|:---:|:---:|:-----------:|:----:| |
| BOOT ROM | Bootloader ROM (4kB) | 3 | 1 | 32 768 | 0 | |
| DEVNULL | Dummy device | 3 | 1 | 0 | 0 | |
| DMEM | Processor-internal data memory (8kB) | 12 | 2 | 65 536 | 0 | |
| GPIO | General purpose input/output ports | 38 | 33 | 0 | 0 | |
| IMEM | Processor-internal instruction memory (16kb) | 7 | 2 | 131 072 | 0 | |
| MTIME | Machine system timer | 269 | 166 | 0 | 0 | |
| PWM | Pulse-width modulation controller | 76 | 69 | 0 | 0 | |
| SPI | Serial peripheral interface | 206 | 125 | 0 | 0 | |
| SYSINFO | System configuration information memory | 7 | 7 | 0 | 0 | |
| TRNG | True random number generator | 104 | 93 | 0 | 0 | |
| TWI | Two-wire interface | 78 | 44 | 0 | 0 | |
| UART | Universal asynchronous receiver/transmitter | 151 | 108 | 0 | 0 | |
| WDT | Watchdog timer | 57 | 45 | 0 | 0 | |
| Module | Description | LEs | FFs | Memory bits | DSPs | |
|:----------|:------------------------------------------------|:---:|:---:|:-----------:|:----:| |
| BOOT ROM | Bootloader ROM (4kB) | 4 | 1 | 32 768 | 0 | |
| BUSSWITCH | Mux for CPU I & D interfaces | 62 | 8 | 0 | 0 | |
| DEVNULL | Dummy device | 3 | 1 | 0 | 0 | |
| DMEM | Processor-internal data memory (8kB) | 12 | 2 | 65 536 | 0 | |
| GPIO | General purpose input/output ports | 40 | 33 | 0 | 0 | |
| IMEM | Processor-internal instruction memory (16kb) | 7 | 2 | 131 072 | 0 | |
| MTIME | Machine system timer | 266 | 166 | 0 | 0 | |
| PWM | Pulse-width modulation controller | 72 | 69 | 0 | 0 | |
| SPI | Serial peripheral interface | 198 | 125 | 0 | 0 | |
| SYSINFO | System configuration information memory | 10 | 9 | 0 | 0 | |
| TRNG | True random number generator | 105 | 93 | 0 | 0 | |
| TWI | Two-wire interface | 75 | 44 | 0 | 0 | |
| UART | Universal asynchronous receiver/transmitter | 153 | 108 | 0 | 0 | |
| WDT | Watchdog timer | 59 | 45 | 0 | 0 | |
|
|
### Exemplary FPGA Setups |
224,13 → 233,13
processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals |
to FPGA pins - except for the Wishbone bus and the interrupt signals. |
|
Results generated for hardware version: `1.2.0.6` |
Results generated for hardware version: `1.3.0.0` |
|
| Vendor | FPGA | Board | Toolchain | Impl. strategy |CPU | LUT / LE | FF / REG | DSP | Memory Bits | BRAM / EBR | SPRAM | Frequency | |
|:--------|:----------------------------------|:-----------------|:------------------------|:---------------|:---------------------------------|:-----------|:-----------|:-------|:-------------|:-----------|:---------|-------------:| |
| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 19.1 | balanced | `rv32imc` + `Zicsr` + `Zifencei` | 4035 (18%) | 1860 (8%) | 0 (0%) | 231424 (38%) | - | - | 101 MHz | |
| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (LSE) | timing | `rv32ic` + `Zicsr` + `Zifencei` | 5001 (95%) | 1694 (32%) | 0 (0%) | - | 12 (40%) | 4 (100%) | c 22.5 MHz | |
| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | default | `rv32imc` + `Zicsr` + `Zifencei` | 2509 (12%) | 1914 (5%) | 0 (0%) | - | 8 (16%) | - | c 100 MHz | |
| Vendor | FPGA | Board | Toolchain | Impl. strategy |CPU | LUT / LE | FF / REG | DSP | Memory Bits | BRAM / EBR | SPRAM | Frequency | |
|:--------|:----------------------------------|:-----------------|:------------------------|:---------------|:---------------------------------|:-----------|:-----------|:-------|:-------------|:-----------|:---------|---------------:| |
| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 19.1 | balanced | `rv32imc` + `Zicsr` + `Zifencei` | 3934 (18%) | 1799 (8%) | 0 (0%) | 231424 (38%) | - | - | 100 MHz | |
| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (LSE) | timing | `rv32ic` + `Zicsr` + `Zifencei` | 4895 (92%) | 1636 (31%) | 0 (0%) | - | 12 (40%) | 4 (100%) | *c* 22.875 MHz | |
| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | default | `rv32imc` + `Zicsr` + `Zifencei` | 2432 (12%) | 1852 (4%) | 0 (0%) | - | 8 (16%) | - | *c* 100 MHz | |
|
**Notes** |
* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DEMEM (each 64kb). |
247,21 → 256,21
[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark |
tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC. |
|
Results generated for hardware version: `1.2.0.0` |
Results generated for hardware version: `1.3.0.0` |
|
~~~ |
**Configuration** |
Hardware: 32kB IMEM, 16kB DMEM, 100MHz clock |
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK |
Compiler: RISCV32-GCC 9.2.0 |
Compiler: RISCV32-GCC 10.1.0 |
Peripherals: UART for printing the results |
~~~ |
|
| CPU | Optimization | CoreMark Score | CoreMarks/MHz | |
|:---------------------------------|:------------:|:--------------:|:-------------:| |
| `rv32i` + `Zicsr` + `Zifencei` | `-O2` | 25.97 | 0.2597 | |
| `rv32im` + `Zicsr` + `Zifencei` | `-O2` | 55.55 | 0.5555 | |
| `rv32imc` + `Zicsr` + `Zifencei` | `-O2` | 54.05 | 0.5405 | |
| CPU | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz | |
|:---------------------------------|:---------------:|:------------:|:--------------:|:-------------:| |
| `rv32i` + `Zicsr` + `Zifencei` | 21 600 bytes | `-O2` | 27.02 | 0.2702 | |
| `rv32im` + `Zicsr` + `Zifencei` | 20 976 bytes | `-O2` | 57.14 | 0.5714 | |
| `rv32imc` + `Zicsr` + `Zifencei` | 16 348 bytes | `-O2` | 57.14 | 0.5714 | |
|
|
### Instruction Cycles |
279,25 → 288,31
dividing the total number of required clock cycles (only the timed core to avoid distortion due to IO wait cycles; sampled via the `cycle[h]` CSRs) |
by the number of executed instructions (`instret[h]` CSRs). The executables were generated using optimization `-O2`. |
|
Results generated for hardware version: `1.2.0.0` |
Results generated for hardware version: `1.3.0.0` |
|
| CPU | Required Clock Cycles | Executed Instructions | Average CPI | |
|:---------------------------------|----------------------:|----------------------:|:-----------:| |
| `rv32i` + `Zicsr` + `Zifencei` | 7 754 927 850 | 1 492 843 669 | 5.2 | |
| `rv32im` + `Zicsr` + `Zifencei` | 3 684 015 850 | 626 274 115 | 5.9 | |
| `rv32imc` + `Zicsr` + `Zifencei` | 3 788 220 853 | 626 274 115 | 6.0 | |
| `rv32i` + `Zicsr` + `Zifencei` | 7 433 933 906 | 1 494 298 800 | 4.97 | |
| `rv32im` + `Zicsr` + `Zifencei` | 3 589 861 906 | 628 281 454 | 5.71 | |
| `rv32imc` + `Zicsr` + `Zifencei` | 3 587 131 226 | 628 282 016 | 5.70 | |
|
|
|
## Top Entity |
## Top Entities |
|
The top entity of the processor is [**neorv32_top.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) (from the `rtl/core` folder). |
The top entity of the **processor** is [**neorv32_top.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) (from the `rtl/core` folder). |
Just instantiate this file in your project and you are ready to go! All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively |
(except for the TWI signals, which are of type *std_logic*). |
|
Use the generics to configure the processor according to your needs. Each generic is initilized with the default configuration. |
The top entity of the **CPU** is [**neorv32_cpu.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd) (from the `rtl/core` folder). |
|
Use the generics to configure the processor/CPU according to your needs. Each generic is initilized with the default configuration. |
Detailed information regarding the signals and configuration generics can be found in the [NEORV32 documentary](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf). |
|
Alternative top entities can be found in [`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder. |
|
### Processor |
|
```vhdl |
entity neorv32_top is |
generic ( |
307,17 → 322,17
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])? |
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension? |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M : boolean := true; -- implement muld/div extension? |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.? |
-- Memory configuration: Instruction memory -- |
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space |
MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte |
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory |
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes |
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM |
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM |
-- Memory configuration: Data memory -- |
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space |
MEM_DSPACE_SIZE : natural := 8*1024; -- total size of data memory space in byte |
326,7 → 341,7
-- Memory configuration: External memory interface -- |
MEM_EXT_USE : boolean := false; -- implement external memory bus interface? |
MEM_EXT_REG_STAGES : natural := 2; -- number of interface register stages (0,1,2) |
MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout (>=1) |
MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout |
-- Processor peripherals -- |
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)? |
335,52 → 350,107
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)? |
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)? |
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)? |
); |
port ( |
-- Global control -- |
clk_i : in std_ulogic := '0'; -- global clock, rising edge |
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async |
clk_i : in std_ulogic := '0'; -- global clock, rising edge |
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async |
-- Wishbone bus interface (available if MEM_EXT_USE = true) -- |
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address |
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data |
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data |
wb_we_o : out std_ulogic; -- read/write |
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable |
wb_stb_o : out std_ulogic; -- strobe |
wb_cyc_o : out std_ulogic; -- valid cycle |
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge |
wb_err_i : in std_ulogic := '0'; -- transfer error |
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address |
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data |
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data |
wb_we_o : out std_ulogic; -- read/write |
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable |
wb_stb_o : out std_ulogic; -- strobe |
wb_cyc_o : out std_ulogic; -- valid cycle |
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge |
wb_err_i : in std_ulogic := '0'; -- transfer error |
-- Advanced memory control signals (available if MEM_EXT_USE = true) -- |
fence_o : out std_ulogic; -- indicates an executed FENCE operation |
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation |
fence_o : out std_ulogic; -- indicates an executed FENCE operation |
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation |
-- GPIO (available if IO_GPIO_USE = true) -- |
gpio_o : out std_ulogic_vector(15 downto 0); -- parallel output |
gpio_i : in std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input |
gpio_o : out std_ulogic_vector(15 downto 0); -- parallel output |
gpio_i : in std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input |
-- UART (available if IO_UART_USE = true) -- |
uart_txd_o : out std_ulogic; -- UART send data |
uart_rxd_i : in std_ulogic := '0'; -- UART receive data |
uart_txd_o : out std_ulogic; -- UART send data |
uart_rxd_i : in std_ulogic := '0'; -- UART receive data |
-- SPI (available if IO_SPI_USE = true) -- |
spi_sck_o : out std_ulogic; -- serial clock line |
spi_sdo_o : out std_ulogic; -- serial data line out |
spi_sdi_i : in std_ulogic := '0'; -- serial data line in |
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS |
spi_sck_o : out std_ulogic; -- SPI serial clock |
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in |
spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out |
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS |
-- TWI (available if IO_TWI_USE = true) -- |
twi_sda_io : inout std_logic := 'H'; -- twi serial data line |
twi_scl_io : inout std_logic := 'H'; -- twi serial clock line |
twi_sda_io : inout std_logic := 'H'; -- twi serial data line |
twi_scl_io : inout std_logic := 'H'; -- twi serial clock line |
-- PWM (available if IO_PWM_USE = true) -- |
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels |
-- Interrupts (available if IO_CLIC_USE = true) -- |
ext_irq_i : in std_ulogic_vector(01 downto 0) := (others => '0'); -- external interrupt request |
ext_ack_o : out std_ulogic_vector(01 downto 0) -- external interrupt request acknowledge |
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels |
-- Interrupts -- |
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt |
mext_irq_i : in std_ulogic := '0' -- machine external interrupt |
); |
end neorv32_top; |
``` |
|
### CPU |
|
```vhdl |
entity neorv32_cpu is |
generic ( |
-- General -- |
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])? |
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id |
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.? |
-- Bus Interface -- |
BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout |
); |
port ( |
-- global control -- |
clk_i : in std_ulogic := '0'; -- global clock, rising edge |
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async |
-- instruction bus interface -- |
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data |
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
i_bus_we_o : out std_ulogic; -- write enable |
i_bus_re_o : out std_ulogic; -- read enable |
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge |
i_bus_err_i : in std_ulogic := '0'; -- bus transfer error |
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation |
-- data bus interface -- |
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data |
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
d_bus_we_o : out std_ulogic; -- write enable |
d_bus_re_o : out std_ulogic; -- read enable |
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge |
d_bus_err_i : in std_ulogic := '0'; -- bus transfer error |
d_bus_fence_o : out std_ulogic; -- executed FENCE operation |
-- system time input from MTIME -- |
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time |
-- interrupts (risc-v compliant) -- |
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt |
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt |
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt |
-- fast interrupts (custom) -- |
firq_i : in std_ulogic_vector(3 downto 0) := (others => '0') |
); |
end neorv32_cpu; |
``` |
|
|
|
## Getting Started |
|
This overview is just a short excerpt from the *Let's Get It Started* section of the NEORV32 documentary: |
388,36 → 458,20
[ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) |
|
|
### Building the Toolchain |
### Toolchain |
|
At first you need the **RISC-V GCC toolchain**. You can either [download the sources](https://github.com/riscv/riscv-gnu-toolchain) |
and build the toolchain by yourself, or you can download a prebuilt one and install it. |
|
To build the toolchain by yourself, get the sources from the official [RISCV-GNU-TOOLCHAIN](https://github.com/riscv/riscv-gnu-toolchain) github page: |
:warning: Keep in mind that – for instance – a `rv32imc` toolchain only provides library code compiled with compressed and |
`mul`/`div` instructions! Hence, this code cannot be executed (without emulation) on an architecture without these extensions! |
|
$ git clone --recursive https://github.com/riscv/riscv-gnu-toolchain |
To build the toolchain by yourself, follow the official [build instructions](https://github.com/riscv/riscv-gnu-toolchain. |
Make sure to use the `ilp32` or `ilp32e` ABI. |
|
Download and install the prerequisite standard packages: |
Alternatively, you can download a prebuilt toolchain. I have uploaded the toolchain(s) I am using to GitHub. This toolchain |
has been compiled on a 64-bit x86 Ubuntu (Ubuntu on Windows, actually). Download the toolchain of choice: |
|
$ sudo apt-get install autoconf automake autotools-dev curl python3 libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev |
|
To build the Linux cross-compiler, pick an install path. If you choose, say, `/opt/riscv`, then add `/opt/riscv/bin` to your `PATH` environment variable. |
|
$ export PATH:$PATH:/opt/riscv/bin |
|
Then, simply run the following commands in the RISC-V GNU toolchain source folder (for the `rv32i` toolchain): |
|
riscv-gnu-toolchain$ ./configure --prefix=/opt/riscv --with-arch=rv32i –with-abi=ilp32 |
riscv-gnu-toolchain$ make |
|
After a while (hours!) you will get `riscv32-unknown-elf-gcc` and all of its friends in your `/opt/riscv/bin` folder. |
|
|
### Using a Prebuilt Toolchain |
|
Alternatively, you can download a prebuilt toolchain. I have uploaded the toolchain I am using to GitHub. This toolchain |
has been compiled on a 64-bit x86 Ubuntu (Ubuntu on Windows). Download the toolchain of choice: |
|
[https://github.com/stnolting/riscv_gcc_prebuilt](https://github.com/stnolting/riscv_gcc_prebuilt) |
|
|
599,6 → 653,6
|
This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org). |
|
. |
|
|
Made with :coffee: in Hannover, Germany. |