URL https://opencores.org/ocsvn/or1k/or1k/trunk

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Rev 13 → Rev 14

/trunk/gen_or1k_isa/tmp/isa.aux

0,0 → 1,7

/trunk/gen_or1k_isa/tmp/isa.tex

0,0 → 1,6760

/trunk/gen_or1k_isa/tmp/body.tex

0,0 → 1,6701

/trunk/gen_or1k_isa/tmp/isa.log

0,0 → 1,1323

/trunk/gen_or1k_isa/tmp/isa.dvi Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/trunk/gen_or1k_isa/tmp/isa.dvi

trunk/gen_or1k_isa/tmp/isa.dvi Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/gen_or1k_isa/gen_or1k_isa =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/gen_or1k_isa/gen_or1k_isa =================================================================== --- trunk/gen_or1k_isa/gen_or1k_isa (nonexistent) +++ trunk/gen_or1k_isa/gen_or1k_isa (revision 14)

trunk/gen_or1k_isa/gen_or1k_isa Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/gen_or1k_isa/sources/gen_or1k_isa.c =================================================================== --- trunk/gen_or1k_isa/sources/gen_or1k_isa.c (nonexistent) +++ trunk/gen_or1k_isa/sources/gen_or1k_isa.c (revision 14) @@ -0,0 +1,296 @@ + +#include + +#define NO_RELOC 20 +#define RELOC_32 1 +#define RELOC_8 2 +#define RELOC_CONST 3 +#define RELOC_CONSTH 4 + +#include "or1.h" +#include "or1k_isadesc.h" + +/* types of data in encoding field. */ +typedef enum { opcode, reserved, operand } encfld_types; + +/* encoding transformed for TeX output */ +struct { + int bitpos[33]; + int fldcnt; + int insn_size; + struct { + encfld_types type; + int value; + int bitsize; + } field[50]; +} decoded; + +void print_encoding() +{ + int i, j; + + printf("\\vspace{10mm}\n"); + printf("{\\centering \\begin{tabular}{"); + + /* organization of the table */ + for(i = 1; i <= decoded.fldcnt; i++) { + printf("|"); + for(j = 0; j < decoded.field[i].bitsize; j++) + printf("c"); + } + printf("|}\n\\hline\n"); + + /* print first row of the table */ + for(i = decoded.insn_size - 1; i > 0; i--) + if (decoded.bitpos[i]) + printf("%d&\n", i); + else + printf("&\n"); + printf("0\\\\\n\\hline\n"); + + /* print second row of the table */ + for(i = 1; i <= decoded.fldcnt; i++) { + if (decoded.field[i].type == opcode) { + printf("\\multicolumn{%d}{", decoded.field[i].bitsize); + printf("%s", (i == 1 ? "|":"")); + printf("c|}{opcode 0x%x}", decoded.field[i].value); + } else if (decoded.field[i].type == operand) { + printf("\\multicolumn{%d}{", decoded.field[i].bitsize); + printf("%s", (i == 1 ? "|":"")); + printf("c|}{%c}", decoded.field[i].value); + } else if (decoded.field[i].type == reserved) { + printf("\\multicolumn{%d}{", decoded.field[i].bitsize); + printf("%s", (i == 1 ? "|":"")); + printf("c|}{reserved}", decoded.field[i].value); + } + if (i == decoded.fldcnt) + printf("\\\\\n"); + else + printf("&\n"); + } + printf("\n\\hline\n"); + + /* print third row of the table */ + for(i = 1; i < decoded.fldcnt; i++) { + printf("\\multicolumn{%d}", decoded.field[i].bitsize); + printf("{%sc|}{%d bits}&\n", (i == 1 ? "|":""), decoded.field[i].bitsize); + } + printf("\\multicolumn{%d}", decoded.field[i].bitsize); + printf("{%sc|}{%d bits}\\\\\n", (i == 1 ? "|":""), decoded.field[i].bitsize); + printf("\n\\hline\n"); + printf("\\end{tabular}\\par}\n"); + +} + +void decode(struct or1_opcode *insn) +{ + int opc_pos = 0; + char *enc; + encfld_types last; + char lastoperand; + int tmp; + + if (!insn) { + printf("internal error: insn pointer NULL\n"); + return; + } + + memset(&decoded, 0, sizeof(decoded)); + + if ((insn->name[0] == 'h') && (insn->name[1] == '.')) + decoded.insn_size = opc_pos = 16; + else + decoded.insn_size = opc_pos = 32; + + last = -1; + + for (enc = insn->encoding; *enc != '\0'; ) + if ((*enc == '0') && (*(enc+1) == 'x')) { + int tmp = strtol(enc, NULL, 16); + if (last != opcode) { + decoded.bitpos[opc_pos] = 1; + decoded.bitpos[opc_pos - 1] = 1; + decoded.field[++decoded.fldcnt].type = opcode; + } + decoded.field[decoded.fldcnt].value <<= 4; + decoded.field[decoded.fldcnt].value += tmp; + decoded.field[decoded.fldcnt].bitsize += 4; + opc_pos -= 4; + enc += 3; + last = opcode; + } + else if (*enc == '0') { + if (last != opcode) { + decoded.bitpos[opc_pos] = 1; + decoded.bitpos[opc_pos - 1] = 1; + decoded.field[++decoded.fldcnt].type = opcode; + } + decoded.field[decoded.fldcnt].value <<= 1; + decoded.field[decoded.fldcnt].bitsize += 1; + opc_pos--; + enc++; + last = opcode; + } + else if (*enc == '-') { + if (last != reserved) { + decoded.bitpos[opc_pos] = 1; + decoded.bitpos[opc_pos - 1] = 1; + decoded.field[++decoded.fldcnt].type = reserved; + } + decoded.field[decoded.fldcnt].value <<= 1; + decoded.field[decoded.fldcnt].bitsize += 1; + opc_pos--; + enc++; + last = reserved; + } + else if (*enc == '1') { + if (last != opcode) { + decoded.bitpos[opc_pos] = 1; + decoded.bitpos[opc_pos - 1] = 1; + decoded.field[++decoded.fldcnt].type = opcode; + } + decoded.field[decoded.fldcnt].value <<= 1; + decoded.field[decoded.fldcnt].value += 1; + decoded.field[decoded.fldcnt].bitsize += 1; + opc_pos--; + enc++; + last = opcode; + } + else if (isalpha(*enc)) { + if ((last != operand) || (lastoperand != *enc)) { + decoded.bitpos[opc_pos] = 1; + decoded.bitpos[opc_pos - 1] = 1; + decoded.field[++decoded.fldcnt].type = operand; + } + decoded.field[decoded.fldcnt].value = *enc; + decoded.field[decoded.fldcnt].bitsize += 1; + opc_pos--; + lastoperand = *enc; + enc++; + last = operand; + } + else + enc++; +} + +void print_header(struct or1_opcode *insn, struct or1k_isa *info) +{ + printf("\n\n\\newpage\n"); + printf("\\vspace{10mm}\n"); + /* printf("\\section{Appendix A}\n"); */ + printf("\\lyxline{\\small}\\vspace{-1\\parskip}\n"); + printf("\\vspace{10mm}\n"); + printf("{\\raggedright \\begin{tabular}{ccc}\n"); + printf("\\textbf{\\textcolor{white}{\\small Left}}\\textcolor{white}{\\small }&\n"); + printf("\\textcolor{white}{\\small }\\textbf{\\textcolor{white}{\\small Middle Middle\n"); + printf("Middle Middle Middle Middle Middle Middle}} \\textcolor{white}{\\small }&\n"); + printf("\\textcolor{white}{\\small }\\textbf{\\textcolor{white}{\\small Right}}\\\\\n"); + printf("\\textbf{\\huge %s}&\n", insn->name); + printf("\\multicolumn{1}{c}{\\textbf{\\huge %s}}&\n", info->title); + printf("\\textbf{\\huge %s}\\\\\n", insn->name); + printf("\\end{tabular}\\par}\n\\bigskip{}\n\n"); +} + +struct or1k_isa *get_or1k_isa(char *name) +{ + int i; + + for (i = 0; strlen(or1k_isa_info[i].name); i++) + if (strcmp(or1k_isa_info[i].name, name) == 0) + break; + + return &or1k_isa_info[i]; +} + +void transform_tex(char *input, char *output) +{ + while (*input != '\0') { + if (*input == '[') { + *output++ = '{'; + *output++ = '['; + *output++ = '}'; + } else if (*input == ']') { + *output++ = '{'; + *output++ = ']'; + *output++ = '}'; + } else if (*input == '\\') { + *output++ = '\\'; + *output++ = '\\'; + } else + *output++ = *input; + input++; + } + *output = '\0'; +} + +void print_body(struct or1_opcode *insn, struct or1k_isa *info) +{ + char tmp[2000]; + + printf("\\vspace{15mm}\n"); + + printf("{\\par\\raggedright \\textbf{\\LARGE Format:}\\LARGE \\par}\n"); + printf("\\vspace{5mm}\n"); + printf("\\begin{quotation}\n"); + printf("\\texttt{\\large %s\\ %s}{\\large \\par}\n", insn->name, insn->args); + printf("\\end{quotation}\n"); + printf("\\vspace{10mm}\n"); + + printf("\\textbf{\\LARGE Description:}{\\LARGE \\par}\n"); + printf("\\vspace{5mm}\n"); + printf("\\begin{quotation}\n"); + printf("\\texttt{\\large %s}{\\large \\par}\n", info->desc); + printf("\\end{quotation}\n"); + printf("\\vspace{10mm}\n"); + + printf("\\textbf{\\LARGE Operation:}{\\LARGE \\par}\n"); + printf("\\vspace{5mm}\n"); + printf("\\begin{quotation}\n"); + transform_tex(info->oper, tmp); + printf("%s\n", tmp); + printf("\\end{quotation}\n"); + printf("\\vspace{10mm}\n"); + + printf("\\textbf{\\LARGE Notes:}{\\LARGE \\par}\n"); + printf("\\vspace{5mm}\n"); + printf("\\begin{quotation}\n"); + printf("\n"); + printf("\\end{quotation}\n"); + printf("\\vspace{10mm}\n"); + + printf("\\vfill\n"); + printf("%s: \n", or1k_isa_classes[info->class].title); + printf("{\\centering \\begin{tabular}{|c|c|c|}\n"); + printf("\\hline\n"); + printf("Architecture Level&\n"); + printf("Execution Mode&\n"); + printf("Implementation\\\\\n"); + printf("\\hline\n"); + printf("%s\n", or1k_isa_classes[info->class].table); + printf("\\hline\n"); + printf("\\end{tabular}\\par}\n"); + + printf("\n"); +} + +int main() +{ + int i; + struct or1k_isa *info; + + printf("\n\\begin{document}\n\\vspace{50mm}"); + printf("\\section{OpenRISC 1000 Instruction Set}\n"); + printf("Draft, Do not distribute\n"); + + for(i = 0; strlen(or1_opcodes[i].name); i++) { + + info = get_or1k_isa(or1_opcodes[i].name); + + print_header(&or1_opcodes[i], info); + decode(&or1_opcodes[i]); + print_encoding(); + print_body(&or1_opcodes[i], info); + } + printf("\n\\end{document}\n"); + return 0; +} Index: trunk/gen_or1k_isa/sources/header.tex =================================================================== --- trunk/gen_or1k_isa/sources/header.tex (nonexistent) +++ trunk/gen_or1k_isa/sources/header.tex (revision 14) @@ -0,0 +1,59 @@ +%% This LaTeX-file was created by Sun Nov 7 03:44:37 1999 +%% LyX 1.0 (C) 1995-1999 by Matthias Ettrich and the LyX Team + +%% Do not edit this file unless you know what you are doing. +\documentclass[oneside]{amsbook} +\usepackage[T1]{fontenc} +\usepackage{fancyhdr} +%% \pagestyle{headings} +\usepackage{color} + +\makeatletter + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% LyX specific LaTeX commands. +\providecommand{\LyX}{L\kern-.1667em\lower.25em\hbox{Y}\kern-.125emX\@} +\newcommand{\lyxline}[1]{ + {#1 \vspace{1ex} \hrule width \columnwidth \vspace{1ex}} +} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% Textclass specific LaTeX commands. +\numberwithin{section}{chapter} +\theoremstyle{plain} +\newtheorem{thm}{Theorem}[section] +\numberwithin{equation}{section} %% Comment out for sequentially-numbered +\numberwithin{figure}{section} %% Comment out for sequentially-numbered + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% User specified LaTeX commands. +\usepackage[T1]{fontenc} +\usepackage{a4wide} +\usepackage{color} + +\makeatletter + + +\usepackage[T1]{fontenc} +\usepackage{geometry} +\geometry{verbose,a4paper,lmargin=20mm,rmargin=20mm} + +\makeatletter + + +\usepackage[T1]{fontenc} +\usepackage{a4} +\pagestyle{fancy} + +\makeatletter + + +\usepackage[T1]{fontenc} + +\makeatletter +\makeatother +\makeatother +\makeatother + + +\makeatother + Index: trunk/gen_or1k_isa/sources/or1k_isadesc.h =================================================================== --- trunk/gen_or1k_isa/sources/or1k_isadesc.h (nonexistent) +++ trunk/gen_or1k_isa/sources/or1k_isadesc.h (revision 14) @@ -0,0 +1,475 @@ +/* Information about OR1K ISA. W/o this we can't generate or1k_isa_part.tex. +*/ + +struct or1k_isa { + char *name; + char *title; + char *desc; + char *oper; + char *except; + int class; +}; + +static struct or1k_isa or1k_isa_info[] = +{ + +{"l.addi32s", "Add Immediate Signed", + "Immediate is signed-extended and added to the contents of general " + "register rB to form the result. The result is placed into general " + "register rA.", + "rA <- rB + exts(Immediate)", "Integer Overflow", 1,}, + +{"l.subi32s", "Subtract Immediate Signed", + "Immediate is signed-extended and subtracted from the contents of general " + "register rB to form the result. The result is placed into general " + "register rA.", + "rA <- rB - exts(Immediate)", "Integer Overflow", 1,}, + +{"l.sub32s", "Subtract Signed", + "The contents of general register rC is subtracted from the contents " + "of general register rB to form the result. The result is placed into " + "general register rA.", + "rA <- rB - rC", "Integer Overflow", 1,}, + +{"h.add32s", "Add Signed", + "The contents of general register rC is added to the contents " + "of general register rB to form the result. The result is placed into " + "general register rA.", + "rA <- rB + rC", "Integer Overflow", 1,}, + +{"h.ext16s", "Extend Half Word with Sign", + "Bit 15 of general register rA is placed in high-order 16 bits of " + "general register rA. The low-order 16 bits of general register rA " + "are left unchanged.", + "rA[31:16] <- rA[15]", "None", 2,}, + +{"h.ext8s", "Extend Byte with Sign", + "Bit 7 of general register rA is placed in high-order 24 bits of " + "general register rA. The low-order eight bits of general register rA " + "are left unchanged.", + "rA[31:8] <- rA[7]", "None", 2,}, + +{"h.ext8z", "Extend Byte with Zero", + "Zero is placed in high-order 24 bits of " + "general register rA. The low-order eight bits of general register rA " + "are left unchanged.", + "rA[31:8] <- 0", "None", 2,}, + +{"h.ext16z", "Extend Half Word with Zero", + "Zero is placed in high-order 16 bits of " + "general register rA. The low-order 16 bits of general register rA " + "are left unchanged.", + "rA[31:16] <- 0", "None", 2,}, + +{"l.load8s", "Load Byte and Extend with Sign", + "Offset is sign-extended and added to the contents of general " + "register rB. Sum represents effective address. The byte in memory " + "addressed by EA is loaded into the low-order eight bits of " + "general register rA. " + "High-order 24 bits of general register rA are replaced with " + "bit 7 of the loaded value.", + "EA <- exts(Immediate) + rB\\rA[7:0] <- (EA)[7:0]\\rA[31:8] <- rA[8]", + "TLB miss\\Page fault\\Bus error", 1,}, + +{"l.load16s", "Load Half Word and Extend with Sign", + "Offset is sign-extended and added to the contents of general " + "register rB. Sum represents effective address. The half word in memory " + "addressed by EA is loaded into the low-order 16 bits of " + "general register rA. " + "High-order 16 bits of general register rA are replaced with " + "bit 15 of the loaded value.", + "EA <- exts(Immediate) + rB\\rA[15:0] <- (EA)[15:0]\\rA[31:16] <- rA[15]", + "TLB miss\\Page fault\\Bus error", 1,}, + +{"l.load8u", "Load Byte and Extend with Zero", + "Offset is sign-extended and added to the contents of general " + "register rB. Sum represents effective address. The byte in memory " + "addressed by EA is loaded into the low-order eight bits of " + "general register rA. " + "High-order 24 bits of general register rA are replaced with " + "zero.", + "EA <- exts(Immediate) + rB\\rA[7:0] <- (EA)[7:0]\\rA[31:8] <- 0", + "TLB miss\\Page fault\\Bus error", 1,}, + +{"l.load16u", "Load Half Word and Extend with Zero", + "Offset is sign-extended and added to the contents of general " + "register rB. Sum represents effective address. The half word in memory " + "addressed by EA is loaded into the low-order 16 bits of " + "general register rA. " + "High-order 16 bits of general register rA are replaced with " + "zero.", + "EA <- exts(Immediate) + rB\\rA[15:0] <- (EA)[15:0]\\rA[31:16] <- 0", + "TLB miss\\Page fault\\Bus error", 1,}, + +{"l.load32u", "Load Word and Extend with Zero", + "Offset is sign-extended and added to the contents of general " + "register rB. Sum represents effective address. The word in memory " + "addressed by EA is loaded into general register rA. ", + "EA <- exts(Immediate) + rB\\rA <- (EA)[31:0]", + "TLB miss\\Page fault\\Bus error", 1,}, + +{"h.load32u", "Load Word and Extend with Zero", + "Offset is sign-extended and added to the contents of general " + "register rB. Sum represents effective address. The word in memory " + "addressed by EA is loaded into general register rA. ", + "EA <- exts(Immediate) + rB\\rA <- (EA)[31:0]", + "TLB miss\\Page fault\\Bus error", 2,}, + +{"l.stor32", "Store Word", + "Offset is sign-extended and added to the contents of general " + "register rA. Sum represents effective address. The word in " + "general register rB is stored to memory addressed by EA. ", + "EA <- exts(Immediate) + rA\\(EA)[31:0] <- rB", + "TLB miss\\Page fault\\Bus error", 1,}, + +{"h.stor32", "Store Word", + "Offset is sign-extended and added to the contents of general " + "register rA. Sum represents effective address. The word in " + "general register rB is stored to memory addressed by EA. ", + "EA <- exts(Immediate) + rA\\(EA)[31:0] <- rB", + "TLB miss\\Page fault\\Bus error", 2,}, + +{"l.stor16", "Store Half Word", + "Offset is sign-extended and added to the contents of general " + "register rA. Sum represents effective address. The low-order 16 bits " + "of general register rB are stored to memory addressed by EA. ", + "EA <- exts(Immediate) + rA\\(EA)[15:0] <- rB[15:0]", + "TLB miss\\Page fault\\Bus error", 1,}, + +{"l.stor8", "Store Byte", + "Offset is sign-extended and added to the contents of general " + "register rA. Sum represents effective address. The low-order 8 bits " + "of general register rB are stored to memory addressed by EA. ", + "EA <- exts(Immediate) + rA\\(EA)[7:0] <- rB[7:0]", + "TLB miss\\Page fault\\Bus error", 1,}, + +{"l.shla32", "Shift Left Arithmetic", + "Immediate is combined with low-order 5 bits of general register rC " + "in a bit-wise logical OR operation. The result specifies the number of " + "bit positions the contents of general register rB are shifted left, " + "inserting zeros into the low-order bits.", + "b <- Immediate | rC\\rA[31:b] <- rB[31-b:0]\\rA[b:0] <- 0", + "None", 1,}, + +{"l.shra32", "Shift Right Arithmetic", + "Immediate is combined with low-order 5 bits of general register rC " + "in a bit-wise logical OR operation. The result specifies the number of " + "bit positions the contents of general register rB are shifted right, " + "sign-extending the high-order bits.", + "b <- Immediate | rC\\rA[31-b:0] <- rB[31:b]\\rA[31-b:31] <- rB[31]", + "None", 1,}, + +{"l.shrl32", "Shift Right Logical", + "Immediate is combined with low-order 5 bits of general register rC " + "in a bit-wise logical OR operation. The result specifies the number of " + "bit positions the contents of general register rB are shifted right, " + "inserting zeros into the high-order bits.", + "b <- Immediate | rC\\rA[31-b:0] <- rB[31:b]\\rA[31-b:31] <- 0", + "None", 1,}, + +{"l.and32", "And", + "The contents of general register rB are combined with the contents " + "of general register rC in a bit-wise logical AND operation. The " + "result is placed into general register rA.", + "rA <- rB AND rC", + "None", 1,}, + +{"l.or32", "Or", + "The contents of general register rB are combined with the contents " + "of general register rC in a bit-wise logical OR operation. The " + "result is placed into general register rA.", + "rA <- rB OR rC", + "None", 1,}, + +{"l.xor32", "Exclusive Or", + "The contents of general register rB are combined with the contents " + "of general register rC in a bit-wise logical XOR operation. The " + "result is placed into general register rA.", + "rA <- rB XOR rC", + "None", 1,}, + +{"l.xori16", "Exclusive Or Immediate Half Word", + "Immediate is zero-extended and combined with the contents of general " + "register rB in a bit-wise logical XOR operation. The result is " + "placed into general register rA.", + "rA <- rB XOR exts(Immediate)", "None", 3,}, + +{"l.muli32s", "Multiply Immediate Signed", + "Immediate and the contents of general register rB are " + "multiplied and the result is truncated to 32 bits and placed into " + "general register rA.", + "rA <- rB * Immediate", "None", 2,}, + +{"l.mul32s", "Multiply Signed", + "The contents of general register rB and the contents of general " + "register rC are multiplied and the result is truncated to 32 " + "bits and placed into general register rA. Both operands are treated " + "as unsigned integers.", + "rA <- rB * rC", "None", 2,}, + +{"l.mul32u", "Multiply Unsigned", + "The contents of general register rB and the contents of general " + "register rC are multiplied and the result is truncated to 32 " + "bits and placed into general register rA. Both operands are treated " + "as unsigned integers.", + "rA <- rB * rC", "None", 2,}, + +{"l.div32s", "Divide Signed", + "The contents of general register rB are divided by the contents of " + "general register rC and the result is placed into general register " + "rA. Both operands are treated as signed integers. A divisor " + "flag is set when the divisor is zero.", + "rA <- rB / rC", "None", 3,}, + +{"l.div32u", "Divide Unsigned", + "The contents of general register rB are divided by the contents of " + "general register rC and the result is placed into general register " + "rA. Both operands are treated as unsigned integers. A divisor " + "flag is set when the divisor is zero.", + "rA <- rB / rC", "None", 3,}, + +{"h.sfeq32", "Set Flag if Equal", + "The contents of general register rA and the contents of general " + "register rB are compared. If the two registers are equal, " + "then the compare flag is set; otherwise the compare flag is cleared.", + "flag <- rA == rB", "None", 1,}, + +{"h.sfne32", "Set Flag if Not Equal", + "The contents of general register rA and the contents of general " + "register rB are compared. If the two registers are not equal, " + "then the compare flag is set; otherwise the compare flag is cleared.", + "flag <- rA != rB", "None", 1,}, + +{"h.sfgt32s", "Set Flag if Greater Than Signed", + "The contents of general register rA and the contents of general " + "register rB are compared as signed integers. If the contents " + "of the first register are greater than the contents of the second " + "register, " + "then the compare flag is set; otherwise the compare flag is cleared.", + "flag <- rA > rB", "None", 1,}, + +{"h.sfge32s", "Set Flag if Greater or Equal Than Signed", + "The contents of general register rA and the contents of general " + "register rB are compared as signed integers. If the contents " + "of the first register are greater or equal than the contents of the second " + "register, " + "then the compare flag is set; otherwise the compare flag is cleared.", + "flag <- rA >= rB", "None", 1,}, + +{"h.sflt32s", "Set Flag if Less Than Signed", + "The contents of general register rA and the contents of general " + "register rB are compared as signed integers. If the contents " + "of the first register are less than the contents of the second " + "register, " + "then the compare flag is set; otherwise the compare flag is cleared.", + "flag <- rA < rB", "None", 1,}, + +{"h.sfle32s", "Set Flag if Less or Equal Than Signed", + "The contents of general register rA and the contents of general " + "register rB are compared as signed integers. If the contents " + "of the first register are less or equal than the contents of the second " + "register, " + "then the compare flag is set; otherwise the compare flag is cleared.", + "flag <- rA <= rB", "None", 1,}, + +{"h.sfgt32u", "Set Flag if Greater Than Unsigned", + "The contents of general register rA and the contents of general " + "register rB are compared as unsigned integers. If the contents " + "of the first register are greater than the contents of the second " + "register, " + "then the compare flag is set; otherwise the compare flag is cleared.", + "flag <- rA > rB", "None", 1,}, + +{"h.sfge32u", "Set Flag if Greater or Equal Than Unsigned", + "The contents of general register rA and the contents of general " + "register rB are compared as unsigned integers. If the contents " + "of the first register are greater or equal than the contents of the second " + "register, " + "then the compare flag is set; otherwise the compare flag is cleared.", + "flag <- rA >= rB", "None", 1,}, + +{"h.sflt32u", "Set Flag if Less Than Unsigned", + "The contents of general register rA and the contents of general " + "register rB are compared as unsigned integers. If the contents " + "of the first register are less than the contents of the second " + "register, " + "then the compare flag is set; otherwise the compare flag is cleared.", + "flag <- rA < rB", "None", 1,}, + +{"h.sfle32u", "Set Flag if Less or Equal Than Unsigned", + "The contents of general register rA and the contents of general " + "register rB are compared as unsigned integers. If the contents " + "of the first register are less or equal than the contents of the second " + "register, " + "then the compare flag is set; otherwise the compare flag is cleared.", + "flag <- rA <= rB", "None", 1,}, + + +{"l.mtsr", "Move To Special Register", + "The contents of general register rA are moved into special register " + "rS.", + "rS <- rA", "None", 4,}, + +{"l.mfsr", "Move From Special Register", + "The contents of special register rS are moved into general register " + "rA.", + "rA <- rS", "None", 4,}, + +{"h.mov32", "Move", + "The contents of general register rB are moved into general register " + "rA.", + "rA <- rB", "None", 2,}, + +{"h.immch32s", "Immediate Byte Signed", + "8 bit immediate is sign-extended to 32 bits and placed into general " + "register rA.", + "rA <- exts(Immediate)", "None", 2,}, + +{"l.immlo16u", "Immediate Low-Order Half Word Unsigned", + "16 bit immediate is placed into low-order 16 bits of general " + "register rA.", + "rA[15:0] <- Immediate", "None", 1,}, + +{"l.immhi16u", "Immediate High-Order Half Word Unsigned", + "16 bit immediate is placed into high-order 16 bits of general " + "register rA.", + "rA[31:16] <- Immediate", "None", 1,}, + +{"l.bf", "Branch if Flag", + "The immediate is shifted left two bits, sign-extended to " + "32 bits and then added to the address of the delay slot. The result " + "is effective address of the branch. If the compare flag is set, " + "then the program branches " + "to EA with a delay of one 32 bit or two 16 bit instructions.", + "EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag set", + "None", 1,}, + +{"l.bnf", "Branch if No Flag", + "The immediate is shifted left two bits, sign-extended to " + "32 bits and then added to the address of the delay slot. The result " + "is effective address of the branch. If the compare flag is cleared, " + "then the program branches " + "to EA with a delay of one 32 bit or two 16 bit instructions.", + "EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag cleared", + "None", 1,}, + +{"h.bf", "Branch if Flag", + "The immediate is shifted left two bits, sign-extended to " + "32 bits and then added to the address of the delay slot. The result " + "is effective address of the branch. If the compare flag is set, " + "then the program branches " + "to EA with a delay of one 32 bit or two 16 bit instructions.", + "EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag set", + "None", 2,}, + +{"h.bnf", "Branch if No Flag", + "The immediate is shifted left two bits, sign-extended to " + "32 bits and then added to the address of the delay slot. The result " + "is effective address of the branch. If the compare flag is cleared, " + "then the program branches " + "to EA with a delay of one 32 bit or two 16 bit instructions.", + "EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag cleared", + "None", 2,}, + +{"l.jal", "Jump and Link", + "The immediate is shifted left two bits, sign-extended to " + "32 bits and then added to the address of the delay slot. The result " + "is effective address of the jump. The program unconditionally jumps " + "to EA with a delay of one 32 bit or two 16 bit instructions. The " + "address of the instruction after the delay slot is placed in the " + "link register. ", + "PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4", "None", 1,}, + +{"l.j", "Jump", + "The immediate is shifted left two bits, sign-extended to " + "32 bits and then added to the address of the delay slot. The result " + "is effective address of the jump. The program unconditionally jumps " + "to EA with a delay of one 32 bit or two 16 bit instructions.", + "PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4", "None", 1,}, + +{"h.j", "Jump", + "The immediate is shifted left two bits, sign-extended to " + "32 bits and then added to the address of the delay slot. The result " + "is effective address of the jump. The program unconditionally jumps " + "to EA with a delay of one 32 bit or two 16 bit instructions.", + "PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4", "None", 2,}, + +{"h.jal", "Jump and Link", + "The immediate is shifted left two bits, sign-extended to " + "32 bits and then added to the address of the delay slot. The result " + "is effective address of the jump. The program unconditionally jumps " + "to EA with a delay of one 32 bit or two 16 bit instructions. The " + "address of the instruction after the delay slot is placed in the " + "link register. ", + "PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4", "None", 2,}, + +{"h.jalr", "Jump and Link Register", + "The contents of general register rA " + "is effective address of the jump. The program unconditionally jumps " + "to EA with a delay of one 32 bit or two 16 bit instructions. The " + "address of the instruction after the delay slot is placed in the " + "link register. ", + "PC <- rA\\LR <- DelayInsnAddr + 4", "None", 1,}, + +{"l.illegal", "Illegal instruction", + "The result of this instruction is always an illegal instruction " + "exception.", + "PC <- address of illegal instruction exception handler", "None", 1,}, + +{"h.nop", "No Operation", + "This instruction does not do anything except it takes at least one " + "clock cycle to complete. It is usually used to fill gaps between " + "16 bit and 32 bit instructions.", + "", "None", 1,}, + +{"h.sched", "Schedule", + "Immediate carries static scheduling information about instruction " + "scheduling. This information is generated by an optimizing compiler.", + "", "None", 3,}, + +{"h.movi32", "Move 32 bit Immediate", + "For simulator. Obsolete", "N/A", "N/A", 0,}, + +{"simrdtsc", "Simulate Read Timer", + "For simulator. Obsolete.", "N/A", "N/A", 0,}, + +{"simprintf", "Simulate printf", + "For simulator. Obsolete.", "N/A", "N/A", 0,}, + +{"l.dcbf", "Data Cache Block Flush", + "TBD", "", "", 5,}, + +{"l.dcbt", "Data Cache Block Touch", + "TBD", "", "", 5,}, + +{"l.dcbi", "Data Cache Block Invalidate", + "TBD", "", "", 5,}, + +{"l.dcia", "Data Cache Invalidate All", + "TBD", "", "", 5,}, + +{"l.dcfa", "Data Cache Flush All", + "TBD", "", "", 5,}, + +{"l.tlbia", "TLB Invalidate All", + "TBD", "", "", 6,}, + +{"", "", "", "", "", 0} + +}; + +struct or1k_isa_classes { + char *title; + char *desc; + char *table; +} or1k_isa_classes[] = { + +{ "Class 0", "Invalid instruction class", "&&\\\\", }, +{ "Class 1", "x", "Core CPU&User and Supervisor&Mandatory always\\\\", }, +{ "Class 2", "x", "Core CPU&User and Supervisor&Recommended\\\\", }, +{ "Class 3", "x", "Core CPU&User and Supervisor&Optional\\\\", }, +{ "Class 4", "x", "System Management&Supervisor only&Mandatory always\\\\", }, +{ "Class 5", "x", "Cache Management&Supervisor only&Mandatory if cache supported\\\\", }, +{ "Class 6", "x", "Virtual Memory&Supervisor only&Mandatory if MMU supported\\\\", }, + +}; Index: trunk/gen_or1k_isa/Makefile =================================================================== --- trunk/gen_or1k_isa/Makefile (nonexistent) +++ trunk/gen_or1k_isa/Makefile (revision 14) @@ -0,0 +1,21 @@ + +all: gen_or1k_isa generate + +gen_or1k_isa: sources/gen_or1k_isa.c sources/or1k_isadesc.h sources/or1.h Makefile + gcc -O2 -o gen_or1k_isa sources/gen_or1k_isa.c + +generate: gen_or1k_isa sources/header.tex + ./gen_or1k_isa > tmp/body.tex + cat sources/header.tex tmp/body.tex > tmp/isa.tex + latex tmp/isa.tex; mv isa.* tmp; dvips -o result/or1k_isa.ps tmp/isa.dvi + rm -f texput.log + ./ps2pdf result/or1k_isa.ps result/or1k_isa.pdf + pslatex tmp/isa.tex; mv isa.* tmp; dvips -o result/or1k_isa_distiller.ps tmp/isa.dvi + rm -f texput.log + +distclean: clean + rm -f gen_or1k_isa + rm -f result/* + +clean: + rm -f tmp/* Index: trunk/gen_or1k_isa/README =================================================================== --- trunk/gen_or1k_isa/README (nonexistent) +++ trunk/gen_or1k_isa/README (revision 14) @@ -0,0 +1,36 @@ + +This utility generates OR1K ISA document (isa.pdf) from two files: + +- or1k_desc.h instruction description included with this utility +- or1.h instruction encoding included in egcs-1.1.2.tar.gz available from + opencores web site. + File is egcs-1.1.2/binutils-2.9.1/include/opcode/or1.h. + +To generate final LaTeX, PostScript and Adobe PDF you need header.tex +(included in sources directory) and the following utilities: + +- latex package (Web2C 7.3.1) (for converting isa.tex to isa.dvi) +- (Omega) odvips(k) 5.86 from Radical Eye Software (www.radicaleye.com) + (for converting isa.dvi to or1k_isa.ps) +- GNU Ghostscript 5.10 (1998-12-17) + (for converting or1k_isa.ps to or1k_isa.pdf; perhaps even better utility is + Adobe's Acrobat Distiller) + +First create s symbolic link sources/or1.h to +egcs-1.1.2/binutils-2.9.1/include/opcode/or1.h. Then execute + +# make gen_or1k_isa + +and you should get generation utility. Then execute + +# make generate + +and you should get result/or1k_isa.ps and result/or1k_isa.pdf (you might need +to punch CR a couple of times during latex -> dvi conversion due to some +bus in isa.tex). Also you'll get result/or1k_isa.ps that should be converted +to PDF with Adobe's Acrobat Distiller to get nice looking PDF (I think +GhostScript generated PDF has some problems with fonts). + +-- + +4/Mar/2000, Damjan Lampret email:lampret@opencores.org Index: trunk/gen_or1k_isa/result/or1k_isa.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/gen_or1k_isa/result/or1k_isa.pdf =================================================================== --- trunk/gen_or1k_isa/result/or1k_isa.pdf (nonexistent) +++ trunk/gen_or1k_isa/result/or1k_isa.pdf (revision 14)

trunk/gen_or1k_isa/result/or1k_isa.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/gen_or1k_isa/result/or1k_isa_distiller.ps =================================================================== --- trunk/gen_or1k_isa/result/or1k_isa_distiller.ps (nonexistent) +++ trunk/gen_or1k_isa/result/or1k_isa_distiller.ps (revision 14) @@ -0,0 +1,2636 @@ +%!PS-Adobe-2.0 +%%Creator: dvips(k) 5.86 Copyright 1999 Radical Eye Software +%%Title: tmp/isa.dvi +%%Pages: 70 +%%PageOrder: Ascend +%%BoundingBox: 0 0 596 842 +%%DocumentFonts: Times-Bold Times-Roman Courier +%%EndComments +%DVIPSWebPage: (www.radicaleye.com) +%DVIPSCommandLine: dvips -o result/or1k_isa_distiller.ps tmp/isa.dvi +%DVIPSParameters: dpi=600, compressed +%DVIPSSource: TeX output 2000.03.04:0315 +%%BeginProcSet: texc.pro +%! +/TeXDict 300 dict def TeXDict begin/N{def}def/B{bind def}N/S{exch}N/X{S +N}B/A{dup}B/TR{translate}N/isls false N/vsize 11 72 mul N/hsize 8.5 72 +mul N/landplus90{false}def/@rigin{isls{[0 landplus90{1 -1}{-1 1}ifelse 0 +0 0]concat}if 72 Resolution div 72 VResolution div neg scale isls{ +landplus90{VResolution 72 div vsize mul 0 exch}{Resolution -72 div hsize +mul 0}ifelse TR}if Resolution VResolution vsize -72 div 1 add mul TR[ +matrix currentmatrix{A A round sub abs 0.00001 lt{round}if}forall round +exch round exch]setmatrix}N/@landscape{/isls true N}B/@manualfeed{ +statusdict/manualfeed true put}B/@copies{/#copies X}B/FMat[1 0 0 -1 0 0] +N/FBB[0 0 0 0]N/nn 0 N/IEn 0 N/ctr 0 N/df-tail{/nn 8 dict N nn begin +/FontType 3 N/FontMatrix fntrx N/FontBBox FBB N string/base X array +/BitMaps X/BuildChar{CharBuilder}N/Encoding IEn N end A{/foo setfont}2 +array copy cvx N load 0 nn put/ctr 0 N[}B/sf 0 N/df{/sf 1 N/fntrx FMat N +df-tail}B/dfs{div/sf X/fntrx[sf 0 0 sf neg 0 0]N df-tail}B/E{pop nn A +definefont setfont}B/Cw{Cd A length 5 sub get}B/Ch{Cd A length 4 sub get +}B/Cx{128 Cd A length 3 sub get sub}B/Cy{Cd A length 2 sub get 127 sub} +B/Cdx{Cd A length 1 sub get}B/Ci{Cd A type/stringtype ne{ctr get/ctr ctr +1 add N}if}B/id 0 N/rw 0 N/rc 0 N/gp 0 N/cp 0 N/G 0 N/CharBuilder{save 3 +1 roll S A/base get 2 index get S/BitMaps get S get/Cd X pop/ctr 0 N Cdx +0 Cx Cy Ch sub Cx Cw add Cy setcachedevice Cw Ch true[1 0 0 -1 -.1 Cx +sub Cy .1 sub]/id Ci N/rw Cw 7 add 8 idiv string N/rc 0 N/gp 0 N/cp 0 N{ +rc 0 ne{rc 1 sub/rc X rw}{G}ifelse}imagemask restore}B/G{{id gp get/gp +gp 1 add N A 18 mod S 18 idiv pl S get exec}loop}B/adv{cp add/cp X}B +/chg{rw cp id gp 4 index getinterval putinterval A gp add/gp X adv}B/nd{ +/cp 0 N rw exit}B/lsh{rw cp 2 copy get A 0 eq{pop 1}{A 255 eq{pop 254}{ +A A add 255 and S 1 and or}ifelse}ifelse put 1 adv}B/rsh{rw cp 2 copy +get A 0 eq{pop 128}{A 255 eq{pop 127}{A 2 idiv S 128 and or}ifelse} +ifelse put 1 adv}B/clr{rw cp 2 index string putinterval adv}B/set{rw cp +fillstr 0 4 index getinterval putinterval adv}B/fillstr 18 string 0 1 17 +{2 copy 255 put pop}for N/pl[{adv 1 chg}{adv 1 chg nd}{1 add chg}{1 add +chg nd}{adv lsh}{adv lsh nd}{adv rsh}{adv rsh nd}{1 add adv}{/rc X nd}{ +1 add set}{1 add clr}{adv 2 chg}{adv 2 chg nd}{pop nd}]A{bind pop} +forall N/D{/cc X A type/stringtype ne{]}if nn/base get cc ctr put nn +/BitMaps get S ctr S sf 1 ne{A A length 1 sub A 2 index S get sf div put +}if put/ctr ctr 1 add N}B/I{cc 1 add D}B/bop{userdict/bop-hook known{ +bop-hook}if/SI save N @rigin 0 0 moveto/V matrix currentmatrix A 1 get A +mul exch 0 get A mul add .99 lt{/QV}{/RV}ifelse load def pop pop}N/eop{ +SI restore userdict/eop-hook known{eop-hook}if showpage}N/@start{ +userdict/start-hook known{start-hook}if pop/VResolution X/Resolution X +1000 div/DVImag X/IEn 256 array N 2 string 0 1 255{IEn S A 360 add 36 4 +index cvrs cvn put}for pop 65781.76 div/vsize X 65781.76 div/hsize X}N +/p{show}N/RMat[1 0 0 -1 0 0]N/BDot 260 string N/Rx 0 N/Ry 0 N/V{}B/RV/v{ +/Ry X/Rx X V}B statusdict begin/product where{pop false[(Display)(NeXT) +(LaserWriter 16/600)]{A length product length le{A length product exch 0 +exch getinterval eq{pop true exit}if}{pop}ifelse}forall}{false}ifelse +end{{gsave TR -.1 .1 TR 1 1 scale Rx Ry false RMat{BDot}imagemask +grestore}}{{gsave TR -.1 .1 TR Rx Ry scale 1 1 false RMat{BDot} +imagemask grestore}}ifelse B/QV{gsave newpath transform round exch round +exch itransform moveto Rx 0 rlineto 0 Ry neg rlineto Rx neg 0 rlineto +fill grestore}B/a{moveto}B/delta 0 N/tail{A/delta X 0 rmoveto}B/M{S p +delta add tail}B/b{S p tail}B/c{-4 M}B/d{-3 M}B/e{-2 M}B/f{-1 M}B/g{0 M} +B/h{1 M}B/i{2 M}B/j{3 M}B/k{4 M}B/w{0 rmoveto}B/l{p -4 w}B/m{p -3 w}B/n{ +p -2 w}B/o{p -1 w}B/q{p 1 w}B/r{p 2 w}B/s{p 3 w}B/t{p 4 w}B/x{0 S +rmoveto}B/y{3 2 roll p a}B/bos{/SS save N}B/eos{SS restore}B end + +%%EndProcSet +%%BeginProcSet: 8r.enc +% @@psencodingfile@{ +% author = "S. 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Fg(Class)26 b(3:)p 926 5710 2229 +4 v 924 5809 4 100 v 967 5779 a(Arc)n(hitecture)h(Lev)n(el)p +1677 5809 V 154 w(Execution)h(Mo)r(de)p 2497 5809 V 155 +w(Implemen)n(tation)p 3152 5809 V 926 5813 2229 4 v 924 +5912 4 100 v 1114 5882 a(Core)e(CPU)p 1677 5912 V 231 +w(User)h(and)g(Sup)r(ervisor)p 2497 5912 V 208 w(Optional)p +3152 5912 V 926 5915 2229 4 v Black 1839 6065 a(70)p +Black eop +%%Trailer +end +userdict /end-hook known{end-hook}if +%%EOF

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