URL
https://opencores.org/ocsvn/rc4-prbs/rc4-prbs/trunk
Subversion Repositories rc4-prbs
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- This comparison shows the changes necessary to convert path
/
- from Rev 13 to Rev 14
- ↔ Reverse comparison
Rev 13 → Rev 14
/rc4-prbs/trunk/rc4.inc
18,4 → 18,4
*/ |
|
|
`define KEY_SIZE 8 |
`define KEY_SIZE 7 |
/rc4-prbs/trunk/rc4_tb.v
70,13 → 70,18
/* Simulation */ |
integer q; |
initial begin |
password[0] = 8'h53; // 'S' |
password[1] = 8'h65; // 'e' |
password[2] = 8'h63; // 'c' |
password[3] = 8'h72; // 'r' |
password[4] = 8'h65; // 'e' |
password[5] = 8'h74; // 't' |
// Test vector: "Secret" --> "04 d4 6b 05 3c a8 7b 59" |
password[0] = 8'h01; // Testvectors http://tools.ietf.org/html/draft-josefsson-rc4-test-vectors-02#page-4 |
password[1] = 8'h02; // |
password[2] = 8'h03; // |
password[3] = 8'h04; // |
password[4] = 8'h05; // |
password[5] = 8'h06; // |
password[6] = 8'h07; // |
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// Key length: 56 bits. |
// key: 0x01020304050607 |
// DEC 0 HEX 0: 29 3f 02 d4 7f 37 c9 b6 33 f2 af 52 85 fe b4 6b |
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$display ("Start..."); |
clk = 0; |
rst = 1; |
84,7 → 89,7
password_input=password[clkcount]; |
#(1*tck) |
rst = 0; |
#(program_cycles*tck+100) |
#(program_cycles*tck+100000) |
$display ("Finish."); |
$finish; |
end |
/rc4-prbs/trunk/rc4.v
2,6 → 2,7
RC4 PRGA module implementation |
Copyright 2012 - Alfredo Ortega |
aortega@alu.itba.edu.ar |
aortega@groundworkstech.com |
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This library is free software: you can redistribute it and/or |
modify it under the terms of the GNU Lesser General Public |
18,7 → 19,7
*/ |
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`include "rc4.inc" |
`include "/home/guest/docto/FPGADesign/rc4-prbs/trunk/rc4.inc" |
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module rc4(clk,rst,output_ready,password_input,K); |
|
48,7 → 49,6
`define KSS_KEYSCHED2 4'h2 |
`define KSS_KEYSCHED3 4'h3 |
`define KSS_CRYPTO 4'h4 |
`define KSS_CRYPTO2 4'h5 |
// Variable names from http://en.wikipedia.org/wiki/RC4 |
reg [3:0] KSState; |
reg [7:0] i; // Counter |
75,7 → 75,7
else begin |
i <= i+1; |
key[i] <= password_input; |
$display ("key[%d] = %08X",i,password_input); |
$display ("rc4: key[%d] = %08X",i,password_input); |
end |
end |
/* |
110,8 → 110,9
begin |
KSState <= `KSS_CRYPTO; |
i <= 8'h01; |
j <= 8'h00; |
j <= S[1]; |
discardCount <= 10'h0; |
output_ready <= 0; // K not valid yet |
end |
else begin |
i <= i + 1; |
129,20 → 130,21
output K |
endwhile |
*/ |
`KSS_CRYPTO: begin //KSS_CRYPTO: Output crypto stream |
j <= (j + S[i]); |
KSState <= `KSS_CRYPTO2; |
output_ready <= 0; // K not valid yet |
end |
`KSS_CRYPTO2: begin |
`KSS_CRYPTO: begin |
S[i] <= S[j]; |
S[j] <= S[i]; // We can do this because of verilog. |
K <= S[ S[i]+S[j] ]; |
if (discardCount<1000) |
if (discardCount<10'h3E8) // discard first 1000 values |
discardCount<=discardCount+1; |
else output_ready <= 1; // Valid K at output |
i <= i+1; |
KSState <= `KSS_CRYPTO; |
// Here is the secret of 1-clock: we develop all possible values of j in the future |
if (j==i+1) |
j <= (j + S[i]); |
else |
if (i==255) j <= (j + S[0]); |
else j <= (j + S[i+1]); |
$display ("rc4: output = %08X",K); |
end |
default: begin |
end |