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Rev 13 → Rev 14

/trunk/vhdl/rlu.vhd
16,28 → 16,32
entity rlu is
port (
clk : in std_logic;
reset : in std_logic;
clk : in std_logic;
reset : in std_logic;
 
lock_register : out LOCK_REGISTER_T;
lock_register : out LOCK_REGISTER_T;
 
clear_reg_lock : in std_logic;
set_reg_lock : in std_logic;
reg_addr : in REGISTER_ADDR_T);
clear_reg_lock0 : in std_logic;
set_reg_lock0 : in std_logic;
reg_addr0 : in REGISTER_ADDR_T;
 
clear_reg_lock1 : in std_logic;
set_reg_lock1 : in std_logic;
reg_addr1 : in REGISTER_ADDR_T);
 
end rlu;
 
 
architecture rlu_rtl of rlu is
 
signal lock_register_int : LOCK_REGISTER_T;
signal lock_register_next : LOCK_REGISTER_T;
signal lock_register_int : LOCK_REGISTER_T;
signal lock_register_next : LOCK_REGISTER_T;
begin -- rlu_rtl
 
lock_register <= lock_register_int;
sync: process (clk, reset)
 
sync : process (clk, reset)
begin -- process
if reset = '0' then -- asynchronous reset (active low)
lock_register_int <= (others => '0');
46,17 → 50,29
end if;
end process;
 
async: process (lock_register_int, clear_reg_lock, set_reg_lock, reg_addr)
async : process (lock_register_int,
clear_reg_lock0, set_reg_lock0, reg_addr0,
clear_reg_lock1, set_reg_lock1, reg_addr1)
begin -- process async
lock_register_next <= lock_register_int;
 
if clear_reg_lock = '1' and set_reg_lock = '0' then
lock_register_next(to_integer(unsigned(reg_addr))) <= '0';
-- first unlock all possible registers and then lock them. because
-- the last assignment counts this also works correct if reg_addr0
-- and reg_addr1 are the same and one unlocks and one locks the
-- register (correct behaviour is that the register is locked).
if clear_reg_lock0 = '1' and set_reg_lock0 = '0' then
lock_register_next(to_integer(unsigned(reg_addr0))) <= '0';
end if;
if set_reg_lock = '1' and clear_reg_lock = '0' then
lock_register_next(to_integer(unsigned(reg_addr))) <= '1';
if clear_reg_lock1 = '1' and set_reg_lock1 = '0' then
lock_register_next(to_integer(unsigned(reg_addr1))) <= '0';
end if;
if set_reg_lock0 = '1' and clear_reg_lock0 = '0' then
lock_register_next(to_integer(unsigned(reg_addr0))) <= '1';
end if;
if set_reg_lock1 = '1' and clear_reg_lock1 = '0' then
lock_register_next(to_integer(unsigned(reg_addr1))) <= '1';
end if;
end process async;
 
end rlu_rtl;

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