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URL https://opencores.org/ocsvn/storm_core/storm_core/trunk

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    from Rev 13 to Rev 14
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Rev 13 → Rev 14

/storm_core/trunk/rtl/WB_UNIT.vhd
38,7 → 38,7
-- ## Forwarding Path ##
-- ###############################################################################################
 
WB_FW_OUT : out STD_LOGIC_VECTOR(40 downto 0) -- forwarding data & ctrl
WB_FW_OUT : out STD_LOGIC_VECTOR(39 downto 0) -- forwarding data & ctrl
 
);
end WB_UNIT;
186,9 → 186,17
 
-- Forwarding Path --------------------------------------------------------------------------------
-- ---------------------------------------------------------------------------------------------------
-- Operation Data Result --
WB_FW_OUT(FWD_DATA_MSB downto FWD_DATA_LSB) <= REG_WB_DATA;
WB_FW_OUT(FWD_RD_MSB downto FWD_RD_LSB) <= CTRL_IN(CTRL_RD_3 downto CTRL_RD_0);
WB_FW_OUT(FWD_WB) <= CTRL_IN(CTRL_EN) and CTRL_IN(CTRL_WB_EN);
-- Destination Register Address --
WB_FW_OUT(FWD_RD_MSB downto FWD_RD_LSB) <= CTRL_IN(CTRL_RD_3 downto CTRL_RD_0);
-- Data Write Back Enabled --
WB_FW_OUT(FWD_WB) <= CTRL_IN(CTRL_EN) and CTRL_IN(CTRL_WB_EN);
-- Carry-Need --
WB_FW_OUT(FWD_CY_NEED) <= '0'; -- not needed here
-- MCR Read Access --
WB_FW_OUT(FWD_MCR_R_ACC) <= '0'; -- not needed here
-- Memory Read Access --
WB_FW_OUT(FWD_MEM_R_ACC) <= '0'; -- not needed here
 
 
end Structure;
/storm_core/trunk/rtl/ACCESS_ARBITER.vhd
222,7 → 222,7
ACCESS_ID: process(CL1_ADR_I, CL2_ADR_I, CL1_ACC_REQ_I, CL2_ACC_REQ_I)
begin
--- Client 1 Access ---
if (to_integer(unsigned(CL1_ADR_I)) < SWITCH_ADR) then
if (to_integer(unsigned(CL1_ADR_I(31 downto 02))) < SWITCH_ADR) then
CL1_RE1_REQ <= CL1_ACC_REQ_I;
CL1_RE2_REQ <= '0';
else
231,7 → 231,7
end if;
 
--- Client 2 Access ---
if (to_integer(unsigned(CL2_ADR_I)) < SWITCH_ADR) then
if (to_integer(unsigned(CL2_ADR_I(31 downto 02))) < SWITCH_ADR) then
CL2_RE1_REQ <= CL2_ACC_REQ_I;
CL2_RE2_REQ <= '0';
else
/storm_core/trunk/rtl/STORM_core.vhd
81,9 → 81,8
constant FWD_RD_MSB : natural := 35; -- Destination Adr Bit 3
constant FWD_WB : natural := 36; -- Data in stage will be written back to reg
constant FWD_CY_NEED : natural := 37; -- Carry flag is needed
constant FWD_MCR_ACC : natural := 38; -- MCR Access
constant FWD_MEM_R_ACC : natural := 40; -- Memory Read Access
constant FWD_MEM_ACC : natural := 41; -- Memory Access
constant FWD_MCR_R_ACC : natural := 38; -- MCR Read Access
constant FWD_MEM_R_ACC : natural := 39; -- Memory Read Access
 
-- CTRL BUS LOCATIONS ---------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
284,10 → 283,10
SHIFT_VAL_OUT : out STD_LOGIC_VECTOR(04 downto 0);
BP1_OUT : out STD_LOGIC_VECTOR(31 downto 0);
HOLD_BUS_OUT : out STD_LOGIC_VECTOR(02 downto 0);
MSU_FW_IN : in STD_LOGIC_VECTOR(40 downto 0);
ALU_FW_IN : in STD_LOGIC_VECTOR(41 downto 0);
MEM_FW_IN : in STD_LOGIC_VECTOR(40 downto 0);
WB_FW_IN : in STD_LOGIC_VECTOR(40 downto 0)
MSU_FW_IN : in STD_LOGIC_VECTOR(39 downto 0);
ALU_FW_IN : in STD_LOGIC_VECTOR(39 downto 0);
MEM_FW_IN : in STD_LOGIC_VECTOR(39 downto 0);
WB_FW_IN : in STD_LOGIC_VECTOR(39 downto 0)
);
end component;
323,7 → 322,7
MODE_IN : in STD_LOGIC_VECTOR(04 downto 0);
ADR_OUT : out STD_LOGIC_VECTOR(31 downto 0);
BP_OUT : out STD_LOGIC_VECTOR(31 downto 0);
LDST_FW_OUT : out STD_LOGIC_VECTOR(40 downto 0);
LDST_FW_OUT : out STD_LOGIC_VECTOR(39 downto 0);
XMEM_MODE : out STD_LOGIC_VECTOR(04 downto 0);
XMEM_ADR : out STD_LOGIC_VECTOR(31 downto 0);
XMEM_WR_DTA : out STD_LOGIC_VECTOR(31 downto 0);
390,7 → 389,7
RESULT_OUT : out STD_LOGIC_VECTOR(31 downto 0);
CARRY_OUT : out STD_LOGIC;
OVFL_OUT : out STD_LOGIC;
MSU_FW_OUT : out STD_LOGIC_VECTOR(40 downto 0)
MSU_FW_OUT : out STD_LOGIC_VECTOR(39 downto 0)
);
end component;
 
443,7 → 442,7
MS_OVFL_IN : in STD_LOGIC;
MCR_DTA_OUT : out STD_LOGIC_VECTOR(31 downto 0);
MCR_DTA_IN : in STD_LOGIC_VECTOR(31 downto 0);
ALU_FW_OUT : out STD_LOGIC_VECTOR(41 downto 0)
ALU_FW_OUT : out STD_LOGIC_VECTOR(39 downto 0)
);
end component;
 
488,7 → 487,7
ADR_BUFF_IN : in STD_LOGIC_VECTOR(31 downto 0);
WB_DATA_OUT : out STD_LOGIC_VECTOR(31 downto 0);
XMEM_RD_DATA : in STD_LOGIC_VECTOR(31 downto 0);
WB_FW_OUT : out STD_LOGIC_VECTOR(40 downto 0)
WB_FW_OUT : out STD_LOGIC_VECTOR(39 downto 0)
);
end component;
 
/storm_core/trunk/rtl/MS_UNIT.vhd
46,7 → 46,7
-- ## Forwarding Path ##
-- ###############################################################################################
 
MSU_FW_OUT : out STD_LOGIC_VECTOR(40 downto 0) -- forwarding path
MSU_FW_OUT : out STD_LOGIC_VECTOR(39 downto 0) -- forwarding path
 
);
end MS_UNIT;
152,11 → 152,11
-- Carry-Need For Rotate Right Extended Shift --
MSU_FW_OUT(FWD_CY_NEED) <= '1' when ((CTRL(CTRL_EN) = '1') and (SHIFT_M_TEMP = S_RRX) and (SHIFT_V_TEMP = "00000")) else '0';
 
-- MCR Access --
MSU_FW_OUT(FWD_MCR_ACC) <= CTRL(CTRL_EN) and CTRL(CTRL_MREG_ACC);
-- MCR Read Access --
MSU_FW_OUT(FWD_MCR_R_ACC) <= CTRL(CTRL_EN) and CTRL(CTRL_MREG_ACC) and (not CTRL(CTRL_MREG_RW));
 
-- Memory Read Access --
MSU_FW_OUT(FWD_MEM_R_ACC) <= CTRL(CTRL_EN) and CTRL(CTRL_MEM_ACC) and (not CTRL(CTRL_MEM_RW));
MSU_FW_OUT(FWD_MEM_R_ACC) <= CTRL(CTRL_EN) and CTRL(CTRL_MEM_ACC) and (not CTRL(CTRL_MEM_RW));
 
 
 
/storm_core/trunk/rtl/MCR_SYS.vhd
204,6 → 204,8
if (RES = '1') then
MCR_PC <= (others => '0'); -- start at 0
MCR_CMSR <= (others => '0');
MCR_CMSR(SREG_FIQ_DIS) <= '1'; -- disable FIQ
MCR_CMSR(SREG_IRQ_DIS) <= '1'; -- disable FIQ
MCR_CMSR(SREG_MODE_4 downto SREG_MODE_0) <= Supervisor32_MODE; -- we're the boss after rest
SMSR_FIQ <= x"ACABBAAF"; -- setup value
SMSR_SVC <= x"00000013"; -- setup value
/storm_core/trunk/rtl/ALU.vhd
51,7 → 51,7
-- ## Forwarding Path ##
-- ###############################################################################################
 
ALU_FW_OUT : out STD_LOGIC_VECTOR(41 downto 0) -- forwarding path
ALU_FW_OUT : out STD_LOGIC_VECTOR(39 downto 0) -- forwarding path
 
);
end ALU;
95,16 → 95,22
 
-- Forwarding Paths ------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
-- Operation Data Result --
ALU_FW_OUT(FWD_DATA_MSB downto FWD_DATA_LSB) <= ALU_OUT(31 downto 0);
ALU_FW_OUT(FWD_RD_MSB downto FWD_RD_LSB) <= CTRL(CTRL_RD_3 downto CTRL_RD_0);
ALU_FW_OUT(FWD_WB) <= CTRL(CTRL_EN) and CTRL(CTRL_WB_EN); --(CTRL(CTRL_EN) and (not CTRL(CTRL_BRANCH)) and CTRL(CTRL_WB_EN)); -- write back enabled
ALU_FW_OUT(FWD_MEM_ACC) <= CTRL(CTRL_EN) and CTRL(CTRL_MEM_ACC); -- memory access
ALU_FW_OUT(FWD_MCR_ACC) <= CTRL(CTRL_EN) and CTRL(CTRL_MREG_ACC); -- mreg access
ALU_FW_OUT(FWD_MEM_R_ACC) <= CTRL(CTRL_EN) and CTRL(CTRL_MEM_ACC) and (not CTRL(CTRL_MEM_RW)); -- memory read access
-- Destination Register Address --
ALU_FW_OUT(FWD_RD_MSB downto FWD_RD_LSB) <= CTRL(CTRL_RD_3 downto CTRL_RD_0);
-- Data Write Back Enabled --
ALU_FW_OUT(FWD_WB) <= CTRL(CTRL_EN) and CTRL(CTRL_WB_EN);
-- Carry-Need --
ALU_FW_OUT(FWD_CY_NEED) <= '0'; -- not needed here
-- MCR Read Access --
ALU_FW_OUT(FWD_MCR_R_ACC) <= CTRL(CTRL_EN) and CTRL(CTRL_MREG_ACC) and (not CTRL(CTRL_MREG_RW));
-- Memory Read Access --
ALU_FW_OUT(FWD_MEM_R_ACC) <= CTRL(CTRL_EN) and CTRL(CTRL_MEM_ACC) and (not CTRL(CTRL_MEM_RW));
 
 
 
 
-- Arithemtical / Logical Units ------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
Arithmetical_Core:
/storm_core/trunk/rtl/OPERAND_UNIT.vhd
3,7 → 3,7
-- # *************************************************** #
-- # Operand Fetch & Data Dependency Detector #
-- # *************************************************** #
-- # Version 2.4.4, 03.08.2011 #
-- # Version 2.4.5, 07.09.2011 #
-- #######################################################
 
library IEEE;
46,10 → 46,10
-- ## Forwarding Paths ##
-- ###############################################################################################
 
MSU_FW_IN : in STD_LOGIC_VECTOR(40 downto 0); -- msu forwarding data & ctrl
ALU_FW_IN : in STD_LOGIC_VECTOR(41 downto 0); -- alu forwarding data & ctrl
MEM_FW_IN : in STD_LOGIC_VECTOR(40 downto 0); -- memory forwarding data & ctrl
WB_FW_IN : in STD_LOGIC_VECTOR(40 downto 0) -- write back forwaring data & ctrl
MSU_FW_IN : in STD_LOGIC_VECTOR(39 downto 0); -- msu forwarding data & ctrl
ALU_FW_IN : in STD_LOGIC_VECTOR(39 downto 0); -- alu forwarding data & ctrl
MEM_FW_IN : in STD_LOGIC_VECTOR(39 downto 0); -- memory forwarding data & ctrl
WB_FW_IN : in STD_LOGIC_VECTOR(39 downto 0) -- write back forwaring data & ctrl
 
);
end OPERAND_UNIT;
57,7 → 57,7
architecture OPERAND_UNIT_STRUCTURE of OPERAND_UNIT is
 
-- Local Signals --
signal OP_A, OP_B, OP_C : STD_LOGIC_VECTOR(31 downto 0);
signal OP_A, OP_B, OP_C : STD_LOGIC_VECTOR(31 downto 0);
-- Address Match --
signal MSU_A_MATCH, MSU_B_MATCH, MSU_C_MATCH : STD_LOGIC;
112,14 → 112,14
MEM_C_MATCH <= MEM_FW_IN(FWD_WB) and CTRL_IN(CTRL_EN);
end if;
 
--- Write Back ---
if (OP_ADR_IN(OP_A_ADR_3 downto OP_A_ADR_0) = WB_FW_IN(FWD_RD_MSB downto FWD_RD_LSB)) and (OP_ADR_IN(OP_A_IS_REG) = '1') then
--- Write Back Unit ---
if (OP_ADR_IN(OP_A_ADR_3 downto OP_A_ADR_0) = WB_FW_IN( FWD_RD_MSB downto FWD_RD_LSB)) and (OP_ADR_IN(OP_A_IS_REG) = '1') then
WB_A_MATCH <= WB_FW_IN(FWD_WB) and CTRL_IN(CTRL_EN);
end if;
if (OP_ADR_IN(OP_B_ADR_3 downto OP_B_ADR_0) = WB_FW_IN(FWD_RD_MSB downto FWD_RD_LSB)) and (OP_ADR_IN(OP_B_IS_REG) = '1') then
if (OP_ADR_IN(OP_B_ADR_3 downto OP_B_ADR_0) = WB_FW_IN( FWD_RD_MSB downto FWD_RD_LSB)) and (OP_ADR_IN(OP_B_IS_REG) = '1') then
WB_B_MATCH <= WB_FW_IN(FWD_WB) and CTRL_IN(CTRL_EN);
end if;
if (OP_ADR_IN(OP_C_ADR_3 downto OP_C_ADR_0) = WB_FW_IN(FWD_RD_MSB downto FWD_RD_LSB)) and (OP_ADR_IN(OP_C_IS_REG) = '1') then
if (OP_ADR_IN(OP_C_ADR_3 downto OP_C_ADR_0) = WB_FW_IN( FWD_RD_MSB downto FWD_RD_LSB)) and (OP_ADR_IN(OP_C_IS_REG) = '1') then
WB_C_MATCH <= WB_FW_IN(FWD_WB) and CTRL_IN(CTRL_EN);
end if;
129,9 → 129,9
 
-- Local Data Dependency Detector & Forwarding Unit ------------------------------------------------------
-- ----------------------------------------------------------------------------------------------------------
LOCAL_DATA_DEPENDENCE_DETECTOR: process (CTRL_IN, ALU_FW_IN, MEM_FW_IN, ALU_A_MATCH, ALU_B_MATCH,
ALU_C_MATCH, MEM_A_MATCH, MEM_B_MATCH, MEM_C_MATCH, WB_A_MATCH,
WB_B_MATCH, WB_C_MATCH, WB_FW_IN, OP_A_IN, OP_B_IN, OP_C_IN)
LOCAL_DATA_DEPENDENCE_DETECTOR: process(CTRL_IN, ALU_FW_IN, MEM_FW_IN, ALU_A_MATCH, ALU_B_MATCH,
ALU_C_MATCH, MEM_A_MATCH, MEM_B_MATCH, MEM_C_MATCH, WB_A_MATCH,
WB_B_MATCH, WB_C_MATCH, WB_FW_IN, OP_A_IN, OP_B_IN, OP_C_IN)
variable LDD_A, LDD_B, LDD_C : std_logic_vector(2 downto 0);
begin
-- Forward OP_X from EX/MEM/WB-stage if source and destination addresses are equal
193,7 → 193,7
 
-- Temporal Data Dependency Detector ---------------------------------------------------------------------
-- ----------------------------------------------------------------------------------------------------------
TEMPORAL_DDD: process(MSU_MATCH, ALU_MATCH, MSU_FW_IN, ALU_FW_IN, MEM_MATCH)
TEMPORAL_DDD: process(MSU_MATCH, ALU_MATCH, MSU_FW_IN, ALU_FW_IN, MEM_FW_IN, MEM_MATCH)
begin
-- Data conflicts that cannot be solved by forwarding = Temporal Data Dependencies
-- -> Pipeline Stalls & Bubbles needed
213,7 → 213,7
-- Data dependency OF <-> WB (mem read) form MS
HOLD_BUS_OUT(2 downto 1) <= "11"; -- 3
HOLD_BUS_OUT(0) <= '1'; -- enable
elsif (MSU_FW_IN(FWD_MCR_ACC) = '1') then
elsif (MSU_FW_IN(FWD_MCR_R_ACC) = '1') then
-- Data dependency OF <-> MA (MCR access)
HOLD_BUS_OUT(2 downto 1) <= "10"; -- 2
HOLD_BUS_OUT(0) <= '1'; -- enable
229,7 → 229,7
-- Data dependency OF <-> WB (mem read) from EX
HOLD_BUS_OUT(2 downto 1) <= "10"; -- 2
HOLD_BUS_OUT(0) <= '1'; -- enable
elsif (ALU_FW_IN(FWD_MCR_ACC) = '1') then
elsif (ALU_FW_IN(FWD_MCR_R_ACC) = '1') then
-- Data dependency OF <-> MA (MCR access)
HOLD_BUS_OUT(2 downto 1) <= "01"; -- 1
HOLD_BUS_OUT(0) <= '1'; -- enable
/storm_core/trunk/rtl/CORE.vhd
96,8 → 96,8
signal OP_B_MS : STD_LOGIC_VECTOR(31 downto 0); -- operand B for multishifter
signal MS_CARRY : STD_LOGIC; -- multishifter carry output
signal MS_OVFL : STD_LOGIC; -- multishifter overflow output
signal MS_FW_PATH : STD_LOGIC_VECTOR(40 downto 0); -- multishifter forwarding bus
signal WB_FW_PATH : STD_LOGIC_VECTOR(40 downto 0); -- write back unit forwarding bus
signal MS_FW_PATH : STD_LOGIC_VECTOR(39 downto 0); -- multishifter forwarding bus
signal WB_FW_PATH : STD_LOGIC_VECTOR(39 downto 0); -- write back unit forwarding bus
signal gCLK : STD_LOGIC; -- global clock line
signal gRES : STD_LOGIC; -- global reset line
signal G_HALT : STD_LOGIC; -- gloabl halt line
119,7 → 119,7
signal EX1_CTRL : STD_LOGIC_VECTOR(31 downto 0); -- EX stage control lines
signal EX_BP1_OUT : STD_LOGIC_VECTOR(31 downto 0); -- bypass 1 register
signal EX_ALU_OUT : STD_LOGIC_VECTOR(31 downto 0); -- alu result output
signal ALU_FW_PATH : STD_LOGIC_VECTOR(41 downto 0); -- alu forwarding path
signal ALU_FW_PATH : STD_LOGIC_VECTOR(39 downto 0); -- alu forwarding path
signal EX_BP_OUT : STD_LOGIC_VECTOR(31 downto 0);
signal EX_ADR_OUT : STD_LOGIC_VECTOR(31 downto 0);
signal EX_RES_OUT : STD_LOGIC_VECTOR(31 downto 0);
128,7 → 128,7
signal MEM_DTA_OUT : STD_LOGIC_VECTOR(31 downto 0); -- mem_data and bp2 register
signal MEM_ADR_OUT : STD_LOGIC_VECTOR(31 downto 0); -- mem_data address bypass
signal MEM_BP_OUT : STD_LOGIC_VECTOR(31 downto 0); -- mem_data and bp2 register
signal MEM_FW_PATH : STD_LOGIC_VECTOR(40 downto 0); -- memory forwarding path
signal MEM_FW_PATH : STD_LOGIC_VECTOR(39 downto 0); -- memory forwarding path
signal SHIFT_VAL_BUFF : STD_LOGIC_VECTOR(04 downto 0); -- shift value for barrelshifter
signal REG_PC : STD_LOGIC_VECTOR(31 downto 0); -- PC value for manual operations
signal JMP_PC : STD_LOGIC_VECTOR(31 downto 0); -- PC value for branches
137,7 → 137,6
signal EXC_PC : STD_LOGIC_VECTOR(31 downto 0); -- PC value for exceptions
signal WB_CTRL : STD_LOGIC_VECTOR(31 downto 0); -- WB stage control lines
signal WB_DATA_LINE : STD_LOGIC_VECTOR(31 downto 0); -- data write back line
signal MODE_INT : STD_LOGIC_VECTOR(04 downto 0); -- current processor mode
 
begin
-- #######################################################################################################
224,18 → 223,6
I_MEM_ADR <= INF_PC;
I_MEM_DQ <= DQ_WORD;
 
-- Delay 'MODE' for 1 cycle, so it is sync to memory interface signals
-- ------------------------------------------------------------------------------
MODE_SYNC: process(gCLK, gRES, G_HALT)
begin
if rising_edge(gCLK) then
if (gRES = '1') then
MODE <= (others => '0');
elsif (G_HALT = '0') then
MODE <= MODE_INT;
end if;
end if;
end process MODE_SYNC;
 
 
-- #######################################################################################################
366,7 → 353,7
ADR_OUT => MEM_ADR_OUT, -- address bypass output
BP_OUT => MEM_BP_OUT, -- bypass(data) output
LDST_FW_OUT => MEM_FW_PATH, -- memory forwarding path
XMEM_MODE => MODE_INT, -- processor mode for access
XMEM_MODE => MODE, -- processor mode for access
XMEM_ADR => D_MEM_ADR, -- D memory address output
XMEM_WR_DTA => D_MEM_WR_DTA, -- memory write data output
XMEM_ACC_REQ => D_MEM_REQ, -- access request
/storm_core/trunk/rtl/LOAD_STORE_UNIT.vhd
40,7 → 40,7
-- ## Forwarding Path ##
-- ###############################################################################################
 
LDST_FW_OUT : out STD_LOGIC_VECTOR(40 downto 0);
LDST_FW_OUT : out STD_LOGIC_VECTOR(39 downto 0);
 
-- ###############################################################################################
-- ## External Memory Interface ##
111,10 → 111,19
 
-- Forwarding Path ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
LDST_FW_OUT(FWD_RD_MSB downto FWD_RD_LSB) <= CTRL_IN(CTRL_RD_3 downto CTRL_RD_0);
LDST_FW_OUT(FWD_WB) <= CTRL_IN(CTRL_EN) and CTRL_IN(CTRL_WB_EN);
-- Forwarding Data--
LDST_FW_OUT(FWD_DATA_MSB downto FWD_DATA_LSB) <= BP_TEMP;
LDST_FW_OUT(FWD_MEM_R_ACC) <= CTRL_IN(CTRL_EN) and CTRL_IN(CTRL_MEM_ACC) and (not CTRL_IN(CTRL_MEM_RW));
-- Destination Register --
LDST_FW_OUT(FWD_RD_MSB downto FWD_RD_LSB) <= CTRL_IN(CTRL_RD_3 downto CTRL_RD_0);
-- Write Back --
LDST_FW_OUT(FWD_WB) <= CTRL_IN(CTRL_EN) and CTRL_IN(CTRL_WB_EN);
-- Carry Needed --
LDST_FW_OUT(FWD_CY_NEED) <= '0'; -- not needed here
-- MCR Read Access --
LDST_FW_OUT(FWD_MCR_R_ACC) <= '0'; -- not needed here
-- Memory Read Access --
LDST_FW_OUT(FWD_MEM_R_ACC) <= CTRL_IN(CTRL_EN) and CTRL_IN(CTRL_MEM_ACC) and (not CTRL_IN(CTRL_MEM_RW));
 
 
 

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