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URL https://opencores.org/ocsvn/usb/usb/trunk

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    from Rev 13 to Rev 14
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Rev 13 → Rev 14

/trunk/rtl/verilog/usbf_utmi_if.v
38,10 → 38,10
 
// CVS Log
//
// $Id: usbf_utmi_if.v,v 1.4 2003-10-17 02:36:57 rudi Exp $
// $Id: usbf_utmi_if.v,v 1.5 2003-11-11 07:15:16 rudi Exp $
//
// $Date: 2003-10-17 02:36:57 $
// $Revision: 1.4 $
// $Date: 2003-11-11 07:15:16 $
// $Revision: 1.5 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 48,15
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.4 2003/10/17 02:36:57 rudi
// - Disabling bit stuffing and NRZI encoding during speed negotiation
// - Now the core can send zero size packets
// - Fixed register addresses for some of the higher endpoints
// (conversion between decimal/hex was wrong)
// - The core now does properly evaluate the function address to
// determine if the packet was intended for it.
// - Various other minor bugs and typos
//
// Revision 1.3 2001/11/04 12:22:45 rudi
//
// - Fixed previous fix (brocke something else ...)
199,7 → 208,7
always @(posedge phy_clk)
if(TxReady || tx_first) DataOut <= tx_data;
else
if(drive_k) DataOut <= 8'hff;
if(drive_k) DataOut <= 8'h00;
 
always @(posedge phy_clk)
tx_ready <= TxReady;
/trunk/rtl/verilog/usbf_top.v
38,10 → 38,10
 
// CVS Log
//
// $Id: usbf_top.v,v 1.6 2003-10-17 02:36:57 rudi Exp $
// $Id: usbf_top.v,v 1.7 2003-11-11 07:15:16 rudi Exp $
//
// $Date: 2003-10-17 02:36:57 $
// $Revision: 1.6 $
// $Date: 2003-11-11 07:15:16 $
// $Revision: 1.7 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 48,15
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.6 2003/10/17 02:36:57 rudi
// - Disabling bit stuffing and NRZI encoding during speed negotiation
// - Now the core can send zero size packets
// - Fixed register addresses for some of the higher endpoints
// (conversion between decimal/hex was wrong)
// - The core now does properly evaluate the function address to
// determine if the packet was intended for it.
// - Various other minor bugs and typos
//
// Revision 1.5 2001/11/04 12:22:45 rudi
//
// - Fixed previous fix (brocke something else ...)
294,7 → 303,7
.XcvSelect( XcvSelect_pad_o ),
.TermSel( TermSel_pad_o ),
.SuspendM( SuspendM_pad_o ),
.LineState( LineState_r ),
.LineState( LineState_pad_i ),
.OpMode( OpMode_pad_o ),
.usb_vbus( usb_vbus_pad_i ),
.rx_data( rx_data ),
/trunk/rtl/verilog/usbf_utmi_ls.v
38,10 → 38,10
 
// CVS Log
//
// $Id: usbf_utmi_ls.v,v 1.5 2003-10-17 02:36:57 rudi Exp $
// $Id: usbf_utmi_ls.v,v 1.6 2003-11-11 07:15:16 rudi Exp $
//
// $Date: 2003-10-17 02:36:57 $
// $Revision: 1.5 $
// $Date: 2003-11-11 07:15:16 $
// $Revision: 1.6 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 48,15
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.5 2003/10/17 02:36:57 rudi
// - Disabling bit stuffing and NRZI encoding during speed negotiation
// - Now the core can send zero size packets
// - Fixed register addresses for some of the higher endpoints
// (conversion between decimal/hex was wrong)
// - The core now does properly evaluate the function address to
// determine if the packet was intended for it.
// - Various other minor bugs and typos
//
// Revision 1.4 2001/11/04 12:22:45 rudi
//
// - Fixed previous fix (brocke something else ...)
177,7 → 186,6
reg idle_cnt_clr;
reg idle_cnt1_clr;
reg [7:0] idle_cnt1, idle_cnt1_next;
reg [5:0] idle_cnt2;
reg T1_gt_2_5_uS, T1_st_3_0_mS, T1_gt_3_0_mS;
reg T1_gt_3_125_mS, T1_gt_5_0_mS;
reg [7:0] me_ps;
315,7 → 323,7
always @(posedge clk)
if(!idle_long || idle_cnt1_clr || idle_cnt_clr) idle_cnt1 <= 8'h0;
else
if(!T1_gt_3_125_mS && ps_cnt_clr) idle_cnt1 <= idle_cnt1_next;
if(!T1_gt_5_0_mS && ps_cnt_clr) idle_cnt1 <= idle_cnt1_next;
 
always @(posedge clk)
idle_cnt1_next <= idle_cnt1 + 8'h1;
323,12 → 331,6
always @(posedge clk) // Clear the uS counter every 62.5 uS
idle_cnt1_clr <= idle_cnt1 == `USBF_T1_C_62_5_US;
 
// Count mS
always @(posedge clk)
if(!idle_long || idle_cnt_clr) idle_cnt2 <= 6'h0;
else
if(!T1_gt_5_0_mS && idle_cnt1_clr) idle_cnt2 <= idle_cnt2 + 6'h1;
 
always @(posedge clk) // Greater Than 2.5uS (Actual Time will be T0+2.75uS)
T1_gt_2_5_uS <= !idle_cnt_clr & (idle_cnt1 > `USBF_T1_C_2_5_US);
 
504,9 → 506,7
end
else
if(k_long) // Start Resuming
begin
next_state = RESUME;
end
else
if(T1_gt_5_0_mS && resume_req_s)
next_state = RESUME_REQUEST;
522,6 → 522,7
xcv_set_hs = 1'b1;
fs_term_off = 1'b1;
end
bit_stuff_on = 1'b1; // Enable Bit Stuffing and NRZI encoding
me_cnt_clr = 1'b1;
next_state = RESUME_WAIT;
end
538,6 → 539,8
// Wait for internal wake up
if(T2_wakeup)
begin
fs_term_on = 1'b1; // Switch Termination to Full Speed
bit_stuff_off = 1'b1; // disable Bit Stuffing and NRZI encoding
me_cnt_clr = 1'b1;
next_state = RESUME_SIG;
end
554,11 → 557,13
ATTACH: // Attach To USB Detected
begin
idle_cnt_clr = 1'b1;
if(me_cnt_100_ms && j_long)
if(me_cnt_100_ms)
//if(me_cnt_100_ms && j_long)
begin
attached_set = 1'b1;
next_state = NORMAL;
end
/*
if(me_cnt_100_ms && se0_long)
begin
attached_set = 1'b1;
565,6 → 570,7
me_cnt_clr = 1'b1;
next_state = RESET;
end
*/
end
 
RESET: // In Reset

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