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URL https://opencores.org/ocsvn/8051/8051/trunk

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Rev 131 → Rev 132

/trunk/rtl/verilog/oc8051_defines.v
376,6 → 376,8
 
`define OC8051_RRS_B 3'b100 // b register
`define OC8051_RRS_DPTR 3'b101 // data pointer
`define OC8051_RRS_PSW 3'b110 // program status word
`define OC8051_RRS_ACC 3'b111 // acc
 
`define OC8051_RRS_DC 3'b000 // don't c
 
398,9 → 400,11
`define OC8051_PIS_DC 3'b000 // dont c
`define OC8051_PIS_AL 3'b000 // alu low
`define OC8051_PIS_AH 3'b001 // alu high
`define OC8051_PIS_ALU 3'b010 // alu {des1, des2}
`define OC8051_PIS_I11 3'b011 // 11 bit immediate
`define OC8051_PIS_I16 3'b100 // 16 bit immediate
`define OC8051_PIS_SO1 3'b010 // relative address, op1
`define OC8051_PIS_SO2 3'b011 // relative address, op2
`define OC8051_PIS_I11 3'b100 // 11 bit immediate
`define OC8051_PIS_I16 3'b101 // 16 bit immediate
`define OC8051_PIS_ALU 3'b110 // alu destination {des2, des1}
 
//
// compare source select
409,7 → 413,7
`define OC8051_CSS_DES 2'b01 // eq = destination == zero
`define OC8051_CSS_CY 2'b10 // eq = cy
`define OC8051_CSS_BIT 2'b11 // eq = b_in
`define OC8051_CSS_DC 2'b00 // don't care
`define OC8051_CSS_DC 2'b01 // don't care
 
 
//
/trunk/rtl/verilog/oc8051_alu.v
46,6 → 46,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.11 2003/04/14 14:29:42 simont
// fiz bug iv pcs operation.
//
// Revision 1.10 2003/01/13 14:14:40 simont
// replace some modules
//
62,7 → 65,7
 
 
 
module oc8051_alu (clk, rst, op_code, rd, src1, src2, src3, srcCy, srcAc, bit_in, des1, des2, des1_r, desCy,
module oc8051_alu (clk, rst, op_code, src1, src2, src3, srcCy, srcAc, bit_in, des1, des2, desCy,
desAc, desOv);
//
// op_code (in) operation code [oc8051_decoder.alu_op -r]
73,7 → 76,6
// srcAc (in) auxiliary carry input [oc8051_psw.data_out[6] ]
// bit_in (in) bit input, used for logic operatins on bits [oc8051_ram_sel.bit_out]
// des1 (out)
// des1_r (out)
// des2 (out)
// desCy (out) carry output [oc8051_ram_top.bit_data_in, oc8051_acc.bit_in, oc8051_b_register.bit_in, oc8051_psw.cy_in, oc8051_ports.bit_in]
// desAc (out) auxiliary carry output [oc8051_psw.ac_in]
80,20 → 82,16
// desOv (out) Overflow output [oc8051_psw.ov_in]
//
 
input srcCy, srcAc, bit_in, clk, rst, rd;
input srcCy, srcAc, bit_in, clk, rst;
input [3:0] op_code;
input [7:0] src1, src2, src3;
output desCy, desAc, desOv;
output [7:0] des1, des2;
output [7:0] des1_r;
 
reg desCy, desAc, desOv;
reg [7:0] des1, des2;
 
reg [7:0] des1_r;
 
 
reg rd_r;
//
//add
//
312,7 → 310,7
enable_div = 1'b0;
end
//operation pcs Add
`OC8051_ALU_PCS: begin
/* `OC8051_ALU_PCS: begin
if (src1[7]) begin
{desCy, des1} = {1'b0, src2} + {1'b0, src1};
des2 = {1'b0, src3} - {8'h0, !desCy};
322,7 → 320,7
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end
end*/
//operation exchange
//if carry = 0 exchange low order digit
`OC8051_ALU_XCH: begin
352,18 → 350,4
endcase
end
 
always @(posedge clk or posedge rst)
if (rst) begin
des1_r <= #1 8'h0;
end else if (rd_r) begin
des1_r <= #1 des1;
end
 
always @(posedge clk or posedge rst)
if (rst) begin
rd_r <= #1 8'h0;
end else begin
rd_r <= #1 rd;
end
 
endmodule
/trunk/rtl/verilog/oc8051_memory_interface.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2003/04/16 10:04:09 simont
// chance idat_ir to 24 bit wide
//
// Revision 1.3 2003/04/11 10:05:08 simont
// Change pc add value from 23'h to 16'h
//
262,6 → 265,8
 
`OC8051_RRS_B : rd_addr = `OC8051_SFR_B;
`OC8051_RRS_DPTR : rd_addr = `OC8051_SFR_DPTR_LO;
`OC8051_RRS_PSW : rd_addr = `OC8051_SFR_PSW;
`OC8051_RRS_ACC : rd_addr = `OC8051_SFR_ACC;
default : rd_addr = 2'bxx;
endcase
 
597,7 → 602,21
end else if (pc_wait)
int_buff <= #1 1'b0;
 
wire [7:0] pcs_source;
reg [15:0] pcs_result;
reg pcs_cy;
 
assign pcs_source = pc_wr_sel[0] ? op3_out : op2_out;
 
always @(pcs_source or pc or pcs_cy)
begin
if (pcs_source[7]) begin
{pcs_cy, pcs_result[7:0]} = {1'b0, pc[7:0]} + {1'b0, pcs_source};
pcs_result[15:8] = pc[15:8] - {7'h0, !pcs_cy};
end else pcs_result = pc + {8'h00, pcs_source};
end
 
 
always @(posedge clk or posedge rst)
begin
if (rst) begin
612,6 → 631,8
`OC8051_PIS_AH: pc_buf[15:8] <= #1 alu[7:0];
`OC8051_PIS_I11: pc_buf[10:0] <= #1 {op1_out[7:5], op2_out};
`OC8051_PIS_I16: pc_buf <= #1 {op2_out, op3_out};
`OC8051_PIS_SO1: pc_buf <= #1 pcs_result;
`OC8051_PIS_SO2: pc_buf <= #1 pcs_result;
endcase
end else
//
/trunk/rtl/verilog/oc8051_sfr.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10 2003/04/10 12:43:19 simont
// defines for pherypherals added
//
// Revision 1.9 2003/04/09 16:24:03 simont
// change wr_sft to 2 bit wire.
//
92,6 → 95,8
desAc, desOv,
srcAc, cy,
psw_set, rmw,
comp_sel,
comp_wait,
 
`ifdef OC8051_PORTS
 
152,7 → 157,8
reti,
wr_bit;
input [1:0] psw_set,
wr_sfr;
wr_sfr,
comp_sel;
input [2:0] ram_rd_sel,
ram_wr_sel;
input [7:0] adr0, //address 0 input
164,7 → 170,8
intr,
srcAc,
cy,
wait_data;
wait_data,
comp_wait;
output [1:0] bank_sel;
output [7:0] dat0, //data output
int_src,
526,7 → 533,22
wr_bit_r <= #1 wr_bit;
end
 
assign comp_wait = !(
((comp_sel==`OC8051_CSS_AZ) &
((wr_sfr==`OC8051_WRS_ACC1) |
(wr_sfr==`OC8051_WRS_ACC2) |
((adr1==`OC8051_SFR_ACC) & we & !wr_bit_r) |
((adr1[7:3]==`OC8051_SFR_B_ACC) & we & wr_bit_r))) |
((comp_sel==`OC8051_CSS_CY) &
((|psw_set) |
((adr1==`OC8051_SFR_PSW) & we & !wr_bit_r) |
((adr1[7:3]==`OC8051_SFR_B_PSW) & we & wr_bit_r))) |
((comp_sel==`OC8051_CSS_BIT) &
((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) & we & !wr_bit_r) |
((adr1==adr0) & adr1[7] & we & !wr_bit_r)));
 
 
 
//
//set output in case of address (byte)
always @(posedge clk or posedge rst)
543,8 → 565,9
(adr1[7] & (adr1==adr0) & we & !wr_bit_r)) & !wait_data) begin //write and read same address
wait_data <= #1 1'b1;
 
end else if (
(((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) | //write to acc
end else if ((
((|psw_set) & (adr0==`OC8051_SFR_PSW)) |
((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) | //write to acc
((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI)) //write to dph
) & !wait_data) begin
wait_data <= #1 1'b1;
/trunk/rtl/verilog/oc8051_comp.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2003/04/02 11:26:21 simont
// updating...
//
// Revision 1.5 2002/09/30 17:33:59 simont
// prepared header
//
57,7 → 60,7
`include "oc8051_defines.v"
 
 
module oc8051_comp (sel, b_in, cy, acc, des, eq);
module oc8051_comp (sel, b_in, cy, acc, des, /*comp_wait, */eq);
//
// sel (in) select whithc sourses to compare (look defines.v) [oc8051_decoder.comp_sel]
// b_in (in) bit in - output from bit addressable memory space [oc8051_ram_sel.bit_out]
71,20 → 74,24
 
 
input [1:0] sel;
input b_in, cy;
input b_in, cy/*, comp_wait*/;
input [7:0] acc, des;
 
output eq;
reg eq;
 
reg eq_r;
 
assign eq = eq_r;// & comp_wait;
 
 
always @(sel or b_in or cy or acc or des)
begin
case (sel)
`OC8051_CSS_AZ : eq = (acc == 8'h00);
`OC8051_CSS_DES : eq = (des == 8'h00);
`OC8051_CSS_CY : eq = cy;
`OC8051_CSS_BIT : eq = b_in;
default: eq = 1'bx;
`OC8051_CSS_AZ : eq_r = (acc == 8'h00);
`OC8051_CSS_DES : eq_r = (des == 8'h00);
`OC8051_CSS_CY : eq_r = cy;
`OC8051_CSS_BIT : eq_r = b_in;
default: eq_r = 1'bx;
endcase
end
 
/trunk/rtl/verilog/oc8051_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.24 2003/04/11 10:05:59 simont
// deifne OC8051_ROM added
//
// Revision 1.23 2003/04/10 12:43:19 simont
// defines for pherypherals added
//
98,7 → 101,7
wbd_dat_o,
wbd_adr_o,
wbd_we_o,
wbd_ack_i,
wbd_ack_i,
wbd_stb_o,
wbd_cyc_o,
wbd_err_i,
277,8 → 280,7
src2, //alu sources 2
src3, //alu sources 3
des1, //alu destination 1
des2, //alu destinations 2
des1_r; //destination 1 registerd (to comp1)
des2; //alu destinations 2
wire desCy, //carry out
desAc,
desOv, //overflow
299,7 → 301,8
srcAc,
cy,
rd_ind,
wr_ind;
wr_ind,
comp_wait;
wire [2:0] op1_cur;
 
wire bit_addr, //bit addresable instruction
353,15 → 356,13
oc8051_alu oc8051_alu1(.rst(wb_rst_i),
.clk(wb_clk_i),
.op_code(alu_op),
.rd(rd),
.src1(src1),
.src1(src1),
.src2(src2),
.src3(src3),
.srcCy(alu_cy),
.srcAc(srcAc),
.des1(des1),
.des2(des2),
.des1_r(des1_r),
.des1(des1),
.des2(des2),
.desCy(desCy),
.desAc(desAc),
.desOv(desOv),
406,11 → 407,13
//
//
oc8051_comp oc8051_comp1(.sel(comp_sel),
.eq(eq),
.b_in(bit_out),
.cy(cy),
.acc(acc),
.des(des1_r));
.eq(eq),
.b_in(bit_out),
.cy(cy),
.acc(acc),
.des(des1)
// .comp_wait(comp_wait)
);
 
 
//
463,7 → 466,7
.wr_bit_i(bit_addr),
.wr_bit_o(bit_addr_o),
.wr_dat(wr_dat),
.des1(des1),
.des1(des1),
.des2(des2),
.rd_addr(rd_addr),
.wr_addr(wr_addr),
521,7 → 524,7
 
//pc
.pc_wr_sel(pc_wr_sel),
.pc_wr(pc_wr),
.pc_wr(pc_wr & comp_wait),
.pc(pc),
 
// sfr's
551,6 → 554,8
.ram_rd_sel(ram_rd_sel),
.ram_wr_sel(ram_wr_sel),
.wr_sfr(wr_sfr),
.comp_sel(comp_sel),
.comp_wait(comp_wait),
// acc
.acc(acc),
// sp
/trunk/rtl/verilog/oc8051_decoder.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.16 2003/04/09 16:24:03 simont
// change wr_sft to 2 bit wire.
//
// Revision 1.15 2003/04/09 15:49:42 simont
// Register oc8051_sfr dato output, add signal wait_data.
//
120,6 → 123,7
// state if 2'b00 then normal execution, sle instructin that need more than one clock
// op instruction buffer
reg [1:0] state;
wire [1:0] state_dec;
reg [7:0] op;
wire [7:0] op_cur;
reg [2:0] ram_rd_sel_r;
130,8 → 134,8
 
assign istb = (!state[1]) && stb_i;
 
assign state_dec = wait_data ? 2'b00 : state;
 
 
assign op_cur = (state[0] || state[1] || mem_wait || wait_data) ? op : op_in;
 
assign op1_c = op_cur[2:0];
145,9 → 149,9
//
// main block
// unregisterd outputs
always @(op_cur or eq or state or mem_wait)
always @(op_cur or eq or state_dec or mem_wait)
begin
case (state)
case (state_dec)
2'b01: begin
casex (op_cur)
`OC8051_MOVC_DP :begin
247,7 → 251,7
`OC8051_CJNE_R : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
pc_sel = `OC8051_PIS_SO2;
comp_sel = `OC8051_CSS_DES;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
256,7 → 260,7
`OC8051_CJNE_I : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
pc_sel = `OC8051_PIS_SO2;
comp_sel = `OC8051_CSS_DES;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
265,7 → 269,7
`OC8051_CJNE_D : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
pc_sel = `OC8051_PIS_SO2;
comp_sel = `OC8051_CSS_DES;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
274,7 → 278,7
`OC8051_CJNE_C : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
pc_sel = `OC8051_PIS_SO2;
comp_sel = `OC8051_CSS_DES;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
283,7 → 287,7
`OC8051_DJNZ_R : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
pc_sel = `OC8051_PIS_SO1;
comp_sel = `OC8051_CSS_DES;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
292,7 → 296,7
`OC8051_DJNZ_D : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
pc_sel = `OC8051_PIS_SO2;
comp_sel = `OC8051_CSS_DES;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
301,7 → 305,7
`OC8051_JB : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = eq;
pc_sel = `OC8051_PIS_ALU;
pc_sel = `OC8051_PIS_SO2;
comp_sel = `OC8051_CSS_BIT;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
310,21 → 314,12
`OC8051_JBC : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = eq;
pc_sel = `OC8051_PIS_ALU;
pc_sel = `OC8051_PIS_SO2;
comp_sel = `OC8051_CSS_BIT;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
bit_addr = 1'b1;
end
`OC8051_JC : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = eq;
pc_sel = `OC8051_PIS_ALU;
comp_sel = `OC8051_CSS_CY;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
bit_addr = 1'b0;
end
`OC8051_JMP_D : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_Y;
337,48 → 332,12
`OC8051_JNB : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
pc_sel = `OC8051_PIS_SO2;
comp_sel = `OC8051_CSS_BIT;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
bit_addr = 1'b1;
end
`OC8051_JNC : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
comp_sel = `OC8051_CSS_CY;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
bit_addr = 1'b0;
end
`OC8051_JNZ : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
comp_sel = `OC8051_CSS_AZ;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
bit_addr = 1'b0;
end
`OC8051_JZ : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = eq;
pc_sel = `OC8051_PIS_ALU;
comp_sel = `OC8051_CSS_AZ;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
bit_addr = 1'b0;
end
`OC8051_SJMP : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_ALU;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
bit_addr = 1'b0;
end
`OC8051_DIV : begin
ram_rd_sel = `OC8051_RRS_B;
pc_wr = `OC8051_PCW_N;
1077,28 → 1036,28
`OC8051_JB : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
pc_sel = `OC8051_PIS_SO2;
comp_sel = `OC8051_CSS_BIT;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
stb_i = 1'b1;
bit_addr = 1'b1;
end
`OC8051_JBC :begin
`OC8051_JBC : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_BIT;
rmw = `OC8051_RMW_Y;
stb_i = 1'b0;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
bit_addr = 1'b1;
end
`OC8051_JC : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
ram_rd_sel = `OC8051_RRS_PSW;
pc_wr = eq;
pc_sel = `OC8051_PIS_SO1;
comp_sel = `OC8051_CSS_CY;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
stb_i = 1'b1;
bit_addr = 1'b0;
end
`OC8051_JMP_D : begin
1110,40 → 1069,41
stb_i = 1'b0;
bit_addr = 1'b0;
end
 
`OC8051_JNB : begin
ram_rd_sel = `OC8051_RRS_D;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
pc_sel = `OC8051_PIS_SO2;
comp_sel = `OC8051_CSS_BIT;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
stb_i = 1'b1;
bit_addr = 1'b1;
end
`OC8051_JNC : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
ram_rd_sel = `OC8051_RRS_PSW;
pc_wr = !eq;
pc_sel = `OC8051_PIS_SO1;
comp_sel = `OC8051_CSS_CY;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
stb_i = 1'b1;
bit_addr = 1'b0;
end
`OC8051_JNZ :begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
`OC8051_JNZ : begin
ram_rd_sel = `OC8051_RRS_ACC;
pc_wr = !eq;
pc_sel = `OC8051_PIS_SO1;
comp_sel = `OC8051_CSS_AZ;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
stb_i = 1'b1;
bit_addr = 1'b0;
end
`OC8051_JZ : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
ram_rd_sel = `OC8051_RRS_ACC;
pc_wr = eq;
pc_sel = `OC8051_PIS_SO1;
comp_sel = `OC8051_CSS_AZ;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
stb_i = 1'b1;
bit_addr = 1'b0;
end
`OC8051_LCALL :begin
1428,11 → 1388,11
end
`OC8051_SJMP : begin
ram_rd_sel = `OC8051_RRS_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_SO1;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b0;
stb_i = 1'b1;
bit_addr = 1'b0;
end
`OC8051_SUBB_D : begin
1547,7 → 1507,7
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end else if (!wait_data) begin
case (state)
case (state_dec)
2'b01: begin
casex (op_cur)
`OC8051_MOVC_DP :begin
1664,83 → 1624,6
end
2'b10:
casex (op_cur)
`OC8051_CJNE_R : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_CJNE_I : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_CJNE_D : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_CJNE_C : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_DJNZ_R : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_DJNZ_D : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_JB : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_JBC : begin
ram_wr_sel <= #1 `OC8051_RWS_D;
src_sel1 <= #1 `OC8051_AS1_DC;
1752,83 → 1635,6
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_JC : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_JMP_D : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_JNB : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_JNC : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_JNZ : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_JZ : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_SJMP : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_DIV : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
1866,72 → 1672,6
 
2'b11:
casex (op_cur)
`OC8051_CJNE_R : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP3;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_CJNE_I : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP3;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_CJNE_D : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP3;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_CJNE_C : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP3;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_DJNZ_R : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP2;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_DJNZ_D : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP3;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_PC;
wr_sfr <= #1 `OC8051_WRS_N;
end
`OC8051_RET : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_RAM;
3107,9 → 2847,9
end
`OC8051_SJMP : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP2;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
3240,36 → 2980,36
2'b11: state <= #1 2'b10;
2'b00:
casex (op_in)
`OC8051_ACALL :state <= #1 2'b01;
`OC8051_AJMP : state <= #1 2'b01;
`OC8051_CJNE_R :state <= #1 2'b11;
`OC8051_CJNE_I :state <= #1 2'b11;
`OC8051_CJNE_D : state <= #1 2'b11;
`OC8051_CJNE_C : state <= #1 2'b11;
`OC8051_LJMP : state <= #1 2'b01;
`OC8051_DJNZ_R :state <= #1 2'b11;
`OC8051_DJNZ_D :state <= #1 2'b11;
`OC8051_LCALL :state <= #1 2'b01;
`OC8051_MOVC_DP :state <= #1 2'b11;
`OC8051_MOVC_PC :state <= #1 2'b11;
`OC8051_MOVX_IA :state <= #1 2'b10;
`OC8051_MOVX_AI :state <= #1 2'b10;
`OC8051_MOVX_PA :state <= #1 2'b10;
`OC8051_MOVX_AP :state <= #1 2'b10;
`OC8051_RET : state <= #1 2'b11;
`OC8051_RETI : state <= #1 2'b11;
`OC8051_SJMP : state <= #1 2'b10;
`OC8051_JB : state <= #1 2'b10;
`OC8051_JBC : state <= #1 2'b10;
`OC8051_JC : state <= #1 2'b10;
`OC8051_JMP_D : state <= #1 2'b10;
`OC8051_JNC : state <= #1 2'b10;
`OC8051_JNB : state <= #1 2'b10;
`OC8051_JNZ : state <= #1 2'b10;
`OC8051_JZ : state <= #1 2'b10;
`OC8051_DIV : state <= #1 2'b11;
`OC8051_MUL : state <= #1 2'b11;
default: state <= #1 2'b00;
`OC8051_ACALL : state <= #1 2'b01;
`OC8051_AJMP : state <= #1 2'b01;
`OC8051_CJNE_R : state <= #1 2'b10;
`OC8051_CJNE_I : state <= #1 2'b10;
`OC8051_CJNE_D : state <= #1 2'b10;
`OC8051_CJNE_C : state <= #1 2'b10;
`OC8051_LJMP : state <= #1 2'b01;
`OC8051_DJNZ_R : state <= #1 2'b10;
`OC8051_DJNZ_D : state <= #1 2'b10;
`OC8051_LCALL : state <= #1 2'b01;
`OC8051_MOVC_DP : state <= #1 2'b11;
`OC8051_MOVC_PC : state <= #1 2'b11;
`OC8051_MOVX_IA : state <= #1 2'b10;
`OC8051_MOVX_AI : state <= #1 2'b10;
`OC8051_MOVX_PA : state <= #1 2'b10;
`OC8051_MOVX_AP : state <= #1 2'b10;
`OC8051_RET : state <= #1 2'b11;
`OC8051_RETI : state <= #1 2'b11;
`OC8051_SJMP : state <= #1 2'b01;
`OC8051_JB : state <= #1 2'b10;
`OC8051_JBC : state <= #1 2'b10;
`OC8051_JC : state <= #1 2'b01;
`OC8051_JMP_D : state <= #1 2'b10;
`OC8051_JNC : state <= #1 2'b01;
`OC8051_JNB : state <= #1 2'b10;
`OC8051_JNZ : state <= #1 2'b01;
`OC8051_JZ : state <= #1 2'b01;
`OC8051_DIV : state <= #1 2'b11;
`OC8051_MUL : state <= #1 2'b11;
default : state <= #1 2'b00;
endcase
default: state <= #1 2'b00;
endcase

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