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URL https://opencores.org/ocsvn/pci/pci/trunk

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Rev 131 → Rev 132

/trunk/bench/verilog/system.v
39,6 → 39,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.20 2003/10/17 09:11:51 markom
// mbist signals updated according to newest convention
//
// Revision 1.19 2003/08/21 21:00:38 tadejm
// Added support for WB B3. Some testcases were updated.
//
201,6 → 204,20
reg mbist_clk ;
`endif
 
`ifdef PCI_CPCI_HS_IMPLEMENT
wire ENUM ;
wire LED ;
reg ES ;
reg LOCAL_PCI_RST ;
reg LOCAL_PCI_GNT ;
initial
begin
ES = 1'b0 ;
LOCAL_PCI_RST = 1'b1 ;
LOCAL_PCI_GNT = 1'b1 ;
end
`endif
 
wire RST ;
`ifdef GUEST
assign RST = ~reset ;
220,10 → 237,15
.CLK ( pci_clock),
.AD ( AD ),
.CBE ( CBE ),
`ifdef PCI_CPCI_HS_IMPLEMENT
.RST ( RST & LOCAL_PCI_RST ),
.GNT ( (MAS0_GNT & LOCAL_PCI_GNT) | tc_gnt_allow),
`else
.RST ( RST ),
.GNT ( MAS0_GNT | tc_gnt_allow),
`endif
.INTA ( INTA ),
.REQ ( MAS0_REQ ),
.GNT ( MAS0_GNT | tc_gnt_allow),
.FRAME ( FRAME ),
.IRDY ( IRDY ),
.IDSEL ( TAR0_IDSEL),
235,7 → 257,11
.SERR ( SERR ),
 
.CLK_I ( wb_clock ),
`ifdef HOST
.RST_I ( reset ),
`else
.RST_I ( 1'bx ),
`endif
.RST_O ( RST_O ),
.INT_I ( INT_I ),
.INT_O ( INT_O ),
276,6 → 302,14
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i ({mbist_en_i, mbist_clk, mbist_rst})
`endif
 
`ifdef PCI_CPCI_HS_IMPLEMENT
,
.ENUM (ENUM) ,
.LED (LED) ,
.ES (ES)
`endif
 
) ;
 
WB_MASTER_BEHAVIORAL wishbone_master
912,8 → 946,14
run_bist_test ;
mbist_rst <= #1 1'b1 ;
`endif
 
test_initial_conf_values ;
 
`ifdef PCI_CPCI_HS_IMPLEMENT
test_insertion_during_active_bus ;
test_insert_extract_interface ;
`endif
 
next_test_name[79:0] <= "Initing...";
test_target_response[`TARGET_ENCODED_PARAMATERS_ENABLE] = 1 ;
 
1125,6 → 1165,7
endtask // run_tests
 
task do_reset; //wb_b3_ok
fork
begin
next_test_name[79:0] <= "Reset.....";
 
1149,8 → 1190,131
`endif
 
end
begin:monitor_pci_oes_for_reset_duration
reg error ;
 
wait(RST === 1'b0) ;
@(posedge pci_clock) ;
 
fork
begin:monitor_pci_oes
 
while (RST === 1'b0)
begin
@(
`PCI_BRIDGE_INSTANCE.INTA_en or
`PCI_BRIDGE_INSTANCE.REQ_en or
`PCI_BRIDGE_INSTANCE.FRAME_en or
`PCI_BRIDGE_INSTANCE.IRDY_en or
`PCI_BRIDGE_INSTANCE.DEVSEL_en or
`PCI_BRIDGE_INSTANCE.TRDY_en or
`PCI_BRIDGE_INSTANCE.STOP_en or
`PCI_BRIDGE_INSTANCE.AD_en or
`PCI_BRIDGE_INSTANCE.CBE_en or
`PCI_BRIDGE_INSTANCE.PAR_en or
`PCI_BRIDGE_INSTANCE.PERR_en or
`PCI_BRIDGE_INSTANCE.SERR_en
`ifdef PCI_CPCI_HS_IMPLEMENT
or
LED or
ENUM
`endif
) ;
 
check_pci_oes_during_reset(error) ;
 
if (error)
begin
$display("At Time %t", $time) ;
$display("The PCI Bridge didn't provide expected values on output enable signals during reset") ;
test_fail("The PCI Bridge didn't provide expected values on output enable signals during reset") ;
end
end
end
begin:wait_reset_end
if (RST === 1'b0)
@(posedge RST) ;
 
disable monitor_pci_oes ;
end
join
 
check_pci_oes_during_reset(error) ;
 
if (error)
begin
$display("At Time %t", $time) ;
$display("The PCI Bridge didn't provide expected values on output enable signals during reset") ;
test_fail("The PCI Bridge didn't provide expected values on output enable signals during reset") ;
end
end
join
endtask
 
task check_pci_oes_during_reset ;
output error ;
 
reg oe_inactive_val ;
begin
 
`ifdef ACTIVE_LOW_OE
oe_inactive_val = 1'b1 ;
`endif
 
`ifdef ACTIVE_HIGH_OE
oe_inactive_val = 1'b0 ;
`endif
 
error = 1'b0 ;
 
if (`PCI_BRIDGE_INSTANCE.INTA_en !== oe_inactive_val)
error = 1'b1 ;
 
if (`PCI_BRIDGE_INSTANCE.REQ_en !== oe_inactive_val)
error = 1'b1 ;
 
if (`PCI_BRIDGE_INSTANCE.FRAME_en !== oe_inactive_val)
error = 1'b1 ;
 
if (`PCI_BRIDGE_INSTANCE.IRDY_en !== oe_inactive_val)
error = 1'b1 ;
 
if (`PCI_BRIDGE_INSTANCE.DEVSEL_en !== oe_inactive_val)
error = 1'b1 ;
 
if (`PCI_BRIDGE_INSTANCE.TRDY_en !== oe_inactive_val)
error = 1'b1 ;
 
if (`PCI_BRIDGE_INSTANCE.STOP_en !== oe_inactive_val)
error = 1'b1 ;
 
if (`PCI_BRIDGE_INSTANCE.AD_en !== {32{oe_inactive_val}})
error = 1'b1 ;
 
if (`PCI_BRIDGE_INSTANCE.CBE_en !== {4{oe_inactive_val}})
error = 1'b1 ;
 
if (`PCI_BRIDGE_INSTANCE.PAR_en !== oe_inactive_val)
error = 1'b1 ;
 
if (`PCI_BRIDGE_INSTANCE.PERR_en !== oe_inactive_val)
error = 1'b1 ;
 
if (`PCI_BRIDGE_INSTANCE.SERR_en !== oe_inactive_val)
error = 1'b1 ;
 
`ifdef PCI_CPCI_HS_IMPLEMENT
if (LED !== 1'b0)
error = 1'b1 ;
 
if (ENUM !== 1'bz)
error = 1'b1 ;
`endif
end
endtask
 
/*############################################################################
WB SLAVE UNIT tasks
===================
1217,6 → 1381,7
reg [31:0] translation_address ;
integer i ;
integer j ;
reg byte_ofs ;
begin:main
pci_ctrl_offset = 12'h4 ;
err_cs_offset = {4'h1, `W_ERR_CS_ADDR, 2'b00} ;
1326,7 → 1491,7
 
fork
begin
write_data`WRITE_ADDRESS = target_address ;
write_data`WRITE_ADDRESS = target_address + ({$random} % 4) ;
write_data`WRITE_DATA = wmem_data[0] ;
write_data`WRITE_SEL = 4'hF ;
 
1343,7 → 1508,7
end
 
// read written data back
read_data`READ_ADDRESS = target_address ;
read_data`READ_ADDRESS = target_address + ({$random} % 4) ;
read_data`READ_SEL = 4'hF ;
write_flags`WB_TRANSFER_AUTO_RTY = 1'b1 ;
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
1380,6 → 1545,64
end
join
 
test_name = "MULTIPLE NON-CONSECUTIVE SINGLE MEMORY WRITES THROUGH WISHBONE SLAVE UNIT" ;
begin:non_consecutive_single_writes_test_blk
integer cur_num_of_writes ;
 
write_data`WRITE_SEL = 4'hF ;
write_flags`WB_TRANSFER_AUTO_RTY = 1'b1 ;
write_flags`WB_TRANSFER_CAB = 1'b0 ;
 
for (cur_num_of_writes = 1 ; cur_num_of_writes <= (2 * `WBW_DEPTH) ; cur_num_of_writes = cur_num_of_writes * 3)
begin
fork
begin:wb_write_gen_blk
integer cur_write ;
reg [31:0] cur_wb_adr ;
write_flags`WB_FAST_B2B = 1'b0 ;
 
for (cur_write = 0 ; cur_write < cur_num_of_writes ; cur_write = cur_write + 1'b1)
begin
cur_wb_adr = (cur_write % 2) ? (target_address + 8 * `WBW_DEPTH - 4 * cur_write) : (target_address + 4 * cur_write) ;
write_data`WRITE_ADDRESS = cur_wb_adr + ({$random} % 4) ;
write_data`WRITE_DATA = wmem_data[cur_wb_adr % 1024] ;
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
if ( write_status`CYC_ACTUAL_TRANSFER !== 1 )
begin
$display("Image testing failed! Bridge failed to process single memory write! Time %t ", $time) ;
test_fail("WB Slave state machine failed to post single memory write");
ok = 0 ;
disable non_consecutive_single_writes_test_blk ;
end
 
write_flags`WB_FAST_B2B = 1'b1 ;
 
end
end
begin:pci_write_chk_blk
integer cur_write ;
reg [31:0] cur_pci_adr ;
for (cur_write = 0 ; cur_write < cur_num_of_writes ; cur_write = cur_write + 1'b1)
begin
cur_pci_adr = (cur_write % 2) ? (target_address + 8 * `WBW_DEPTH - 4 * cur_write) : (target_address + 4 * cur_write) ;
pci_transaction_progress_monitor( cur_pci_adr, `BC_MEM_WRITE, 1, 0, 1, 0, 0, ok ) ;
if ( ok !== 1 )
begin
test_fail("because single memory write from WB to PCI didn't engage expected transaction on PCI bus") ;
disable non_consecutive_single_writes_test_blk ;
end
end
end
join
end
end
 
if (ok === 1)
test_ok ;
 
write_flags`WB_FAST_B2B = 1'b0 ;
 
// if address translation is implemented - try it out
translation_address = image_base ;
`ifdef ADDR_TRAN_IMPL
1425,7 → 1648,7
 
fork
begin
write_data`WRITE_ADDRESS = target_address + 4 ;
write_data`WRITE_ADDRESS = target_address + 4 + ({$random} % 4) ;
write_data`WRITE_DATA = wmem_data[1] ;
write_data`WRITE_SEL = 4'hF ;
 
1446,7 → 1669,7
end
 
// read written data back
read_data`READ_ADDRESS = target_address + 4 ;
read_data`READ_ADDRESS = target_address + 4 + ({$random} % 4) ;
read_data`READ_SEL = 4'hF ;
 
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
1487,11 → 1710,11
 
// now do one burst write - length of 6 - minimum depth of fifo is 8, one loc. is always free and one is taken up by address entry
// prepare write data
 
byte_ofs = ({$random} % 4) ;
for ( i = 0 ; i < 6 ; i = i + 1 )
begin
write_data`WRITE_DATA = wmem_data[2 + i] ;
write_data`WRITE_ADDRESS = target_address + 8 + 4*i ;
write_data`WRITE_ADDRESS = target_address + 8 + 4*i + byte_ofs ;
write_data`WRITE_SEL = 4'hF ;
wishbone_master.blk_write_data[i] = write_data ;
end
1529,10 → 1752,12
write_flags`WB_TRANSFER_CAB = 1 ;
write_flags`WB_TRANSFER_SIZE = 4 ;
 
byte_ofs = ({$random} % 4) ;
 
// prepare read data
for ( i = 0 ; i < 4 ; i = i + 1 )
begin
read_data`READ_ADDRESS = target_address + 8 + 4*i ;
read_data`READ_ADDRESS = target_address + 8 + 4*i + byte_ofs ;
read_data`READ_SEL = 4'hF ;
wishbone_master.blk_read_data_in[i] = read_data ;
end
1628,7 → 1853,7
end
join
 
read_data`READ_ADDRESS = target_address ;
read_data`READ_ADDRESS = target_address + ({$random} % 4) ;
read_data`READ_SEL = 4'hF ;
 
test_name = "SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED" ;
1697,7 → 1922,7
end
join
 
read_data`READ_ADDRESS = target_address + 4 ;
read_data`READ_ADDRESS = target_address + 4 + ({$random} % 4) ;
read_data`READ_SEL = 4'hF ;
 
test_name = "SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED" ;
1766,7 → 1991,7
end
join
 
read_data`READ_ADDRESS = target_address + 8 ;
read_data`READ_ADDRESS = target_address + 8 + ({$random} % 4) ;
read_data`READ_SEL = 4'hF ;
 
test_name = "SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED" ;
1805,7 → 2030,7
disable main ;
end
 
write_data`WRITE_ADDRESS = target_address ;
write_data`WRITE_ADDRESS = target_address + 1 ;
write_data`WRITE_DATA = wmem_data[11] ;
write_data`WRITE_SEL = 4'hF ;
 
1812,7 → 2037,7
// don't handle retries from now on
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
 
test_name = "I/O WRITE TRANSACTION FROM WB TO PCI TEST" ;
test_name = "I/O WRITE TRANSACTION FROM WB TO PCI" ;
fork
begin
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
1833,7 → 2058,7
end
join
 
read_data`READ_ADDRESS = target_address ;
read_data`READ_ADDRESS = target_address + 2 ;
read_data`READ_SEL = 4'hF ;
 
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
1860,7 → 2085,7
join
 
// test byte addressing
read_data`READ_ADDRESS = target_address + 2 ;
read_data`READ_ADDRESS = target_address ;
read_data`READ_SEL = 4'b1100 ;
 
fork
1905,7 → 2130,7
disable main ;
end
 
write_data`WRITE_ADDRESS = {target_address[31], 31'h7FFF_FFFF} ;
write_data`WRITE_ADDRESS = {target_address[31], 31'h7FFF_FFFC} ;
write_data`WRITE_DATA = wmem_data[11] ;
write_data`WRITE_SEL = 4'b1000 ;
 
1924,7 → 2149,7
end
begin
// currently IO commands not supported in behavioral models - master abort
pci_transaction_progress_monitor( write_data`WRITE_ADDRESS, `BC_IO_WRITE, 0, 0, 1'b0, 1'b0, 0, ok ) ;
pci_transaction_progress_monitor( write_data`WRITE_ADDRESS + 3, `BC_IO_WRITE, 0, 0, 1'b0, 1'b0, 0, ok ) ;
if ( ok !== 1 )
test_fail( "single I/O write didn't engage expected transaction on PCI bus" ) ;
else
1932,8 → 2157,8
end
join
 
read_data`READ_ADDRESS = write_data`WRITE_ADDRESS ;
read_data`READ_SEL = write_data`WRITE_SEL ;
read_data`READ_ADDRESS = write_data`WRITE_ADDRESS + 3 ;
read_data`READ_SEL = 4'b0001 ;
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
 
fork
1949,7 → 2174,7
else test_ok ;
end
begin
pci_transaction_progress_monitor( read_data`READ_ADDRESS, `BC_IO_READ, 0, 0, 1'b0, 1'b0, 0, ok ) ;
pci_transaction_progress_monitor( read_data`READ_ADDRESS - 3, `BC_IO_READ, 0, 0, 1'b0, 1'b0, 0, ok ) ;
if ( ok !== 1 )
test_fail( "single I/O read didn't engage expected transaction on PCI bus" ) ;
end
2070,6 → 2295,7
 
skip = 0 ;
 
/* Commented out, because non alligned access is now allowed
// memory mapped image - access is erroneous when address is not alligned
write_data`WRITE_ADDRESS = target_address + 1 ;
write_data`WRITE_DATA = wmem_data[0] ;
2161,7 → 2387,6
end
 
// prepare read data
 
for ( i = 0 ; i < 6 ; i = i + 1 )
begin
read_data`READ_ADDRESS = target_address + 4*i + 3 ;
2183,6 → 2408,7
test_ok ;
 
$display("************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************") ;
*/
$display("***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************") ;
 
// map image to IO space
2202,6 → 2428,7
 
skip = 0 ;
 
/*
write_data`WRITE_ADDRESS = target_address ;
write_data`WRITE_DATA = wmem_data[0] ;
write_data`WRITE_SEL = 4'b1010 ;
2321,6 → 2548,7
end
 
test_ok ;
*/
 
test_name = "CAB I/O WRITE TO WB SLAVE" ;
 
2401,83 → 2629,8
 
`endif
`ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
`else
 
if (do_write_test)
begin
write_data`WRITE_ADDRESS = target_address + 1 ;
write_data`WRITE_DATA = wmem_data[0] ;
write_data`WRITE_SEL = 4'hF ;
// don't handle retries
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
 
test_name = "ERRONEOUS WB CONFIGURATION WRITE ACCESS" ;
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
if ( (write_status`CYC_ACTUAL_TRANSFER !== 0) || (write_status`CYC_ERR !== 1) )
begin
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on access to non-alligned configuration address! Time %t ", $time) ;
$display("WISHBONE slave response: ACK = %b, RTY = %b, ERR = %b ", write_status`CYC_ACK, write_status`CYC_RTY, write_status`CYC_ERR) ;
test_fail("WB Slave state machine didn't reject erroneous Configuration write as expected") ;
disable no_transaction ;
disable main ;
end
// try write to configuration cycle address register with non alligned address
write_data`WRITE_ADDRESS = target_address + {4'h1, `CNF_ADDR_ADDR, 2'b10} ;
 
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
if ( (write_status`CYC_ACTUAL_TRANSFER !== 0) || (write_status`CYC_ERR !== 1) )
begin
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on access to non-alligned configuration address! Time %t ", $time) ;
$display("WISHBONE slave response: ACK = %b, RTY = %b, ERR = %b ", write_status`CYC_ACK, write_status`CYC_RTY, write_status`CYC_ERR) ;
test_fail("WB Slave state machine didn't reject erroneous Configuration write as expected") ;
disable no_transaction ;
disable main ;
end
write_data`WRITE_ADDRESS = target_address + {4'h1, `CNF_DATA_ADDR, 2'b11} ;
 
// try write to configuration cycle data register with non alligned address
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
if ( (write_status`CYC_ACTUAL_TRANSFER !== 0) || (write_status`CYC_ERR !== 1) )
begin
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on access to non-alligned configuration address! Time %t ", $time) ;
$display("WISHBONE slave response: ACK = %b, RTY = %b, ERR = %b ", write_status`CYC_ACK, write_status`CYC_RTY, write_status`CYC_ERR) ;
test_fail("WB Slave state machine didn't reject erroneous Configuration write as expected") ;
disable no_transaction ;
disable main ;
end
test_ok ;
end
 
if (do_read_test)
begin
test_name = "ERRONEOUS WB CONFIGURATION READ ACCESS" ;
// try read from configuration cycle data register with non alligned address
read_data`READ_ADDRESS = target_address + {4'h1, `CNF_DATA_ADDR, 2'b01} ;
read_data`READ_SEL = 4'hF ;
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
if ( (read_status`CYC_ACTUAL_TRANSFER !== 0) || (read_status`CYC_ERR !== 1) )
begin
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on access to non-alligned configuration address! Time %t ", $time) ;
$display("WISHBONE slave response: ACK = %b, RTY = %b, ERR = %b ", write_status`CYC_ACK, write_status`CYC_RTY, write_status`CYC_ERR) ;
test_fail("WB Slave state machine didn't reject erroneous Configuration read as expected") ;
disable no_transaction ;
disable main ;
end
test_ok ;
end
 
`endif
 
if (do_write_test)
begin
// prepare write data
test_name = "WB CAB CONFIGURATION WRITE ACCESS" ;
 
2594,6 → 2747,7
integer num_of_trans ;
integer current ;
integer i ;
reg [ 1: 0] byte_ofs ;
begin:main
 
$display("************************** Testing handling of PCI bus errors *******************************************") ;
2678,7 → 2832,7
// perform two writes - one to error address and one to OK address
// prepare write buffer
 
write_data`WRITE_ADDRESS = target_address ;
write_data`WRITE_ADDRESS = target_address + ({$random} % 4) ;
write_data`WRITE_DATA = wmem_data[100] ;
write_data`WRITE_SEL = 4'hF ;
 
2731,16 → 2885,25
 
// read data from second write
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
read_data`READ_ADDRESS = target_address ;
read_data`READ_ADDRESS = target_address + ({$random} % 4) ;
read_data`READ_SEL = 4'hF ;
 
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
 
if ((read_status`CYC_ACTUAL_TRANSFER !== 0) | (read_status`CYC_ERR !== 1'b1))
begin
$display("PCI bus error handling testing failed! WB slave didn't respond with error on Master Aborted single read! Time %t ", $time) ;
$display("WISHBONE slave response: ACK = %b, RTY = %b, ERR = %b ", read_status`CYC_ACK, read_status`CYC_RTY, read_status`CYC_ERR) ;
test_fail("WB Slave Unit didn't process the Master Abort error during single read properly");
disable main ;
end
 
/*
if ( read_status`READ_DATA !== wmem_data[101] )
begin
display_warning( target_address, wmem_data[101], read_status`READ_DATA ) ;
end
 
*/
// read error status register - no errors should be reported since reporting was disabled
test_name = "CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERROR" ;
 
2818,9 → 2981,10
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
 
// prepare data for erroneous write
byte_ofs = ({$random} % 4) ;
for ( i = 0 ; i < 3 ; i = i + 1 )
begin
write_data`WRITE_ADDRESS = target_address + 4*i ;
write_data`WRITE_ADDRESS = target_address + 4*i + byte_ofs ;
write_data`WRITE_DATA = wmem_data[110 + i] ;
write_data`WRITE_SEL = 4'hF ;
wishbone_master.blk_write_data[i] = write_data ;
3028,9 → 3192,10
32'h0000_0007 // data
) ;
// prepare data for ok write
byte_ofs = ({$random} % 4) ;
for ( i = 0 ; i < 3 ; i = i + 1 )
begin
write_data`WRITE_ADDRESS = target_address + 4*i ;
write_data`WRITE_ADDRESS = target_address + 4*i + byte_ofs ;
write_data`WRITE_DATA = wmem_data[113 + i] ;
write_data`WRITE_SEL = 4'hF ;
wishbone_master.blk_write_data[i] = write_data ;
3047,9 → 3212,10
end
 
// do a read
byte_ofs = ({$random} % 4) ;
for ( i = 0 ; i < 3 ; i = i + 1 )
begin
read_data`READ_ADDRESS = target_address + 4*i ;
read_data`READ_ADDRESS = target_address + 4*i + byte_ofs ;
read_data`READ_SEL = 4'hF ;
wishbone_master.blk_read_data_in[i] = read_data ;
end
3089,7 → 3255,7
32'h0000_0000 // data
) ;
// set read data
read_data`READ_ADDRESS = target_address ;
read_data`READ_ADDRESS = target_address + ({$random} % 4) ;
read_data`READ_SEL = 4'hF ;
 
// enable automatic retry handling
3147,7 → 3313,7
) ;
 
test_name = "CHECK NORMAL READ AFTER MASTER ABORT TERMINATED READ" ;
read_data`READ_ADDRESS = target_address ;
read_data`READ_ADDRESS = target_address + ({$random} % 4) ;
read_data`READ_SEL = 4'hF ;
 
wishbone_master.wb_single_read(read_data, write_flags, read_status) ;
3206,9 → 3372,10
) ;
 
 
byte_ofs = ({$random} % 4) ;
for ( i = 0 ; i < 3 ; i = i + 1 )
begin
read_data`READ_ADDRESS = target_address + 4*i ;
read_data`READ_ADDRESS = target_address + 4*i + byte_ofs ;
read_data`READ_SEL = 4'hF ;
wishbone_master.blk_read_data_in[i] = read_data ;
end
3301,13 → 3468,15
test_target_response[`TARGET_ENCODED_TERMINATION] = `Test_Target_Abort ;
test_target_response[`TARGET_ENCODED_TERMINATE_ON] = 1 ;
 
write_data`WRITE_ADDRESS = target_address ;
byte_ofs = ({$random} % 4) ;
 
write_data`WRITE_ADDRESS = target_address + byte_ofs ;
write_data`WRITE_DATA = wmem_data[0] ;
write_data`WRITE_SEL = 4'hF ;
 
wishbone_master.blk_write_data[0] = write_data ;
 
write_data`WRITE_ADDRESS = target_address + 4;
write_data`WRITE_ADDRESS = target_address + 4 + byte_ofs ;
write_data`WRITE_DATA = wmem_data[1] ;
write_data`WRITE_SEL = 4'hF ;
 
3334,7 → 3503,7
end
 
// read data back to see, if it was written OK
read_data`READ_ADDRESS = target_address + 4;
read_data`READ_ADDRESS = target_address + 4 + ({$random} % 4) ;
read_data`READ_SEL = 4'hF ;
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
3448,9 → 3617,10
disable main ;
end
 
byte_ofs = ({$random} % 4) ;
for ( i = 0 ; i < 3 ; i = i + 1 )
begin
write_data`WRITE_ADDRESS = target_address + 8 + 4*i ;
write_data`WRITE_ADDRESS = target_address + 8 + 4*i + byte_ofs ;
write_data`WRITE_DATA = wmem_data[120 + i] ;
write_data`WRITE_SEL = 4'b1010 ;
wishbone_master.blk_write_data[i] = write_data ;
3778,7 → 3948,7
 
$display("Introducing Target Abort error to single read!") ;
// set read data
read_data`READ_ADDRESS = target_address + 8 ;
read_data`READ_ADDRESS = target_address + 8 + ({$random} % 4) ;
read_data`READ_SEL = 4'hF ;
 
// enable automatic retry handling
3853,9 → 4023,11
$display("Introducing Target Abort error to CAB read!") ;
test_name = "TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READ" ;
 
byte_ofs = ({$random} % 4) ;
 
for ( i = 0 ; i < 4 ; i = i + 1 )
begin
read_data`READ_ADDRESS = target_address + 8 + 4*i ;
read_data`READ_ADDRESS = target_address + 8 + 4*i + byte_ofs ;
read_data`READ_SEL = 4'b1010 ;
wishbone_master.blk_read_data_in[i] = read_data ;
end
3919,9 → 4091,10
test_target_response[`TARGET_ENCODED_TERMINATE_ON] = 0 ;
 
test_name = "CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READ" ;
byte_ofs = ({$random} % 4) ;
for ( i = 0 ; i < 3 ; i = i + 1 )
begin
read_data`READ_ADDRESS = target_address + 4*i ;
read_data`READ_ADDRESS = target_address + 4*i + byte_ofs ;
read_data`READ_SEL = 4'b1111 ;
wishbone_master.blk_read_data_in[i] = read_data ;
end
3942,9 → 4115,10
 
test_name = "TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READ" ;
 
byte_ofs = ({$random} % 4) ;
for ( i = 0 ; i < 3 ; i = i + 1 )
begin
read_data`READ_ADDRESS = target_address + 8 + 4*i ;
read_data`READ_ADDRESS = target_address + 8 + 4*i + byte_ofs ;
read_data`READ_SEL = 4'b1111 ;
wishbone_master.blk_read_data_in[i] = read_data ;
end
4014,9 → 4188,11
test_target_response[`TARGET_ENCODED_TERMINATE_ON] = 0 ;
 
test_name = "CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READ" ;
byte_ofs = ({$random} % 4) ;
 
for ( i = 0 ; i < 3 ; i = i + 1 )
begin
read_data`READ_ADDRESS = target_address + 4*i ;
read_data`READ_ADDRESS = target_address + 4*i + byte_ofs ;
read_data`READ_SEL = 4'b1111 ;
wishbone_master.blk_read_data_in[i] = read_data ;
end
4039,7 → 4215,7
// change base address
config_write( ba_offset, image_base + 1, 4'hF, ok ) ;
write_data`WRITE_SEL = 4'b0101 ;
write_data`WRITE_ADDRESS = target_address ;
write_data`WRITE_ADDRESS = target_address + ({$random} % 4) ;
write_data`WRITE_DATA = 32'hAAAA_AAAA ;
 
write_flags`WB_TRANSFER_CAB = 0 ;
4282,7 → 4458,7
disable main ;
end
 
write_data`WRITE_ADDRESS = target_address ;
write_data`WRITE_ADDRESS = target_address + ({$random} % 4) ;
write_data`WRITE_DATA = wmem_data[0] ;
write_data`WRITE_SEL = 4'b1111 ;
 
4556,7 → 4732,7
$display(" Introducing Parity Errors to Master reads ! " ) ;
 
read_data = 0 ;
read_data`READ_ADDRESS = target_address ;
read_data`READ_ADDRESS = target_address + ({$random} % 4) ;
read_data`READ_SEL = 4'hF ;
 
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
6698,7 → 6874,7
integer i ;
integer required_reads ;
integer writes_left ;
 
reg [ 1: 0] byte_ofs ;
begin:main
ctrl_offset = {4'h1, `W_IMG_CTRL1_ADDR, 2'b00} ;
ba_offset = {4'h1, `W_BA1_ADDR, 2'b00} ;
6786,7 → 6962,7
end
 
$display("Testing single write transaction progress from WB to PCI!") ;
write_data`WRITE_ADDRESS = target_address ;
write_data`WRITE_ADDRESS = target_address + ({$random} % 4) ;
write_data`WRITE_DATA = wmem_data[0] ;
write_data`WRITE_SEL = 4'hF ;
 
6834,13 → 7010,14
join
 
$display("Testing burst write transaction progress from WB to PCI!") ;
write_data`WRITE_ADDRESS = target_address ;
byte_ofs = ({$random} % 4) ;
write_data`WRITE_ADDRESS = target_address + byte_ofs ;
write_data`WRITE_DATA = wmem_data[0] ;
write_data`WRITE_SEL = 4'hF ;
 
wishbone_master.blk_write_data[0] = write_data ;
 
write_data`WRITE_ADDRESS = target_address + 4 ;
write_data`WRITE_ADDRESS = target_address + 4 + byte_ofs ;
write_data`WRITE_DATA = wmem_data[1] ;
write_data`WRITE_SEL = 4'hF ;
 
6957,7 → 7134,7
join
 
// do the same thing with burst length of 3
write_data`WRITE_ADDRESS = target_address + 8 ;
write_data`WRITE_ADDRESS = target_address + 8 + byte_ofs ;
write_data`WRITE_DATA = wmem_data[2] ;
write_data`WRITE_SEL = 4'hF ;
 
7063,9 → 7240,10
join
 
// prepare data to fill whole write FIFO + 1 - in parallel prepare read data!
byte_ofs = ({$random} % 4) ;
for ( i = 0 ; i < `WBW_DEPTH - 1 ; i = i + 1 )
begin
write_data`WRITE_ADDRESS = target_address + i*4 ;
write_data`WRITE_ADDRESS = target_address + i*4 + byte_ofs ;
write_data`WRITE_DATA = wmem_data[i] ;
write_data`WRITE_SEL = 4'hF ;
 
7186,7 → 7364,7
test_ok ;
 
$display("Testing single read transaction progress from WB to PCI!") ;
read_data`READ_ADDRESS = target_address + 8 ;
read_data`READ_ADDRESS = target_address + 8 + ({$random} % 4) ;
read_data`READ_SEL = 4'hF ;
 
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
7239,9 → 7417,10
 
test_name = "FILL TARGET MEMORY WITH DATA" ;
// first fill target's memory with enough data to fill WBR_FIFO
byte_ofs = ({$random} % 4) ;
for ( i = 0 ; i < `WBR_DEPTH ; i = i + 1 )
begin
write_data`WRITE_ADDRESS = target_address + i*4 ;
write_data`WRITE_ADDRESS = target_address + i*4 + byte_ofs ;
write_data`WRITE_DATA = wmem_data[i] ;
write_data`WRITE_SEL = 4'hF ;
 
7264,7 → 7443,8
 
test_name = "SINGLE READ TO PUSH WRITE DATA FROM FIFO" ;
// perform single read to force write data to pci
read_data`READ_ADDRESS = target_address + 8;
byte_ofs = ({$random} % 4) ;
read_data`READ_ADDRESS = target_address + 8 + byte_ofs ;
read_data`READ_SEL = 4'hF ;
 
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
7279,12 → 7459,12
 
wishbone_master.blk_read_data_in[0] = read_data ;
 
read_data`READ_ADDRESS = target_address + 12 ;
read_data`READ_ADDRESS = target_address + 12 + byte_ofs ;
read_data`READ_SEL = 4'hF ;
 
wishbone_master.blk_read_data_in[1] = read_data ;
 
read_data`READ_ADDRESS = target_address + 16 ;
read_data`READ_ADDRESS = target_address + 16 + byte_ofs ;
read_data`READ_SEL = 4'hF ;
 
wishbone_master.blk_read_data_in[2] = read_data ;
7402,12 → 7582,13
join
 
// now try burst read with normal termination
read_data`READ_ADDRESS = target_address + 12 ;
byte_ofs = ({$random} % 4) ;
read_data`READ_ADDRESS = target_address + 12 + byte_ofs ;
read_data`READ_SEL = 4'hF ;
 
wishbone_master.blk_read_data_in[0] = read_data ;
 
read_data`READ_ADDRESS = target_address + 16 ;
read_data`READ_ADDRESS = target_address + 16 + byte_ofs ;
read_data`READ_SEL = 4'hF ;
 
wishbone_master.blk_read_data_in[1] = read_data ;
7476,10 → 7657,10
write_flags`WB_TRANSFER_CAB = 1 ;
 
test_name = "NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4" ;
 
byte_ofs = ({$random} % 4) ;
for ( i = 0 ; i < 4 ; i = i + 1 )
begin
read_data`READ_ADDRESS = target_address + i*4 ;
read_data`READ_ADDRESS = target_address + i*4 + byte_ofs ;
read_data`READ_SEL = 4'b1010 ;
 
wishbone_master.blk_read_data_in[i] = read_data ;
7521,7 → 7702,7
test_ok ;
 
// do one single read with different byte enables
read_data`READ_ADDRESS = target_address + 4 ;
read_data`READ_ADDRESS = target_address + 4 + ({$random} % 4) ;
read_data`READ_SEL = 4'b1010 ;
 
test_name = "SINGLE READ WITH FUNNY BYTE ENABLE COMBINATION" ;
7571,9 → 7752,10
end
 
test_name = "BURST READ WITH NORMAL COMPLETION FILLING FULL FIFO - MRL AND PREFETCH BOTH ENABLED" ;
byte_ofs = ({$random} % 4) ;
for ( i = 0 ; i < `WBR_DEPTH ; i = i + 1 )
begin
read_data`READ_ADDRESS = target_address + i*4 ;
read_data`READ_ADDRESS = target_address + i*4 + byte_ofs ;
read_data`READ_SEL = 4'b1111 ;
 
wishbone_master.blk_read_data_in[i] = read_data ;
7611,7 → 7793,7
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
write_flags`WB_TRANSFER_CAB = 1 ;
 
read_data`READ_ADDRESS = target_address + (`WBR_DEPTH - 1) * 4 ;
read_data`READ_ADDRESS = target_address + (`WBR_DEPTH - 1) * 4 + byte_ofs ;
read_data`READ_SEL = 4'hF ;
 
wishbone_master.blk_read_data_in[0] = read_data ;
7632,7 → 7814,7
// write unsupported value to cache line size register
config_write( lat_tim_cls_offset, 32'h0000_04_05, 4'b0011, ok ) ;
 
read_data`READ_ADDRESS = target_address ;
read_data`READ_ADDRESS = target_address + ({$random} % 4) ;
read_data`READ_SEL = 4'hF ;
wishbone_master.blk_read_data_in[0] = read_data ;
 
7716,9 → 7898,10
$display("Testing Master's latency timer operation!") ;
$display("Testing Latency timer during Master Writes!") ;
 
byte_ofs = ({$random} % 4) ;
for ( i = 0 ; i < 6 ; i = i + 1 )
begin
write_data`WRITE_ADDRESS = target_address + i*4 ;
write_data`WRITE_ADDRESS = target_address + i*4 + byte_ofs ;
write_data`WRITE_SEL = 4'b1111 ;
write_data`WRITE_DATA = wmem_data[1023 - i] ;
 
7822,9 → 8005,10
join
 
// perform a read to check data
byte_ofs = ({$random} % 4) ;
for ( i = 0 ; i < 6 ; i = i + 1 )
begin
read_data`READ_ADDRESS = target_address + i*4 ;
read_data`READ_ADDRESS = target_address + i*4 + byte_ofs ;
read_data`READ_SEL = 4'b1111 ;
 
wishbone_master.blk_read_data_in[i] = read_data ;
7996,7 → 8180,7
temp_var = { `WB_CONFIGURATION_BASE, 12'h000 } ;
temp_var[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
 
read_data`READ_ADDRESS = temp_var + { 4'h1, `INT_ACK_ADDR, 2'b00 } ;
read_data`READ_ADDRESS = temp_var + { 4'h1, `INT_ACK_ADDR, 2'b00 } + ({$random} % 4) ;
read_data`READ_SEL = 4'hF ;
 
flags = 0 ;
8241,6 → 8425,7
integer i ;
 
reg error_monitor_done ;
reg [ 1: 0] byte_ofs ;
begin:main
write_flags`INIT_WAITS = wb_init_waits ;
write_flags`SUBSEQ_WAITS = wb_subseq_waits ;
8376,9 → 8561,10
test_name = "SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGET" ;
 
// prepare wb_master write and read data
byte_ofs = ({$random} % 4) ;
for ( i = 0 ; i < 4 ; i = i + 1 )
begin
write_data`WRITE_ADDRESS = wb_target_address + i*4 ;
write_data`WRITE_ADDRESS = wb_target_address + i*4 + byte_ofs ;
write_data`WRITE_DATA = wmem_data[500 + i] ;
write_data`WRITE_SEL = 4'hF ;
 
8815,7 → 9001,7
ok = 0 ;
end
 
pci_transaction_progress_monitor( write_data`WRITE_ADDRESS, `BC_MEM_WRITE, 0, 0, 1'b1, 1'b0, 1'b1, ok ) ;
pci_transaction_progress_monitor( write_data`WRITE_ADDRESS & 32'hFFFF_FFFC, `BC_MEM_WRITE, 0, 0, 1'b1, 1'b0, 1'b1, ok ) ;
// while ( FRAME === 0 || IRDY === 0 )
// @(posedge pci_clock) ;
 
8823,7 → 9009,7
test_target_response[`TARGET_ENCODED_TERMINATION] = `Test_Target_Normal_Completion ;
test_target_response[`TARGET_ENCODED_TERMINATE_ON] = 1 ;
 
pci_transaction_progress_monitor( write_data`WRITE_ADDRESS, `BC_MEM_WRITE, 1, 0, 1'b1, 1'b0, 1'b1, ok ) ;
pci_transaction_progress_monitor( write_data`WRITE_ADDRESS & 32'hFFFF_FFFC, `BC_MEM_WRITE, 1, 0, 1'b1, 1'b0, 1'b1, ok ) ;
if ( ok !== 1 )
begin
$display("Transaction ordering test failed! PCI Master started invalid transaction or none at all on PCI bus after single memory write was posted! Time %t ", $time) ;
8832,7 → 9018,7
end
 
// now wait for delayed read to finish
pci_transaction_progress_monitor( read_data`READ_ADDRESS, `BC_MEM_READ, 1, 0, 1'b1, 1'b0, 1'b0, ok ) ;
pci_transaction_progress_monitor( read_data`READ_ADDRESS & 32'hFFFF_FFFC, `BC_MEM_READ, 1, 0, 1'b1, 1'b0, 1'b0, ok ) ;
if ( ok !== 1 )
begin
$display("Transaction ordering test failed! PCI Master started invalid transaction or none at all on PCI bus after single memory read was requested! Time %t ", $time) ;
8909,7 → 9095,7
ok = 0 ;
end
 
pci_transaction_progress_monitor( write_data`WRITE_ADDRESS, `BC_MEM_WRITE, 1, 0, 1'b1, 1'b0, 1'b0, ok ) ;
pci_transaction_progress_monitor( write_data`WRITE_ADDRESS & 32'hFFFF_FFFC, `BC_MEM_WRITE, 1, 0, 1'b1, 1'b0, 1'b0, ok ) ;
if ( ok !== 1 )
begin
$display("Transaction ordering test failed! PCI Master started invalid transaction or none at all on PCI bus after single memory write was posted! Time %t ", $time) ;
8992,7 → 9178,7
end
 
// now wait for this read to finish on pci
pci_transaction_progress_monitor( read_data`READ_ADDRESS, `BC_MEM_READ, 1, 0, 1'b1, 1'b0, 1'b0, ok ) ;
pci_transaction_progress_monitor( read_data`READ_ADDRESS & 32'hFFFF_FFFC, `BC_MEM_READ, 1, 0, 1'b1, 1'b0, 1'b0, ok ) ;
if ( ok !== 1 )
begin
$display("Transaction ordering test failed! PCI Master started invalid transaction or none at all on PCI bus after single delayed read was requested! Time %t ", $time) ;
9022,7 → 9208,7
end
 
// write must come through
pci_transaction_progress_monitor( write_data`WRITE_ADDRESS, `BC_MEM_WRITE, 1, 0, 1'b1, 1'b0, 1'b0, ok ) ;
pci_transaction_progress_monitor( write_data`WRITE_ADDRESS & 32'hFFFF_FFFC, `BC_MEM_WRITE, 1, 0, 1'b1, 1'b0, 1'b0, ok ) ;
if ( ok !== 1 )
begin
$display("Transaction ordering test failed! PCI Master started invalid transaction or none at all on PCI bus after single memory write was posted! Time %t ", $time) ;
10545,12 → 10731,10
temp_var = { `WB_CONFIGURATION_BASE, 12'h000 } ;
temp_var[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
 
write_data`WRITE_ADDRESS = temp_var + { 4'h1, `CNF_ADDR_ADDR, 2'b00 } ;
write_data`WRITE_ADDRESS = temp_var + { 4'h1, `CNF_ADDR_ADDR, 2'b00 } + ({$random} % 4) ;
write_data`WRITE_DATA = { 8'h00, bus_num, device_num, func_num, reg_num, type } ;
 
`ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
 
write_data`WRITE_SEL = 4'b0001 ;
write_data`WRITE_SEL = 4'b0001 ;
repeat(4)
begin
wishbone_master.wb_single_write(write_data, flags, write_status) ;
10563,29 → 10747,13
disable main ;
end
 
write_data`WRITE_ADDRESS = write_data`WRITE_ADDRESS + 'h1 ;
write_data`WRITE_SEL = write_data`WRITE_SEL << 1 ;
end
 
`else
write_data`WRITE_SEL = 4'hF ;
wishbone_master.wb_single_write(write_data, flags, write_status) ;
 
// check if write succeeded
if (write_status`CYC_ACTUAL_TRANSFER !== 1)
begin
$display("Configuration cycle generation failed! Couldn't write to configuration address register! Time %t ", $time) ;
in_use = 0 ;
disable main ;
end
 
`endif
 
// setup flags for wb master to handle retries and read and write data
flags`WB_TRANSFER_AUTO_RTY = 1 ;
 
read_data`READ_ADDRESS = temp_var + {4'b0001, `CNF_DATA_ADDR, 2'b00} ;
read_data`READ_ADDRESS = temp_var + {4'b0001, `CNF_DATA_ADDR, 2'b00} + ({$random} % 4) ;
write_data`WRITE_ADDRESS = read_data`READ_ADDRESS ;
read_data`READ_SEL = byte_enables ;
write_data`WRITE_SEL = byte_enables ;
10595,8 → 10763,6
 
temp_var = 32'hxxxx_xxxx ;
 
`ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
 
for (i = 0 ; i < 4 ; i = i + 1)
begin
 
10605,13 → 10771,6
read_data`READ_SEL = 4'h1 << i ;
write_data`WRITE_SEL = read_data`READ_SEL ;
 
`else
 
begin
begin
 
`endif
 
fork
begin
if (read0_write1 === 0)
10652,8 → 10811,6
end
join
 
`ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
 
temp_var = read_status`READ_DATA ;
 
if (read0_write1 === 0)
10665,17 → 10822,14
4'b1000:data[31:24] = temp_var[31:24] ;
endcase
end
 
`else
 
if (read0_write1 === 0)
data = read_status`READ_DATA ;
 
`endif
 
end
read_data`READ_ADDRESS = read_data`READ_ADDRESS + 1'b1 ;
write_data`WRITE_ADDRESS = write_data`WRITE_ADDRESS + 1'b1 ;
read_data`READ_ADDRESS = read_data`READ_ADDRESS >> 2 ;
read_data`READ_ADDRESS = read_data`READ_ADDRESS << 2 ;
read_data`READ_ADDRESS = read_data`READ_ADDRESS + ({$random} % 4) ;
write_data`WRITE_ADDRESS = write_data`WRITE_ADDRESS >> 2 ;
write_data`WRITE_ADDRESS = write_data`WRITE_ADDRESS << 2 ;
write_data`WRITE_ADDRESS = write_data`WRITE_ADDRESS + ({$random} % 4) ;
end
 
in_use = 0 ;
10720,7 → 10874,7
temp_var = { `WB_CONFIGURATION_BASE, 12'h000 } ;
temp_var[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
 
write_data`WRITE_ADDRESS = temp_var + { 4'h1, `CNF_ADDR_ADDR, 2'b00 } ;
write_data`WRITE_ADDRESS = temp_var + { 4'h1, `CNF_ADDR_ADDR, 2'b00 } + ({$random} % 4) ;
temp_var = 0 ;
temp_var[15:11] = `TAR1_IDSEL_INDEX - 11 ; // device number field
write_data`WRITE_DATA = temp_var ;
10743,7 → 10897,7
temp_var = { `WB_CONFIGURATION_BASE, 12'h000 } ;
temp_var[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
 
read_data`READ_ADDRESS = temp_var + {4'b0001, `CNF_DATA_ADDR, 2'b00} ;
read_data`READ_ADDRESS = temp_var + {4'b0001, `CNF_DATA_ADDR, 2'b00} + ({$random} % 4) ;
write_data`WRITE_ADDRESS = read_data`READ_ADDRESS ;
read_data`READ_SEL = 4'hF ;
write_data`WRITE_SEL = 4'hF ;
10922,7 → 11076,7
temp_var = { `WB_CONFIGURATION_BASE, 12'h000 } ;
temp_var[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
 
write_data`WRITE_ADDRESS = temp_var + { 4'h1, `CNF_ADDR_ADDR, 2'b00 } ;
write_data`WRITE_ADDRESS = temp_var + { 4'h1, `CNF_ADDR_ADDR, 2'b00 } + ({$random} % 4) ;
write_data`WRITE_DATA = pci_address ;
write_data`WRITE_SEL = 4'hF ;
 
10943,7 → 11097,7
temp_var = { `WB_CONFIGURATION_BASE, 12'h000 } ;
temp_var[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
 
read_data`READ_ADDRESS = temp_var + {4'b0001, `CNF_DATA_ADDR, 2'b00} ;
read_data`READ_ADDRESS = temp_var + {4'b0001, `CNF_DATA_ADDR, 2'b00} + ({$random} % 4) ;
write_data`WRITE_ADDRESS = read_data`READ_ADDRESS ;
read_data`READ_SEL = 4'hF ;
write_data`WRITE_SEL = 4'hF ;
11082,7 → 11236,7
temp_var = { `WB_CONFIGURATION_BASE, 12'h000 } ;
temp_var[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
 
write_data`WRITE_ADDRESS = temp_var + { 4'h1, `CNF_ADDR_ADDR, 2'b00 } ;
write_data`WRITE_ADDRESS = temp_var + { 4'h1, `CNF_ADDR_ADDR, 2'b00 } + ({$random} % 4) ;
write_data`WRITE_DATA = pci_address ;
write_data`WRITE_SEL = 4'hF ;
 
11103,7 → 11257,7
temp_var = { `WB_CONFIGURATION_BASE, 12'h000 } ;
temp_var[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
 
read_data`READ_ADDRESS = temp_var + {4'b0001, `CNF_DATA_ADDR, 2'b00} ;
read_data`READ_ADDRESS = temp_var + {4'b0001, `CNF_DATA_ADDR, 2'b00} + ({$random} % 4) ;
write_data`WRITE_ADDRESS = read_data`READ_ADDRESS ;
read_data`READ_SEL = 4'hF ;
write_data`WRITE_SEL = 4'hF ;
11242,7 → 11396,7
temp_var = { `WB_CONFIGURATION_BASE, 12'h000 } ;
temp_var[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
 
write_data`WRITE_ADDRESS = temp_var + { 4'h1, `CNF_ADDR_ADDR, 2'b00 } ;
write_data`WRITE_ADDRESS = temp_var + { 4'h1, `CNF_ADDR_ADDR, 2'b00 } + ({$random} % 4) ;
write_data`WRITE_DATA = pci_address ;
write_data`WRITE_SEL = 4'hF ;
 
11263,7 → 11417,7
temp_var = { `WB_CONFIGURATION_BASE, 12'h000 } ;
temp_var[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
 
read_data`READ_ADDRESS = temp_var + {4'b0001, `CNF_DATA_ADDR, 2'b00} ;
read_data`READ_ADDRESS = temp_var + {4'b0001, `CNF_DATA_ADDR, 2'b00} + ({$random} % 4) ;
write_data`WRITE_ADDRESS = read_data`READ_ADDRESS ;
read_data`READ_SEL = 4'b0101 ;
write_data`WRITE_SEL = 4'b1010 ;
11495,7 → 11649,7
// test MEM/IO map bit initial value in each PCI BAR
register_offset = {1'b1, `P_BA0_ADDR, 2'b00} ;
 
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE, register_offset} ;
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE, register_offset} + ({$random} % 4) ;
 
wishbone_master.wb_single_read(read_data, flags, read_status) ;
 
11528,7 → 11682,7
 
register_offset = {1'b1, `P_BA1_ADDR, 2'b00} ;
 
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE, register_offset} ;
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE, register_offset} + ({$random} % 4) ;
 
wishbone_master.wb_single_read(read_data, flags, read_status) ;
 
11553,7 → 11707,7
register_offset = {1'b1, `P_BA2_ADDR, 2'b00} ;
 
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE, register_offset} ;
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE, register_offset} + ({$random} % 4) ;
 
wishbone_master.wb_single_read(read_data, flags, read_status) ;
 
11582,7 → 11736,7
 
register_offset = {1'b1, `P_BA3_ADDR, 2'b00} ;
 
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE, register_offset} ;
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE, register_offset} + ({$random} % 4) ;
 
wishbone_master.wb_single_read(read_data, flags, read_status) ;
 
11611,7 → 11765,7
 
register_offset = {1'b1, `P_BA4_ADDR, 2'b00} ;
 
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE, register_offset} ;
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE, register_offset} + ({$random} % 4) ;
 
wishbone_master.wb_single_read(read_data, flags, read_status) ;
 
11640,7 → 11794,7
 
register_offset = {1'b1, `P_BA5_ADDR, 2'b00} ;
 
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE, register_offset} ;
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE, register_offset} + ({$random} % 4) ;
 
wishbone_master.wb_single_read(read_data, flags, read_status) ;
 
11670,7 → 11824,7
// test Address Mask initial values
register_offset = {1'b1, `P_AM0_ADDR, 2'b00} ;
 
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE, register_offset} ;
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE, register_offset} + ({$random} % 4) ;
 
wishbone_master.wb_single_read(read_data, flags, read_status) ;
 
11704,7 → 11858,7
 
register_offset = {1'b1, `P_AM1_ADDR, 2'b00} ;
 
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE, register_offset} ;
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE, register_offset} + ({$random} % 4) ;
 
wishbone_master.wb_single_read(read_data, flags, read_status) ;
 
11728,7 → 11882,7
 
register_offset = {1'b1, `P_AM2_ADDR, 2'b00} ;
 
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE, register_offset} ;
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE, register_offset} + ({$random} % 4) ;
 
wishbone_master.wb_single_read(read_data, flags, read_status) ;
 
11756,7 → 11910,7
register_offset = {1'b1, `P_AM3_ADDR, 2'b00} ;
 
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE, register_offset} ;
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE, register_offset} + ({$random} % 4) ;
 
wishbone_master.wb_single_read(read_data, flags, read_status) ;
 
11784,7 → 11938,7
 
register_offset = {1'b1, `P_AM4_ADDR, 2'b00} ;
 
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE, register_offset} ;
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE, register_offset} + ({$random} % 4) ;
 
wishbone_master.wb_single_read(read_data, flags, read_status) ;
 
11812,7 → 11966,7
 
register_offset = {1'b1, `P_AM5_ADDR, 2'b00} ;
 
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE, register_offset} ;
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE, register_offset} + ({$random} % 4) ;
 
wishbone_master.wb_single_read(read_data, flags, read_status) ;
 
12241,11 → 12395,2512
end
endtask
 
`ifdef PCI_CPCI_HS_IMPLEMENT
 
task test_insertion_during_active_bus ;
reg [31: 0] pci_address ;
 
reg error ;
reg pci_error_monitor_done ;
begin
pci_error_monitor_done = 1'b0 ;
error = 1'b0 ;
 
test_name = "HOT SWAP LOCAL_PCI_RESET RELEASE IN MID TRANSACTION ON THE PCI BUS" ;
fork
begin
// configure behavioral target 1
@(posedge pci_clock) ;
configure_target(1) ;
repeat(5)
@(posedge pci_clock);
pci_address = `BEH_TAR1_MEM_START ;
pci_behaviorial_device2.pci_behaviorial_master.keep_master_mask = 1'b1 ;
pci_behaviorial_device2.pci_behaviorial_master.keep_master_data = 1'b1 ;
PCIU_MEM_WRITE ("MEM_WRITE ", `Test_Master_2 ,
pci_address, 32'hFFFF_FF00, `BC_CONF_READ,
256, `Test_One_Zero_Master_WS, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
do_pause( 10 ) ;
fork
begin
LOCAL_PCI_RST <= 1'b0 ;
repeat (10)
@(posedge pci_clock) ;
LOCAL_PCI_RST <= 1'b1 ;
disable monitor_pci_bridge_oes ;
end
begin:monitor_pci_bridge_oes
wait (LOCAL_PCI_RST === 1'b0) ;
@(posedge pci_clock) ;
while (LOCAL_PCI_RST === 1'b0)
begin
@(
`PCI_BRIDGE_INSTANCE.INTA_en or
`PCI_BRIDGE_INSTANCE.REQ_en or
`PCI_BRIDGE_INSTANCE.FRAME_en or
`PCI_BRIDGE_INSTANCE.IRDY_en or
`PCI_BRIDGE_INSTANCE.DEVSEL_en or
`PCI_BRIDGE_INSTANCE.TRDY_en or
`PCI_BRIDGE_INSTANCE.STOP_en or
`PCI_BRIDGE_INSTANCE.AD_en or
`PCI_BRIDGE_INSTANCE.CBE_en or
`PCI_BRIDGE_INSTANCE.PAR_en or
`PCI_BRIDGE_INSTANCE.PERR_en or
`PCI_BRIDGE_INSTANCE.SERR_en
`ifdef PCI_CPCI_HS_IMPLEMENT
or
LED or
ENUM
`endif
) ;
check_pci_oes_during_reset(error) ;
if (error)
begin
$display("At Time %t", $time) ;
$display("The PCI Bridge didn't provide expected values on output enable signals during reset") ;
test_fail("The PCI Bridge didn't provide expected values on output enable signals during reset") ;
end
end
end
join
if (error === 1'b0)
begin
check_pci_oes_during_reset(error) ;
if (error)
begin
$display("At Time %t", $time) ;
$display("The PCI Bridge didn't provide expected values on output enable signals during reset") ;
test_fail("The PCI Bridge didn't provide expected values on output enable signals during reset") ;
end
end
do_pause(100) ;
pci_behaviorial_device2.pci_behaviorial_master.keep_master_mask = 1'b0 ;
pci_behaviorial_device2.pci_behaviorial_master.keep_master_data = 1'b0 ;
 
if (~pci_error_monitor_done)
begin
@(posedge pci_clock) ;
while (FRAME === 1'b0)
@(posedge pci_clock) ;
end
 
repeat (5)
@(posedge pci_clock) ;
 
if (~pci_error_monitor_done)
disable pci_error_monitor ;
 
if (~pci_error_monitor_done & ~error)
test_ok ;
end
begin:pci_error_monitor
@(error_event_int) ;
test_fail("either PCI Monitor or PCI Master detected an error on the PCI bus during the test") ;
pci_error_monitor_done = 1'b1 ;
end
join
end
endtask // test_insertion_during_active_bus
 
task test_insert_extract_interface ;
reg generate_pci_transfers ;
reg enum_monitor_done ;
reg pci_err_monitor_done ;
reg debounce_time_exp ;
integer debounce_period ;
reg [31: 0] read_data ;
 
reg [31: 0] pci_master_data ;
reg [31: 0] pci_master_addr ;
reg [31: 0] rnd_seed ;
 
reg error ;
begin
error = 1'b0 ;
rnd_seed = 32'h01020_f0e0 ;
 
ES = 1'b0 ;
 
generate_pci_transfers = 1'b1 ;
 
pci_err_monitor_done = 1'b0 ;
enum_monitor_done = 1'b0 ;
debounce_time_exp = 1'b0 ;
 
`ifdef PCI_CPCI_SIM
`ifdef PCI66
debounce_period = 15 * 20 ;
`else
debounce_period = 30 * 20 ;
`endif
`else
debounce_period = 2000000 ;
`endif
 
debounce_time_exp <= #(debounce_period + debounce_period/4) 1'b1 ;
 
test_name = "HOT SWAP ENUM NOT ASSERTED AFTER INSERTION IF HANDLE SWITCH OPEN" ;
fork
begin
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
6'h1, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
 
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from device status register") ;
test_fail("INVALID Data value read from device status register") ;
error = 1'b1 ;
end
 
if (read_data[20] !== 1'b1)
begin
$display("At time %t", $time) ;
$display("Capabilities List bit in Device status register not set") ;
test_fail("Capabilities List bit in Device status register was not set") ;
error = 1'b1 ;
end
 
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
6'hD, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
 
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Capabilities Pointer register") ;
test_fail("INVALID Data value was read from Capabilities Pointer register") ;
error = 1'b1 ;
end
 
if (read_data !== {24'h0, `PCI_CAP_PTR_VAL})
begin
$display("At time %t", $time) ;
$display("Data value read from capabilities pointer register not as expected") ;
test_fail("Data value read from capabilities pointer register was not as expected") ;
error = 1'b1 ;
end
 
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
read_data[7:0] >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
 
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
 
if (read_data !== 32'h0000_0006)
begin
$display("At time %t", $time) ;
$display("Data value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Data value read from Hot Swap Control and Status Register was not as expected") ;
error = 1'b1 ;
end
 
while (generate_pci_transfers)
begin
pci_master_data = $random(rnd_seed) ;
pci_master_addr = `BEH_TAR1_MEM_START + {$random(rnd_seed)} % 128 ;
pci_master_addr = pci_master_addr >> 2 ;
pci_master_addr = pci_master_addr << 2 ;
 
PCIU_MEM_WRITE ("MEM_WRITE ", `Test_Master_2 ,
pci_master_addr, pci_master_data, `BC_CONF_READ,
8, `Test_One_Zero_Master_WS, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
do_pause( 1 ) ;
 
PCIU_MEM_READ("MEM_READ ", `Test_Master_2,
pci_master_addr, pci_master_data,
8, 8'h0_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
 
do_pause( 1 ) ;
 
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data !== 32'h0000_0006)
begin
$display("At time %t", $time) ;
$display("Data value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Data value read from Hot Swap Control and Status Register was not as expected") ;
error = 1'b1 ;
end
end
 
disable ES_bounce_blk0 ;
end
begin:enum_monitor0
if (ENUM === 1'bz)
@(ENUM or debounce_time_exp) ;
 
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM not in HighZ after insertion and handle switch open") ;
test_fail("ENUM didn't stay in HighZ after insertion with Handle Switch open") ;
error = 1'b1 ;
end
 
generate_pci_transfers = 1'b0 ;
if (pci_err_monitor_done !== 1'b1)
disable pci_err_monitor0 ;
else
error = 1'b1 ;
end
begin:pci_err_monitor0
@(error_event_int) ;
test_fail("either PCI Monitor or PCI Master detected an error on the PCI bus during the test") ;
pci_err_monitor_done = 1'b1 ;
end
begin:ES_bounce_blk0
forever
begin
ES = ~ES ;
#(debounce_period/4) ;
end
end
join
 
while (debounce_time_exp !== 1'b1)
begin
@(ENUM or debounce_time_exp) ;
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM not in HighZ after insertion and handle switch open") ;
test_fail("ENUM didn't stay in HighZ after insertion with Handle Switch open") ;
error = 1'b1 ;
end
end
 
if (error !== 1'b1)
test_ok ;
 
error = 1'b0 ;
 
ES = 1'b0 ;
 
debounce_time_exp = 1'b0 ;
 
repeat(2)
@(posedge pci_clock) ;
 
test_name = "HOT SWAP ENUM ASSERTION AFTER INSERT AND HANDLE SWITCH CLOSED" ;
 
ES = 1'b1 ;
 
debounce_time_exp <= #(debounce_period + debounce_period / 4) 1'b1 ;
 
generate_pci_transfers = 1'b1 ;
fork
begin
while (generate_pci_transfers)
begin
pci_master_data = $random(rnd_seed) ;
pci_master_addr = `BEH_TAR1_MEM_START + {$random(rnd_seed)} % 128 ;
pci_master_addr = pci_master_addr >> 2 ;
pci_master_addr = pci_master_addr << 2 ;
 
PCIU_MEM_WRITE ("MEM_WRITE ", `Test_Master_2 ,
pci_master_addr, pci_master_data, `BC_CONF_READ,
8, `Test_One_Zero_Master_WS, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
do_pause( 1 ) ;
 
PCIU_MEM_READ("MEM_READ ", `Test_Master_2,
pci_master_addr, pci_master_data,
8, 8'h0_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
 
do_pause( 1 ) ;
end
end
begin
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM not in HighZ after insertion and handle switch open") ;
test_fail("ENUM didn't stay in HighZ after insertion with Handle Switch open") ;
error = 1'b1 ;
end
else
@(ENUM or debounce_time_exp) ;
 
if (ENUM !== 1'b0)
begin
$display("At time %t", $time) ;
$display("ENUM not asserted after insertion and handle switch closed") ;
test_fail("ENUM was not asserted after insertion with Handle Switch closed") ;
error = 1'b1 ;
end
 
generate_pci_transfers = 1'b0 ;
 
end
join
 
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data[23] !== 1'b1)
begin
$display("At time %t", $time) ;
$display("INS bit in Hot Swap Control and Status Register not set when expected") ;
test_fail("INS bit in Hot Swap Control and Status Register not set when expected") ;
error = 1'b1 ;
end
 
if (read_data !== 32'h0080_0006)
begin
$display("At time %t", $time) ;
$display("Value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Unexpected value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
 
configuration_cycle_write
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data to write [31:0]
) ;
 
// the ENUM is de-asserted 2 clocks after the write to the register is complete
// start checking the states starting with the 3rd clock after the write
repeat(3)
@(posedge pci_clock) ;
 
while (debounce_time_exp !== 1'b1)
begin
@(ENUM or debounce_time_exp) ;
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM not in HighZ after clear of INS bit and handle switch closed") ;
test_fail("ENUM didn't go in HighZ after clear of INS bit with Handle Switch closed") ;
error = 1'b1 ;
end
end
 
if (error !== 1'b1)
test_ok ;
 
error = 1'b0 ;
test_name = "HOT SWAP INS BIT CLEARED, ENUM DE-ASSERTED AS A RESULT, HANDLE SWITCH CLOSED" ;
generate_pci_transfers = 1'b1 ;
 
debounce_time_exp = 1'b0 ;
 
debounce_time_exp <= #(debounce_period + debounce_period / 4) 1'b1 ;
 
fork
begin
while (generate_pci_transfers)
begin
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data !== 32'h0000_0006)
begin
$display("At time %t", $time) ;
$display("Data value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Data value read from Hot Swap Control and Status Register was not as expected") ;
error = 1'b1 ;
end
 
pci_master_data = $random(rnd_seed) ;
pci_master_addr = `BEH_TAR1_MEM_START + {$random(rnd_seed)} % 128 ;
pci_master_addr = pci_master_addr >> 2 ;
pci_master_addr = pci_master_addr << 2 ;
 
PCIU_MEM_WRITE ("MEM_WRITE ", `Test_Master_2 ,
pci_master_addr, pci_master_data, `BC_CONF_READ,
8, `Test_One_Zero_Master_WS, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
do_pause( 1 ) ;
 
PCIU_MEM_READ("MEM_READ ", `Test_Master_2,
pci_master_addr, pci_master_data,
8, 8'h0_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
 
do_pause( 1 ) ;
end
 
disable ES_bounce_blk1 ;
end
begin:enum_monitor1
if (ENUM === 1'bz)
@(ENUM or debounce_time_exp) ;
 
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM not in HighZ after INS bit cleared and handle switch closed") ;
test_fail("ENUM didn't stay in HighZ after INS bit has been cleared and Handle Switch remained closed") ;
error = 1'b1 ;
end
 
generate_pci_transfers = 1'b0 ;
if (pci_err_monitor_done !== 1'b1)
disable pci_err_monitor1 ;
else
error = 1'b1 ;
end
begin:pci_err_monitor1
@(error_event_int) ;
test_fail("either PCI Monitor or PCI Master detected an error on the PCI bus during the test") ;
pci_err_monitor_done = 1'b1 ;
end
begin:ES_bounce_blk1
forever
begin
ES = ~ES ;
#(debounce_period/4) ;
end
end
join
 
while (debounce_time_exp !== 1'b1)
begin
@(ENUM or debounce_time_exp) ;
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM not in HighZ after clear of INS bit and handle switch closed") ;
test_fail("ENUM didn't stay in HighZ after clear of INS bit with Handle Switch remaining closed") ;
error = 1'b1 ;
end
end
 
if (error !== 1'b1)
test_ok ;
 
error = 1'b0 ;
 
test_name = "HOT SWAP EXT BIT SET AND ENUM ASSERTION AFTER INS BIT CLEARED AND HANDLE SWITCH OPENED" ;
generate_pci_transfers = 1'b1 ;
 
debounce_time_exp = 1'b0 ;
 
debounce_time_exp <= #(debounce_period + debounce_period / 4) 1'b1 ;
 
ES = 1'b0 ;
 
fork
begin
while (generate_pci_transfers)
begin
pci_master_data = $random(rnd_seed) ;
pci_master_addr = `BEH_TAR1_MEM_START + {$random(rnd_seed)} % 128 ;
pci_master_addr = pci_master_addr >> 2 ;
pci_master_addr = pci_master_addr << 2 ;
 
PCIU_MEM_WRITE ("MEM_WRITE ", `Test_Master_2 ,
pci_master_addr, pci_master_data, `BC_CONF_READ,
8, `Test_One_Zero_Master_WS, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
do_pause( 1 ) ;
 
PCIU_MEM_READ("MEM_READ ", `Test_Master_2,
pci_master_addr, pci_master_data,
8, 8'h0_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
 
do_pause( 1 ) ;
end
end
begin
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM not in HighZ after INS bit cleared and handle switch closed") ;
test_fail("ENUM didn't stay in HighZ after INS bit cleared and Handle Switch remaining closed") ;
error = 1'b1 ;
end
else
@(ENUM or debounce_time_exp) ;
 
if (ENUM !== 1'b0)
begin
$display("At time %t", $time) ;
$display("ENUM not asserted after INS bit cleared and handle switch opened") ;
test_fail("ENUM was not asserted after INS bit cleared and handle switch opened") ;
error = 1'b1 ;
end
 
generate_pci_transfers = 1'b0 ;
 
end
join
 
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data[22] !== 1'b1)
begin
$display("At time %t", $time) ;
$display("EXT bit in Hot Swap Control and Status Register not set when expected") ;
test_fail("EXT bit in Hot Swap Control and Status Register not set when expected") ;
error = 1'b1 ;
end
 
if (read_data !== 32'h0040_0006)
begin
$display("At time %t", $time) ;
$display("Data value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Data value read from Hot Swap Control and Status Register was not as expected") ;
error = 1'b1 ;
end
 
// turn on the led as well
read_data[19] = 1'b1 ;
configuration_cycle_write
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data to write [31:0]
) ;
 
repeat(3)
@(posedge pci_clock) ;
 
while (debounce_time_exp !== 1'b1)
begin
@(ENUM or debounce_time_exp or LED) ;
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM not in HighZ after clear of EXT bit and handle switch opened") ;
test_fail("ENUM didn't go in HighZ after clear of EXT bit with Handle Switch opened") ;
error = 1'b1 ;
end
 
if (LED !== 1'b0)
begin
$display("At time %t", $time) ;
$display("LED not asserted when LOO bit set") ;
test_fail("LED output was not asserted when LOO bit was set") ;
error = 1'b1 ;
end
end
 
if (error !== 1'b1)
test_ok ;
 
error = 1'b0 ;
 
test_name = "HOT SWAP EXT BIT CLEARED, ENUM DE-ASSERTED AS A RESULT, HANDLE SWITCH OPEN, LED ON" ;
generate_pci_transfers = 1'b1 ;
 
debounce_time_exp = 1'b0 ;
 
debounce_time_exp <= #(debounce_period + debounce_period / 4) 1'b1 ;
 
fork
begin
while (generate_pci_transfers)
begin
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data !== 32'h0008_0006)
begin
$display("At time %t", $time) ;
$display("Data value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Data value read from Hot Swap Control and Status Register was not as expected") ;
error = 1'b1 ;
end
 
pci_master_data = $random(rnd_seed) ;
pci_master_addr = `BEH_TAR1_MEM_START + {$random(rnd_seed)} % 128 ;
pci_master_addr = pci_master_addr >> 2 ;
pci_master_addr = pci_master_addr << 2 ;
 
PCIU_MEM_WRITE ("MEM_WRITE ", `Test_Master_2 ,
pci_master_addr, pci_master_data, `BC_CONF_READ,
8, `Test_One_Zero_Master_WS, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
do_pause( 1 ) ;
 
PCIU_MEM_READ("MEM_READ ", `Test_Master_2,
pci_master_addr, pci_master_data,
8, 8'h0_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
 
do_pause( 1 ) ;
end
 
disable ES_bounce_blk2 ;
end
begin:enum_monitor2
if ((ENUM === 1'bz) & (LED === 1'b0))
@(ENUM or debounce_time_exp or LED) ;
 
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM not in HighZ after EXT bit cleared and handle switch opened") ;
test_fail("ENUM didn't stay in HighZ after EXT bit has been cleared and Handle Switch remained opened") ;
error = 1'b1 ;
end
 
if (LED !== 1'b0)
begin
$display("At time %t", $time) ;
$display("LED not asserted when LOO bit set") ;
test_fail("LED output was not asserted when LOO bit was set") ;
error = 1'b1 ;
end
 
generate_pci_transfers = 1'b0 ;
if (pci_err_monitor_done !== 1'b1)
disable pci_err_monitor2 ;
else
error = 1'b1 ;
end
begin:pci_err_monitor2
@(error_event_int) ;
test_fail("either PCI Monitor or PCI Master detected an error on the PCI bus during the test") ;
pci_err_monitor_done = 1'b1 ;
end
begin:ES_bounce_blk2
forever
begin
ES = ~ES ;
#(debounce_period/4) ;
end
end
join
 
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data !== 32'h0008_0006)
begin
$display("At time %t", $time) ;
$display("Data value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Data value read from Hot Swap Control and Status Register was not as expected") ;
error = 1'b1 ;
end
 
// turn off the led
read_data = 32'hffff_ffff ;
read_data[19] = 1'b0 ;
read_data[17] = 1'b0 ;
 
configuration_cycle_write
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data to write [31:0]
) ;
 
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data !== 32'h0000_0006)
begin
$display("At time %t", $time) ;
$display("Data value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Data value read from Hot Swap Control and Status Register was not as expected") ;
error = 1'b1 ;
end
 
while (debounce_time_exp !== 1'b1)
begin
@(ENUM or debounce_time_exp or LED) ;
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM not in HighZ after clear of EXT bit and handle switch opened") ;
test_fail("ENUM didn't stay in HighZ after clear of EXT bit with Handle Switch opened") ;
error = 1'b1 ;
end
 
if (LED !== 1'bz)
begin
$display("At time %t", $time) ;
$display("LED not de-asserted when LOO bit not set") ;
test_fail("LED output was not de-asserted when LOO bit was unset") ;
error = 1'b1 ;
end
end
 
if (error !== 1'b1)
test_ok ;
 
error = 1'b0 ;
 
test_name = "HOT SWAP INS BIT SET AFTER EXT BIT CLEARED AND HANDLE SWITCH CLOSED" ;
 
generate_pci_transfers = 1'b1 ;
 
debounce_time_exp = 1'b0 ;
 
debounce_time_exp <= #(debounce_period + debounce_period / 4) 1'b1 ;
 
ES = 1'b1 ;
 
fork
begin
while (generate_pci_transfers)
begin
pci_master_data = $random(rnd_seed) ;
pci_master_addr = `BEH_TAR1_MEM_START + {$random(rnd_seed)} % 128 ;
pci_master_addr = pci_master_addr >> 2 ;
pci_master_addr = pci_master_addr << 2 ;
 
PCIU_MEM_WRITE ("MEM_WRITE ", `Test_Master_2 ,
pci_master_addr, pci_master_data, `BC_CONF_READ,
8, `Test_One_Zero_Master_WS, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
do_pause( 1 ) ;
 
PCIU_MEM_READ("MEM_READ ", `Test_Master_2,
pci_master_addr, pci_master_data,
8, 8'h0_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
 
do_pause( 1 ) ;
end
end
begin
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM not in HighZ after EXT bit cleared and handle switch open") ;
test_fail("ENUM didn't stay in HighZ after EXT bit was cleared and Handle Switch remained open") ;
error = 1'b1 ;
end
else
@(ENUM or debounce_time_exp) ;
 
if (ENUM !== 1'b0)
begin
$display("At time %t", $time) ;
$display("ENUM not asserted after EXT bit cleared and handle switch closed") ;
test_fail("ENUM was not asserted after EXT bit was cleared and Handle Switch was closed") ;
error = 1'b1 ;
end
 
generate_pci_transfers = 1'b0 ;
 
end
join
 
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data[23] !== 1'b1)
begin
$display("At time %t", $time) ;
$display("INS bit in Hot Swap Control and Status Register not set when expected") ;
test_fail("INS bit in Hot Swap Control and Status Register not set when expected") ;
error = 1'b1 ;
end
 
if (read_data !== 32'h0080_0006)
begin
$display("At time %t", $time) ;
$display("Value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Unexpected value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
 
while (debounce_time_exp !== 1'b1)
begin
@(ENUM or debounce_time_exp or LED) ;
if (ENUM !== 1'b0)
begin
$display("At time %t", $time) ;
$display("ENUM de-asserted when INS bit set and ENUM not masked") ;
test_fail("ENUM was de-asserted when INS bit was set and ENUM was not masked") ;
error = 1'b1 ;
end
 
if (LED !== 1'bz)
begin
$display("At time %t", $time) ;
$display("LED not de-asserted when LOO bit not set") ;
test_fail("LED output was not de-asserted when LOO bit was unset") ;
error = 1'b1 ;
end
end
 
if (error !== 1'b1)
test_ok ;
error = 1'b0 ;
 
test_name = "AFTER HOT SWAP INS BIT SET, MASK ENUM, OPEN HANDLE SWITCH" ;
 
generate_pci_transfers = 1'b1 ;
 
debounce_time_exp = 1'b0 ;
 
read_data = 32'hffff_ffff ;
 
read_data[23] = 1'b0 ;
read_data[19] = 1'b0 ;
 
// mask enum, do not clear INS bit
configuration_cycle_write
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data to write [31:0]
) ;
 
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data[23] !== 1'b1)
begin
$display("At time %t", $time) ;
$display("INS bit in Hot Swap Control and Status Register not set when expected") ;
test_fail("INS bit in Hot Swap Control and Status Register not set when expected") ;
error = 1'b1 ;
end
 
if (read_data !== 32'h0082_0006)
begin
$display("At time %t", $time) ;
$display("Value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Unexpected value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
 
debounce_time_exp <= #(debounce_period + debounce_period / 4) 1'b1 ;
 
ES = 1'b0 ;
 
fork
begin
while (generate_pci_transfers)
begin
 
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data[23] !== 1'b1)
begin
$display("At time %t", $time) ;
$display("INS bit in Hot Swap Control and Status Register not set when expected") ;
test_fail("INS bit in Hot Swap Control and Status Register not set when expected") ;
error = 1'b1 ;
end
if (read_data !== 32'h0082_0006)
begin
$display("At time %t", $time) ;
$display("Value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Unexpected value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
 
pci_master_data = $random(rnd_seed) ;
pci_master_addr = `BEH_TAR1_MEM_START + {$random(rnd_seed)} % 128 ;
pci_master_addr = pci_master_addr >> 2 ;
pci_master_addr = pci_master_addr << 2 ;
 
PCIU_MEM_WRITE ("MEM_WRITE ", `Test_Master_2 ,
pci_master_addr, pci_master_data, `BC_CONF_READ,
8, `Test_One_Zero_Master_WS, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
do_pause( 1 ) ;
 
PCIU_MEM_READ("MEM_READ ", `Test_Master_2,
pci_master_addr, pci_master_data,
8, 8'h0_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
 
do_pause( 1 ) ;
end
end
begin
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM not in HighZ after EIM and INS bits both set") ;
test_fail("ENUM didn't go to HighZ after EIM bit was set and INS bit was asserted") ;
error = 1'b1 ;
end
else
@(ENUM or debounce_time_exp) ;
 
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM not in HighZ after EIM and INS bits both set") ;
test_fail("ENUM didn't go to HighZ after EIM bit was set and INS bit was asserted") ;
error = 1'b1 ;
end
 
generate_pci_transfers = 1'b0 ;
 
end
join
 
while (debounce_time_exp !== 1'b1)
begin
@(ENUM or debounce_time_exp or LED) ;
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM not in HighZ after EIM and INS bits both set") ;
test_fail("ENUM didn't go to HighZ after EIM bit was set and INS bit was asserted") ;
error = 1'b1 ;
end
 
if (LED !== 1'bz)
begin
$display("At time %t", $time) ;
$display("LED not de-asserted when LOO bit not set") ;
test_fail("LED output was not de-asserted when LOO bit was unset") ;
error = 1'b1 ;
end
end
 
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data[23] !== 1'b1)
begin
$display("At time %t", $time) ;
$display("INS bit in Hot Swap Control and Status Register not set when expected") ;
test_fail("INS bit in Hot Swap Control and Status Register not set when expected") ;
error = 1'b1 ;
end
if (read_data !== 32'h0082_0006)
begin
$display("At time %t", $time) ;
$display("Value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Unexpected value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
 
if (error !== 1'b1)
test_ok ;
 
error = 1'b0 ;
 
test_name = "CLEAR HOT SWAP INS BIT, UNMASK ENUM, HANDLE SWITCH OPENED" ;
 
generate_pci_transfers = 1'b1 ;
 
debounce_time_exp = 1'b0 ;
 
read_data = 32'hffff_ffff ;
read_data[23] = 1'b0 ;
read_data[19] = 1'b0 ;
read_data[17] = 1'b0 ;
 
configuration_cycle_write
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
 
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data[23] !== 1'b1)
begin
$display("At time %t", $time) ;
$display("INS bit in Hot Swap Control and Status Register not set when expected") ;
test_fail("INS bit in Hot Swap Control and Status Register not set when expected") ;
error = 1'b1 ;
end
if (read_data !== 32'h0080_0006)
begin
$display("At time %t", $time) ;
$display("Value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Unexpected value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
 
debounce_time_exp <= #(debounce_period + debounce_period / 4) 1'b1 ;
 
fork
begin
 
read_data = 32'hffff_ffff ;
read_data[19] = 1'b0 ;
read_data[17] = 1'b0 ;
 
configuration_cycle_write
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
 
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data[22] !== 1'b1)
begin
$display("At time %t", $time) ;
$display("EXT bit in Hot Swap Control and Status Register not set when expected") ;
test_fail("EXT bit in Hot Swap Control and Status Register not set when expected") ;
error = 1'b1 ;
end
if (read_data !== 32'h0040_0006)
begin
$display("At time %t", $time) ;
$display("Value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Unexpected value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
 
while (generate_pci_transfers)
begin
 
pci_master_data = $random(rnd_seed) ;
pci_master_addr = `BEH_TAR1_MEM_START + {$random(rnd_seed)} % 128 ;
pci_master_addr = pci_master_addr >> 2 ;
pci_master_addr = pci_master_addr << 2 ;
 
PCIU_MEM_WRITE ("MEM_WRITE ", `Test_Master_2 ,
pci_master_addr, pci_master_data, `BC_CONF_READ,
8, `Test_One_Zero_Master_WS, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
do_pause( 1 ) ;
 
PCIU_MEM_READ("MEM_READ ", `Test_Master_2,
pci_master_addr, pci_master_data,
8, 8'h0_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
 
do_pause( 1 ) ;
end
end
begin
if (ENUM !== 1'b0)
begin
$display("At time %t", $time) ;
$display("ENUM not asserted when INS bit set and ENUM mask unset") ;
test_fail("ENUM was not asserted when INS bit was set and ENUM mask was unset") ;
error = 1'b1 ;
end
else
begin
@(ENUM or debounce_time_exp) ;
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM not de-asserted when INS bit cleared") ;
test_fail("ENUM was not de-asserted when INS bit was cleared") ;
error = 1'b1 ;
end
else
begin
repeat(2)
@(posedge pci_clock) ;
 
if (ENUM !== 1'b0)
begin
$display("At time %t", $time) ;
$display("ENUM not asserted when INS cleared and Handle Switch opened") ;
test_fail("ENUM was not asserted when INS bit was cleared and handle switch was opened") ;
error = 1'b1 ;
end
else
begin
@(ENUM or debounce_time_exp) ;
end
end
end
 
if (ENUM !== 1'b0)
begin
$display("At time %t", $time) ;
$display("ENUM not asserted after INS bit cleared and Handle Switch open") ;
test_fail("ENUM was not asserted after INS bit was cleared and Handle Switch was open") ;
error = 1'b1 ;
end
 
generate_pci_transfers = 1'b0 ;
 
end
join
 
while (debounce_time_exp !== 1'b1)
begin
@(ENUM or debounce_time_exp or LED) ;
if (ENUM !== 1'b0)
begin
$display("At time %t", $time) ;
$display("ENUM not asserted after INS bit cleared and Handle Switch open") ;
test_fail("ENUM was not asserted after INS bit was cleared and Handle Switch was open") ;
error = 1'b1 ;
end
 
if (LED !== 1'bz)
begin
$display("At time %t", $time) ;
$display("LED not de-asserted when LOO bit not set") ;
test_fail("LED output was not de-asserted when LOO bit was unset") ;
error = 1'b1 ;
end
end
 
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data[22] !== 1'b1)
begin
$display("At time %t", $time) ;
$display("EXT bit in Hot Swap Control and Status Register not set when expected") ;
test_fail("EXT bit in Hot Swap Control and Status Register not set when expected") ;
error = 1'b1 ;
end
if (read_data !== 32'h0040_0006)
begin
$display("At time %t", $time) ;
$display("Value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Unexpected value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
 
if (error !== 1'b1)
test_ok ;
 
error = 1'b0 ;
 
test_name = "AFTER HOT SWAP EXT BIT SET, MASK ENUM, CLOSE HANDLE SWITCH" ;
 
generate_pci_transfers = 1'b1 ;
 
debounce_time_exp = 1'b0 ;
 
read_data = 32'hffff_ffff ;
 
read_data[22] = 1'b0 ;
read_data[19] = 1'b0 ;
 
// mask enum, do not clear EXT bit
configuration_cycle_write
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data to write [31:0]
) ;
 
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data[22] !== 1'b1)
begin
$display("At time %t", $time) ;
$display("INS bit in Hot Swap Control and Status Register not set when expected") ;
test_fail("INS bit in Hot Swap Control and Status Register not set when expected") ;
error = 1'b1 ;
end
 
if (read_data !== 32'h0042_0006)
begin
$display("At time %t", $time) ;
$display("Value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Unexpected value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
 
debounce_time_exp <= #(debounce_period + debounce_period / 4) 1'b1 ;
 
ES = 1'b1 ;
 
fork
begin
while (generate_pci_transfers)
begin
 
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data[22] !== 1'b1)
begin
$display("At time %t", $time) ;
$display("INS bit in Hot Swap Control and Status Register not set when expected") ;
test_fail("INS bit in Hot Swap Control and Status Register not set when expected") ;
error = 1'b1 ;
end
if (read_data !== 32'h0042_0006)
begin
$display("At time %t", $time) ;
$display("Value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Unexpected value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
 
pci_master_data = $random(rnd_seed) ;
pci_master_addr = `BEH_TAR1_MEM_START + {$random(rnd_seed)} % 128 ;
pci_master_addr = pci_master_addr >> 2 ;
pci_master_addr = pci_master_addr << 2 ;
 
PCIU_MEM_WRITE ("MEM_WRITE ", `Test_Master_2 ,
pci_master_addr, pci_master_data, `BC_CONF_READ,
8, `Test_One_Zero_Master_WS, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
do_pause( 1 ) ;
 
PCIU_MEM_READ("MEM_READ ", `Test_Master_2,
pci_master_addr, pci_master_data,
8, 8'h0_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
 
do_pause( 1 ) ;
end
end
begin
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM not in HighZ after EIM and EXT bits both set") ;
test_fail("ENUM didn't go to HighZ after EIM bit was set and EXT bit was asserted") ;
error = 1'b1 ;
end
else
@(ENUM or debounce_time_exp) ;
 
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM not in HighZ after EIM and EXT bits both set") ;
test_fail("ENUM didn't go to HighZ after EIM bit was set and EXT bit was asserted") ;
error = 1'b1 ;
end
 
generate_pci_transfers = 1'b0 ;
 
end
join
 
while (debounce_time_exp !== 1'b1)
begin
@(ENUM or debounce_time_exp or LED) ;
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM not in HighZ after EIM and EXT bits both set") ;
test_fail("ENUM didn't go to HighZ after EIM bit was set and EXT bit was asserted") ;
error = 1'b1 ;
end
 
if (LED !== 1'bz)
begin
$display("At time %t", $time) ;
$display("LED not de-asserted when LOO bit not set") ;
test_fail("LED output was not de-asserted when LOO bit was unset") ;
error = 1'b1 ;
end
end
 
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data[22] !== 1'b1)
begin
$display("At time %t", $time) ;
$display("EXT bit in Hot Swap Control and Status Register not set when expected") ;
test_fail("EXT bit in Hot Swap Control and Status Register not set when expected") ;
error = 1'b1 ;
end
if (read_data !== 32'h0042_0006)
begin
$display("At time %t", $time) ;
$display("Value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Unexpected value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
 
if (error !== 1'b1)
test_ok ;
 
error = 1'b0 ;
 
test_name = "CLEAR HOT SWAP EXT BIT, UNMASK ENUM, HANDLE SWITCH CLOSED" ;
 
generate_pci_transfers = 1'b1 ;
 
debounce_time_exp = 1'b0 ;
 
read_data = 32'hffff_ffff ;
read_data[23] = 1'b0 ;
read_data[22] = 1'b0 ;
read_data[19] = 1'b0 ;
read_data[17] = 1'b0 ;
 
configuration_cycle_write
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
 
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data[22] !== 1'b1)
begin
$display("At time %t", $time) ;
$display("EXT bit in Hot Swap Control and Status Register not set when expected") ;
test_fail("EXT bit in Hot Swap Control and Status Register not set when expected") ;
error = 1'b1 ;
end
if (read_data !== 32'h0040_0006)
begin
$display("At time %t", $time) ;
$display("Value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Unexpected value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
 
debounce_time_exp <= #(debounce_period + debounce_period / 4) 1'b1 ;
 
fork
begin
 
read_data = 32'hffff_ffff ;
read_data[19] = 1'b0 ;
read_data[17] = 1'b0 ;
 
configuration_cycle_write
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
 
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data[23] !== 1'b1)
begin
$display("At time %t", $time) ;
$display("INS bit in Hot Swap Control and Status Register not set when expected") ;
test_fail("INS bit in Hot Swap Control and Status Register not set when expected") ;
error = 1'b1 ;
end
if (read_data !== 32'h0080_0006)
begin
$display("At time %t", $time) ;
$display("Value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Unexpected value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
 
while (generate_pci_transfers)
begin
 
pci_master_data = $random(rnd_seed) ;
pci_master_addr = `BEH_TAR1_MEM_START + {$random(rnd_seed)} % 128 ;
pci_master_addr = pci_master_addr >> 2 ;
pci_master_addr = pci_master_addr << 2 ;
 
PCIU_MEM_WRITE ("MEM_WRITE ", `Test_Master_2 ,
pci_master_addr, pci_master_data, `BC_CONF_READ,
8, `Test_One_Zero_Master_WS, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
do_pause( 1 ) ;
 
PCIU_MEM_READ("MEM_READ ", `Test_Master_2,
pci_master_addr, pci_master_data,
8, 8'h0_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
 
do_pause( 1 ) ;
end
end
begin
if (ENUM !== 1'b0)
begin
$display("At time %t", $time) ;
$display("ENUM not asserted when EXT bit set and ENUM mask unset") ;
test_fail("ENUM was not asserted when EXT bit was set and ENUM mask was unset") ;
error = 1'b1 ;
end
else
begin
@(ENUM or debounce_time_exp) ;
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM not de-asserted when EXT bit cleared") ;
test_fail("ENUM was not de-asserted when EXT bit was cleared") ;
error = 1'b1 ;
end
else
begin
repeat(2)
@(posedge pci_clock) ;
 
if (ENUM !== 1'b0)
begin
$display("At time %t", $time) ;
$display("ENUM not asserted when EXT cleared and Handle Switch closed") ;
test_fail("ENUM was not asserted when EXT bit was cleared and handle switch was closed") ;
error = 1'b1 ;
end
else
begin
@(ENUM or debounce_time_exp) ;
end
end
end
 
if (ENUM !== 1'b0)
begin
$display("At time %t", $time) ;
$display("ENUM not asserted after EXT bit cleared and Handle Switch closed") ;
test_fail("ENUM was not asserted after EXT bit was cleared and Handle Switch was closed") ;
error = 1'b1 ;
end
 
generate_pci_transfers = 1'b0 ;
 
end
join
 
while (debounce_time_exp !== 1'b1)
begin
@(ENUM or debounce_time_exp or LED) ;
if (ENUM !== 1'b0)
begin
$display("At time %t", $time) ;
$display("ENUM not asserted after EXT bit cleared and Handle Switch closed") ;
test_fail("ENUM was not asserted after EXT bit was cleared and Handle Switch was closed") ;
error = 1'b1 ;
end
 
if (LED !== 1'bz)
begin
$display("At time %t", $time) ;
$display("LED not de-asserted when LOO bit not set") ;
test_fail("LED output was not de-asserted when LOO bit was unset") ;
error = 1'b1 ;
end
end
 
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data[23] !== 1'b1)
begin
$display("At time %t", $time) ;
$display("INS bit in Hot Swap Control and Status Register not set when expected") ;
test_fail("INS bit in Hot Swap Control and Status Register not set when expected") ;
error = 1'b1 ;
end
if (read_data !== 32'h0080_0006)
begin
$display("At time %t", $time) ;
$display("Value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Unexpected value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
 
if (error !== 1'b1)
test_ok ;
 
error = 1'b0 ;
 
test_name = "MASK HOT SWAP ENUM WHEN INS BIT SET, ENUM DE-ASSERTION, CLEAR ENUM MASK AND INS AT THE SAME TIME" ;
 
generate_pci_transfers = 1'b1 ;
 
debounce_time_exp = 1'b0 ;
 
read_data = 32'hffff_ffff ;
read_data[23] = 1'b0 ;
read_data[22] = 1'b0 ;
read_data[19] = 1'b0 ;
read_data[17] = 1'b1 ;
 
configuration_cycle_write
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
 
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data[23] !== 1'b1)
begin
$display("At time %t", $time) ;
$display("INS bit in Hot Swap Control and Status Register not set when expected") ;
test_fail("INS bit in Hot Swap Control and Status Register not set when expected") ;
error = 1'b1 ;
end
if (read_data !== 32'h0082_0006)
begin
$display("At time %t", $time) ;
$display("Value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Unexpected value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
 
debounce_time_exp <= #(debounce_period + debounce_period / 4) 1'b1 ;
 
fork
begin
 
read_data = 32'hffff_ffff ;
read_data[22] = 1'b0 ;
read_data[19] = 1'b0 ;
read_data[17] = 1'b0 ;
 
configuration_cycle_write
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
 
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data !== 32'h0000_0006)
begin
$display("At time %t", $time) ;
$display("Value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Unexpected value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
 
while (generate_pci_transfers)
begin
 
pci_master_data = $random(rnd_seed) ;
pci_master_addr = `BEH_TAR1_MEM_START + {$random(rnd_seed)} % 128 ;
pci_master_addr = pci_master_addr >> 2 ;
pci_master_addr = pci_master_addr << 2 ;
 
PCIU_MEM_WRITE ("MEM_WRITE ", `Test_Master_2 ,
pci_master_addr, pci_master_data, `BC_CONF_READ,
8, `Test_One_Zero_Master_WS, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
do_pause( 1 ) ;
 
PCIU_MEM_READ("MEM_READ ", `Test_Master_2,
pci_master_addr, pci_master_data,
8, 8'h0_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
 
do_pause( 1 ) ;
end
end
begin
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM asserted when INS bit set and ENUM masked") ;
test_fail("ENUM was asserted when INS bit was set and ENUM was masked") ;
error = 1'b1 ;
end
else
begin
@(ENUM or debounce_time_exp) ;
end
 
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM not de-asserted after INS bit cleared.") ;
test_fail("ENUM was not de-asserted after INS bit was cleared") ;
error = 1'b1 ;
end
 
generate_pci_transfers = 1'b0 ;
 
end
join
 
while (debounce_time_exp !== 1'b1)
begin
@(ENUM or debounce_time_exp or LED) ;
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM not de-asserted after INS bit cleared") ;
test_fail("ENUM was not de-asserted after INS bit was cleared") ;
error = 1'b1 ;
end
 
if (LED !== 1'bz)
begin
$display("At time %t", $time) ;
$display("LED not de-asserted when LOO bit not set") ;
test_fail("LED output was not de-asserted when LOO bit was unset") ;
error = 1'b1 ;
end
end
 
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data !== 32'h0000_0006)
begin
$display("At time %t", $time) ;
$display("Value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Unexpected value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
 
if (error !== 1'b1)
test_ok ;
 
error = 1'b0 ;
 
test_name = "OPEN HOT SWAP SWITCH AFTER INS CLEARED, MASK ENUM" ;
 
generate_pci_transfers = 1'b1 ;
 
debounce_time_exp = 1'b0 ;
 
read_data = 32'hffff_ffff ;
read_data[23] = 1'b0 ;
read_data[22] = 1'b0 ;
read_data[19] = 1'b1 ;
read_data[17] = 1'b1 ;
 
configuration_cycle_write
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
 
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data !== 32'h000A_0006)
begin
$display("At time %t", $time) ;
$display("Value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Unexpected value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
 
debounce_time_exp <= #(debounce_period + debounce_period / 4) 1'b1 ;
ES = 1'b0 ;
 
fork
begin
while (generate_pci_transfers)
begin
 
pci_master_data = $random(rnd_seed) ;
pci_master_addr = `BEH_TAR1_MEM_START + {$random(rnd_seed)} % 128 ;
pci_master_addr = pci_master_addr >> 2 ;
pci_master_addr = pci_master_addr << 2 ;
 
PCIU_MEM_WRITE ("MEM_WRITE ", `Test_Master_2 ,
pci_master_addr, pci_master_data, `BC_CONF_READ,
8, `Test_One_Zero_Master_WS, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
do_pause( 1 ) ;
 
PCIU_MEM_READ("MEM_READ ", `Test_Master_2,
pci_master_addr, pci_master_data,
8, 8'h0_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
 
do_pause( 1 ) ;
end
end
begin
if ((ENUM !== 1'bz) | (LED !== 1'b0))
begin
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM asserted when INS and EXT bits cleared and ENUM masked") ;
test_fail("ENUM was asserted when INS and EXT bits were clear and ENUM was masked") ;
error = 1'b1 ;
end
 
if (LED !== 1'b0)
begin
$display("At time %t", $time) ;
$display("LED not asserted when LOO bit set in HS_CSR") ;
test_fail("LED was not asserted when LOO bit was set in HS_CSR") ;
error = 1'b1 ;
end
end
else
begin
@(ENUM or debounce_time_exp or LED) ;
end
 
if ((ENUM !== 1'bz) | (LED !== 1'b0))
begin
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM asserted when INS and EXT bits cleared and ENUM masked") ;
test_fail("ENUM was asserted when INS and EXT bits were clear and ENUM was masked") ;
error = 1'b1 ;
end
 
if (LED !== 1'b0)
begin
$display("At time %t", $time) ;
$display("LED not asserted when LOO bit set in HS_CSR") ;
test_fail("LED was not asserted when LOO bit was set in HS_CSR") ;
error = 1'b1 ;
end
end
 
generate_pci_transfers = 1'b0 ;
 
end
join
 
while (debounce_time_exp !== 1'b1)
begin
@(ENUM or debounce_time_exp or LED) ;
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM asserted when INS and EXT bits cleared and ENUM masked") ;
test_fail("ENUM was asserted when INS and EXT bits were clear and ENUM was masked") ;
error = 1'b1 ;
end
 
if (LED !== 1'b0)
begin
$display("At time %t", $time) ;
$display("LED not asserted when LOO bit set") ;
test_fail("LED output was not asserted when LOO bit was set") ;
error = 1'b1 ;
end
end
 
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data[22] !== 1'b1)
begin
$display("At time %t", $time) ;
$display("EXT bit is HS_CSR not set when expected") ;
test_fail("EXT bit is HS_CSR was not set when expected") ;
error = 1'b1 ;
end
 
if (read_data !== 32'h004A_0006)
begin
$display("At time %t", $time) ;
$display("Value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Unexpected value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
 
if (error !== 1'b1)
test_ok ;
 
test_name = "CLEAR HOT SWAP EXT BIT AND UNMASK ENUM AT THE SAME TIME, ENUM IN HIGHZ ALL THE TIME" ;
 
generate_pci_transfers = 1'b1 ;
 
debounce_time_exp = 1'b0 ;
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
 
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data !== 32'h004A_0006)
begin
$display("At time %t", $time) ;
$display("Value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Unexpected value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
 
debounce_time_exp <= #(debounce_period + debounce_period / 4) 1'b1 ;
 
fork
begin
read_data = 32'hffff_ffff ;
read_data[23] = 1'b0 ;
read_data[19] = 1'b0 ;
read_data[17] = 1'b0 ;
configuration_cycle_write
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data !== 32'h0000_0006)
begin
$display("At time %t", $time) ;
$display("Value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Unexpected value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
 
while (generate_pci_transfers)
begin
 
pci_master_data = $random(rnd_seed) ;
pci_master_addr = `BEH_TAR1_MEM_START + {$random(rnd_seed)} % 128 ;
pci_master_addr = pci_master_addr >> 2 ;
pci_master_addr = pci_master_addr << 2 ;
 
PCIU_MEM_WRITE ("MEM_WRITE ", `Test_Master_2 ,
pci_master_addr, pci_master_data, `BC_CONF_READ,
8, `Test_One_Zero_Master_WS, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
do_pause( 1 ) ;
 
PCIU_MEM_READ("MEM_READ ", `Test_Master_2,
pci_master_addr, pci_master_data,
8, 8'h0_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
 
do_pause( 1 ) ;
end
end
begin
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM asserted when INS and EXT bits cleared") ;
test_fail("ENUM was asserted when INS and EXT bits were clear") ;
error = 1'b1 ;
end
else
begin
@(ENUM or debounce_time_exp) ;
end
 
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM asserted when INS and EXT bits cleared") ;
test_fail("ENUM was asserted when INS and EXT bits were clear") ;
error = 1'b1 ;
end
 
generate_pci_transfers = 1'b0 ;
 
end
join
 
while (debounce_time_exp !== 1'b1)
begin
@(ENUM or debounce_time_exp or LED) ;
if (ENUM !== 1'bz)
begin
$display("At time %t", $time) ;
$display("ENUM asserted when INS and EXT bits cleared") ;
test_fail("ENUM was asserted when INS and EXT bits were clear") ;
error = 1'b1 ;
end
 
if (LED !== 1'bz)
begin
$display("At time %t", $time) ;
$display("LED not de-asserted when LOO bit not set") ;
test_fail("LED output was not de-asserted when LOO bit was not set") ;
error = 1'b1 ;
end
end
 
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
(`PCI_CAP_PTR_VAL) >> 2, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
if ((read_data ^ read_data) !== 'h0)
begin
$display("At time %t", $time) ;
$display("INVALID Data value read from Hot Swap Control and Status Register") ;
test_fail("INVALID Data value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
if (read_data !== 32'h0000_0006)
begin
$display("At time %t", $time) ;
$display("Value read from Hot Swap Control and Status Register not as expected") ;
test_fail("Unexpected value was read from Hot Swap Control and Status Register") ;
error = 1'b1 ;
end
 
if (error !== 1'b1)
test_ok ;
end
endtask
 
`endif
 
task display_warning;
input [31:0] error_address ;
input [31:0] expected_data ;
input [31:0] actual ;
begin
$display("At time %t", $time) ;
$display("Read from address %h produced wrong result! \nExpected value was %h\tread value was %h!", error_address, expected_data, actual) ;
end
endtask // display warning
12735,7 → 15390,7
write_flags`SUBSEQ_WAITS = wb_subseq_waits ;
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
 
write_data`WRITE_ADDRESS = { `WB_CONFIGURATION_BASE, offset } ;
write_data`WRITE_ADDRESS = { `WB_CONFIGURATION_BASE, offset } + ({$random} % 4) ;
write_data`WRITE_SEL = 4'h1 ;
write_data`WRITE_DATA = data ;
 
12754,7 → 15409,7
offset = {4'h1, `P_BA0_ADDR, 2'b00} ; // PCI Base Address 0
data = Target_Base_Addr_R[0] ; // `TAR0_BASE_ADDR_0 = 32'h1000_0000
 
write_data`WRITE_ADDRESS = temp_var + offset ;
write_data`WRITE_ADDRESS = temp_var + offset + ({$random} % 4) ;
write_data`WRITE_SEL = 4'hf ;
write_data`WRITE_DATA = data ;
 
12834,7 → 15489,7
temp_var = { `WB_CONFIGURATION_BASE, 12'h000 } ;
temp_var[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
 
write_data`WRITE_ADDRESS = temp_var + offset ;
write_data`WRITE_ADDRESS = temp_var + offset + ({$random} % 4) ;
write_data`WRITE_SEL = 4'h1 ;
write_data`WRITE_DATA = data ;
 
12850,7 → 15505,7
offset = {4'h1, `P_BA0_ADDR, 2'b00} ; // PCI Base Address 0
data = Target_Base_Addr_R[0] ; // `TAR0_BASE_ADDR_0 = 32'h1000_0000
 
write_data`WRITE_ADDRESS = temp_var + offset ;
write_data`WRITE_ADDRESS = temp_var + offset + ({$random} % 4) ;
write_data`WRITE_SEL = 4'hf ;
write_data`WRITE_DATA = data ;
 
12876,7 → 15531,7
offset = {4'h1, `P_BA1_ADDR, 2'b00} ; // PCI Base Address 1
data = Target_Base_Addr_R[1] ; // `TAR0_BASE_ADDR_1 = 32'h2000_0000
 
write_data`WRITE_ADDRESS = temp_var + offset ;
write_data`WRITE_ADDRESS = temp_var + offset + ({$random} % 4) ;
write_data`WRITE_SEL = 4'hf ;
write_data`WRITE_DATA = data ;
 
12891,7 → 15546,7
offset = {4'h1, `P_BA2_ADDR, 2'b00} ; // PCI Base Address 2
data = Target_Base_Addr_R[2] ; // `TAR0_BASE_ADDR_2 = 32'h3000_0000
 
write_data`WRITE_ADDRESS = temp_var + offset ;
write_data`WRITE_ADDRESS = temp_var + offset + ({$random} % 4) ;
write_data`WRITE_SEL = 4'hf ;
write_data`WRITE_DATA = data ;
 
12906,7 → 15561,7
offset = {4'h1, `P_BA3_ADDR, 2'b00} ; // PCI Base Address 3
data = Target_Base_Addr_R[3] ; // `TAR0_BASE_ADDR_3 = 32'h4000_0000
 
write_data`WRITE_ADDRESS = temp_var + offset ;
write_data`WRITE_ADDRESS = temp_var + offset + ({$random} % 4) ;
write_data`WRITE_SEL = 4'hf ;
write_data`WRITE_DATA = data ;
 
12921,7 → 15576,7
offset = {4'h1, `P_BA4_ADDR, 2'b00} ; // PCI Base Address 4
data = Target_Base_Addr_R[4] ; // `TAR0_BASE_ADDR_4 = 32'h5000_0000
 
write_data`WRITE_ADDRESS = temp_var + offset ;
write_data`WRITE_ADDRESS = temp_var + offset + ({$random} % 4) ;
write_data`WRITE_SEL = 4'hf ;
write_data`WRITE_DATA = data ;
 
12936,7 → 15591,7
offset = {4'h1, `P_BA5_ADDR, 2'b00} ; // PCI Base Address 5
data = Target_Base_Addr_R[5] ; // `TAR0_BASE_ADDR_5 = 32'h6000_0000
 
write_data`WRITE_ADDRESS = temp_var + offset ;
write_data`WRITE_ADDRESS = temp_var + offset + ({$random} % 4) ;
write_data`WRITE_SEL = 4'hf ;
write_data`WRITE_DATA = data ;
 
19406,7 → 22061,7
write_flags`WB_TRANSFER_AUTO_RTY = 1'b0 ;
 
// initiate a read request
read_data`READ_ADDRESS = target_address ;
read_data`READ_ADDRESS = target_address + ({$random} % 4) ;
read_data`READ_SEL = 4'hF ;
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
if ((read_status`CYC_ACTUAL_TRANSFER !== 0) || (read_status`CYC_RTY !== 1'b1))
19419,7 → 22074,7
// handle retries from now on
write_flags`WB_TRANSFER_AUTO_RTY = 1'b1 ;
 
write_data`WRITE_ADDRESS = target_address + 4 ;
write_data`WRITE_ADDRESS = target_address + 4 + ({$random} % 4) ;
write_data`WRITE_DATA = 32'hF0F0_0F0F ;
write_data`WRITE_SEL = 4'hF ;
 
19436,7 → 22091,7
@(posedge wb_clock) ;
// now perform a read
read_data`READ_ADDRESS = target_address + 4 ;
read_data`READ_ADDRESS = target_address + 4 + ({$random} % 4) ;
read_data`READ_SEL = 4'hF ;
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
if (read_status`CYC_ACTUAL_TRANSFER !== 1)
19541,7 → 22196,7
 
temp_var = { `WB_CONFIGURATION_BASE, 12'h000 } ;
temp_var[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
write_data`WRITE_ADDRESS = temp_var + offset ;
write_data`WRITE_ADDRESS = temp_var + offset + ({$random} % 4) ;
write_data`WRITE_SEL = byte_enable ;
write_data`WRITE_DATA = data ;
 
19625,7 → 22280,7
temp_var = { `WB_CONFIGURATION_BASE, 12'h000 } ;
temp_var[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
 
read_data`READ_ADDRESS = temp_var + offset ;
read_data`READ_ADDRESS = temp_var + offset + ({$random} % 4) ;
read_data`READ_SEL = byte_enable ;
 
wishbone_master.wb_single_read( read_data, read_flags, read_status ) ;
20307,7 → 22962,7
begin
 
// do one dummy read, to receive bus gnt
read_data`READ_ADDRESS = target_address ;
read_data`READ_ADDRESS = target_address + ({$random} % 4) ;
read_data`READ_SEL = 4'hF ;
 
// handle retries
20321,13 → 22976,13
disable main ;
end
 
write_data`WRITE_ADDRESS = target_address + 64;
write_data`WRITE_ADDRESS = target_address + 64 + ({$random} % 4) ;
write_data`WRITE_DATA = 32'hABCD_EF12 ;
write_data`WRITE_SEL = 4'hF ;
 
wishbone_master.blk_write_data[0] = write_data ;
write_data`WRITE_ADDRESS = target_address + 128 ;
write_data`WRITE_ADDRESS = target_address + 128 + ({$random} % 4) ;
write_data`WRITE_DATA = ~write_data`WRITE_DATA ;
write_data`WRITE_SEL = 4'hF ;
 
20347,7 → 23002,7
end
 
// read data back
read_data`READ_ADDRESS = target_address + 64 ;
read_data`READ_ADDRESS = target_address + 64 + ({$random} % 4) ;
read_data`READ_SEL = 4'hF ;
 
// handle retries
20369,7 → 23024,7
end
 
// read second data back
read_data`READ_ADDRESS = target_address + 128 ;
read_data`READ_ADDRESS = target_address + 128 + ({$random} % 4) ;
read_data`READ_SEL = 4'hF ;
 
// handle retries
20511,7 → 23166,6
// configure target image 1 via bus accesses
pci_configure_pci_target_image
(
1'b1, // selects whether to configure image with bus accesses or directly with dot notation in the configuration space
test_image_num, // image number
Target_Base_Addr_R[test_image_num], // base address
Target_Addr_Mask_R[test_image_num], // address mask
20682,7 → 23336,6
 
reg [31:0] image_base ;
reg [31:0] target_address ;
 
begin:main
 
// set behavioral target to respond normally
20724,7 → 23377,6
 
pci_configure_wb_slave_image
(
1'b1, // use_bus
test_image_num, // image_num
image_base, // base address
32'hFFFF_C000, // address mask
21096,7 → 23748,6
// disable the image
pci_configure_wb_slave_image
(
1'b1, // use_bus
test_image_num, // image_num
image_base, // base address
32'h0000_0000, // address mask
21223,15 → 23874,15
case (cur_inc_burst_type)
2'b00:
begin
write_data`WRITE_ADDRESS = image_base + i * 4 + 'd8 ;
write_data`WRITE_ADDRESS = image_base + i * 4 + 'd8 + ({$random} % 4) ;
end
2'b01:
begin
write_data`WRITE_ADDRESS = ( image_base[31:4] + (i >> 2) ) << 4 ;
write_data`WRITE_ADDRESS = (( image_base[31:4] + (i >> 2) ) << 4) + ({$random} % 4) ;
if ( (i % 4) === 0 )
write_data`WRITE_ADDRESS = write_data`WRITE_ADDRESS + 'd8 ;
write_data`WRITE_ADDRESS = write_data`WRITE_ADDRESS + 'd8 + ({$random} % 4) ;
else
write_data`WRITE_ADDRESS = write_data`WRITE_ADDRESS + (4'd8 + (i * 4 % 4) ;
write_data`WRITE_ADDRESS = write_data`WRITE_ADDRESS + (4'd8 + (i * 4 % 4) + ({$random} % 4) ;
end
2'b10:
begin
21242,10 → 23893,10
endcase
 
if (cur_inc_burst_type === 0)
write_data`WRITE_ADDRESS = image_base + i * 4 + 4 ;
write_data`WRITE_ADDRESS = image_base + i * 4 + 4 + ({$random} % 4) ;
 
if ( (i % 4) === 0)
write_data`WRITE_ADDRESS = {image_base[31:4] + (i >> 2), 4'h4}
write_data`WRITE_ADDRESS = {image_base[31:4] + (i >> 2), 4'h4} + ({$random} % 4) ;
end
fork
/trunk/bench/verilog/pci_bench_common_tasks.v
38,10 → 38,12
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2003/01/21 16:06:50 mihad
// Bug fixes, testcases added.
//
//
 
task pci_configure_pci_target_image ;
input use_bus ; // selects whether to configure image with bus accesses or directly with dot notation in the configuration space
input [2:0] image_num ; // image number
input [31:0] ba ; // base address
input [31:0] am ; // address mask
66,174 → 68,86
end
 
in_use = 1'b1 ;
if (use_bus !== 1'b0)
 
if (image_num === 0)
begin
if (image_num === 0)
begin
ctrl_offset = {4'h1, `P_IMG_CTRL0_ADDR, 2'b00} ;
ba_offset = {4'h1, `P_BA0_ADDR, 2'b00} ;
am_offset = {4'h1, `P_AM0_ADDR, 2'b00} ;
ta_offset = {4'h1, `P_TA0_ADDR, 2'b00} ;
end
else if (image_num === 1)
begin
ctrl_offset = {4'h1, `P_IMG_CTRL1_ADDR, 2'b00} ;
ba_offset = {4'h1, `P_BA1_ADDR, 2'b00} ;
am_offset = {4'h1, `P_AM1_ADDR, 2'b00} ;
ta_offset = {4'h1, `P_TA1_ADDR, 2'b00} ;
end
else if (image_num === 2)
begin
ctrl_offset = {4'h1, `P_IMG_CTRL2_ADDR, 2'b00} ;
ba_offset = {4'h1, `P_BA2_ADDR, 2'b00} ;
am_offset = {4'h1, `P_AM2_ADDR, 2'b00} ;
ta_offset = {4'h1, `P_TA2_ADDR, 2'b00} ;
end
else if (image_num === 3)
begin
ctrl_offset = {4'h1, `P_IMG_CTRL3_ADDR, 2'b00} ;
ba_offset = {4'h1, `P_BA3_ADDR, 2'b00} ;
am_offset = {4'h1, `P_AM3_ADDR, 2'b00} ;
ta_offset = {4'h1, `P_TA3_ADDR, 2'b00} ;
end
else if (image_num === 4)
begin
ctrl_offset = {4'h1, `P_IMG_CTRL4_ADDR, 2'b00} ;
ba_offset = {4'h1, `P_BA4_ADDR, 2'b00} ;
am_offset = {4'h1, `P_AM4_ADDR, 2'b00} ;
ta_offset = {4'h1, `P_TA4_ADDR, 2'b00} ;
end
else if (image_num === 5)
begin
ctrl_offset = {4'h1, `P_IMG_CTRL5_ADDR, 2'b00} ;
ba_offset = {4'h1, `P_BA5_ADDR, 2'b00} ;
am_offset = {4'h1, `P_AM5_ADDR, 2'b00} ;
ta_offset = {4'h1, `P_TA5_ADDR, 2'b00} ;
end
ctrl_offset = {4'h1, `P_IMG_CTRL0_ADDR, 2'b00} ;
ba_offset = {4'h1, `P_BA0_ADDR, 2'b00} ;
am_offset = {4'h1, `P_AM0_ADDR, 2'b00} ;
ta_offset = {4'h1, `P_TA0_ADDR, 2'b00} ;
end
else if (image_num === 1)
begin
ctrl_offset = {4'h1, `P_IMG_CTRL1_ADDR, 2'b00} ;
ba_offset = {4'h1, `P_BA1_ADDR, 2'b00} ;
am_offset = {4'h1, `P_AM1_ADDR, 2'b00} ;
ta_offset = {4'h1, `P_TA1_ADDR, 2'b00} ;
end
else if (image_num === 2)
begin
ctrl_offset = {4'h1, `P_IMG_CTRL2_ADDR, 2'b00} ;
ba_offset = {4'h1, `P_BA2_ADDR, 2'b00} ;
am_offset = {4'h1, `P_AM2_ADDR, 2'b00} ;
ta_offset = {4'h1, `P_TA2_ADDR, 2'b00} ;
end
else if (image_num === 3)
begin
ctrl_offset = {4'h1, `P_IMG_CTRL3_ADDR, 2'b00} ;
ba_offset = {4'h1, `P_BA3_ADDR, 2'b00} ;
am_offset = {4'h1, `P_AM3_ADDR, 2'b00} ;
ta_offset = {4'h1, `P_TA3_ADDR, 2'b00} ;
end
else if (image_num === 4)
begin
ctrl_offset = {4'h1, `P_IMG_CTRL4_ADDR, 2'b00} ;
ba_offset = {4'h1, `P_BA4_ADDR, 2'b00} ;
am_offset = {4'h1, `P_AM4_ADDR, 2'b00} ;
ta_offset = {4'h1, `P_TA4_ADDR, 2'b00} ;
end
else if (image_num === 5)
begin
ctrl_offset = {4'h1, `P_IMG_CTRL5_ADDR, 2'b00} ;
ba_offset = {4'h1, `P_BA5_ADDR, 2'b00} ;
am_offset = {4'h1, `P_AM5_ADDR, 2'b00} ;
ta_offset = {4'h1, `P_TA5_ADDR, 2'b00} ;
end
 
// Set Base Address of IMAGE
config_write( ba_offset, ba | {31'h0, io_nmem}, 4'hF, ok ) ;
if ( ok !== 1 )
begin
in_use = 1'b0 ;
disable main ;
end
// Set Base Address of IMAGE
config_write( ba_offset, ba | {31'h0, io_nmem}, 4'hF, ok ) ;
if ( ok !== 1 )
begin
in_use = 1'b0 ;
disable main ;
end
 
// Set Address Mask of IMAGE
config_write( am_offset, am, 4'hF, ok ) ;
if ( ok !== 1 )
begin
in_use = 1'b0 ;
disable main ;
end
// Set Address Mask of IMAGE
config_write( am_offset, am, 4'hF, ok ) ;
if ( ok !== 1 )
begin
in_use = 1'b0 ;
disable main ;
end
 
// Set Translation Address of IMAGE
config_write( ta_offset, ta, 4'hF, ok ) ;
if ( ok !== 1 )
begin
in_use = 1'b0 ;
disable main ;
end
// Set Translation Address of IMAGE
config_write( ta_offset, ta, 4'hF, ok ) ;
if ( ok !== 1 )
begin
in_use = 1'b0 ;
disable main ;
end
 
// Set IMAGE Control Register
config_write( ctrl_offset, {29'd0, at_en, pref_en, 1'b0}, 4'hF, ok ) ;
if ( ok !== 1 )
begin
in_use = 1'b0 ;
disable main ;
end
end
else
// Set IMAGE Control Register
config_write( ctrl_offset, {29'd0, at_en, pref_en, 1'b0}, 4'hF, ok ) ;
if ( ok !== 1 )
begin
if (image_num === 0)
begin
`ifdef HOST
`ifdef NO_CNF_IMAGE
`ifdef PCI_IMAGE0 // if PCI bridge is HOST and IMAGE0 is assigned as general image space
// set base address
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba0_bit31_12 = ba[31:12] ;
// set control register
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl0_bit2_1 = {at_en, pref_en} ;
// set memory map - part of base address
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba0_bit0 = io_nmem ;
// set address mask
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am0 = am[31:12] ;
// set translation address
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta0 = ta[31:12] ;
`endif
`else // if PCI bridge is HOST and IMAGE0 is assigned to PCI configuration space
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba0_bit31_12 = ba[31:12] ;
`endif
`else // if PCI bridge is GUEST, then IMAGE0 is assigned to PCI configuration space
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba0_bit31_12 = ba[31:12] ;
`endif
end
else if (image_num === 1)
begin
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl1_bit2_1 = {at_en, pref_en} ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba1_bit31_12 = ba[31:12] ;
`ifdef HOST
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba1_bit0 = io_nmem ;
`endif
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am1 = am[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta1 = ta[31:12] ;
end
else if (image_num === 2)
begin
`ifdef PCI_IMAGE2
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl2_bit2_1 = {at_en, pref_en} ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba2_bit31_12 = ba[31:12] ;
`ifdef HOST
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba2_bit0 = io_nmem ;
`endif
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am2 = am[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta2 = ta[31:12] ;
`endif
end
else if (image_num === 3)
begin
`ifdef PCI_IMAGE3
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl3_bit2_1 = {at_en, pref_en} ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba3_bit31_12 = ba[31:12] ;
`ifdef HOST
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba3_bit0 = io_nmem ;
`endif
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am3 = am[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta3 = ta[31:12] ;
`endif
end
else if (image_num === 4)
begin
`ifdef PCI_IMAGE4
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl4_bit2_1 = {at_en, pref_en} ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba4_bit31_12 = ba[31:12] ;
`ifdef HOST
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba4_bit0 = io_nmem ;
`endif
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am4 = am[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta4 = ta[31:12] ;
`endif
end
else if (image_num === 5)
begin
`ifdef PCI_IMAGE5
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl5_bit2_1 = {at_en, pref_en} ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba5_bit31_12 = ba[31:12] ;
`ifdef HOST
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba5_bit0 = io_nmem ;
`endif
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am5 = am[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta5 = ta[31:12] ;
`endif
end
in_use = 1'b0 ;
disable main ;
end
 
in_use = 1'b0 ;
end
endtask // pci_configure_pci_target_image
 
task pci_configure_wb_slave_image ;
input use_bus ; // selects whether to configure image with bus accesses or directly with dot notation in the configuration space
input [2:0] image_num ; // image number
input [31:0] ba ; // base address
input [31:0] am ; // address mask
259,136 → 173,73
end
 
in_use = 1'b1 ;
if (use_bus !== 1'b0)
 
if (image_num === 1)
begin
if (image_num === 1)
begin
ctrl_offset = {4'h1, `W_IMG_CTRL1_ADDR, 2'b00} ;
ba_offset = {4'h1, `W_BA1_ADDR, 2'b00} ;
am_offset = {4'h1, `W_AM1_ADDR, 2'b00} ;
ta_offset = {4'h1, `W_TA1_ADDR, 2'b00} ;
end
else if (image_num === 2)
begin
ctrl_offset = {4'h1, `W_IMG_CTRL2_ADDR, 2'b00} ;
ba_offset = {4'h1, `W_BA2_ADDR, 2'b00} ;
am_offset = {4'h1, `W_AM2_ADDR, 2'b00} ;
ta_offset = {4'h1, `W_TA2_ADDR, 2'b00} ;
end
else if (image_num === 3)
begin
ctrl_offset = {4'h1, `W_IMG_CTRL3_ADDR, 2'b00} ;
ba_offset = {4'h1, `W_BA3_ADDR, 2'b00} ;
am_offset = {4'h1, `W_AM3_ADDR, 2'b00} ;
ta_offset = {4'h1, `W_TA3_ADDR, 2'b00} ;
end
else if (image_num === 4)
begin
ctrl_offset = {4'h1, `W_IMG_CTRL4_ADDR, 2'b00} ;
ba_offset = {4'h1, `W_BA4_ADDR, 2'b00} ;
am_offset = {4'h1, `W_AM4_ADDR, 2'b00} ;
ta_offset = {4'h1, `W_TA4_ADDR, 2'b00} ;
end
else if (image_num === 5)
begin
ctrl_offset = {4'h1, `W_IMG_CTRL5_ADDR, 2'b00} ;
ba_offset = {4'h1, `W_BA5_ADDR, 2'b00} ;
am_offset = {4'h1, `W_AM5_ADDR, 2'b00} ;
ta_offset = {4'h1, `W_TA5_ADDR, 2'b00} ;
end
 
// Set Base Address of IMAGE
config_write( ba_offset, ba | {31'h0, io_nmem}, 4'hF, ok ) ;
if ( ok !== 1 )
begin
in_use = 1'b0 ;
disable main ;
end
 
// Set Address Mask of IMAGE
config_write( am_offset, am, 4'hF, ok ) ;
if ( ok !== 1 )
begin
in_use = 1'b0 ;
disable main ;
end
 
// Set Translation Address of IMAGE
config_write( ta_offset, ta, 4'hF, ok ) ;
if ( ok !== 1 )
begin
in_use = 1'b0 ;
disable main ;
end
 
// Set IMAGE Control Register
config_write( ctrl_offset, {29'd0, at_en, pref_en, 1'b0}, 4'hF, ok ) ;
if ( ok !== 1 )
begin
in_use = 1'b0 ;
disable main ;
end
ctrl_offset = {4'h1, `W_IMG_CTRL1_ADDR, 2'b00} ;
ba_offset = {4'h1, `W_BA1_ADDR, 2'b00} ;
am_offset = {4'h1, `W_AM1_ADDR, 2'b00} ;
ta_offset = {4'h1, `W_TA1_ADDR, 2'b00} ;
end
else
else if (image_num === 2)
begin
if (image_num === 1)
begin
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_img_ctrl1_bit2_0 = {at_en, pref_en, mrl_en} ;
ctrl_offset = {4'h1, `W_IMG_CTRL2_ADDR, 2'b00} ;
ba_offset = {4'h1, `W_BA2_ADDR, 2'b00} ;
am_offset = {4'h1, `W_AM2_ADDR, 2'b00} ;
ta_offset = {4'h1, `W_TA2_ADDR, 2'b00} ;
end
else if (image_num === 3)
begin
ctrl_offset = {4'h1, `W_IMG_CTRL3_ADDR, 2'b00} ;
ba_offset = {4'h1, `W_BA3_ADDR, 2'b00} ;
am_offset = {4'h1, `W_AM3_ADDR, 2'b00} ;
ta_offset = {4'h1, `W_TA3_ADDR, 2'b00} ;
end
else if (image_num === 4)
begin
ctrl_offset = {4'h1, `W_IMG_CTRL4_ADDR, 2'b00} ;
ba_offset = {4'h1, `W_BA4_ADDR, 2'b00} ;
am_offset = {4'h1, `W_AM4_ADDR, 2'b00} ;
ta_offset = {4'h1, `W_TA4_ADDR, 2'b00} ;
end
else if (image_num === 5)
begin
ctrl_offset = {4'h1, `W_IMG_CTRL5_ADDR, 2'b00} ;
ba_offset = {4'h1, `W_BA5_ADDR, 2'b00} ;
am_offset = {4'h1, `W_AM5_ADDR, 2'b00} ;
ta_offset = {4'h1, `W_TA5_ADDR, 2'b00} ;
end
 
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba1_bit31_12 = ba[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba1_bit0 = io_nmem ;
// Set Base Address of IMAGE
config_write( ba_offset, ba | {31'h0, io_nmem}, 4'hF, ok ) ;
if ( ok !== 1 )
begin
in_use = 1'b0 ;
disable main ;
end
 
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_am1 = am[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ta1 = ta[31:12] ;
end
else if (image_num === 2)
begin
`ifdef WB_IMAGE2
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_img_ctrl2_bit2_0 = {at_en, pref_en, mrl_en} ;
// Set Address Mask of IMAGE
config_write( am_offset, am, 4'hF, ok ) ;
if ( ok !== 1 )
begin
in_use = 1'b0 ;
disable main ;
end
 
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba2_bit31_12 = ba[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba2_bit0 = io_nmem ;
// Set Translation Address of IMAGE
config_write( ta_offset, ta, 4'hF, ok ) ;
if ( ok !== 1 )
begin
in_use = 1'b0 ;
disable main ;
end
 
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_am2 = am[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ta2 = ta[31:12] ;
`endif
end
else if (image_num === 3)
begin
`ifdef WB_IMAGE3
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_img_ctrl3_bit2_0 = {at_en, pref_en, mrl_en} ;
 
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba3_bit31_12 = ba[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba3_bit0 = io_nmem ;
 
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_am3 = am[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ta3 = ta[31:12] ;
`endif
end
else if (image_num === 4)
begin
`ifdef WB_IMAGE4
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_img_ctrl4_bit2_0 = {at_en, pref_en, mrl_en} ;
 
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba4_bit31_12 = ba[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba4_bit0 = io_nmem ;
 
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_am4 = am[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ta4 = ta[31:12] ;
`endif
end
else if (image_num === 5)
begin
`ifdef WB_IMAGE5
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_img_ctrl5_bit2_0 = {at_en, pref_en, mrl_en} ;
 
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba5_bit31_12 = ba[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba5_bit0 = io_nmem ;
 
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_am5 = am[31:12] ;
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ta5 = ta[31:12] ;
`endif
end
// Set IMAGE Control Register
config_write( ctrl_offset, {29'd0, at_en, pref_en, 1'b0}, 4'hF, ok ) ;
if ( ok !== 1 )
begin
in_use = 1'b0 ;
disable main ;
end
 
in_use = 1'b0 ;
/trunk/bench/verilog/pci_behaviorial_master.v
1,5 → 1,5
//===========================================================================
// $Id: pci_behaviorial_master.v,v 1.3 2003-08-08 16:29:00 tadejm Exp $
// $Id: pci_behaviorial_master.v,v 1.4 2003-12-19 11:11:28 mihad Exp $
//
// Copyright 2001 Blue Beaver. All Rights Reserved.
//
177,6 → 177,16
reg [PCI_BUS_DATA_RANGE:0] master_received_data ;
reg master_received_data_valid ;
 
// MihaD - added an option to keep the byte enables the same through complete
// transfer
reg keep_master_mask ;
reg keep_master_data ;
initial
begin
keep_master_mask = 1'b0 ;
keep_master_data = 1'b0 ;
end
 
// Let test commander know when this PCI Master has accepted the command.
reg test_accepted_next, test_accepted_int;
// Display on negative edge so easy to see
322,8 → 332,16
up_temp[15: 8] = master_write_data[15: 8] + 8'h01;
up_temp[ 7: 0] = master_write_data[ 7: 0] + 8'h01;
// Wrap adds so that things repeat in the 256 Byte (64 Word) Target SRAM
master_write_data_next[PCI_BUS_DATA_RANGE:0] = up_temp[PCI_BUS_DATA_RANGE:0];// & 32'h3F3F3F3F; commented by Tadej M. on 07.12.2001
master_mask_l_next[PCI_BUS_CBE_RANGE:0] = {master_mask_l[2:0], master_mask_l[3]};
if (~keep_master_data)
master_write_data_next[PCI_BUS_DATA_RANGE:0] = up_temp[PCI_BUS_DATA_RANGE:0];// & 32'h3F3F3F3F; commented by Tadej M. on 07.12.2001
else
master_write_data_next = master_write_data ;
 
// MihaD - added an option to keep byte enables the same through complete transfer
if (~keep_master_mask)
master_mask_l_next[PCI_BUS_CBE_RANGE:0] = {master_mask_l[2:0], master_mask_l[3]};
else
master_mask_l_next = master_mask_l ;
end
endtask
 
/trunk/bench/verilog/pci_testbench_defines.v
14,10 → 14,10
// they are used to generate both clocks with same period and phase shift of define's value in nano seconds
 
//`define PCI_CLOCK_FOLLOWS_WB_CLOCK 2
`define WB_CLOCK_FOLLOWS_PCI_CLOCK 2
//`define WB_CLOCK_FOLLOWS_PCI_CLOCK 2
// wishbone period in ns
`define WB_PERIOD 30.0
`define WB_PERIOD 10.0
// values of image registers of PCI bridge device - valid are only upper 20 bits, others must be ZERO !
`define TAR0_BASE_ADDR_0 32'h1000_0000
/trunk/bench/verilog/pci_regression_constants.v
39,6 → 39,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2003/07/29 08:19:46 mihad
// Found and simulated the problem in the synchronization logic.
// Repaired the synchronization logic in the FIFOs.
//
// Revision 1.3 2002/08/13 11:03:51 mihad
// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image
//
343,6 → 347,11
`define TAR0_IDSEL_ADDR (32'h0000_0001 << `TAR0_IDSEL_INDEX)
`define TAR1_IDSEL_ADDR (32'h0000_0001 << `TAR1_IDSEL_INDEX)
`define TAR2_IDSEL_ADDR (32'h0000_0001 << `TAR2_IDSEL_INDEX)
 
`ifdef GUEST
// if guest implementation - test compact pci hot swap
`define PCI_CPCI_HS_IMPLEMENT
`endif
/*=======================================================================================
Following defines are used in a script file for regression testing !!!
=========================================================================================
/trunk/rtl/verilog/pci_rst_int.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2003/01/27 16:49:31 mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.1 2002/02/01 14:43:31 mihad
// *** empty log message ***
//
70,12 → 73,11
pci_intan_in,
conf_int_in,
int_i,
out_bckp_perr_en_in,
out_bckp_serr_en_in,
pci_intan_out,
pci_intan_en_out,
int_o,
conf_isr_int_prop_out
conf_isr_int_prop_out,
init_complete_in
);
 
input clk_in;
92,13 → 94,13
input pci_intan_in;
input conf_int_in;
input int_i;
input out_bckp_perr_en_in;
input out_bckp_serr_en_in;
output pci_intan_out;
output pci_intan_en_out;
output int_o;
output conf_isr_int_prop_out;
 
input init_complete_in ;
 
/*--------------------------------------------------------------------------------------------------------
RESET logic
--------------------------------------------------------------------------------------------------------*/
147,7 → 149,7
.reset_in ( reset ),
.clk_in ( clk_in) ,
.dat_en_in ( 1'b1 ),
.en_en_in ( 1'b1 ),
.en_en_in ( init_complete_in ),
.dat_in ( 1'b0 ) , // active low
.en_in ( conf_int_in ) ,
.en_out ( interrupt_a_en ),
/trunk/rtl/verilog/pci_target32_sm.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10 2003/08/08 16:36:33 tadejm
// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.
//
// Revision 1.9 2003/01/27 16:49:31 mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
132,7 → 135,6
load_medium_reg_out,
sel_fifo_mreg_out,
sel_conf_fifo_out,
fetch_conf_out,
load_to_pciw_fifo_out,
load_to_conf_out,
same_read_in,
227,7 → 229,6
output load_medium_reg_out ;// Load data from PCIR_FIFO to medium register (first data must be prepared on time)
output sel_fifo_mreg_out ; // Read data selection between PCIR_FIFO and medium register
output sel_conf_fifo_out ; // Read data selection between Configuration registers and "FIFO"
output fetch_conf_out ; // Read enable for configuration space registers
output load_to_pciw_fifo_out ;// Write enable to PCIW_FIFO
output load_to_conf_out ; // Write enable to Configuration space registers
 
269,7 → 270,7
begin
if (reset_in)
begin
previous_frame <= #`FF_DELAY 1'b1 ;
previous_frame <= #`FF_DELAY 1'b0 ;
read_completed_reg <= #`FF_DELAY 1'b0 ;
end
else
689,10 → 690,6
assign sel_conf_fifo_out = (cnf_progress || norm_access_to_conf_reg) ;
`endif
 
// NOT USED NOW, SINCE READ IS ASYNCHRONOUS
//assign fetch_conf_out = ((cnf_progress || norm_access_to_conf_reg) && ~rw_cbe0 && ~bckp_devsel_in) ;
assign fetch_conf_out = 1'b0 ;
 
// Write control signals assignments
assign
load_to_pciw_fifo_out = (
/trunk/rtl/verilog/pci_conf_space.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2003/08/14 13:06:02 simons
// synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.
//
// Revision 1.2 2003/03/26 13:16:18 mihad
// Added the reset value parameter to the synchronizer flop module.
// Added resets to all synchronizer flop instances.
113,9 → 116,17
// output from conf. cycle generation register (sddress), int. control register & interrupt output
config_addr, icr_soft_res, int_out,
// input to interrupt status register
isr_sys_err_int, isr_par_err_int, isr_int_prop ) ;
isr_sys_err_int, isr_par_err_int, isr_int_prop,
 
init_complete
 
`ifdef PCI_CPCI_HS_IMPLEMENT
,
pci_cpci_hs_enum_oe_o, pci_cpci_hs_led_oe_o, pci_cpci_hs_es_i
`endif
) ;
 
 
/*###########################################################################################################
/////////////////////////////////////////////////////////////////////////////////////////////////////////////
Input and output ports
255,7 → 266,38
input isr_par_err_int ;
input isr_int_prop ;
 
output init_complete ;
 
`ifdef PCI_CPCI_HS_IMPLEMENT
output pci_cpci_hs_enum_oe_o ;
output pci_cpci_hs_led_oe_o ;
input pci_cpci_hs_es_i ;
 
reg pci_cpci_hs_enum_oe_o ;
reg pci_cpci_hs_led_oe_o ;
 
// set the hot swap ejector switch debounce counter width
// it is only 4 for simulation purposes
`ifdef PCI_CPCI_SIM
 
parameter hs_es_cnt_width = 4 ;
 
`else
 
`ifdef PCI33
parameter hs_es_cnt_width = 16 ;
`endif
`ifdef PCI66
parameter hs_es_cnt_width = 17 ;
`endif
`endif
 
`endif
/*###########################################################################################################
/////////////////////////////////////////////////////////////////////////////////////////////////////////////
REGISTERS definition
264,7 → 306,7
###########################################################################################################*/
 
// Decoded Register Select signals for writting (only one address decoder)
reg [55 : 0] w_reg_select_dec ;
reg [56 : 0] w_reg_select_dec ;
 
/*###########################################################################################################
-------------------------------------------------------------------------------------------------------------
295,6 → 337,21
reg status_bit8 ;
parameter r_status_bit7 = 1'b1 ; // fast back-to-back capable response !!!
parameter r_status_bit5 = `HEADER_66MHz ; // 1'b0 indicates 33 MHz capable !!!
 
`ifdef PCI_CPCI_HS_IMPLEMENT
wire r_status_bit4 = 1 ;
reg hs_ins ;
reg hs_ext ;
wire [ 1: 0] hs_pi = 2'b00 ;
reg hs_loo ;
reg hs_eim ;
wire [ 7: 0] hs_cap_id = 8'h06 ;
reg hs_ins_armed ;
reg hs_ext_armed ;
`else
wire r_status_bit4 = 0 ;
`endif
 
parameter r_revision_id = `HEADER_REVISION_ID ;
`ifdef HOST
parameter r_class_code = 24'h06_00_00 ;
656,10 → 713,10
-----------------------------------------------------------------------------------------------------------*/
reg icr_bit31 ;
`ifdef HOST
reg [4 : 3] icr_bit4_3 ;
reg [4 : 3] isr_bit4_3 ;
reg [2 : 0] icr_bit2_0 ;
reg [2 : 0] isr_bit2_0 ;
reg [4 : 3] icr_bit4_3 ;
reg [4 : 3] isr_bit4_3 ;
reg [2 : 0] icr_bit2_0 ;
reg [2 : 0] isr_bit2_0 ;
`else // GUEST
wire [4 : 3] icr_bit4_3 = 2'h0 ;
wire [4 : 3] isr_bit4_3 = 2'h0 ;
667,7 → 724,32
reg [2 : 0] isr_bit2_0 ;
`endif
 
/*###########################################################################################################
-------------------------------------------------------------------------------------------------------------
Initialization complete identifier
When using I2C or similar initialisation mechanism,
the bridge must not respond to transaction requests on PCI bus,
not even to configuration cycles.
Therefore, only when init_complete is set, the bridge starts
participating on the PCI bus as an active device.
Two additional flip flops are also provided for GUEST implementation,
to synchronize to the pci clock after PCI reset is asynchronously de-asserted.
-------------------------------------------------------------------------------------------------------------
###########################################################################################################*/
 
`ifdef GUEST
 
reg rst_inactive_sync ;
reg rst_inactive ;
 
`else
 
wire rst_inactive = 1'b1 ;
 
`endif
 
reg init_complete ;
 
/*###########################################################################################################
-------------------------------------------------------------------------------------------------------------
 
681,7 → 763,7
`else
 
always@(r_conf_address_in or
status_bit15_11 or status_bit8 or command_bit8 or command_bit6 or command_bit2_0 or
status_bit15_11 or status_bit8 or r_status_bit4 or command_bit8 or command_bit6 or command_bit2_0 or
latency_timer or cache_line_size_reg or
pci_ba0_bit31_12 or
pci_img_ctrl0_bit2_1 or pci_am0 or pci_ta0 or pci_ba0_bit0 or
702,6 → 784,10
wb_err_cs_bit31_24 or /*wb_err_cs_bit10 or*/ wb_err_cs_bit9 or wb_err_cs_bit8 or wb_err_cs_bit0 or
wb_err_addr or wb_err_data or
cnf_addr_bit23_2 or cnf_addr_bit0 or icr_bit31 or icr_bit4_3 or icr_bit2_0 or isr_bit4_3 or isr_bit2_0
 
`ifdef PCI_CPCI_HS_IMPLEMENT
or hs_ins or hs_ext or hs_pi or hs_loo or hs_eim or hs_cap_id
`endif
)
begin
case (r_conf_address_in[8])
713,8 → 799,8
// PCI header - configuration space
case (r_conf_address_in[5:2])
4'h0: r_conf_data_out = { r_device_id, r_vendor_id } ;
4'h1: r_conf_data_out = { status_bit15_11, r_status_bit10_9, status_bit8, r_status_bit7, 1'h0, r_status_bit5,
5'h00, 7'h00, command_bit8, 1'h0, command_bit6, 3'h0, command_bit2_0 } ;
4'h1: r_conf_data_out = { status_bit15_11, r_status_bit10_9, status_bit8, r_status_bit7, 1'h0, r_status_bit5, r_status_bit4,
4'h0, 7'h00, command_bit8, 1'h0, command_bit6, 3'h0, command_bit2_0 } ;
4'h2: r_conf_data_out = { r_class_code, r_revision_id } ;
4'h3: r_conf_data_out = { 8'h00, r_header_type, latency_timer, cache_line_size_reg } ;
4'h4:
759,12 → 845,31
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
r_conf_data_out[0] = pci_ba5_bit0 & pci_am5[31];
end
`ifdef PCI_CPCI_HS_IMPLEMENT
4'hD:
begin
r_conf_data_out = {24'h0000_00, `PCI_CAP_PTR_VAL} ;
end
`endif
4'hf: r_conf_data_out = { r_max_lat, r_min_gnt, r_interrupt_pin, interrupt_line } ;
default : r_conf_data_out = 32'h0000_0000 ;
default: r_conf_data_out = 32'h0000_0000 ;
endcase
end
default :
r_conf_data_out = 32'h0000_0000 ;
begin
`ifdef PCI_CPCI_HS_IMPLEMENT
if ( (r_conf_address_in[7:0] >> 2) == ((`PCI_CAP_PTR_VAL) >> 2) )
begin
r_conf_data_out = {8'h00, hs_ins, hs_ext, hs_pi, hs_loo, 1'b0, hs_eim, 1'b0, 8'h00, hs_cap_id} ;
end
else
begin
r_conf_data_out = 32'h0000_0000 ;
end
`else
r_conf_data_out = 32'h0000_0000 ;
`endif
end
endcase
end
default :
995,7 → 1100,7
`endif
 
always@(w_conf_address_in or
status_bit15_11 or status_bit8 or command_bit8 or command_bit6 or command_bit2_0 or
status_bit15_11 or status_bit8 or r_status_bit4 or command_bit8 or command_bit6 or command_bit2_0 or
latency_timer or cache_line_size_reg or
pci_ba0_bit31_12 or
pci_img_ctrl0_bit2_1 or pci_am0 or pci_ta0 or pci_ba0_bit0 or
1016,6 → 1121,10
wb_err_cs_bit31_24 or /*wb_err_cs_bit10 or*/ wb_err_cs_bit9 or wb_err_cs_bit8 or wb_err_cs_bit0 or
wb_err_addr or wb_err_data or
cnf_addr_bit23_2 or cnf_addr_bit0 or icr_bit31 or icr_bit4_3 or icr_bit2_0 or isr_bit4_3 or isr_bit2_0
 
`ifdef PCI_CPCI_HS_IMPLEMENT
or hs_ins or hs_ext or hs_pi or hs_loo or hs_eim or hs_cap_id
`endif
)
begin
case (w_conf_address_in[8])
1029,23 → 1138,23
4'h0:
begin
w_conf_data_out = { r_device_id, r_vendor_id } ;
w_reg_select_dec = 56'h00_0000_0000_0000 ; // Read-Only register
w_reg_select_dec = 57'h000_0000_0000_0000 ; // Read-Only register
end
4'h1: // w_reg_select_dec bit 0
begin
w_conf_data_out = { status_bit15_11, r_status_bit10_9, status_bit8, r_status_bit7, 1'h0, r_status_bit5,
5'h00, 7'h00, command_bit8, 1'h0, command_bit6, 3'h0, command_bit2_0 } ;
w_reg_select_dec = 56'h00_0000_0000_0001 ;
w_conf_data_out = { status_bit15_11, r_status_bit10_9, status_bit8, r_status_bit7, 1'h0, r_status_bit5, r_status_bit4,
4'h0, 7'h00, command_bit8, 1'h0, command_bit6, 3'h0, command_bit2_0 } ;
w_reg_select_dec = 57'h000_0000_0000_0001 ;
end
4'h2:
begin
w_conf_data_out = { r_class_code, r_revision_id } ;
w_reg_select_dec = 56'h00_0000_0000_0000 ; // Read-Only register
w_reg_select_dec = 57'h000_0000_0000_0000 ; // Read-Only register
end
4'h3: // w_reg_select_dec bit 1
begin
w_conf_data_out = { 8'h00, r_header_type, latency_timer, cache_line_size_reg } ;
w_reg_select_dec = 56'h00_0000_0000_0002 ;
w_reg_select_dec = 57'h000_0000_0000_0002 ;
end
4'h4: // w_reg_select_dec bit 4
begin
1053,7 → 1162,7
pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
w_conf_data_out[0] = pci_ba0_bit0 & pci_am0[31];
w_reg_select_dec = 56'h00_0000_0000_0010 ; // The same for another address
w_reg_select_dec = 57'h000_0000_0000_0010 ; // The same for another address
end
4'h5: // w_reg_select_dec bit 8
begin
1061,7 → 1170,7
pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
w_conf_data_out[0] = pci_ba1_bit0 & pci_am1[31];
w_reg_select_dec = 56'h00_0000_0000_0100 ; // The same for another address
w_reg_select_dec = 57'h000_0000_0000_0100 ; // The same for another address
end
4'h6: // w_reg_select_dec bit 12
begin
1069,7 → 1178,7
pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
w_conf_data_out[0] = pci_ba2_bit0 & pci_am2[31];
w_reg_select_dec = 56'h00_0000_0000_1000 ; // The same for another address
w_reg_select_dec = 57'h000_0000_0000_1000 ; // The same for another address
end
4'h7: // w_reg_select_dec bit 16
begin
1077,7 → 1186,7
pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
w_conf_data_out[0] = pci_ba3_bit0 & pci_am3[31];
w_reg_select_dec = 56'h00_0000_0001_0000 ; // The same for another address
w_reg_select_dec = 57'h000_0000_0001_0000 ; // The same for another address
end
4'h8: // w_reg_select_dec bit 20
begin
1085,7 → 1194,7
pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
w_conf_data_out[0] = pci_ba4_bit0 & pci_am4[31];
w_reg_select_dec = 56'h00_0000_0010_0000 ; // The same for another address
w_reg_select_dec = 57'h000_0000_0010_0000 ; // The same for another address
end
4'h9: // w_reg_select_dec bit 24
begin
1093,24 → 1202,44
pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
w_conf_data_out[0] = pci_ba5_bit0 & pci_am5[31];
w_reg_select_dec = 56'h00_0000_0100_0000 ; // The same for another address
w_reg_select_dec = 57'h000_0000_0100_0000 ; // The same for another address
end
`ifdef PCI_CPCI_HS_IMPLEMENT
4'hD:
begin
w_conf_data_out = {24'h0000_00, `PCI_CAP_PTR_VAL} ;
w_reg_select_dec = 57'h000_0000_0000_0000 ; // Read-Only register
end
`endif
4'hf: // w_reg_select_dec bit 2
begin
w_conf_data_out = { r_max_lat, r_min_gnt, r_interrupt_pin, interrupt_line } ;
w_reg_select_dec = 56'h00_0000_0000_0004 ;
w_reg_select_dec = 57'h000_0000_0000_0004 ;
end
default :
begin
w_conf_data_out = 32'h0000_0000 ;
w_reg_select_dec = 56'h00_0000_0000_0000 ;
w_reg_select_dec = 57'h000_0000_0000_0000 ;
end
endcase
end
default :
begin
`ifdef PCI_CPCI_HS_IMPLEMENT
if ( (w_conf_address_in[7:0] >> 2) == ((`PCI_CAP_PTR_VAL) >> 2) )
begin
w_reg_select_dec = 57'h100_0000_0000_0000 ;
w_conf_data_out = {8'h00, hs_ins, hs_ext, hs_pi, hs_loo, 1'b0, hs_eim, 1'b0, 8'h00, hs_cap_id} ;
end
else
begin
w_reg_select_dec = 57'h000_0000_0000_0000 ;
w_conf_data_out = 32'h0000_0000 ;
end
`else
w_conf_data_out = 32'h0000_0000 ;
w_reg_select_dec = 56'h00_0000_0000_0000 ;
w_reg_select_dec = 57'h000_0000_0000_0000 ;
`endif
end
endcase
end
1121,7 → 1250,7
`P_IMG_CTRL0_ADDR: // w_reg_select_dec bit 3
begin
w_conf_data_out = { 29'h00000000, pci_img_ctrl0_bit2_1, 1'h0 } ;
w_reg_select_dec = 56'h00_0000_0000_0008 ;
w_reg_select_dec = 57'h000_0000_0000_0008 ;
end
`P_BA0_ADDR: // w_reg_select_dec bit 4
begin
1129,24 → 1258,24
pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
w_conf_data_out[0] = pci_ba0_bit0 & pci_am0[31];
w_reg_select_dec = 56'h00_0000_0000_0010 ; // The same for another address
w_reg_select_dec = 57'h000_0000_0000_0010 ; // The same for another address
end
`P_AM0_ADDR: // w_reg_select_dec bit 5
begin
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
w_reg_select_dec = 56'h00_0000_0000_0020 ;
w_reg_select_dec = 57'h000_0000_0000_0020 ;
end
`P_TA0_ADDR: // w_reg_select_dec bit 6
begin
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
w_reg_select_dec = 56'h00_0000_0000_0040 ;
w_reg_select_dec = 57'h000_0000_0000_0040 ;
end
`P_IMG_CTRL1_ADDR: // w_reg_select_dec bit 7
begin
w_conf_data_out = { 29'h00000000, pci_img_ctrl1_bit2_1, 1'h0 } ;
w_reg_select_dec = 56'h00_0000_0000_0080 ;
w_reg_select_dec = 57'h000_0000_0000_0080 ;
end
`P_BA1_ADDR: // w_reg_select_dec bit 8
begin
1154,24 → 1283,24
pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
w_conf_data_out[0] = pci_ba1_bit0 & pci_am1[31];
w_reg_select_dec = 56'h00_0000_0000_0100 ; // The same for another address
w_reg_select_dec = 57'h000_0000_0000_0100 ; // The same for another address
end
`P_AM1_ADDR: // w_reg_select_dec bit 9
begin
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
w_reg_select_dec = 56'h00_0000_0000_0200 ;
w_reg_select_dec = 57'h000_0000_0000_0200 ;
end
`P_TA1_ADDR: // w_reg_select_dec bit 10
begin
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
w_reg_select_dec = 56'h00_0000_0000_0400 ;
w_reg_select_dec = 57'h000_0000_0000_0400 ;
end
`P_IMG_CTRL2_ADDR: // w_reg_select_dec bit 11
begin
w_conf_data_out = { 29'h00000000, pci_img_ctrl2_bit2_1, 1'h0 } ;
w_reg_select_dec = 56'h00_0000_0000_0800 ;
w_reg_select_dec = 57'h000_0000_0000_0800 ;
end
`P_BA2_ADDR: // w_reg_select_dec bit 12
begin
1179,24 → 1308,24
pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
w_conf_data_out[0] = pci_ba2_bit0 & pci_am2[31];
w_reg_select_dec = 56'h00_0000_0000_1000 ; // The same for another address
w_reg_select_dec = 57'h000_0000_0000_1000 ; // The same for another address
end
`P_AM2_ADDR: // w_reg_select_dec bit 13
begin
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
w_reg_select_dec = 56'h00_0000_0000_2000 ;
w_reg_select_dec = 57'h000_0000_0000_2000 ;
end
`P_TA2_ADDR: // w_reg_select_dec bit 14
begin
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
w_reg_select_dec = 56'h00_0000_0000_4000 ;
w_reg_select_dec = 57'h000_0000_0000_4000 ;
end
`P_IMG_CTRL3_ADDR: // w_reg_select_dec bit 15
begin
w_conf_data_out = { 29'h00000000, pci_img_ctrl3_bit2_1, 1'h0 } ;
w_reg_select_dec = 56'h00_0000_0000_8000 ;
w_reg_select_dec = 57'h000_0000_0000_8000 ;
end
`P_BA3_ADDR: // w_reg_select_dec bit 16
begin
1204,24 → 1333,24
pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
w_conf_data_out[0] = pci_ba3_bit0 & pci_am3[31];
w_reg_select_dec = 56'h00_0000_0001_0000 ; // The same for another address
w_reg_select_dec = 57'h000_0000_0001_0000 ; // The same for another address
end
`P_AM3_ADDR: // w_reg_select_dec bit 17
begin
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
w_reg_select_dec = 56'h00_0000_0002_0000 ;
w_reg_select_dec = 57'h000_0000_0002_0000 ;
end
`P_TA3_ADDR: // w_reg_select_dec bit 18
begin
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
w_reg_select_dec = 56'h00_0000_0004_0000 ;
w_reg_select_dec = 57'h000_0000_0004_0000 ;
end
`P_IMG_CTRL4_ADDR: // w_reg_select_dec bit 19
begin
w_conf_data_out = { 29'h00000000, pci_img_ctrl4_bit2_1, 1'h0 } ;
w_reg_select_dec = 56'h00_0000_0008_0000 ;
w_reg_select_dec = 57'h000_0000_0008_0000 ;
end
`P_BA4_ADDR: // w_reg_select_dec bit 20
begin
1229,24 → 1358,24
pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
w_conf_data_out[0] = pci_ba4_bit0 & pci_am4[31];
w_reg_select_dec = 56'h00_0000_0010_0000 ; // The same for another address
w_reg_select_dec = 57'h000_0000_0010_0000 ; // The same for another address
end
`P_AM4_ADDR: // w_reg_select_dec bit 21
begin
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
w_reg_select_dec = 56'h00_0000_0020_0000 ;
w_reg_select_dec = 57'h000_0000_0020_0000 ;
end
`P_TA4_ADDR: // w_reg_select_dec bit 22
begin
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
w_reg_select_dec = 56'h00_0000_0040_0000 ;
w_reg_select_dec = 57'h000_0000_0040_0000 ;
end
`P_IMG_CTRL5_ADDR: // w_reg_select_dec bit 23
begin
w_conf_data_out = { 29'h00000000, pci_img_ctrl5_bit2_1, 1'h0 } ;
w_reg_select_dec = 56'h00_0000_0080_0000 ;
w_reg_select_dec = 57'h000_0000_0080_0000 ;
end
`P_BA5_ADDR: // w_reg_select_dec bit 24
begin
1254,46 → 1383,46
pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
w_conf_data_out[0] = pci_ba5_bit0 & pci_am5[31];
w_reg_select_dec = 56'h00_0000_0100_0000 ; // The same for another address
w_reg_select_dec = 57'h000_0000_0100_0000 ; // The same for another address
end
`P_AM5_ADDR: // w_reg_select_dec bit 25
begin
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
w_reg_select_dec = 56'h00_0000_0200_0000 ;
w_reg_select_dec = 57'h000_0000_0200_0000 ;
end
`P_TA5_ADDR: // w_reg_select_dec bit 26
begin
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
w_reg_select_dec = 56'h00_0000_0400_0000 ;
w_reg_select_dec = 57'h000_0000_0400_0000 ;
end
`P_ERR_CS_ADDR: // w_reg_select_dec bit 27
begin
w_conf_data_out = { pci_err_cs_bit31_24, 13'h0000, pci_err_cs_bit10, pci_err_cs_bit9,
pci_err_cs_bit8, 7'h00, pci_err_cs_bit0 } ;
w_reg_select_dec = 56'h00_0000_0800_0000 ;
w_reg_select_dec = 57'h000_0000_0800_0000 ;
end
`P_ERR_ADDR_ADDR: // w_reg_select_dec bit 28
begin
w_conf_data_out = pci_err_addr ;
w_reg_select_dec = 56'h00_0000_0000_0000 ; // = 56'h00_0000_1000_0000 ;
w_reg_select_dec = 57'h000_0000_0000_0000 ; // = 56'h00_0000_1000_0000 ;
end
`P_ERR_DATA_ADDR: // w_reg_select_dec bit 29
begin
w_conf_data_out = pci_err_data ;
w_reg_select_dec = 56'h00_0000_0000_0000 ; // = 56'h00_0000_2000_0000 ;
w_reg_select_dec = 57'h000_0000_0000_0000 ; // = 56'h00_0000_2000_0000 ;
end
// WB slave - configuration space
`WB_CONF_SPC_BAR_ADDR:
begin
w_conf_data_out = { wb_ba0_bit31_12, 11'h000, wb_ba0_bit0 } ;
w_reg_select_dec = 56'h00_0000_0000_0000 ; // Read-Only register
w_reg_select_dec = 57'h000_0000_0000_0000 ; // Read-Only register
end
`W_IMG_CTRL1_ADDR: // w_reg_select_dec bit 30
begin
w_conf_data_out = { 29'h00000000, wb_img_ctrl1_bit2_0 } ;
w_reg_select_dec = 56'h00_0000_4000_0000 ;
w_reg_select_dec = 57'h000_0000_4000_0000 ;
end
`W_BA1_ADDR: // w_reg_select_dec bit 31
begin
1301,24 → 1430,24
wb_am1[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
w_conf_data_out[0] = wb_ba1_bit0 ;
w_reg_select_dec = 56'h00_0000_8000_0000 ;
w_reg_select_dec = 57'h000_0000_8000_0000 ;
end
`W_AM1_ADDR: // w_reg_select_dec bit 32
begin
w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am1[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
w_reg_select_dec = 56'h00_0001_0000_0000 ;
w_reg_select_dec = 57'h000_0001_0000_0000 ;
end
`W_TA1_ADDR: // w_reg_select_dec bit 33
begin
w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta1[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
w_reg_select_dec = 56'h00_0002_0000_0000 ;
w_reg_select_dec = 57'h000_0002_0000_0000 ;
end
`W_IMG_CTRL2_ADDR: // w_reg_select_dec bit 34
begin
w_conf_data_out = { 29'h00000000, wb_img_ctrl2_bit2_0 } ;
w_reg_select_dec = 56'h00_0004_0000_0000 ;
w_reg_select_dec = 57'h000_0004_0000_0000 ;
end
`W_BA2_ADDR: // w_reg_select_dec bit 35
begin
1326,24 → 1455,24
wb_am2[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
w_conf_data_out[0] = wb_ba2_bit0 ;
w_reg_select_dec = 56'h00_0008_0000_0000 ;
w_reg_select_dec = 57'h000_0008_0000_0000 ;
end
`W_AM2_ADDR: // w_reg_select_dec bit 36
begin
w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am2[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
w_reg_select_dec = 56'h00_0010_0000_0000 ;
w_reg_select_dec = 57'h000_0010_0000_0000 ;
end
`W_TA2_ADDR: // w_reg_select_dec bit 37
begin
w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta2[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
w_reg_select_dec = 56'h00_0020_0000_0000 ;
w_reg_select_dec = 57'h000_0020_0000_0000 ;
end
`W_IMG_CTRL3_ADDR: // w_reg_select_dec bit 38
begin
w_conf_data_out = { 29'h00000000, wb_img_ctrl3_bit2_0 } ;
w_reg_select_dec = 56'h00_0040_0000_0000 ;
w_reg_select_dec = 57'h000_0040_0000_0000 ;
end
`W_BA3_ADDR: // w_reg_select_dec bit 39
begin
1351,24 → 1480,24
wb_am3[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
w_conf_data_out[0] = wb_ba3_bit0 ;
w_reg_select_dec = 56'h00_0080_0000_0000 ;
w_reg_select_dec = 57'h000_0080_0000_0000 ;
end
`W_AM3_ADDR: // w_reg_select_dec bit 40
begin
w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am3[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
w_reg_select_dec = 56'h00_0100_0000_0000 ;
w_reg_select_dec = 57'h000_0100_0000_0000 ;
end
`W_TA3_ADDR: // w_reg_select_dec bit 41
begin
w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta3[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
w_reg_select_dec = 56'h00_0200_0000_0000 ;
w_reg_select_dec = 57'h000_0200_0000_0000 ;
end
`W_IMG_CTRL4_ADDR: // w_reg_select_dec bit 42
begin
w_conf_data_out = { 29'h00000000, wb_img_ctrl4_bit2_0 } ;
w_reg_select_dec = 56'h00_0400_0000_0000 ;
w_reg_select_dec = 57'h000_0400_0000_0000 ;
end
`W_BA4_ADDR: // w_reg_select_dec bit 43
begin
1376,24 → 1505,24
wb_am4[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
w_conf_data_out[0] = wb_ba4_bit0 ;
w_reg_select_dec = 56'h00_0800_0000_0000 ;
w_reg_select_dec = 57'h000_0800_0000_0000 ;
end
`W_AM4_ADDR: // w_reg_select_dec bit 44
begin
w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am4[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
w_reg_select_dec = 56'h00_1000_0000_0000 ;
w_reg_select_dec = 57'h000_1000_0000_0000 ;
end
`W_TA4_ADDR: // w_reg_select_dec bit 45
begin
w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta4[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
w_reg_select_dec = 56'h00_2000_0000_0000 ;
w_reg_select_dec = 57'h000_2000_0000_0000 ;
end
`W_IMG_CTRL5_ADDR: // w_reg_select_dec bit 46
begin
w_conf_data_out = { 29'h00000000, wb_img_ctrl5_bit2_0 } ;
w_reg_select_dec = 56'h00_4000_0000_0000 ;
w_reg_select_dec = 57'h000_4000_0000_0000 ;
end
`W_BA5_ADDR: // w_reg_select_dec bit 47
begin
1401,40 → 1530,40
wb_am5[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
w_conf_data_out[0] = wb_ba5_bit0 ;
w_reg_select_dec = 56'h00_8000_0000_0000 ;
w_reg_select_dec = 57'h000_8000_0000_0000 ;
end
`W_AM5_ADDR: // w_reg_select_dec bit 48
begin
w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am5[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
w_reg_select_dec = 56'h01_0000_0000_0000 ;
w_reg_select_dec = 57'h001_0000_0000_0000 ;
end
`W_TA5_ADDR: // w_reg_select_dec bit 49
begin
w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta5[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
w_reg_select_dec = 56'h02_0000_0000_0000 ;
w_reg_select_dec = 57'h002_0000_0000_0000 ;
end
`W_ERR_CS_ADDR: // w_reg_select_dec bit 50
begin
w_conf_data_out = { wb_err_cs_bit31_24, /*13*/14'h0000, /*wb_err_cs_bit10,*/
wb_err_cs_bit9, wb_err_cs_bit8, 7'h00, wb_err_cs_bit0 } ;
w_reg_select_dec = 56'h04_0000_0000_0000 ;
w_reg_select_dec = 57'h004_0000_0000_0000 ;
end
`W_ERR_ADDR_ADDR: // w_reg_select_dec bit 51
begin
w_conf_data_out = wb_err_addr ;
w_reg_select_dec = 56'h08_0000_0000_0000 ;
w_reg_select_dec = 57'h008_0000_0000_0000 ;
end
`W_ERR_DATA_ADDR: // w_reg_select_dec bit 52
begin
w_conf_data_out = wb_err_data ;
w_reg_select_dec = 56'h10_0000_0000_0000 ;
w_reg_select_dec = 57'h010_0000_0000_0000 ;
end
`CNF_ADDR_ADDR: // w_reg_select_dec bit 53
begin
w_conf_data_out = { 8'h00, cnf_addr_bit23_2, 1'h0, cnf_addr_bit0 } ;
w_reg_select_dec = 56'h20_0000_0000_0000 ;
w_reg_select_dec = 57'h020_0000_0000_0000 ;
end
// `CNF_DATA_ADDR: implemented elsewhere !!!
// `INT_ACK_ADDR: implemented elsewhere !!!
1441,17 → 1570,17
`ICR_ADDR: // w_reg_select_dec bit 54
begin
w_conf_data_out = { icr_bit31, 26'h0000_000, icr_bit4_3, icr_bit2_0 } ;
w_reg_select_dec = 56'h40_0000_0000_0000 ;
w_reg_select_dec = 57'h040_0000_0000_0000 ;
end
`ISR_ADDR: // w_reg_select_dec bit 55
begin
w_conf_data_out = { 27'h0000_000, isr_bit4_3, isr_bit2_0 } ;
w_reg_select_dec = 56'h80_0000_0000_0000 ;
w_reg_select_dec = 57'h080_0000_0000_0000 ;
end
default:
begin
w_conf_data_out = 32'h0000_0000 ;
w_reg_select_dec = 56'h00_0000_0000_0000 ;
w_reg_select_dec = 57'h000_0000_0000_0000 ;
end
endcase
end
1583,6 → 1712,20
icr_bit2_0[2:0] <= 3'h0 ;
`endif
/*isr_bit4_3 ; isr_bit2_0 ;*/
 
// Not register bit; used only internally after reset!
init_complete <= 1'b0 ;
 
`ifdef GUEST
rst_inactive_sync <= 1'b0 ;
rst_inactive <= 1'b0 ;
`endif
 
`ifdef PCI_CPCI_HS_IMPLEMENT
/*hs_ins hs_ext*/ hs_loo <= 1'b0; hs_eim <= 1'b0;
// Not register bits; used only internally after reset!
/*hs_ins_armed hs_ext_armed*/
`endif
end
/* -----------------------------------------------------------------------------------------------------------
Following register bits should have asynchronous RESET & SET! That is why they are IMPLEMENTED separately
1610,6 → 1753,8
isr_bit4_0[2] <= 1'b1 & icr_bit4_0[2] ;
isr_bit4_0[1] <= 1'b1 & icr_bit4_0[1] ;
isr_bit4_0[0] <= 1'b1 & icr_bit4_0[0] ;
 
hs_ins; hs_ext;
-----------------------------------------------------------------------------------------------------------*/
// Here follows normal writting to registers (only to their valid bits) !
else
2115,7 → 2260,9
begin
if (~w_byte_en[3])
icr_bit31 <= w_conf_data_in[31] ;
 
if (~w_byte_en[0])
begin
`ifdef HOST
icr_bit4_3 <= w_conf_data_in[4:3] ;
icr_bit2_0 <= w_conf_data_in[2:0] ;
2122,8 → 2269,29
`else
icr_bit2_0[2:0] <= w_conf_data_in[2:0] ;
`endif
end
end
end
end
 
`ifdef PCI_CPCI_HS_IMPLEMENT
if (w_reg_select_dec[56])
begin
if (~w_byte_en[2])
begin
hs_loo <= w_conf_data_in[19];
hs_eim <= w_conf_data_in[17];
end
end
`endif
end // end of we
 
// Not register bits; used only internally after reset!
`ifdef GUEST
rst_inactive_sync <= 1'b1 ;
rst_inactive <= rst_inactive_sync ;
`endif
 
if (rst_inactive)
init_complete <= 1'b1 ;
end
end
 
2145,84 → 2313,19
// This are aditional register bits, which are resets when their value is '1' !!!
always@(w_we or w_reg_select_dec or w_conf_data_in or w_byte_en)
begin
// If '1' is written into, then it also sets signals to '1'
case ({w_we, w_reg_select_dec[0], w_reg_select_dec[27], w_reg_select_dec[50], w_reg_select_dec[55]})
{1'b1, 4'b1000} :
begin
delete_status_bit15 <= w_conf_data_in[31] & !w_byte_en[3] ;
delete_status_bit14 <= w_conf_data_in[30] & !w_byte_en[3] ;
delete_status_bit13 <= w_conf_data_in[29] & !w_byte_en[3] ;
delete_status_bit12 <= w_conf_data_in[28] & !w_byte_en[3] ;
delete_status_bit11 <= w_conf_data_in[27] & !w_byte_en[3] ;
delete_status_bit8 <= w_conf_data_in[24] & !w_byte_en[3] ;
delete_pci_err_cs_bit8 <= 1'b0 ;
delete_wb_err_cs_bit8 <= 1'b0 ;
delete_isr_bit4 <= 1'b0 ;
delete_isr_bit3 <= 1'b0 ;
delete_isr_bit2 <= 1'b0 ;
delete_isr_bit1 <= 1'b0 ;
end
{1'b1, 4'b0100} :
begin
delete_status_bit15 <= 1'b0 ;
delete_status_bit14 <= 1'b0 ;
delete_status_bit13 <= 1'b0 ;
delete_status_bit12 <= 1'b0 ;
delete_status_bit11 <= 1'b0 ;
delete_status_bit8 <= 1'b0 ;
delete_pci_err_cs_bit8 <= w_conf_data_in[8] & !w_byte_en[1] ;
delete_wb_err_cs_bit8 <= 1'b0 ;
delete_isr_bit4 <= 1'b0 ;
delete_isr_bit3 <= 1'b0 ;
delete_isr_bit2 <= 1'b0 ;
delete_isr_bit1 <= 1'b0 ;
end
{1'b1, 4'b0010} :
begin
delete_status_bit15 <= 1'b0 ;
delete_status_bit14 <= 1'b0 ;
delete_status_bit13 <= 1'b0 ;
delete_status_bit12 <= 1'b0 ;
delete_status_bit11 <= 1'b0 ;
delete_status_bit8 <= 1'b0 ;
delete_pci_err_cs_bit8 <= 1'b0 ;
delete_wb_err_cs_bit8 <= w_conf_data_in[8] & !w_byte_en[1] ;
delete_isr_bit4 <= 1'b0 ;
delete_isr_bit3 <= 1'b0 ;
delete_isr_bit2 <= 1'b0 ;
delete_isr_bit1 <= 1'b0 ;
end
{1'b1, 4'b0001} :
begin
delete_status_bit15 <= 1'b0 ;
delete_status_bit14 <= 1'b0 ;
delete_status_bit13 <= 1'b0 ;
delete_status_bit12 <= 1'b0 ;
delete_status_bit11 <= 1'b0 ;
delete_status_bit8 <= 1'b0 ;
delete_pci_err_cs_bit8 <= 1'b0 ;
delete_wb_err_cs_bit8 <= 1'b0 ;
delete_isr_bit4 <= w_conf_data_in[4] & !w_byte_en[0] ;
delete_isr_bit3 <= w_conf_data_in[3] & !w_byte_en[0] ;
delete_isr_bit2 <= w_conf_data_in[2] & !w_byte_en[0] ;
delete_isr_bit1 <= w_conf_data_in[1] & !w_byte_en[0] ;
end
default :
begin
delete_status_bit15 <= 1'b0 ;
delete_status_bit14 <= 1'b0 ;
delete_status_bit13 <= 1'b0 ;
delete_status_bit12 <= 1'b0 ;
delete_status_bit11 <= 1'b0 ;
delete_status_bit8 <= 1'b0 ;
delete_pci_err_cs_bit8 <= 1'b0 ;
delete_wb_err_cs_bit8 <= 1'b0 ;
delete_isr_bit4 <= 1'b0 ;
delete_isr_bit3 <= 1'b0 ;
delete_isr_bit2 <= 1'b0 ;
delete_isr_bit1 <= 1'b0 ;
end
endcase
// I' is written into, then it also sets signals to '1'
delete_status_bit15 = w_conf_data_in[31] & !w_byte_en[3] & w_we & w_reg_select_dec[0] ;
delete_status_bit14 = w_conf_data_in[30] & !w_byte_en[3] & w_we & w_reg_select_dec[0] ;
delete_status_bit13 = w_conf_data_in[29] & !w_byte_en[3] & w_we & w_reg_select_dec[0] ;
delete_status_bit12 = w_conf_data_in[28] & !w_byte_en[3] & w_we & w_reg_select_dec[0] ;
delete_status_bit11 = w_conf_data_in[27] & !w_byte_en[3] & w_we & w_reg_select_dec[0] ;
delete_status_bit8 = w_conf_data_in[24] & !w_byte_en[3] & w_we & w_reg_select_dec[0] ;
delete_pci_err_cs_bit8 = w_conf_data_in[8] & !w_byte_en[1] & w_we & w_reg_select_dec[27] ;
delete_wb_err_cs_bit8 = w_conf_data_in[8] & !w_byte_en[1] & w_we & w_reg_select_dec[50] ;
delete_isr_bit4 = w_conf_data_in[4] & !w_byte_en[0] & w_we & w_reg_select_dec[55] ;
delete_isr_bit3 = w_conf_data_in[3] & !w_byte_en[0] & w_we & w_reg_select_dec[55] ;
delete_isr_bit2 = w_conf_data_in[2] & !w_byte_en[0] & w_we & w_reg_select_dec[55] ;
delete_isr_bit1 = w_conf_data_in[1] & !w_byte_en[0] & w_we & w_reg_select_dec[55] ;
end
 
// STATUS BITS of PCI Header status register
3155,6 → 3258,103
end
`endif
 
 
`ifdef PCI_CPCI_HS_IMPLEMENT
reg [hs_es_cnt_width - 1:0] hs_es_cnt ; // debounce counter
reg hs_es_in_state, // current state of ejector switch input - synchronized
hs_es_sync, // synchronization flop for ejector switch input
hs_es_cur_state ; // current valid state of ejector switch
 
`ifdef ACTIVE_HIGH_OE
wire oe_active_val = 1'b1 ;
`endif
 
`ifdef ACTIVE_LOW_OE
wire oe_active_val = 1'b0 ;
`endif
 
always@(posedge pci_clk or posedge reset)
begin
if (reset)
begin
hs_ins <= 1'b0 ;
hs_ins_armed <= 1'b1 ;
hs_ext <= 1'b0 ;
hs_ext_armed <= 1'b0 ;
hs_es_in_state <= 1'b0 ;
hs_es_sync <= 1'b0 ;
hs_es_cur_state <= 1'b0 ;
hs_es_cnt <= 'h0 ;
 
`ifdef ACTIVE_LOW_OE
pci_cpci_hs_enum_oe_o <= 1'b1 ;
pci_cpci_hs_led_oe_o <= 1'b0 ;
`endif
 
`ifdef ACTIVE_HIGH_OE
pci_cpci_hs_enum_oe_o <= 1'b0 ;
pci_cpci_hs_led_oe_o <= 1'b1 ;
`endif
 
end
else
begin
// INS
if (hs_ins)
begin
if (w_conf_data_in[23] & ~w_byte_en[2] & w_we & w_reg_select_dec[56]) // clear
hs_ins <= 1'b0 ;
end
else if (hs_ins_armed) // set
hs_ins <= init_complete & (hs_es_cur_state == 1'b1) ;
 
// INS armed
if (~hs_ins & hs_ins_armed & init_complete & (hs_es_cur_state == 1'b1)) // clear
hs_ins_armed <= 1'b0 ;
else if (hs_ext) // set
hs_ins_armed <= w_conf_data_in[22] & ~w_byte_en[2] & w_we & w_reg_select_dec[56] ;
 
// EXT
if (hs_ext) // clear
begin
if (w_conf_data_in[22] & ~w_byte_en[2] & w_we & w_reg_select_dec[56])
hs_ext <= 1'b0 ;
end
else if (hs_ext_armed) // set
hs_ext <= (hs_es_cur_state == 1'b0) ;
 
// EXT armed
if (~hs_ext & hs_ext_armed & (hs_es_cur_state == 1'b0)) // clear
hs_ext_armed <= 1'b0 ;
else if (hs_ins) // set
hs_ext_armed <= w_conf_data_in[23] & !w_byte_en[2] & w_we & w_reg_select_dec[56] ;
 
// ejector switch debounce counter logic
hs_es_sync <= pci_cpci_hs_es_i ;
hs_es_in_state <= hs_es_sync ;
 
if (hs_es_in_state == hs_es_cur_state)
hs_es_cnt <= 'h0 ;
else
hs_es_cnt <= hs_es_cnt + 1'b1 ;
 
if (hs_es_cnt == {hs_es_cnt_width{1'b1}})
hs_es_cur_state <= hs_es_in_state ;
 
if ((hs_ins | hs_ext) & ~hs_eim)
pci_cpci_hs_enum_oe_o <= oe_active_val ;
else
pci_cpci_hs_enum_oe_o <= ~oe_active_val ;
 
if (~init_complete | hs_loo)
pci_cpci_hs_led_oe_o <= oe_active_val ;
else
pci_cpci_hs_led_oe_o <= ~oe_active_val ;
end
end
`endif
 
 
/*-----------------------------------------------------------------------------------------------------------
OUTPUTs from registers !!!
-----------------------------------------------------------------------------------------------------------*/
/trunk/rtl/verilog/pci_io_mux.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2003/01/27 16:49:31 mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.3 2002/02/01 15:25:12 mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
127,7 → 130,9
pci_trdy_in,
pci_irdy_in,
pci_frame_in,
pci_stop_in
pci_stop_in,
 
init_complete_in
);
 
input reset_in, clk_in ;
200,6 → 205,8
input master_load_on_transfer_in ;
input target_load_on_transfer_in ;
 
input init_complete_in ;
 
wire [31:0] temp_ad = tar_ad_en_reg_in ? tar_ad_in : mas_ad_in ;
 
wire ad_en_ctrl_low ;
834,7 → 841,7
.dat_en_in ( 1'b1 ),
.en_en_in ( 1'b1 ),
.dat_in ( req_in ) ,
.en_in ( 1'b1 ) ,
.en_in ( init_complete_in ) ,
.en_out ( req_en_out ),
.dat_out ( req_out )
);
/trunk/rtl/verilog/pci_bridge32.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.15 2003/12/10 12:02:54 mihad
// The wbs B3 to B2 translation logic had wrong reset wire connected!
//
// Revision 1.14 2003/12/09 09:33:57 simons
// Some warning cleanup.
//
439,7 → 442,6
wire pciu_err_signal_out ;
wire pciu_err_source_out ;
wire pciu_err_rty_exp_out ;
wire pciu_conf_select_out ;
wire [11:0] pciu_conf_offset_out ;
wire pciu_conf_renable_out ;
wire pciu_conf_wenable_out ;
539,6 → 541,7
wire [23:0] conf_ccyc_addr_out ;
wire conf_soft_res_out ;
wire conf_int_out ;
wire conf_init_complete_out ;
 
// PCI IO MUX OUTPUTS
wire pci_mux_frame_out ;
654,8 → 657,7
wire pci_inti_pci_intan_in = pci_inta_i ;
wire pci_inti_conf_int_in = conf_int_out ;
wire pci_inti_int_i = wb_int_i ;
wire pci_inti_out_bckp_perr_en_in = out_bckp_perr_en_out ;
wire pci_inti_out_bckp_serr_en_in = out_bckp_serr_en_out ;
wire pci_into_init_complete_in = conf_init_complete_out ;
 
pci_rst_int pci_resets_and_interrupts
(
670,12 → 672,11
.pci_intan_in (pci_inti_pci_intan_in),
.conf_int_in (pci_inti_conf_int_in),
.int_i (pci_inti_int_i),
.out_bckp_perr_en_in (pci_inti_out_bckp_perr_en_in),
.out_bckp_serr_en_in (pci_inti_out_bckp_serr_en_in),
.pci_intan_out (pci_into_pci_intan_out),
.pci_intan_en_out (pci_into_pci_intan_en_out),
.int_o (pci_into_int_o),
.conf_isr_int_prop_out (pci_into_conf_isr_int_prop_out)
.conf_isr_int_prop_out (pci_into_conf_isr_int_prop_out),
.init_complete_in (pci_into_init_complete_in)
);
 
 
1121,7 → 1122,6
.pciu_conf_wenable_out (pciu_conf_wenable_out),
.pciu_conf_be_out (pciu_conf_be_out),
.pciu_conf_data_out (pciu_conf_data_out),
.pciu_conf_select_out (pciu_conf_select_out),
.pciu_pci_drcomp_pending_out (pciu_pci_drcomp_pending_out),
.pciu_pciw_fifo_empty_out (pciu_pciw_fifo_empty_out)
 
1298,8 → 1298,10
.int_out (conf_int_out),
.isr_int_prop (conf_isr_int_prop_in),
.isr_par_err_int (conf_par_err_int_in),
.isr_sys_err_int (conf_sys_err_int_in)
.isr_sys_err_int (conf_sys_err_int_in),
 
.init_complete (conf_init_complete_out)
 
`ifdef PCI_CPCI_HS_IMPLEMENT
,
.pci_cpci_hs_enum_oe_o (pci_cpci_hs_enum_oe_o) ,
1348,6 → 1350,8
wire pci_mux_pci_frame_in = pci_frame_i ;
wire pci_mux_pci_stop_in = pci_stop_i ;
 
wire pci_mux_init_complete_in = conf_init_complete_out ;
 
pci_io_mux pci_io_mux
(
.reset_in (reset),
1413,7 → 1417,9
.pci_trdy_in (pci_mux_pci_trdy_in),
.pci_frame_in (pci_mux_pci_frame_in),
.pci_stop_in (pci_mux_pci_stop_in),
.ad_en_unregistered_out (pci_mux_ad_en_unregistered_out)
.ad_en_unregistered_out (pci_mux_ad_en_unregistered_out),
 
.init_complete_in (pci_mux_init_complete_in)
);
 
pci_cur_out_reg output_backup
1546,8 → 1552,9
 
pci_in_reg input_register
(
.reset_in (reset),
.clk_in (pci_clk),
.reset_in (reset),
.clk_in (pci_clk),
.init_complete_in (conf_init_complete_out),
 
.pci_gnt_in (in_reg_gnt_in),
.pci_frame_in (in_reg_frame_in),
/trunk/rtl/verilog/pci_wbs_wbb3_2_wbb2.v
40,6 → 40,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2003/12/01 16:20:56 simons
// ifdef - endif statements put in separate lines for flint compatibility.
//
// Revision 1.1 2003/08/12 13:58:19 mihad
// Module that converts slave WISHBONE B3 accesses to
// WISHBONE B2 accesses with CAB.
126,6 → 129,7
wbs_sel_o <= 4'h0 ;
wbs_we_o <= 1'b0 ;
wbs_dat_i_o_valid <= 1'b0 ;
wbs_cab_o <= 1'b0 ;
end
else
begin:transfer_and_transfer_adr_ctrl_blk
186,19 → 190,19
wbs_cab_o <= 1'b1 ;
end
2'b01: begin
if (wbs_adr_i[3:0] == 4'b0000)
if (wbs_adr_i[3:2] == 2'b00)
wbs_cab_o <= 1'b1 ;
else
wbs_cab_o <= 1'b0 ;
end
2'b10: begin
if (wbs_adr_i[4:0] == 5'b00000)
if (wbs_adr_i[4:2] == 3'b000)
wbs_cab_o <= 1'b1 ;
else
wbs_cab_o <= 1'b0 ;
end
2'b11: begin
if (wbs_adr_i[5:0] == 6'b000000)
if (wbs_adr_i[5:2] == 4'b0000)
wbs_cab_o <= 1'b1 ;
else
wbs_cab_o <= 1'b0 ;
/trunk/rtl/verilog/pci_user_constants.v
39,6 → 39,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2003/08/03 18:05:06 mihad
// Added limited WISHBONE B3 support for WISHBONE Slave Unit.
// Doesn't support full speed bursts yet.
//
// Revision 1.8 2003/03/14 15:31:57 mihad
// Entered the option to disable no response counter in wb master.
//
76,29 → 80,29
// If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and
// WB_FIFO_RAM_ADDR_LENGTH.
 
`define WBW_ADDR_LENGTH 3
`define WBR_ADDR_LENGTH 5
`define PCIW_ADDR_LENGTH 3
`define PCIR_ADDR_LENGTH 3
`define WBW_ADDR_LENGTH 7
`define WBR_ADDR_LENGTH 7
`define PCIW_ADDR_LENGTH 7
`define PCIR_ADDR_LENGTH 7
 
`define FPGA
`define XILINX
//`define FPGA
//`define XILINX
 
//`define WB_RAM_DONT_SHARE
`define PCI_RAM_DONT_SHARE
//`define PCI_RAM_DONT_SHARE
 
`ifdef FPGA
`ifdef XILINX
`define PCI_FIFO_RAM_ADDR_LENGTH 4 // PCI target unit fifo storage definition
`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition
//`define PCI_XILINX_RAMB4
`define PCI_XILINX_RAMB4
`define WB_XILINX_RAMB4
`define PCI_XILINX_DIST_RAM
//`define PCI_XILINX_DIST_RAM
//`define WB_XILINX_DIST_RAM
`endif
`else
`define PCI_FIFO_RAM_ADDR_LENGTH 4 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
`define WB_FIFO_RAM_ADDR_LENGTH 7 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
// `define WB_ARTISAN_SDP
// `define PCI_ARTISAN_SDP
// `define PCI_VS_STP
126,7 → 130,7
// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of PCI images,
// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
// smaller the number here, faster the decoder operation
`define PCI_NUM_OF_DEC_ADDR_LINES 12
`define PCI_NUM_OF_DEC_ADDR_LINES 20
 
// no. of PCI Target IMAGES
// - PCI provides 6 base address registers for image implementation.
140,14 → 144,14
// or GUEST implementation.
`ifdef HOST
`ifdef NO_CNF_IMAGE
`define PCI_IMAGE0
//`define PCI_IMAGE0
`endif
`endif
 
//`define PCI_IMAGE2
//`define PCI_IMAGE3
//`define PCI_IMAGE4
//`define PCI_IMAGE5
`define PCI_IMAGE2
`define PCI_IMAGE3
`define PCI_IMAGE4
`define PCI_IMAGE5
 
// initial value for PCI image address masks. Address masks can be defined in enabled state,
// to allow device independent software to detect size of image and map base addresses to
176,7 → 180,7
// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images,
// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
// smaller the number here, faster the decoder operation
`define WB_NUM_OF_DEC_ADDR_LINES 3
`define WB_NUM_OF_DEC_ADDR_LINES 20
 
// no. of WISHBONE Slave IMAGES
// WB image 0 is always used for access to configuration space. In case configuration space access is not implemented,
183,15 → 187,15
// ( both GUEST and NO_CNF_IMAGE defined ), then WB image 0 is not implemented. User doesn't need to define image 0.
// WB Image 1 is always implemented and user doesnt need to specify its definition
// WB images' 2 through 5 implementation by defining each one.
//`define WB_IMAGE2
//`define WB_IMAGE3
//`define WB_IMAGE4
//`define WB_IMAGE5
`define WB_IMAGE2
`define WB_IMAGE3
`define WB_IMAGE4
`define WB_IMAGE5
 
// If this define is commented out, then address translation will not be implemented.
// addresses will pass through bridge unchanged, regardles of address translation enable bits.
// Address translation also slows down the decoding
//`define ADDR_TRAN_IMPL
`define ADDR_TRAN_IMPL
 
// decode speed for WISHBONE definition - initial cycle on WISHBONE bus will take 1 WS for FAST, 2 WSs for MEDIUM and 3 WSs for slow.
// slower decode speed can be used, to provide enough time for address to be decoded.
200,7 → 204,7
//`define WB_DECODE_SLOW
 
// Base address for Configuration space access from WB bus. This value cannot be changed during runtime
`define WB_CONFIGURATION_BASE 20'hF300_0
`define WB_CONFIGURATION_BASE 20'h0000_0
 
// Turn registered WISHBONE slave outputs on or off
// all outputs from WB Slave state machine are registered, if this is defined - WB bus outputs as well as
227,7 → 231,7
// Turn registered WISHBONE master outputs on or off
// all outputs from WB Master state machine are registered, if this is defined - WB bus outputs as well as
// outputs to internals of the core.
`define REGISTER_WBM_OUTPUTS
//`define REGISTER_WBM_OUTPUTS
 
// MAX Retry counter value for WISHBONE Master state-machine
// This value is 8-bit because of 8-bit retry counter !!!
235,9 → 239,11
 
// define the macro below to disable internal retry generation in the wishbone master interface
// used when wb master accesses extremly slow devices.
`define PCI_WBM_NO_RESPONSE_CNT_DISABLE
//`define PCI_WBM_NO_RESPONSE_CNT_DISABLE
 
//`define PCI_WB_REV_B3
`define PCI_WB_REV_B3
//`define PCI_WBS_B3_RTY_DISABLE
 
//`define PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
`ifdef GUEST
`define PCI_CPCI_HS_IMPLEMENT
`endif
/trunk/rtl/verilog/pci_master32_sm_if.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2003/06/12 10:12:22 mihad
// Changed one critical PCI bus signal logic.
//
// Revision 1.4 2003/01/27 16:49:31 mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
393,11 → 396,45
current_byte_address <= #`FF_DELAY new_address[1:0] ;
end
 
// address output to PCI master state machine assignement
assign address_out = { current_dword_address, current_byte_address } ;
// byte address generation logic
reg [ 1: 0] generated_byte_adr ;
reg [ 1: 0] pci_byte_adr ;
 
always@(be_out)
begin
casex(be_out)
4'bxxx0:generated_byte_adr = 2'b00 ;
4'bxx01:generated_byte_adr = 2'b01 ;
4'bx011:generated_byte_adr = 2'b10 ;
4'b0111:generated_byte_adr = 2'b11 ;
4'b1111:generated_byte_adr = 2'b00 ;
endcase
end
 
always@(generated_byte_adr or bc_out or current_byte_address)
begin
// for memory access commands, set lower 2 address bits to 0
if ((bc_out == `BC_MEM_READ) | (bc_out == `BC_MEM_WRITE) |
(bc_out == `BC_MEM_READ_MUL) | (bc_out == `BC_MEM_READ_LN) |
(bc_out == `BC_MEM_WRITE_INVAL))
begin
pci_byte_adr = 2'b00 ;
end
else if ((bc_out == `BC_IO_WRITE) | (bc_out == `BC_IO_READ))
begin
pci_byte_adr = generated_byte_adr ;
end
else
begin
pci_byte_adr = current_byte_address ;
end
end
 
// address output to PCI master state machine assignment
assign address_out = { current_dword_address, pci_byte_adr } ;
 
// the same for erroneous address assignement
assign err_addr_out = { current_dword_address, current_byte_address } ;
assign err_addr_out = { current_dword_address, pci_byte_adr } ;
 
// cacheline size counter - for read transaction length control
// cache line count is enabled during burst reads when data is actually transfered
/trunk/rtl/verilog/pci_target_unit.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.14 2003/10/17 09:11:52 markom
// mbist signals updated according to newest convention
//
// Revision 1.13 2003/08/21 20:55:14 tadejm
// Corrected bug when writing to FIFO (now it is registered).
//
177,7 → 180,6
pciu_conf_wenable_out,
pciu_conf_be_out,
pciu_conf_data_out,
pciu_conf_select_out,
pciu_pci_drcomp_pending_out,
pciu_pciw_fifo_empty_out
 
277,7 → 279,6
output pciu_err_source_out ;
output pciu_err_rty_exp_out ;
 
output pciu_conf_select_out ;
output [11:0] pciu_conf_offset_out ;
output pciu_conf_renable_out ;
output pciu_conf_wenable_out ;
326,7 → 327,6
wire pcit_sm_load_medium_reg_out ;
wire pcit_sm_sel_fifo_mreg_out ;
wire pcit_sm_sel_conf_fifo_out ;
wire pcit_sm_fetch_conf_out ;
wire pcit_sm_load_to_pciw_fifo_out ;
wire pcit_sm_load_to_conf_out ;
 
371,7 → 371,6
wire [31:0] pcit_if_pciw_fifo_addr_data_out ;
wire [3:0] pcit_if_pciw_fifo_cbe_out ;
wire [3:0] pcit_if_pciw_fifo_control_out ;
wire pcit_if_conf_hit_out ;
wire [11:0] pcit_if_conf_addr_out ;
wire [31:0] pcit_if_conf_data_out ;
wire [3:0] pcit_if_conf_be_out ;
380,7 → 379,6
 
// pci target state machine outputs
// pci interface signals
assign pciu_conf_select_out = pcit_if_conf_hit_out ;
assign pciu_conf_offset_out = pcit_if_conf_addr_out ;
assign pciu_conf_renable_out = pcit_if_conf_re_out ;
assign pciu_conf_wenable_out = pcit_if_conf_we_out ;
650,7 → 648,6
wire pcit_if_load_medium_reg_in = pcit_sm_load_medium_reg_out ;
wire pcit_if_sel_fifo_mreg_in = pcit_sm_sel_fifo_mreg_out ;
wire pcit_if_sel_conf_fifo_in = pcit_sm_sel_conf_fifo_out ;
wire pcit_if_fetch_conf_in = pcit_sm_fetch_conf_out ;
wire pcit_if_load_to_pciw_fifo_in = pcit_sm_load_to_pciw_fifo_out ;
wire pcit_if_load_to_conf_in = pcit_sm_load_to_conf_out ;
wire pcit_if_req_req_pending_in = del_sync_req_req_pending_out ;
734,7 → 731,6
.load_medium_reg_in (pcit_if_load_medium_reg_in),
.sel_fifo_mreg_in (pcit_if_sel_fifo_mreg_in),
.sel_conf_fifo_in (pcit_if_sel_conf_fifo_in),
.fetch_conf_in (pcit_if_fetch_conf_in),
.load_to_pciw_fifo_in (pcit_if_load_to_pciw_fifo_in),
.load_to_conf_in (pcit_if_load_to_conf_in),
.same_read_out (pcit_if_same_read_out),
779,7 → 775,6
.pciw_fifo_full_in (pcit_if_pciw_fifo_full_in),
.wbw_fifo_empty_in (pcit_if_wbw_fifo_empty_in),
.wbu_del_read_comp_pending_in (pcit_if_wbu_del_read_comp_pending_in),
.conf_hit_out (pcit_if_conf_hit_out),
.conf_addr_out (pcit_if_conf_addr_out),
.conf_data_out (pcit_if_conf_data_out),
.conf_data_in (pcit_if_conf_data_in),
907,7 → 902,6
.load_medium_reg_out (pcit_sm_load_medium_reg_out),
.sel_fifo_mreg_out (pcit_sm_sel_fifo_mreg_out),
.sel_conf_fifo_out (pcit_sm_sel_conf_fifo_out),
.fetch_conf_out (pcit_sm_fetch_conf_out),
.load_to_pciw_fifo_out (pcit_sm_load_to_pciw_fifo_out),
.load_to_conf_out (pcit_sm_load_to_conf_out),
.same_read_in (pcit_sm_same_read_in),
/trunk/rtl/verilog/pci_wbw_wbr_fifos.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2003/10/17 09:11:52 markom
// mbist signals updated according to newest convention
//
// Revision 1.4 2003/08/14 13:06:03 simons
// synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.
//
527,11 → 530,11
begin
if (wbw_clear)
begin
inGreyCount <= #`FF_DELAY 0 ;
inGreyCount <= #3 0 ;
end
else
if (in_count_en)
inGreyCount <= #`FF_DELAY inNextGreyCount ;
inGreyCount <= #3 inNextGreyCount ;
end
 
wire [(WBW_ADDR_LENGTH-2):0] pci_clk_sync_inGreyCount ;
/trunk/rtl/verilog/pci_wb_slave.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2003/08/14 18:01:53 simons
// ifdefs moved to thier own lines, this confuses some of the tools.
//
// Revision 1.2 2003/08/03 18:05:06 mihad
// Added limited WISHBONE B3 support for WISHBONE Slave Unit.
// Doesn't support full speed bursts yet.
421,9 → 424,6
// applies for reads only - delayed write cannot be a burst
wire do_dread_completion = del_completion_allow && del_addr_hit ;
 
// address allignement indicator
wire alligned_address = ~|(wb_addr_in[1:0]) ;
 
`ifdef GUEST
 
// wires indicating allowance for configuration cycle generation requests
452,18 → 452,10
reg current_delayed_is_ccyc ;
reg current_delayed_is_iack ;
 
wire wccyc_hit = (wb_addr_in[8:2] == {1'b1, `CNF_DATA_ADDR})
`ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
`else
&& alligned_address
`endif
;
wire wiack_hit = (wb_addr_in[8:2] == {1'b1, `INT_ACK_ADDR})
`ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
`else
&& alligned_address
`endif
;
wire wccyc_hit = (wb_addr_in[8:2] == {1'b1, `CNF_DATA_ADDR}) ;
 
wire wiack_hit = (wb_addr_in[8:2] == {1'b1, `INT_ACK_ADDR}) ;
 
reg iack_hit ;
reg ccyc_hit ;
always@(posedge reset_in or posedge wb_clock_in)
524,18 → 516,6
// burst access indicator
wire burst_transfer = CYC_I && CAB_I ;
 
// SEL_I error indicator for IO accesses - select lines must be alligned with address
reg sel_error ;
always@(wb_addr_in or SEL_I)
begin
case (wb_addr_in[1:0])
2'b00: sel_error = ~SEL_I[0] ; // select 0 must be 1, all others are don't cares.
2'b01: sel_error = ~SEL_I[1] || SEL_I[0] ; // byte 0 can't be selected, byte 1 must be selected
2'b10: sel_error = ~SEL_I[2] || SEL_I[1] || SEL_I[0] ; // bytes 0 and 1 can't be selected, byte 2 must be selected
2'b11: sel_error = ~SEL_I[3] || SEL_I[2] || SEL_I[1] || SEL_I[0] ; // bytes 0, 1 and 2 can't be selected, byte 3 must be selected
endcase
end
 
// WBW_FIFO control output
reg [3:0] wbw_fifo_control ;
 
615,8 → 595,7
 
reg del_in_progress ; // state machine indicates whether current read completion is in progress on WISHBONE bus
 
wire image_access_error = (map && (burst_transfer || sel_error)) || // IO write is a burst or has wrong select lines active= Error
(~map && ~alligned_address) ; // Mem write to nonaligned address = error;
wire image_access_error = (map && burst_transfer) ; // IO write is a burst
 
`ifdef HOST
reg [1:0] wbw_data_out_sel ;
653,7 → 632,6
burst_transfer or
wb_hit or
map or
alligned_address or
rattempt or
do_dread_completion or
wbr_fifo_control_in or
833,10 → 811,10
 
S_W_ADDR_DATA: begin
wbw_data_out_sel = SEL_DATA_IN ;
err = burst_transfer && wattempt && ~alligned_address ;
err = 1'b0 ;
rty = burst_transfer && wattempt && (wbw_fifo_almost_full_in || wbw_fifo_full_in) ;
 
if ( ~burst_transfer || wattempt && ( ~alligned_address || wbw_fifo_almost_full_in || wbw_fifo_full_in ) )
if ( ~burst_transfer || wattempt && ( wbw_fifo_almost_full_in || wbw_fifo_full_in ) )
begin
n_state = S_IDLE ;
 
860,14 → 838,13
// this state is for reads only - in this state read is in progress all the time
del_in_progress = 1'b1 ;
 
ack = burst_transfer && rattempt && ~wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] && alligned_address && ~wbr_fifo_empty_in ;
err = burst_transfer && rattempt && ((wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] || ~alligned_address) && ~wbr_fifo_empty_in) ;
//rty = burst_transfer && rattempt && wbr_fifo_empty_in && alligned_address ;
ack = burst_transfer && rattempt && ~wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] && ~wbr_fifo_empty_in ;
err = burst_transfer && rattempt && wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] && ~wbr_fifo_empty_in ;
 
// if acknowledge is beeing signalled then enable read from wbr fifo
wbr_fifo_renable = burst_transfer && rattempt && alligned_address && ~wbr_fifo_empty_in ;
wbr_fifo_renable = burst_transfer && rattempt && ~wbr_fifo_empty_in ;
 
if ( ~burst_transfer || rattempt && (~alligned_address || wbr_fifo_empty_in || wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] || wbr_fifo_control_in[`LAST_CTRL_BIT]) )
if ( ~burst_transfer || rattempt && (wbr_fifo_empty_in || wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] || wbr_fifo_control_in[`LAST_CTRL_BIT]) )
begin
n_state = S_IDLE ;
del_done = 1'b1 ;
882,34 → 859,14
S_CONF_WRITE: begin
`ifdef HOST
wbw_data_out_sel = SEL_CCYC_ADDR ;
del_req = do_ccyc_req && ~burst_transfer
`ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
`else
&& alligned_address
`endif
;
del_done = do_ccyc_comp && ~burst_transfer
`ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
`else
&& alligned_address
`endif
;
del_in_progress = do_ccyc_comp && ~burst_transfer
`ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
`else
&& alligned_address
`endif
;
del_req = do_ccyc_req && ~burst_transfer ;
del_done = do_ccyc_comp && ~burst_transfer ;
del_in_progress = do_ccyc_comp && ~burst_transfer ;
`endif
 
n_state = S_IDLE ; // next state after configuration access is always idle
 
if ( burst_transfer
`ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
`else
| ~alligned_address
`endif
)
if ( burst_transfer )
begin
err = 1'b1 ;
end
941,40 → 898,15
S_CONF_READ: begin
`ifdef HOST
wbw_data_out_sel = SEL_CCYC_ADDR ;
del_req = ~burst_transfer
`ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
`else
&& alligned_address
`endif
&& ( do_ccyc_req || do_iack_req ) ;
del_done = ~burst_transfer
`ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
`else
&& alligned_address
`endif
&& ( do_ccyc_comp || do_iack_comp ) ;
del_in_progress = ~burst_transfer
`ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
`else
&& alligned_address
`endif
&& ( do_ccyc_comp || do_iack_comp ) ;
wbr_fifo_renable = ~burst_transfer
`ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
`else
&& alligned_address
`endif
&& ( do_ccyc_comp || do_iack_comp ) ;
del_req = ~burst_transfer && ( do_ccyc_req || do_iack_req ) ;
del_done = ~burst_transfer && ( do_ccyc_comp || do_iack_comp ) ;
del_in_progress = ~burst_transfer && ( do_ccyc_comp || do_iack_comp ) ;
wbr_fifo_renable = ~burst_transfer && ( do_ccyc_comp || do_iack_comp ) ;
`endif
 
n_state = S_IDLE ; // next state after configuration access is always idle
 
if ( burst_transfer
`ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
`else
| ~alligned_address
`endif
)
if ( burst_transfer )
begin
err = 1'b1 ;
end
/trunk/rtl/verilog/pci_in_reg.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2003/01/27 16:49:31 mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.3 2002/02/01 15:25:12 mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
60,9 → 63,10
// Module is used for registering PCI input signals
// It provides data flip flops with reset
module pci_in_reg
(
(
reset_in,
clk_in,
init_complete_in,
 
pci_gnt_in,
pci_frame_in,
86,7 → 90,7
 
);
 
input reset_in, clk_in ;
input reset_in, clk_in, init_complete_in ;
 
input pci_gnt_in ;
input pci_frame_in ;
124,7 → 128,7
if ( reset_in )
begin
pci_gnt_reg_out <= #`FF_DELAY 1'b1 ;
pci_frame_reg_out <= #`FF_DELAY 1'b1 ;
pci_frame_reg_out <= #`FF_DELAY 1'b0 ;
pci_irdy_reg_out <= #`FF_DELAY 1'b1 ;
pci_trdy_reg_out <= #`FF_DELAY 1'b1 ;
pci_stop_reg_out <= #`FF_DELAY 1'b1 ;
133,7 → 137,7
pci_ad_reg_out <= #`FF_DELAY 32'h0000_0000 ;
pci_cbe_reg_out <= #`FF_DELAY 4'h0 ;
end
else
else if (init_complete_in)
begin
pci_gnt_reg_out <= #`FF_DELAY pci_gnt_in ;
pci_frame_reg_out <= #`FF_DELAY pci_frame_in ;
/trunk/rtl/verilog/pci_target32_interface.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2003/08/21 20:55:14 tadejm
// Corrected bug when writing to FIFO (now it is registered).
//
// Revision 1.8 2003/08/08 16:36:33 tadejm
// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.
//
102,7 → 105,6
load_medium_reg_in,
sel_fifo_mreg_in,
sel_conf_fifo_in,
fetch_conf_in,
load_to_pciw_fifo_in,
load_to_conf_in,
same_read_out,
154,7 → 156,6
wbu_del_read_comp_pending_in,
 
// Configuration space signals
conf_hit_out,
conf_addr_out,
conf_data_out,
conf_data_in,
234,7 → 235,6
input load_medium_reg_in ;// Load data from PCIR_FIFO to medium register (first data must be prepared on time)
input sel_fifo_mreg_in ; // Read data selection between PCIR_FIFO and medium register
input sel_conf_fifo_in ; // Read data selection between Configuration registers and "FIFO"
input fetch_conf_in ; // Read enable for configuration space registers
input load_to_pciw_fifo_in ;// Write enable to PCIW_FIFO
input load_to_conf_in ; // Write enable to Configuration space registers
 
312,7 → 312,6
Configuration space signals - from and to registers
==================================================================================================================*/
// BUS for reading and writing to configuration space registers
output conf_hit_out ; // like "chip select" for configuration space
output [11:0] conf_addr_out ; // address to configuration space when there is access to it
output [31:0] conf_data_out ; // data to configuration space - for writing to registers
input [31:0] conf_data_in ; // data from configuration space - for reading from registers
/trunk/rtl/verilog/pci_constants.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/02/01 14:43:31 mihad
// *** empty log message ***
//
// Revision 1.2 2001/10/05 08:14:28 mihad
// Updated all files with inclusion of timescale file for simulation purposes.
//
87,6 → 90,7
// This does not include address offsets of PCI Header registers - they starts at offset 0 (see PCI spec.)
// ALL VALUES are without 2 LSBits AND there is required that address bit [8] is set while
// accessing this registers, otherwise the configuration header will be accessed !!!
`define PCI_CAP_PTR_VAL 8'h80
`define P_IMG_CTRL0_ADDR 6'h00 // Address offset = h 100
`define P_BA0_ADDR 6'h01 // Address offset = h 104
`define P_AM0_ADDR 6'h02 // Address offset = h 108
/trunk/apps/test/rtl/verilog/pci_bridge32.v
43,9 → 43,25
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2003/06/12 02:55:26 mihad
// Added a test application!
// Revision 1.15 2003/12/10 12:02:54 mihad
// The wbs B3 to B2 translation logic had wrong reset wire connected!
//
// Revision 1.14 2003/12/09 09:33:57 simons
// Some warning cleanup.
//
// Revision 1.13 2003/10/17 09:11:52 markom
// mbist signals updated according to newest convention
//
// Revision 1.12 2003/08/21 20:49:03 tadejm
// Added signals for WB Master B3.
//
// Revision 1.11 2003/08/08 16:36:33 tadejm
// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.
//
// Revision 1.10 2003/08/03 18:05:06 mihad
// Added limited WISHBONE B3 support for WISHBONE Slave Unit.
// Doesn't support full speed bursts yet.
//
// Revision 1.9 2003/01/27 16:49:31 mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
102,7 → 118,18
wbs_cyc_i,
wbs_stb_i,
wbs_we_i,
 
`ifdef PCI_WB_REV_B3
 
wbs_cti_i,
wbs_bte_i,
 
`else
 
wbs_cab_i,
 
`endif
 
wbs_ack_o,
wbs_rty_o,
wbs_err_o,
115,7 → 142,8
wbm_cyc_o,
wbm_stb_o,
wbm_we_o,
wbm_cab_o,
wbm_cti_o,
wbm_bte_o,
wbm_ack_i,
wbm_rty_i,
wbm_err_i,
187,6 → 215,7
irdy_en_o,
pci_ad_bckp_o
 
 
`ifdef PCI_BIST
,
// debug chain signals
194,6 → 223,16
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
 
`ifdef PCI_CPCI_HS_IMPLEMENT
,
// Compact PCI Hot Swap signals
pci_cpci_hs_enum_o , // ENUM# output with output enable (open drain)
pci_cpci_hs_enum_oe_o , // ENUM# enum output enable
pci_cpci_hs_led_o , // LED output with output enable (open drain)
pci_cpci_hs_led_oe_o , // LED output enable
pci_cpci_hs_es_i // ejector switch state indicator input
`endif
);
 
// WISHBONE system signals
211,7 → 250,18
input wbs_cyc_i ;
input wbs_stb_i ;
input wbs_we_i ;
input wbs_cab_i ;
 
`ifdef PCI_WB_REV_B3
 
input [2:0] wbs_cti_i ;
input [1:0] wbs_bte_i ;
 
`else
 
input wbs_cab_i ;
 
`endif
 
output wbs_ack_o ;
output wbs_rty_o ;
output wbs_err_o ;
224,7 → 274,8
output wbm_cyc_o ;
output wbm_stb_o ;
output wbm_we_o ;
output wbm_cab_o ;
output [2:0] wbm_cti_o ;
output [1:0] wbm_bte_o ;
input wbm_ack_i ;
input wbm_rty_i ;
input wbm_err_i ;
304,10 → 355,18
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
 
// internal wires for serial chain connection
wire SO_internal ;
wire SI_internal = SO_internal ;
`ifdef PCI_CPCI_HS_IMPLEMENT
// Compact PCI Hot Swap signals
output pci_cpci_hs_enum_o ; // ENUM# output with output enable (open drain)
output pci_cpci_hs_enum_oe_o ; // ENUM# enum output enable
output pci_cpci_hs_led_o ; // LED output with output enable (open drain)
output pci_cpci_hs_led_oe_o ; // LED output enable
input pci_cpci_hs_es_i ; // ejector switch state indicator input
 
assign pci_cpci_hs_enum_o = 1'b0 ;
assign pci_cpci_hs_led_o = 1'b0 ;
`endif
 
// declare clock and reset wires
370,12 → 429,6
wire wbu_ad_load_on_transfer_out ;
wire wbu_pciif_frame_load_out ;
 
// assign wishbone slave unit's outputs to top outputs where possible
assign wbs_dat_o = wbu_sdata_out ;
assign wbs_ack_o = wbu_ack_out ;
assign wbs_rty_o = wbu_rty_out ;
assign wbs_err_o = wbu_err_out ;
 
// PCI TARGET UNIT OUTPUTS
wire [31:0] pciu_adr_out ;
wire [31:0] pciu_mdata_out ;
382,8 → 435,9
wire pciu_cyc_out ;
wire pciu_stb_out ;
wire pciu_we_out ;
wire [2:0] pciu_cti_out ;
wire [1:0] pciu_bte_out ;
wire [3:0] pciu_sel_out ;
wire pciu_cab_out ;
wire pciu_pciif_trdy_out ;
wire pciu_pciif_stop_out ;
wire pciu_pciif_devsel_out ;
402,7 → 456,6
wire pciu_err_signal_out ;
wire pciu_err_source_out ;
wire pciu_err_rty_exp_out ;
wire pciu_conf_select_out ;
wire [11:0] pciu_conf_offset_out ;
wire pciu_conf_renable_out ;
wire pciu_conf_wenable_out ;
413,12 → 466,13
 
// assign pci target unit's outputs to top outputs where possible
assign wbm_adr_o = pciu_adr_out ;
assign wbm_dat_o = pciu_mdata_out ;
assign wbm_dat_o = pciu_mdata_out ;
assign wbm_cyc_o = pciu_cyc_out ;
assign wbm_stb_o = pciu_stb_out ;
assign wbm_we_o = pciu_we_out ;
assign wbm_cti_o = pciu_cti_out ;
assign wbm_bte_o = pciu_bte_out ;
assign wbm_sel_o = pciu_sel_out ;
assign wbm_cab_o = pciu_cab_out ;
 
// CONFIGURATION SPACE OUTPUTS
wire [31:0] conf_w_data_out ;
501,6 → 555,7
wire [23:0] conf_ccyc_addr_out ;
wire conf_soft_res_out ;
wire conf_int_out ;
wire conf_init_complete_out ;
 
// PCI IO MUX OUTPUTS
wire pci_mux_frame_out ;
616,8 → 671,7
wire pci_inti_pci_intan_in = pci_inta_i ;
wire pci_inti_conf_int_in = conf_int_out ;
wire pci_inti_int_i = wb_int_i ;
wire pci_inti_out_bckp_perr_en_in = out_bckp_perr_en_out ;
wire pci_inti_out_bckp_serr_en_in = out_bckp_serr_en_out ;
wire pci_into_init_complete_in = conf_init_complete_out ;
 
pci_rst_int pci_resets_and_interrupts
(
632,15 → 686,89
.pci_intan_in (pci_inti_pci_intan_in),
.conf_int_in (pci_inti_conf_int_in),
.int_i (pci_inti_int_i),
.out_bckp_perr_en_in (pci_inti_out_bckp_perr_en_in),
.out_bckp_serr_en_in (pci_inti_out_bckp_serr_en_in),
.pci_intan_out (pci_into_pci_intan_out),
.pci_intan_en_out (pci_into_pci_intan_en_out),
.int_o (pci_into_int_o),
.conf_isr_int_prop_out (pci_into_conf_isr_int_prop_out)
.conf_isr_int_prop_out (pci_into_conf_isr_int_prop_out),
.init_complete_in (pci_into_init_complete_in)
);
 
 
`ifdef PCI_WB_REV_B3
 
wire wbs_wbb3_2_wbb2_cyc_o ;
wire wbs_wbb3_2_wbb2_stb_o ;
wire [31:0] wbs_wbb3_2_wbb2_adr_o ;
wire [31:0] wbs_wbb3_2_wbb2_dat_i_o ;
wire [31:0] wbs_wbb3_2_wbb2_dat_o_o ;
wire wbs_wbb3_2_wbb2_we_o ;
wire [ 3:0] wbs_wbb3_2_wbb2_sel_o ;
wire wbs_wbb3_2_wbb2_ack_o ;
wire wbs_wbb3_2_wbb2_err_o ;
wire wbs_wbb3_2_wbb2_rty_o ;
wire wbs_wbb3_2_wbb2_cab_o ;
 
// assign wishbone slave unit's outputs to top outputs where possible
assign wbs_dat_o = wbs_wbb3_2_wbb2_dat_o_o ;
assign wbs_ack_o = wbs_wbb3_2_wbb2_ack_o ;
assign wbs_rty_o = wbs_wbb3_2_wbb2_rty_o ;
assign wbs_err_o = wbs_wbb3_2_wbb2_err_o ;
 
wire wbs_wbb3_2_wbb2_cyc_i = wbs_cyc_i ;
wire wbs_wbb3_2_wbb2_stb_i = wbs_stb_i ;
wire wbs_wbb3_2_wbb2_we_i = wbs_we_i ;
wire wbs_wbb3_2_wbb2_ack_i = wbu_ack_out ;
wire wbs_wbb3_2_wbb2_err_i = wbu_err_out ;
wire wbs_wbb3_2_wbb2_rty_i = wbu_rty_out ;
wire [31:0] wbs_wbb3_2_wbb2_adr_i = wbs_adr_i ;
wire [ 3:0] wbs_wbb3_2_wbb2_sel_i = wbs_sel_i ;
wire [31:0] wbs_wbb3_2_wbb2_dat_i_i = wbs_dat_i ;
wire [31:0] wbs_wbb3_2_wbb2_dat_o_i = wbu_sdata_out ;
wire [ 2:0] wbs_wbb3_2_wbb2_cti_i = wbs_cti_i ;
wire [ 1:0] wbs_wbb3_2_wbb2_bte_i = wbs_bte_i ;
 
pci_wbs_wbb3_2_wbb2 i_pci_wbs_wbb3_2_wbb2
(
.wb_clk_i ( wb_clk_i ) ,
.wb_rst_i ( reset ) ,
 
.wbs_cyc_i ( wbs_wbb3_2_wbb2_cyc_i ) ,
.wbs_cyc_o ( wbs_wbb3_2_wbb2_cyc_o ) ,
.wbs_stb_i ( wbs_wbb3_2_wbb2_stb_i ) ,
.wbs_stb_o ( wbs_wbb3_2_wbb2_stb_o ) ,
.wbs_adr_i ( wbs_wbb3_2_wbb2_adr_i ) ,
.wbs_adr_o ( wbs_wbb3_2_wbb2_adr_o ) ,
.wbs_dat_i_i ( wbs_wbb3_2_wbb2_dat_i_i ) ,
.wbs_dat_i_o ( wbs_wbb3_2_wbb2_dat_i_o ) ,
.wbs_dat_o_i ( wbs_wbb3_2_wbb2_dat_o_i ) ,
.wbs_dat_o_o ( wbs_wbb3_2_wbb2_dat_o_o ) ,
.wbs_we_i ( wbs_wbb3_2_wbb2_we_i ) ,
.wbs_we_o ( wbs_wbb3_2_wbb2_we_o ) ,
.wbs_sel_i ( wbs_wbb3_2_wbb2_sel_i ) ,
.wbs_sel_o ( wbs_wbb3_2_wbb2_sel_o ) ,
.wbs_ack_i ( wbs_wbb3_2_wbb2_ack_i ) ,
.wbs_ack_o ( wbs_wbb3_2_wbb2_ack_o ) ,
.wbs_err_i ( wbs_wbb3_2_wbb2_err_i ) ,
.wbs_err_o ( wbs_wbb3_2_wbb2_err_o ) ,
.wbs_rty_i ( wbs_wbb3_2_wbb2_rty_i ) ,
.wbs_rty_o ( wbs_wbb3_2_wbb2_rty_o ) ,
.wbs_cti_i ( wbs_wbb3_2_wbb2_cti_i ) ,
.wbs_bte_i ( wbs_wbb3_2_wbb2_bte_i ) ,
.wbs_cab_o ( wbs_wbb3_2_wbb2_cab_o )
) ;
 
// WISHBONE SLAVE UNIT INPUTS
wire [31:0] wbu_addr_in = wbs_wbb3_2_wbb2_adr_o ;
wire [31:0] wbu_sdata_in = wbs_wbb3_2_wbb2_dat_i_o ;
wire wbu_cyc_in = wbs_wbb3_2_wbb2_cyc_o ;
wire wbu_stb_in = wbs_wbb3_2_wbb2_stb_o ;
wire wbu_we_in = wbs_wbb3_2_wbb2_we_o ;
wire [3:0] wbu_sel_in = wbs_wbb3_2_wbb2_sel_o ;
wire wbu_cab_in = wbs_wbb3_2_wbb2_cab_o ;
 
`else
 
// WISHBONE SLAVE UNIT INPUTS
wire [31:0] wbu_addr_in = wbs_adr_i ;
wire [31:0] wbu_sdata_in = wbs_dat_i ;
wire wbu_cyc_in = wbs_cyc_i ;
649,6 → 777,14
wire [3:0] wbu_sel_in = wbs_sel_i ;
wire wbu_cab_in = wbs_cab_i ;
 
// assign wishbone slave unit's outputs to top outputs where possible
assign wbs_dat_o = wbu_sdata_out ;
assign wbs_ack_o = wbu_ack_out ;
assign wbs_rty_o = wbu_rty_out ;
assign wbs_err_o = wbu_err_out ;
 
`endif
 
wire [5:0] wbu_map_in = {
conf_wb_mem_io5_out,
conf_wb_mem_io4_out,
907,6 → 1043,7
wire pciu_pciif_idsel_reg_in = in_reg_idsel_out ;
wire [31:0] pciu_pciif_ad_reg_in = in_reg_ad_out ;
wire [3:0] pciu_pciif_cbe_reg_in = in_reg_cbe_out ;
wire [3:0] pciu_pciif_cbe_in = pci_cbe_i ;
 
wire pciu_pciif_bckp_trdy_en_in = out_bckp_trdy_en_out ;
wire pciu_pciif_bckp_devsel_in = out_bckp_devsel_out ;
920,17 → 1057,18
.reset_in (reset),
.wb_clock_in (wb_clk),
.pci_clock_in (pci_clk),
.ADR_O (pciu_adr_out),
.MDATA_O (pciu_mdata_out),
.MDATA_I (pciu_mdata_in),
.CYC_O (pciu_cyc_out),
.STB_O (pciu_stb_out),
.WE_O (pciu_we_out),
.SEL_O (pciu_sel_out),
.ACK_I (pciu_ack_in),
.RTY_I (pciu_rty_in),
.ERR_I (pciu_err_in),
.CAB_O (pciu_cab_out),
.pciu_wbm_adr_o (pciu_adr_out),
.pciu_wbm_dat_o (pciu_mdata_out),
.pciu_wbm_dat_i (pciu_mdata_in),
.pciu_wbm_cyc_o (pciu_cyc_out),
.pciu_wbm_stb_o (pciu_stb_out),
.pciu_wbm_we_o (pciu_we_out),
.pciu_wbm_cti_o (pciu_cti_out),
.pciu_wbm_bte_o (pciu_bte_out),
.pciu_wbm_sel_o (pciu_sel_out),
.pciu_wbm_ack_i (pciu_ack_in),
.pciu_wbm_rty_i (pciu_rty_in),
.pciu_wbm_err_i (pciu_err_in),
.pciu_mem_enable_in (pciu_mem_enable_in),
.pciu_io_enable_in (pciu_io_enable_in),
.pciu_map_in (pciu_map_in),
968,6 → 1106,7
.pciu_pciif_idsel_reg_in (pciu_pciif_idsel_reg_in),
.pciu_pciif_ad_reg_in (pciu_pciif_ad_reg_in),
.pciu_pciif_cbe_reg_in (pciu_pciif_cbe_reg_in),
.pciu_pciif_cbe_in (pciu_pciif_cbe_in),
.pciu_pciif_bckp_trdy_en_in (pciu_pciif_bckp_trdy_en_in),
.pciu_pciif_bckp_devsel_in (pciu_pciif_bckp_devsel_in),
.pciu_pciif_bckp_trdy_in (pciu_pciif_bckp_trdy_in),
997,7 → 1136,6
.pciu_conf_wenable_out (pciu_conf_wenable_out),
.pciu_conf_be_out (pciu_conf_be_out),
.pciu_conf_data_out (pciu_conf_data_out),
.pciu_conf_select_out (pciu_conf_select_out),
.pciu_pci_drcomp_pending_out (pciu_pci_drcomp_pending_out),
.pciu_pciw_fifo_empty_out (pciu_pciw_fifo_empty_out)
 
1174,7 → 1312,16
.int_out (conf_int_out),
.isr_int_prop (conf_isr_int_prop_in),
.isr_par_err_int (conf_par_err_int_in),
.isr_sys_err_int (conf_sys_err_int_in)
.isr_sys_err_int (conf_sys_err_int_in),
 
.init_complete (conf_init_complete_out)
 
`ifdef PCI_CPCI_HS_IMPLEMENT
,
.pci_cpci_hs_enum_oe_o (pci_cpci_hs_enum_oe_o) ,
.pci_cpci_hs_led_oe_o (pci_cpci_hs_led_oe_o ) ,
.pci_cpci_hs_es_i (pci_cpci_hs_es_i)
`endif
) ;
 
// pci data io multiplexer inputs
1217,6 → 1364,8
wire pci_mux_pci_frame_in = pci_frame_i ;
wire pci_mux_pci_stop_in = pci_stop_i ;
 
wire pci_mux_init_complete_in = conf_init_complete_out ;
 
pci_io_mux pci_io_mux
(
.reset_in (reset),
1282,7 → 1431,9
.pci_trdy_in (pci_mux_pci_trdy_in),
.pci_frame_in (pci_mux_pci_frame_in),
.pci_stop_in (pci_mux_pci_stop_in),
.ad_en_unregistered_out (pci_mux_ad_en_unregistered_out)
.ad_en_unregistered_out (pci_mux_ad_en_unregistered_out),
 
.init_complete_in (pci_mux_init_complete_in)
);
 
pci_cur_out_reg output_backup
1337,9 → 1488,6
.serr_out (out_bckp_serr_out),
.serr_en_out (out_bckp_serr_en_out)
) ;
assign irdy_o = out_bckp_irdy_out ;
assign irdy_en_o = out_bckp_irdy_en_out ;
assign pci_ad_bckp_o = out_bckp_ad_out ;
 
// PARITY CHECKER INPUTS
wire parchk_pci_par_in = pci_par_i ;
1416,12 → 1564,11
wire [31:0] in_reg_ad_in = pci_ad_i ;
wire [3:0] in_reg_cbe_in = pci_cbe_i ;
 
assign trdy_reg_o = in_reg_trdy_out ;
 
pci_in_reg input_register
(
.reset_in (reset),
.clk_in (pci_clk),
.reset_in (reset),
.clk_in (pci_clk),
.init_complete_in (conf_init_complete_out),
 
.pci_gnt_in (in_reg_gnt_in),
.pci_frame_in (in_reg_frame_in),
1444,4 → 1591,9
.pci_cbe_reg_out (in_reg_cbe_out)
);
 
assign trdy_reg_o = in_reg_trdy_out ;
assign irdy_o = out_bckp_irdy_out ;
assign irdy_en_o = out_bckp_irdy_en_out ;
assign pci_ad_bckp_o = out_bckp_ad_out ;
 
endmodule
/trunk/apps/test/rtl/verilog/test.v
2,6 → 2,8
`include "timescale.v"
// synopsys translate_on
 
`include "pci_user_constants.v"
 
module test
(
pci_clk_i,
10,7 → 12,18
wbm_cyc_o,
wbm_stb_o,
 
`ifdef PCI_WB_REV_B3
 
wbm_cti_o,
wbm_bte_o,
 
`else
 
wbm_cab_o,
 
`endif
 
wbm_we_o,
wbm_adr_o,
wbm_sel_o,
22,7 → 35,8
 
wbs_cyc_i,
wbs_stb_i,
wbs_cab_i,
wbs_cti_i,
wbs_bte_i,
wbs_we_i,
wbs_adr_i,
wbs_sel_i,
45,9 → 59,21
output wbm_cyc_o,
wbm_stb_o,
wbm_cab_o,
wbm_we_o ;
 
`ifdef PCI_WB_REV_B3
 
output [ 2: 0] wbm_cti_o ;
output [ 1: 0] wbm_bte_o ;
 
assign wbm_bte_o = 2'b00 ;
 
`else
 
output wbm_cab_o ;
 
`endif
 
output [31:0] wbm_adr_o ;
output [3:0] wbm_sel_o ;
assign wbm_sel_o = 4'hF ;
59,9 → 85,11
 
input wbs_cyc_i,
wbs_stb_i,
wbs_cab_i,
wbs_we_i ;
 
input [ 2: 0] wbs_cti_i ;
input [ 1: 0] wbs_bte_i ;
 
input [31:0] wbs_adr_i ;
input [3:0] wbs_sel_i ;
input [31:0] wbs_dat_i ;
328,7 → 356,7
 
if (sel_target_burst_transaction_count & wbs_write & sel_registers)
target_burst_transaction_count <= 0 ;
else if (wbs_cyc_i & ~wbs_cyc_i_previous & wbs_cab_i)
else if (wbs_cyc_i & ~wbs_cyc_i_previous & (wbs_cti_i == 3'b010) & (wbs_bte_i == 2'b00))
target_burst_transaction_count <= target_burst_transaction_count + 1 ;
 
if (sel_target_test_size & wbs_write & sel_registers)
538,7 → 566,11
assign wbs_err_o = 1'b0 ;
assign wbs_rty_o = 1'b0 ;
 
reg wbm_cyc_o, wbm_cab_o, wbm_stb_o;
reg wbm_cyc_o, wbm_stb_o;
 
reg [ 2: 0] wbm_cti_o ;
reg wbm_cab_o ;
 
reg [31:0] wbm_adr_o ;
reg [31:0] wbm_next_adr_o ;
 
551,6 → 583,7
begin
wbm_cyc_o <= 1'b0 ;
wbm_cab_o <= 1'b0 ;
wbm_cti_o <= 3'h7 ;
wbm_stb_o <= 1'b0 ;
wbm_adr_o <= 32'h0 ;
master_current_transaction_size <= 11'h0 ;
573,6 → 606,7
begin
wbm_cyc_o <= 1'b1 ;
wbm_cab_o <= (master_transaction_size != 11'h1) ;
wbm_cti_o <= (master_transaction_size != 11'h1) ? 3'b010 : 3'b111 ;
wbm_stb_o <= 1'b1 ;
master_current_transaction_size <= master_transaction_size ;
end
580,9 → 614,10
begin
if (wbm_end_cycle)
begin
wbm_cyc_o <= 1'b0 ;
wbm_stb_o <= 1'b0 ;
wbm_cab_o <= 1'b0 ;
wbm_cyc_o <= 1'b0 ;
wbm_stb_o <= 1'b0 ;
wbm_cab_o <= 1'b0 ;
wbm_cti_o <= 3'b111 ;
end
else
begin
589,6 → 624,9
if (wbm_stb_o & wbm_ack_i)
begin
master_current_transaction_size <= master_current_transaction_size - 1'b1 ;
if (master_current_transaction_size == 2)
wbm_cti_o <= 3'b111 ;
end
end
end
/trunk/apps/test/rtl/verilog/pci_user_constants.v
39,6 → 39,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2003/08/03 18:05:06 mihad
// Added limited WISHBONE B3 support for WISHBONE Slave Unit.
// Doesn't support full speed bursts yet.
//
// Revision 1.8 2003/03/14 15:31:57 mihad
// Entered the option to disable no response counter in wb master.
//
97,8 → 101,8
//`define WB_XILINX_DIST_RAM
`endif
`else
`define PCI_FIFO_RAM_ADDR_LENGTH 4 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
`define WB_FIFO_RAM_ADDR_LENGTH 7 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
// `define WB_ARTISAN_SDP
// `define PCI_ARTISAN_SDP
// `define PCI_VS_STP
140,11 → 144,11
// or GUEST implementation.
`ifdef HOST
`ifdef NO_CNF_IMAGE
`define PCI_IMAGE0
//`define PCI_IMAGE0
`endif
`endif
 
`define PCI_IMAGE2
//`define PCI_IMAGE2
//`define PCI_IMAGE3
//`define PCI_IMAGE4
//`define PCI_IMAGE5
183,7 → 187,7
// ( both GUEST and NO_CNF_IMAGE defined ), then WB image 0 is not implemented. User doesn't need to define image 0.
// WB Image 1 is always implemented and user doesnt need to specify its definition
// WB images' 2 through 5 implementation by defining each one.
`define WB_IMAGE2
//`define WB_IMAGE2
//`define WB_IMAGE3
//`define WB_IMAGE4
//`define WB_IMAGE5
191,7 → 195,7
// If this define is commented out, then address translation will not be implemented.
// addresses will pass through bridge unchanged, regardles of address translation enable bits.
// Address translation also slows down the decoding
`define ADDR_TRAN_IMPL
//`define ADDR_TRAN_IMPL
 
// decode speed for WISHBONE definition - initial cycle on WISHBONE bus will take 1 WS for FAST, 2 WSs for MEDIUM and 3 WSs for slow.
// slower decode speed can be used, to provide enough time for address to be decoded.
200,7 → 204,7
//`define WB_DECODE_SLOW
 
// Base address for Configuration space access from WB bus. This value cannot be changed during runtime
`define WB_CONFIGURATION_BASE 20'hF300_0
`define WB_CONFIGURATION_BASE 20'h0000_0
 
// Turn registered WISHBONE slave outputs on or off
// all outputs from WB Slave state machine are registered, if this is defined - WB bus outputs as well as
227,7 → 231,7
// Turn registered WISHBONE master outputs on or off
// all outputs from WB Master state machine are registered, if this is defined - WB bus outputs as well as
// outputs to internals of the core.
`define REGISTER_WBM_OUTPUTS
//`define REGISTER_WBM_OUTPUTS
 
// MAX Retry counter value for WISHBONE Master state-machine
// This value is 8-bit because of 8-bit retry counter !!!
236,3 → 240,10
// define the macro below to disable internal retry generation in the wishbone master interface
// used when wb master accesses extremly slow devices.
//`define PCI_WBM_NO_RESPONSE_CNT_DISABLE
 
`define PCI_WB_REV_B3
//`define PCI_WBS_B3_RTY_DISABLE
 
`ifdef GUEST
//`define PCI_CPCI_HS_IMPLEMENT
`endif
/trunk/apps/test/rtl/verilog/pci_test_top_2clks.v
1,3 → 1,5
`include "pci_user_constants.v"
 
module pci_test_top
(
pci_clk_pad_i,
116,6 → 118,9
wbm_test_wbs_pci_we,
wbs_pci_wbm_test_ack ;
 
wire [ 2: 0] wbm_test_wbs_pci_cti ;
wire [ 1: 0] wbm_test_wbs_pci_bte ;
 
wire [31:0] wbm_test_wbs_pci_adr,
wbm_test_wbs_pci_dat,
wbs_pci_wbm_test_dat ;
125,10 → 130,12
// wires for test slave to pci master connections
wire wbm_pci_wbs_test_cyc,
wbm_pci_wbs_test_stb,
wbm_pci_wbs_test_cab,
wbm_pci_wbs_test_we,
wbs_test_wbm_pci_ack ;
 
wire [ 2: 0] wbm_pci_wbs_test_cti ;
wire [ 1: 0] wbm_pci_wbs_test_bte ;
 
wire [31:0] wbm_pci_wbs_test_adr,
wbm_pci_wbs_test_dat,
wbs_test_wbm_pci_dat ;
242,7 → 249,13
 
.wbm_cyc_o (wbm_test_wbs_pci_cyc),
.wbm_stb_o (wbm_test_wbs_pci_stb),
 
`ifdef PCI_WB_REV_B3
.wbm_cti_o (wbm_test_wbs_pci_cti),
.wbm_bte_o (wbm_test_wbs_pci_bte),
`else
.wbm_cab_o (wbm_test_wbs_pci_cab),
`endif
.wbm_we_o (wbm_test_wbs_pci_we),
.wbm_adr_o (wbm_test_wbs_pci_adr),
.wbm_sel_o (wbm_test_wbs_pci_sel),
254,7 → 267,8
 
.wbs_cyc_i (test_wbs_cyc),
.wbs_stb_i (wbm_pci_wbs_test_stb),
.wbs_cab_i (wbm_pci_wbs_test_cab),
.wbs_cti_i (wbm_pci_wbs_test_cti),
.wbs_bte_i (wbm_pci_wbs_test_bte),
.wbs_we_i (wbm_pci_wbs_test_we),
.wbs_adr_i (wbm_pci_wbs_test_adr),
.wbs_sel_i (wbm_pci_wbs_test_sel),
427,7 → 441,13
.wbs_cyc_i(pci_wbs_cyc),
.wbs_stb_i(wbm_test_wbs_pci_stb),
.wbs_we_i (wbm_test_wbs_pci_we),
 
`ifdef PCI_WB_REV_B3
.wbs_cti_i (wbm_test_wbs_pci_cti),
.wbs_bte_i (wbm_test_wbs_pci_bte),
`else
.wbs_cab_i(wbm_test_wbs_pci_cab),
`endif
.wbs_ack_o(wbs_pci_wbm_test_ack),
.wbs_rty_o(),
.wbs_err_o(),
440,7 → 460,8
.wbm_cyc_o(wbm_pci_wbs_test_cyc),
.wbm_stb_o(wbm_pci_wbs_test_stb),
.wbm_we_o (wbm_pci_wbs_test_we),
.wbm_cab_o(wbm_pci_wbs_test_cab),
.wbm_cti_o(wbm_pci_wbs_test_cti),
.wbm_bte_o(wbm_pci_wbs_test_bte),
.wbm_ack_i(wbs_test_wbm_pci_ack),
.wbm_rty_i(1'b0),
.wbm_err_i(1'b0),
506,10 → 527,10
.pci_serr_o (pci_serr_o),
.pci_serr_oe_o (pci_serr_oe),
 
// debug
.trdy_reg_o (pci_trdy_reg),
.irdy_o (pci_irdy_out),
.irdy_en_o (pci_irdy_en),
.pci_ad_bckp_o (pci_ad_bckp)
.trdy_reg_o (pci_trdy_reg),
.irdy_o (pci_irdy_out),
.irdy_en_o (pci_irdy_en),
.pci_ad_bckp_o (pci_ad_bckp)
);
 
endmodule // pci_test_top
/trunk/apps/test/syn/synplify/pci_test_top_2clks.sdc
1,7 → 1,7
# Synplicity, Inc. constraint file
# /shared/projects/pci/mihad/pci/apps/test/syn/synplify/pci_test_top_2clks.sdc
# Written on Mon Apr 28 09:08:50 2003
# by Amplify, Amplify 3.1 Scope Editor
# /shared/projects/pci/mihad/pci_new_bist/apps/test/syn/synplify/pci_test_top_2clks.sdc
# Written on Tue Dec 16 13:13:13 2003
# by Synplify Pro, 7.3.4 Scope Editor
 
#
# Clocks
10,98 → 10,102
define_clock -name {i_bufg_wb_clk} -freq 50.000 -clockgroup clk_clkgrp
 
#
# Clock to Clock
#
 
#
# Inputs/Outputs
#
define_input_delay {pci_devsel_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
define_input_delay {pci_trdy_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
define_input_delay {pci_stop_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
define_input_delay {pci_idsel_pad_i} 23.00 -route 2.00 -ref pci_clk_pad_i:r
define_input_delay {pci_frame_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
define_input_delay {pci_irdy_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
define_input_delay {pci_gnt_pad_i} 20.00 -route 2.00 -ref pci_clk_pad_i:r
define_input_delay {pci_par_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
define_input_delay {pci_perr_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad0_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad1_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad2_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad3_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad4_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad5_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad6_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad7_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad8_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad9_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad10_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad11_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad12_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad13_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad14_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad15_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad16_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad17_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad18_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad19_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad20_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad21_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad22_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad23_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad24_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad25_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad26_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad27_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad28_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad29_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad30_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_ad31_pad_io} 23.00 -ref pci_clk_pad_i:r
define_input_delay {pci_cbe0_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
define_input_delay {pci_cbe1_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
define_input_delay {pci_cbe2_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
define_input_delay {pci_cbe3_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad0_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad1_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad2_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad3_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad4_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad5_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad6_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad7_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad8_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad9_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad10_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad11_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad12_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad13_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad14_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad15_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad16_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad17_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad18_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad19_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad20_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad21_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad22_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad23_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad24_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad25_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad26_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad27_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad28_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad29_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad30_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_ad31_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_cbe0_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_cbe1_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_cbe2_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_cbe3_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_devsel_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_trdy_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_stop_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_frame_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_irdy_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_req_pad_o} 18.00 -ref pci_clk_pad_i:r
define_output_delay {pci_par_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_perr_pad_io} 19.00 -ref pci_clk_pad_i:r
define_output_delay {pci_serr_pad_o} 19.00 -ref pci_clk_pad_i:r
define_input_delay {pci_devsel_pad_io} 23.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_trdy_pad_io} 23.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_stop_pad_io} 23.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_idsel_pad_i} 23.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_frame_pad_io} 23.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_irdy_pad_io} 23.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_gnt_pad_i} 20.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_par_pad_io} 23.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_perr_pad_io} 23.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad0_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad1_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad2_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad3_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad4_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad5_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad6_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad7_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad8_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad9_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad10_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad11_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad12_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad13_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad14_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad15_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad16_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad17_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad18_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad19_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad20_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad21_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad22_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad23_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad24_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad25_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad26_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad27_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad28_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad29_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad30_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_ad31_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_cbe0_pad_io} 23.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_cbe1_pad_io} 23.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_cbe2_pad_io} 23.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r}
define_input_delay {pci_cbe3_pad_io} 23.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad0_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad1_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad2_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad3_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad4_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad5_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad6_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad7_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad8_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad9_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad10_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad11_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad12_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad13_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad14_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad15_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad16_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad17_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad18_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad19_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad20_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad21_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad22_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad23_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad24_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad25_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad26_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad27_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad28_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad29_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad30_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_ad31_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_cbe0_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_cbe1_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_cbe2_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_cbe3_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_devsel_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_trdy_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_stop_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_frame_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_irdy_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_req_pad_o} 18.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_par_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_perr_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
define_output_delay {pci_serr_pad_o} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r}
 
#
# Registers
117,6 → 121,10
#
 
#
# Delay Path
#
 
#
# Attributes
#
define_attribute {pci_clk_pad_i} xc_loc {P185}
170,25 → 178,25
define_attribute {pci_ad0_pad_io} xc_loc {P67}
define_attribute {clk_pad_i} xc_loc {P182}
define_global_attribute syn_useioff {1}
define_attribute {v:work.pci_cbe_en_crit} syn_hier {hard}
define_attribute {v:work.pci_frame_crit} syn_hier {hard}
define_attribute {v:work.pci_frame_en_crit} syn_hier {hard}
define_attribute {v:work.pci_frame_load_crit} syn_hier {hard}
define_attribute {v:work.pci_irdy_out_crit} syn_hier {hard}
define_attribute {v:work.pci_mas_ad_en_crit} syn_hier {hard}
define_attribute {v:work.pci_mas_ad_load_crit} syn_hier {hard}
define_attribute {v:work.pci_mas_ch_state_crit} syn_hier {hard}
define_attribute {v:work.pci_par_crit} syn_hier {hard}
define_attribute {v:work.pci_io_mux_ad_en_crit} syn_hier {hard}
define_attribute {v:work.pci_io_mux_ad_load_crit} syn_hier {hard}
define_attribute {v:work.pci_target32_clk_en} syn_hier {hard}
define_attribute {v:work.pci_target32_devs_crit} syn_hier {hard}
define_attribute {v:work.pci_target32_stop_crit} syn_hier {hard}
define_attribute {v:work.pci_target32_trdy_crit} syn_hier {hard}
define_attribute {v:work.pci_perr_crit} syn_hier {hard}
define_attribute {v:work.pci_perr_en_crit} syn_hier {hard}
define_attribute {v:work.pci_serr_crit} syn_hier {hard}
define_attribute {v:work.pci_serr_en_crit} syn_hier {hard}
define_attribute -disable {v:work.pci_cbe_en_crit} syn_hier {hard}
define_attribute -disable {v:work.pci_frame_crit} syn_hier {hard}
define_attribute -disable {v:work.pci_frame_en_crit} syn_hier {hard}
define_attribute -disable {v:work.pci_frame_load_crit} syn_hier {hard}
define_attribute -disable {v:work.pci_irdy_out_crit} syn_hier {hard}
define_attribute -disable {v:work.pci_mas_ad_en_crit} syn_hier {hard}
define_attribute -disable {v:work.pci_mas_ad_load_crit} syn_hier {hard}
define_attribute -disable {v:work.pci_mas_ch_state_crit} syn_hier {hard}
define_attribute -disable {v:work.pci_par_crit} syn_hier {hard}
define_attribute -disable {v:work.pci_io_mux_ad_en_crit} syn_hier {hard}
define_attribute -disable {v:work.pci_io_mux_ad_load_crit} syn_hier {hard}
define_attribute -disable {v:work.pci_target32_clk_en} syn_hier {hard}
define_attribute -disable {v:work.pci_target32_devs_crit} syn_hier {hard}
define_attribute -disable {v:work.pci_target32_stop_crit} syn_hier {hard}
define_attribute -disable {v:work.pci_target32_trdy_crit} syn_hier {hard}
define_attribute -disable {v:work.pci_perr_crit} syn_hier {hard}
define_attribute -disable {v:work.pci_perr_en_crit} syn_hier {hard}
define_attribute -disable {v:work.pci_serr_crit} syn_hier {hard}
define_attribute -disable {v:work.pci_serr_en_crit} syn_hier {hard}
define_attribute {pci_gnt_pad_i} xc_padtype {IBUF_PCI33_5}
define_attribute {pci_req_pad_o} xc_padtype {OBUFT_PCI33_5}
define_attribute {pci_ad31_pad_io} xc_padtype {IOBUF_PCI33_5}
236,19 → 244,19
define_attribute {pci_ad2_pad_io} xc_padtype {IOBUF_PCI33_5}
define_attribute {pci_ad1_pad_io} xc_padtype {IOBUF_PCI33_5}
define_attribute {pci_ad0_pad_io} xc_padtype {IOBUF_PCI33_5}
define_attribute {v:work.synchronizer_flop_1_0} syn_hier {hard}
define_attribute {v:work.synchronizer_flop_3_0} syn_hier {hard}
define_attribute {v:work.synchronizer_flop_4_0} syn_hier {hard}
define_attribute {v:work.synchronizer_flop_4_1} syn_hier {hard}
define_attribute {v:work.synchronizer_flop_4_3} syn_hier {hard}
define_attribute {v:work.synchronizer_flop_6_0} syn_hier {hard}
define_attribute {v:work.synchronizer_flop_7_0} syn_hier {hard}
define_attribute {v:work.synchronizer_flop_7_3} syn_hier {hard}
define_attribute -disable {v:work.synchronizer_flop_1_0} syn_hier {hard}
define_attribute -disable {v:work.synchronizer_flop_3_0} syn_hier {hard}
define_attribute -disable {v:work.synchronizer_flop_4_0} syn_hier {hard}
define_attribute -disable {v:work.synchronizer_flop_4_1} syn_hier {hard}
define_attribute -disable {v:work.synchronizer_flop_4_3} syn_hier {hard}
define_attribute -disable {v:work.synchronizer_flop_6_0} syn_hier {hard}
define_attribute -disable {v:work.synchronizer_flop_7_0} syn_hier {hard}
define_attribute -disable {v:work.synchronizer_flop_7_3} syn_hier {hard}
 
#
# Other Constraints
# Compile Points
#
 
#
# Order of waveforms
# Other Constraints
#
/trunk/apps/test/syn/synplify/pci_test_top.prj
1,12 → 1,11
#-- Synplicity, Inc.
#-- Version 7.2
#-- Project file /shared/projects/pci/mihad/pci/apps/test/syn/synplify/pci_test_top.prj
#-- Written on Tue Jul 29 12:49:45 2003
#-- Version 7.3.4
#-- Project file /shared/projects/pci/mihad/pci_new_bist/apps/test/syn/synplify/pci_test_top.prj
#-- Written on Tue Dec 16 12:47:51 2003
 
 
#add_file options
add_file -verilog "$LIB/xilinx/virtex.v"
add_file -verilog "../../../../rtl/verilog/meta_flop.v"
add_file -verilog "../../../../rtl/verilog/pci_async_reset_flop.v"
add_file -verilog "../../rtl/verilog/pci_bridge32.v"
add_file -verilog "../../../../rtl/verilog/pci_cbe_en_crit.v"
59,10 → 58,11
add_file -verilog "../../../../rtl/verilog/pci_wb_tpram.v"
add_file -verilog "../../../../rtl/verilog/pci_wbw_fifo_control.v"
add_file -verilog "../../../../rtl/verilog/pci_wbw_wbr_fifos.v"
add_file -verilog "../../../../rtl/verilog/synchronizer_flop.v"
add_file -verilog "../../../../rtl/verilog/pci_synchronizer_flop.v"
add_file -constraint "pci_test_top_2clks.sdc"
add_file -verilog "../../../../rtl/verilog/pci_wbs_wbb3_2_wbb2.v"
add_file -verilog "../../rtl/verilog/test.v"
add_file -verilog "../../rtl/verilog/pci_test_top_2clks.v"
add_file -constraint "pci_test_top_2clks.sdc"
 
 
#implementation: "rev_1"
70,9 → 70,9
 
#device options
set_option -technology SPARTAN2
set_option -part XC2S150
set_option -part XC2S200
set_option -package PQ208
set_option -speed_grade -5
set_option -speed_grade -6
 
#compilation/mapping options
set_option -default_enum_encoding default
85,6 → 85,7
set_option -fanout_limit 16
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -fixgatedclocks 0
set_option -retiming 0
set_option -modular 0
set_option -update_models_cp 0
102,7 → 103,8
 
#implementation attributes
set_option -vlog_std v2001
set_option -compiler_compatible 0
 
#implementation attributes
set_option -random_floorplan 0
set_option -popfeed 1
set_option -constprop 1
/trunk/apps/test/syn/synplify/pci_test_top.ucf
2,27 → 2,4
INST "i_clkdll" LOC = DLL0 ;
INST "i_bufg_clk0" LOC = GCLKBUF0 ;
INST "i_bufg_wb_clk" LOC = GCLKBUF1 ;
NET "pci_clk_pad_i" TNM_NET = "pci_clk_pad_i";
#INST "i_pci_bridge32/wishbone_slave_unit/fifos/i_synchronizer_reg_inGreyCount/sync_data_out[*]" TNM = "wbw_sync_to_pci_clk";
#INST "i_pci_bridge32/wishbone_slave_unit/fifos/wbw_fifo_ctrl/i_synchronizer_reg_wgrey_next/sync_data_out[*]" TNM = "wbw_sync_to_pci_clk";
#INST "i_pci_bridge32/wishbone_slave_unit/fifos/pci_clk_inGreyCount[*]" TNM = "wbw_pci_clk_grey_addr_dest";
#INST "i_pci_bridge32/wishbone_slave_unit/fifos/wbw_fifo_ctrl/rclk_wgrey_next[*]" TNM = "wbw_pci_clk_grey_addr_dest";
#INST "i_pci_bridge32/wishbone_slave_unit/fifos/wbw_fifo_ctrl/i_synchronizer_reg_rgrey_addr/sync_data_out[*]" TNM = "wbw_sync_to_wb_clk";
#INST "i_pci_bridge32/wishbone_slave_unit/fifos/wbw_fifo_ctrl/i_synchronizer_reg_rgrey_minus1/sync_data_out[*]" TNM = "wbw_sync_to_wb_clk";
#INST "i_pci_bridge32/wishbone_slave_unit/fifos/wbw_fifo_ctrl/wclk_rgrey_addr[*]" TNM = "wbw_wb_clk_grey_addr_dest";
#INST "i_pci_bridge32/wishbone_slave_unit/fifos/wbw_fifo_ctrl/wclk_rgrey_minus1[*]" TNM = "wbw_wb_clk_grey_addr_dest";
#
#TIMESPEC "TS_wbw_wb2pci_sync" = FROM "wbw_sync_to_pci_clk" TO "wbw_pci_clk_grey_addr_dest" 4 ns;
#TIMESPEC "TS_wbw_pci2wb_sync" = FROM "wbw_sync_to_wb_clk" TO "wbw_wb_clk_grey_addr_dest" 4 ns;
 
#INST "i_pci_bridge32/pci_target_unit/fifos/i_synchronizer_reg_inGreyCount/sync_data_out[*]" TNM = "pciw_sync_to_wb_clk" ;
#INST "i_pci_bridge32/pci_target_unit/fifos/pciw_fifo_ctrl/i_synchronizer_reg_wgrey_addr/sync_data_out[*]" TNM = "pciw_sync_to_wb_clk" ;
#INST "i_pci_bridge32/pci_target_unit/fifos/pciw_fifo_ctrl/rclk_wgrey_addr[*]" TNM = "pciw_wb_clk_grey_addr_dest" ;
#INST "i_pci_bridge32/pci_target_unit/fifos/wb_clk_inGreyCount[*]" TNM = "pciw_wb_clk_grey_addr_dest" ;
#INST "i_pci_bridge32/pci_target_unit/fifos/pciw_fifo_ctrl/i_synchronizer_reg_rgrey_addr/sync_data_out[*]" TNM = "pciw_sync_to_pci_clk" ;
#INST "i_pci_bridge32/pci_target_unit/fifos/pciw_fifo_ctrl/i_synchronizer_reg_rgrey_minus2/sync_data_out[*]" TNM = "pciw_sync_to_pci_clk" ;
#INST "i_pci_bridge32/pci_target_unit/fifos/pciw_fifo_ctrl/wclk_rgrey_addr[*]" TNM = "pciw_pci_clk_grey_addr_dest" ;
#INST "i_pci_bridge32/pci_target_unit/fifos/pciw_fifo_ctrl/wclk_rgrey_minus2[*]" TNM = "pciw_pci_clk_grey_addr_dest" ;
#
#TIMESPEC "TS_pciw_wb2pci_sync" = FROM "pciw_sync_to_pci_clk" TO "pciw_pci_clk_grey_addr_dest" 4 ns;
#TIMESPEC "TS_pciw_pci2wb_sync" = FROM "pciw_sync_to_wb_clk" TO "pciw_wb_clk_grey_addr_dest" 4 ns;
NET "pci_clk_pad_i" TNM_NET = "pci_clk_pad_i";
/trunk/doc/pci_specification.doc Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/doc/pci_specification.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/sim/rtl_sim/log/get_log_err_war
1,19 → 1,19
clear
echo "***************** Extracted warnings from ncvlog logs ****************"
echo
cat ncvlog*.log | grep -B 3 *W
cat *ncvlog*.log | grep -B 3 *W
echo
 
echo "***************** Extracted errors from ncvlog logs ******************"
echo
cat ncvlog*.log | grep -B 3 *E
cat *ncvlog*.log | grep -B 3 *E
echo
 
echo "***************** Extracted warnings from ncelab logs ****************"
echo
cat ncelab*.log | grep -B 3 *W
cat *ncelab*.log | grep -B 3 *W
echo
 
echo "***************** Extracted errors from ncelab logs ******************"
cat ncelab*.log | grep -B 3 *E
cat *ncelab*.log | grep -B 3 *E
echo
/trunk/sim/rtl_sim/run/ncelab.args
1,6 → 1,6
//
// ncelab.args: Arguments passed to the NC-Verilog elaborator.
// Created by ncprep on Tue Jan 29 18:18:34 2002
// Created by ncprep on Fri Dec 19 08:07:37 2003
 
// Turn on informative messages.
-MESSAGES
10,33 → 10,5
// -LOGFILE ncelab.log
 
// Top level module(s)
CBE_EN_CRIT
PCI_TPRAM
CONF_CYC_ADDR_DEC
FRAME_CRIT
PCI_TARGET32_CLK_EN
FRAME_EN_CRIT
PAR_CRIT
FRAME_LOAD_CRIT
PCI_TARGET32_DEVS_CRIT
PERR_CRIT
PCI_DECODER
PERR_EN_CRIT
DECODER
SERR_CRIT
IRDY_OUT_CRIT
PCI_IO_MUX
PCI_IO_MUX_AD_EN_CRIT
PCI_IO_MUX_AD_LOAD_CRIT
SERR_EN_CRIT
MAS_AD_EN_CRIT
MAS_AD_LOAD_CRIT
PCI_TARGET32_STOP_CRIT
synchronizer_flop
MAS_CH_STATE_CRIT
PCI_TARGET32_TRDY_CRIT
TOP
PCI_RST_INT
SYNC_MODULE
WB_TPRAM
pci_bridge32
 
/trunk/sim/rtl_sim/run/top_groups.do
116,8 → 116,8
define variable nofullpathfilenames
include bookmark with filenames
include scope history without filenames
define waveform window listpane 5.78
define waveform window namepane 13.93
define waveform window listpane 5.36
define waveform window namepane 14.00
define multivalueindication
define pattern curpos dot
define pattern cursor1 dot
212,7 → 212,13
SYSTEM.RTY_I \
SYSTEM.test_name[799:0]'a \
 
add group \
CPCI \
SYSTEM.LED \
SYSTEM.ENUM \
SYSTEM.ES \
 
 
deselect all
open window waveform 1 geometry 10 59 1368 926
zoom at 815149.757(0)ns 0.00214844 0.00000000
open window waveform 1 geometry 14 61 1268 912
zoom at 74657.632(0)ns 0.00214844 0.00000000
/trunk/sim/rtl_sim/run/run_pci_sim_regr.scr
117,7 → 117,6
endif
 
echo "-DEFINE HOST " >> ./defines.args
echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
echo "-DEFINE PCI_DECODE_MAX " >> ./defines.args
echo "-DEFINE WB_DECODE_MIN " >> ./defines.args
echo "-DEFINE PCI33 " >> ./defines.args
124,7 → 123,12
echo "-DEFINE WB_CLK10 " >> ./defines.args
echo "-DEFINE ACTIVE_LOW_OE " >> ./defines.args
echo "-DEFINE REGISTER_WBM_OUTPUTS" >> ./defines.args
echo "-DEFINE REGISTER_WBS_OUTPUTS" >> ./defines.args
echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
 
if ($arg_wb_b3 == 0) then
echo "-DEFINE REGISTER_WBS_OUTPUTS" >> ./defines.args
endif
 
echo "-DEFINE ADDR_TRAN_IMPL " >> ./defines.args
echo "-DEFINE PCI_IMAGE0 " >> ./defines.args
echo "-DEFINE PCI_IMAGE2 " >> ./defines.args
159,7 → 163,6
endif
 
echo "-DEFINE HOST " >> ./defines.args
echo "-DEFINE WB_DECODE_MEDIUM " >> ./defines.args
echo "-DEFINE PCI_DECODE_MED " >> ./defines.args
echo "-DEFINE WB_DECODE_MED " >> ./defines.args
echo "-DEFINE PCI33 " >> ./defines.args
166,7 → 169,14
echo "-DEFINE WB_CLK66 " >> ./defines.args
echo "-DEFINE ACTIVE_LOW_OE " >> ./defines.args
echo "-DEFINE REGISTER_WBM_OUTPUTS" >> ./defines.args
echo "-DEFINE REGISTER_WBS_OUTPUTS" >> ./defines.args
 
if ($arg_wb_b3 == 0) then
echo "-DEFINE WB_DECODE_MEDIUM " >> ./defines.args
echo "-DEFINE REGISTER_WBS_OUTPUTS" >> ./defines.args
else
echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
endif
 
echo "-DEFINE ADDR_TRAN_IMPL " >> ./defines.args
echo "-DEFINE PCI_IMAGE0 " >> ./defines.args
echo "-DEFINE PCI_IMAGE2 " >> ./defines.args
188,7 → 198,6
 
echo "-DEFINE HOST " >> ./defines.args
echo "-DEFINE REGR_FIFO_LARGE_GENERIC" >> ./defines.args
echo "-DEFINE WB_DECODE_SLOW " >> ./defines.args
echo "-DEFINE PCI_DECODE_MIN " >> ./defines.args
echo "-DEFINE WB_DECODE_MAX " >> ./defines.args
echo "-DEFINE PCI66 " >> ./defines.args
195,9 → 204,15
echo "-DEFINE WB_CLK66 " >> ./defines.args
echo "-DEFINE ACTIVE_LOW_OE " >> ./defines.args
echo "-DEFINE REGISTER_WBM_OUTPUTS " >> ./defines.args
echo "-DEFINE REGISTER_WBS_OUTPUTS " >> ./defines.args
echo "-DEFINE WB_IMAGE5 " >> ./defines.args
 
if ($arg_wb_b3 == 0) then
echo "-DEFINE WB_DECODE_SLOW " >> ./defines.args
echo "-DEFINE REGISTER_WBS_OUTPUTS" >> ./defines.args
else
echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
endif
 
endif
 
if ($iter == 4) then
210,7 → 225,6
 
echo "-DEFINE GUEST " >> ./defines.args
echo "-DEFINE REGR_FIFO_SMALL_GENERIC" >> ./defines.args
echo "-DEFINE WB_DECODE_SLOW " >> ./defines.args
echo "-DEFINE PCI_DECODE_MED " >> ./defines.args
echo "-DEFINE WB_DECODE_MIN " >> ./defines.args
echo "-DEFINE PCI66 " >> ./defines.args
217,10 → 231,17
echo "-DEFINE WB_CLK220 " >> ./defines.args
echo "-DEFINE ACTIVE_LOW_OE " >> ./defines.args
echo "-DEFINE REGISTER_WBM_OUTPUTS " >> ./defines.args
echo "-DEFINE REGISTER_WBS_OUTPUTS " >> ./defines.args
echo "-DEFINE PCI_IMAGE0 " >> ./defines.args
echo "-DEFINE PCI_IMAGE5 " >> ./defines.args
echo "-DEFINE WB_IMAGE4 " >> ./defines.args
 
if ($arg_wb_b3 == 0) then
echo "-DEFINE WB_DECODE_SLOW " >> ./defines.args
echo "-DEFINE REGISTER_WBS_OUTPUTS" >> ./defines.args
else
echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
endif
 
endif
 
if ($iter == 5) then
246,7 → 267,6
endif
 
echo "-DEFINE GUEST " >> ./defines.args
echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
echo "-DEFINE PCI_DECODE_MIN " >> ./defines.args
echo "-DEFINE WB_DECODE_MAX " >> ./defines.args
echo "-DEFINE PCI33 " >> ./defines.args
253,7 → 273,6
echo "-DEFINE WB_CLK220 " >> ./defines.args
echo "-DEFINE ACTIVE_LOW_OE " >> ./defines.args
echo "-DEFINE REGISTER_WBM_OUTPUTS " >> ./defines.args
echo "-DEFINE REGISTER_WBS_OUTPUTS " >> ./defines.args
echo "-DEFINE ADDR_TRAN_IMPL " >> ./defines.args
echo "-DEFINE PCI_IMAGE0 " >> ./defines.args
echo "-DEFINE PCI_IMAGE2 " >> ./defines.args
260,6 → 279,14
echo "-DEFINE WB_IMAGE2 " >> ./defines.args
echo "-DEFINE WB_IMAGE3 " >> ./defines.args
echo "-DEFINE WB_IMAGE4 " >> ./defines.args
 
if ($arg_wb_b3 == 0) then
echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
echo "-DEFINE REGISTER_WBS_OUTPUTS" >> ./defines.args
else
echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
endif
 
endif
 
if ($iter == 6) then
272,7 → 299,6
 
echo "-DEFINE GUEST " >> ./defines.args
echo "-DEFINE REGR_FIFO_LARGE_GENERIC" >> ./defines.args
echo "-DEFINE WB_DECODE_MEDIUM " >> ./defines.args
echo "-DEFINE PCI_DECODE_MAX " >> ./defines.args
echo "-DEFINE WB_DECODE_MED " >> ./defines.args
echo "-DEFINE PCI66 " >> ./defines.args
279,8 → 305,15
echo "-DEFINE WB_CLK10 " >> ./defines.args
echo "-DEFINE ACTIVE_LOW_OE " >> ./defines.args
echo "-DEFINE REGISTER_WBM_OUTPUTS " >> ./defines.args
echo "-DEFINE REGISTER_WBS_OUTPUTS " >> ./defines.args
echo "-DEFINE ADDR_TRAN_IMPL " >> ./defines.args
 
if ($arg_wb_b3 == 0) then
echo "-DEFINE WB_DECODE_MEDIUM " >> ./defines.args
echo "-DEFINE REGISTER_WBS_OUTPUTS" >> ./defines.args
else
echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
endif
 
endif
 
if ($iter == 7) then
305,7 → 338,6
endif
 
echo "-DEFINE HOST " >> ./defines.args
echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
echo "-DEFINE PCI_DECODE_MAX " >> ./defines.args
echo "-DEFINE WB_DECODE_MIN " >> ./defines.args
echo "-DEFINE PCI66 " >> ./defines.args
315,6 → 347,14
echo "-DEFINE NO_CNF_IMAGE " >> ./defines.args
echo "-DEFINE PCI_IMAGE0 " >> ./defines.args
echo "-DEFINE PCI_IMAGE4 " >> ./defines.args
 
if ($arg_wb_b3 == 0) then
echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
# echo "-DEFINE REGISTER_WBS_OUTPUTS" >> ./defines.args
else
echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
endif
 
endif
 
if ($iter == 8) then
328,7 → 368,6
 
echo "-DEFINE HOST " >> ./defines.args
echo "-DEFINE REGR_FIFO_MEDIUM_GENERIC" >> ./defines.args
echo "-DEFINE WB_DECODE_MEDIUM " >> ./defines.args
echo "-DEFINE PCI_DECODE_MED " >> ./defines.args
echo "-DEFINE WB_DECODE_MED " >> ./defines.args
echo "-DEFINE PCI66 " >> ./defines.args
345,6 → 384,14
echo "-DEFINE WB_IMAGE3 " >> ./defines.args
echo "-DEFINE WB_IMAGE4 " >> ./defines.args
echo "-DEFINE WB_IMAGE5 " >> ./defines.args
 
if ($arg_wb_b3 == 0) then
echo "-DEFINE WB_DECODE_MEDIUM " >> ./defines.args
# echo "-DEFINE REGISTER_WBS_OUTPUTS" >> ./defines.args
else
echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
endif
 
endif
 
if ($iter == 9) then
357,7 → 404,6
 
echo "-DEFINE HOST " >> ./defines.args
echo "-DEFINE REGR_FIFO_LARGE_GENERIC" >> ./defines.args
echo "-DEFINE WB_DECODE_SLOW " >> ./defines.args
echo "-DEFINE PCI_DECODE_MIN " >> ./defines.args
echo "-DEFINE WB_DECODE_MAX " >> ./defines.args
echo "-DEFINE PCI33 " >> ./defines.args
367,6 → 413,14
echo "-DEFINE WB_CNF_BASE_ZERO " >> ./defines.args
echo "-DEFINE NO_CNF_IMAGE " >> ./defines.args
echo "-DEFINE WB_IMAGE3 " >> ./defines.args
 
if ($arg_wb_b3 == 0) then
echo "-DEFINE WB_DECODE_SLOW " >> ./defines.args
# echo "-DEFINE REGISTER_WBS_OUTPUTS" >> ./defines.args
else
echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
endif
 
endif
 
if ($iter == 10) then
379,7 → 433,6
echo "-DEFINE GUEST " >> ./defines.args
echo "-DEFINE REGR_FIFO_SMALL_GENERIC" >> ./defines.args
echo "-DEFINE WB_DECODE_SLOW " >> ./defines.args
echo "-DEFINE PCI_DECODE_MED " >> ./defines.args
echo "-DEFINE WB_DECODE_MIN " >> ./defines.args
echo "-DEFINE PCI33 " >> ./defines.args
390,6 → 443,14
echo "-DEFINE NO_CNF_IMAGE " >> ./defines.args
echo "-DEFINE PCI_IMAGE0 " >> ./defines.args
echo "-DEFINE PCI_IMAGE3 " >> ./defines.args
 
if ($arg_wb_b3 == 0) then
echo "-DEFINE WB_DECODE_SLOW " >> ./defines.args
# echo "-DEFINE REGISTER_WBS_OUTPUTS" >> ./defines.args
else
echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
endif
 
endif
 
if ($iter == 11) then
419,7 → 480,6
endif
 
echo "-DEFINE GUEST " >> ./defines.args
echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
echo "-DEFINE PCI_DECODE_MIN " >> ./defines.args
echo "-DEFINE WB_DECODE_MAX " >> ./defines.args
echo "-DEFINE PCI66 " >> ./defines.args
433,6 → 493,14
echo "-DEFINE PCI_IMAGE4 " >> ./defines.args
echo "-DEFINE PCI_IMAGE5 " >> ./defines.args
echo "-DEFINE WB_IMAGE2 " >> ./defines.args
 
if ($arg_wb_b3 == 0) then
echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
# echo "-DEFINE REGISTER_WBS_OUTPUTS" >> ./defines.args
else
echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
endif
 
endif
 
if ($iter == 12) then
445,7 → 513,6
echo "-DEFINE GUEST " >> ./defines.args
echo "-DEFINE REGR_FIFO_LARGE_GENERIC" >> ./defines.args
echo "-DEFINE WB_DECODE_MEDIUM " >> ./defines.args
echo "-DEFINE PCI_DECODE_MAX " >> ./defines.args
echo "-DEFINE WB_DECODE_MED " >> ./defines.args
echo "-DEFINE PCI33 " >> ./defines.args
458,6 → 525,14
echo "-DEFINE WB_IMAGE4 " >> ./defines.args
echo "-DEFINE WB_IMAGE5 " >> ./defines.args
 
if ($arg_wb_b3 == 0) then
echo "-DEFINE WB_DECODE_MEDIUM " >> ./defines.args
# echo "-DEFINE REGISTER_WBS_OUTPUTS" >> ./defines.args
else
echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
endif
 
 
endif
 
if ($iter == 13) then
483,7 → 558,6
endif
 
echo "-DEFINE GUEST " >> ./defines.args
echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
echo "-DEFINE PCI_DECODE_MAX " >> ./defines.args
echo "-DEFINE WB_DECODE_MED " >> ./defines.args
echo "-DEFINE PCI66 " >> ./defines.args
493,6 → 567,14
echo "-DEFINE NO_CNF_IMAGE " >> ./defines.args
echo "-DEFINE WB_CLOCK_FOLLOWS_PCI_CLOCK=2" >> ./defines.args
 
if ($arg_wb_b3 == 0) then
echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
# echo "-DEFINE REGISTER_WBS_OUTPUTS" >> ./defines.args
else
echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
endif
 
 
endif
 
if ($iter == 14) then
510,7 → 592,6
echo "-DEFINE REGR_FIFO_SMALL_GENERIC" >> ./defines.args
 
echo "-DEFINE GUEST " >> ./defines.args
echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
echo "-DEFINE PCI_DECODE_MAX " >> ./defines.args
echo "-DEFINE WB_DECODE_MED " >> ./defines.args
echo "-DEFINE PCI66 " >> ./defines.args
520,6 → 601,14
echo "-DEFINE NO_CNF_IMAGE " >> ./defines.args
echo "-DEFINE PCI_CLOCK_FOLLOWS_WB_CLOCK=2" >> ./defines.args
 
if ($arg_wb_b3 == 0) then
echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
# echo "-DEFINE REGISTER_WBS_OUTPUTS" >> ./defines.args
else
echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
endif
 
 
endif
 
if ($arg_dis_comp_exp_test) then
533,7 → 622,6
if ($arg_wbs_non_alligned) then
echo "-DEFINE PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS" >> ./defines.args
endif
 
endif
endif
 
556,6 → 644,9
if (($arg_regression == 1) && ($iter <= $all_iterations)) then
cat ./defines.args >> ./ncvlog.args
endif
 
echo '-DEFINE PCI_CPCI_SIM' >> ./ncvlog.args
 
# adding RTL and Sim files to .args file
cat ../bin/rtl_file_list.lst >> ./ncvlog.args
cat ../bin/sim_file_list.lst >> ./ncvlog.args
701,5 → 792,9
echo ""
echo "disable_completion_expired_tests : if you want to disable completion expiration testing during regression run, because these are time consuming tests"
echo ""
echo "wb_b3 : Run complete regression with WISHBONE Slave Unit's WB B3 to WB B2 cycle translation enabled"
echo ""
echo "wb_na : Run regression with WISHBONE Slave Unit's non alligned configuration accesses enabled"
echo ""
exit
 
/trunk/sim/rtl_sim/bin/hdl.var
1,9 → 1,2
#
# hdl.var: Defines variables used by the INCA tools.
# Created by ncprep on Sat Aug 4 10:51:23 2001
#
 
softinclude $CDS_INST_DIR/tools/inca/files/hdl.var
 
define LIB_MAP ( $LIB_MAP, + => worklib )
define VIEW_MAP ( $VIEW_MAP, .v => v)
define WORK worklib
include $CDS_INST_DIR/tools/inca/files/hdl.var

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