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URL https://opencores.org/ocsvn/plasma/plasma/trunk

Subversion Repositories plasma

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    from Rev 131 to Rev 132
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Rev 131 → Rev 132

/trunk/vhdl/tbench.vhd
18,7 → 18,7
 
architecture logic of tbench is
constant memory_type : string :=
"GENERIC";
"DEFAULT";
-- "ALTERA";
-- "XILINX";
 
/trunk/vhdl/shifter.vhd
15,7 → 15,7
use work.mlite_pack.all;
 
entity shifter is
generic(shifter_type : string := "GENERIC");
generic(shifter_type : string := "DEFAULT");
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
47,7 → 47,7
shift16R <= fills(31 downto 16) & shift8R(31 downto 16) when shift_amount(4) = '1' else shift8R;
 
-- synthesis translate_off
GENERIC_SHIFTER: if shifter_type = "GENERIC" generate
GENERIC_SHIFTER: if shifter_type = "DEFAULT" generate
-- synthesis translate_on
 
c_shift <= shift16L when shift_func = SHIFT_LEFT_UNSIGNED else
/trunk/vhdl/mlite_pack.vhd
302,8 → 302,8
end component;
 
component alu
generic(adder_type : string := "GENERIC";
alu_type : string := "GENERIC");
generic(adder_type : string := "DEFAULT";
alu_type : string := "DEFAULT");
port(a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in alu_function_type;
311,7 → 311,7
end component;
 
component shifter
generic( shifter_type : string := "GENERIC" );
generic( shifter_type : string := "DEFAULT" );
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
320,8 → 320,8
 
component mult
generic (
adder_type : string := "GENERIC";
mult_type : string := "GENERIC");
adder_type : string := "DEFAULT";
mult_type : string := "DEFAULT");
port (
clk : in std_logic;
reset_in : in std_logic;
363,8 → 363,8
 
component mlite_cpu
generic(memory_type : string := "ALTERA";
mult_type : string := "GENERIC";
shifter_type : string := "GENERIC";
mult_type : string := "DEFAULT";
shifter_type : string := "DEFAULT";
pipeline_stages : natural := 3);
port(clk : in std_logic;
reset_in : in std_logic;
379,7 → 379,7
end component;
 
component ram
generic(memory_type : string := "GENERIC");
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
mem_byte_sel : in std_logic_vector(3 downto 0);
mem_write : in std_logic;
400,7 → 400,7
end component; --uart
 
component plasma
generic(memory_type : string := "GENERIC";
generic(memory_type : string := "DEFAULT";
log_file : string := "UNUSED");
port(clk_in : in std_logic;
reset_in : in std_logic;
/trunk/vhdl/reg_bank.vhd
16,7 → 16,7
use work.mlite_pack.all;
 
entity reg_bank is
generic(memory_type : string := "GENERIC");
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
107,7 → 107,7
-- One tri-port RAM, two read-ports, one write-port
-- 32 registers 32-bits wide
tri_port_mem:
if memory_type = "GENERIC" generate
if memory_type = "DEFAULT" generate
ram_proc: process(clk, addr_a1, addr_a2, addr_b, reg_dest_new,
write_enable)
variable tri_port_ram : ram_type;
/trunk/vhdl/ram.vhd
21,7 → 21,7
use work.mlite_pack.all;
 
entity ram is
generic(memory_type : string := "GENERIC");
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
mem_byte_sel : in std_logic_vector(3 downto 0);
mem_write : in std_logic;
45,7 → 45,7
"0000";
 
generic_ram:
if memory_type = "GENERIC" generate
if memory_type = "DEFAULT" generate
ram_proc: process(clk, mem_byte_sel, mem_write,
mem_address, mem_data_w, mem_sel)
variable mem_size : natural := 2 ** ADDRESS_WIDTH;
/trunk/vhdl/mlite_cpu.vhd
74,11 → 74,11
use ieee.std_logic_unsigned.all;
 
entity mlite_cpu is
generic(memory_type : string := "GENERIC"; --DUAL_PORT_XILINX_XC4000XLA
adder_type : string := "GENERIC"; --AREA_OPTIMIZED
mult_type : string := "GENERIC"; --AREA_OPTIMIZED
shifter_type : string := "GENERIC"; --AREA_OPTIMIZED
alu_type : string := "GENERIC"; --AREA_OPTIMIZED
generic(memory_type : string := "DEFAULT"; --DUAL_PORT_XILINX_XC4000XLA
adder_type : string := "DEFAULT"; --AREA_OPTIMIZED
mult_type : string := "DEFAULT"; --AREA_OPTIMIZED
shifter_type : string := "DEFAULT"; --AREA_OPTIMIZED
alu_type : string := "DEFAULT"; --AREA_OPTIMIZED
pipeline_stages : natural := 3;
accurate_timing : boolean := true);
port(clk : in std_logic;
/trunk/vhdl/mult.vhd
41,8 → 41,8
use work.mlite_pack.all;
 
entity mult is
generic(adder_type : string := "GENERIC";
mult_type : string := "GENERIC");
generic(adder_type : string := "DEFAULT";
mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
80,7 → 80,7
begin
--sum = aa + bb
generic_adder: if adder_type = "GENERIC" generate
generic_adder: if adder_type = "DEFAULT" generate
sum <= (aa + bb) when do_mult_reg = '1' else
(aa - bb);
end generate; --generic_adder
113,7 → 113,7
ZERO;
 
 
GENERIC_MULT: if MULT_TYPE = "GENERIC" generate
GENERIC_MULT: if MULT_TYPE = "DEFAULT" generate
--multiplication/division unit
mult_proc: process(clk, reset_in, a, b, mult_func,

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