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openmsp430/trunk/doc/area_speed_analysis.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: openmsp430/trunk/doc/html/software_development_tools.html =================================================================== --- openmsp430/trunk/doc/html/software_development_tools.html (revision 134) +++ openmsp430/trunk/doc/html/software_development_tools.html (revision 135) @@ -1,250 +1,579 @@ - + + + + +

Table of content

+

-
• 1. Introduction
-
• 2. openmsp430-loader
-
• 3. openmsp430-minidebug
-
• 4. openmsp430-gdbproxy
-
• 5. MSPGCC(4) Toolchain -
  -
  • 5.1 Compiler options
  -
  • 5.2 MCU selection
  -
  • 5.3 Custom linker script
  -
  -
+ +
• 1. Introduction
+
• 2. openmsp430-loader
+
• 3. openmsp430-minidebug
+
• 4. openmsp430-gdbproxy
+
• 5. MSPGCC Toolchain +
  +
  • 5.1 Compiler options
  +
  • 5.2 MCU selection
  +
  • 5.3 Custom linker +script
  +
  +

1. Introduction

-Building on the serial debug interface capabilities provided by the openMSP430, three small utility programs are provided: +Building on the serial debug interface capabilities provided by the +openMSP430, three utility programs are provided:

-
• openmsp430-loader: a simple command line boot loader.
-
• openmsp430-minidebug: a minimalistic debugger with simple GUI.
-
• openmsp430-gdbproxy: GDB Proxy server to be used together with MSP430-GDB and the Eclipse, DDD, or Insight graphical front-ends.
-

-All these software development tools have been developed in TCL/TK and were successfully tested on both Linux and Windows (XP/Vista/7). -

-Note: in order to be able to directly execute the scripts, TCL/TK -needs to be installed on your system. Optionally for Windows users, the scripts can be turned into single-file binary executable programs -using freeWrap by running/clicking the "tools/freewrap642/generate_exec.bat" file provided in the project repository. +

openmsp430-loader: a simple command line boot loader.

+

openmsp430-minidebug: a minimalistic debugger with simple +GUI.

+

openmsp430-gdbproxy: GDB Proxy server to be used together +with MSP430-GDB and the Eclipse, DDD, or Insight GUI front-ends.

+ +All these software development tools have been developed in +TCL/TK and were successfully tested on both Linux and Windows +(XP/Vista/7). +
+
+ +Note: to be able to execute the scripts, TCL/TK +needs to be installed on your system.
+ +
+ +In order to connect the host PC to the openMSP430 serial debug +interface, a serial cable is required.
+ +Typically, the following solutions will suit any kind of development +board:
+ +

+ +
• USB +to RS232 converter
+
• USB +to Serial TTL converter
  +
+

+

2. openmsp430-loader

+ This simple program allows the user to load the openMSP430 program -memory with an executable file (ELF or Intel-HEX format) provided as argument.
-It is typically used in conjunction with 'make' in order to automatically load the program after the compile step (see 'Makefile' from software examples provided with the project's FPGA implementation).
+memory with an executable file (ELF or Intel-HEX format) provided as +argument.
+ +It is typically used in conjunction with 'make' in order +to automatically load the program after the compile step (see 'Makefile' +from software examples provided with the project's FPGA implementation).
+ The program can be called with the following syntax: -

+
+ +
+ - - - - - + + + + + - -

-	-	-	- openmsp430-loader.tcl [-device <communication device>] [-baudrate <communication speed>] <elf/ihex-file> - -Examples: openmsp430-loader.tcl -device /dev/ttyUSB0 -baudrate 9600 leds.elf           openmsp430-loader.tcl + +
+	+	+	openmsp430-loader.tcl [-device <communication +device>] [-baudrate <communication speed>] +<elf/ihex-file> + + +Examples: openmsp430-loader.tcl -device /dev/ttyUSB0 -baudrate 9600 +leds.elf +          openmsp430-loader.tcl -device COM2: -baudrate 38400 ta_uart.ihex -

+ + + + +
+ These screenshots show the script in action under Linux and Windows: -

- -

-
+ +
+ + +
+ +
+ + +
+

3. openmsp430-minidebug

-This small program provides a minimalistic graphical interface enabling simple interaction with the openMSP430: -

- -

+ +This small program provides a minimalistic graphical interface enabling +simple interaction with the openMSP430: +
+ +
+ + +
+ +
+ As you can see from the screenshot, it allows the following actions:

-
• (1)  Connect to the openMSP430 Serial Debug Interface.
-
• (2)  Load the program memory with an ELF or Intel-HEX file
-
• (3)  Control the CPU: Reset, Stop, Start, Single-Step and Software breakpoints
-
• (4)  Read/Write access of the CPU registers
-
• (5)  Read/Write access of the whole memory range (program, data, peripherals)
-
• (6)  Basic disassembled view of the loaded program (current PC location is highlighted in green, software breakpoints in yellow, pink and violet)
-
• (7)  Choose the disassembled view type
-
• (8)  Source a custom external TCL script
+ +
• (1)  Connect to the +openMSP430 Serial Debug Interface.
+
• (2)  Load the +program memory with an ELF or Intel-HEX file
+
• (3)  Control the +CPU: Reset, Stop, Start, Single-Step and Software breakpoints
+
• (4)  Read/Write +access of the CPU registers
+
• (5)  Read/Write +access of the whole memory range (program, data, peripherals)
+
• (6)  Basic +disassembled view of the loaded program (current PC location is +highlighted in green, software breakpoints in yellow, pink and violet)
+
• (7)  Choose the +disassembled view type
+
• (8)  Source a +custom external TCL script

4. openmsp430-gdbproxy

-The purpose of this program is to replace the 'msp430-gdbproxy' utility provided by the mspgcc toolchain.
-Typically, a GDB proxy creates a local port for gdb to connect to, and + +The purpose of this program is to replace the 'msp430-gdbproxy' +utility provided by the mspgcc toolchain.
+ +Typically, a GDB proxy creates a local port for GDB to connect to, and handles the communication with the target hardware. In our case, it is basically a bridge between the RSP communication protocol from GDB and the serial debug interface from the openMSP430.
+ Schematically the communication flow looks as following: -

- -

-Like the original 'msp430-gdbproxy' program, 'openmsp430-gdbproxy' can be controlled from the command line. However, it also provides a small graphical interface: -

- -

-These two additional screenshots show the script in action together with the Eclipse and DDD graphical frontends: -

- -

- -

-Tip: There are several tutorials on Internet explaining how to +
+ +
+ + +
+ +
+ +Like the original 'msp430-gdbproxy' program, 'openmsp430-gdbproxy' +can be controlled from the command line. However, it also provides a +simple graphical interface: +
+ +
+ + +
+ +
+ +These two additional screenshots show the script in action together +with the Eclipse and DDD graphical frontends:
+ +
+ + +
+ +
+ + +
+ +
+ +Tip 1: There are several tutorials on Internet explaining how to configure Eclipse for the MSP430. As an Eclipse newbie, I found the -followings quite helpful (the msp430-gdbproxy sections should of course be ignored as we are using our own openmsp430-gdbproxy program :-) ): +followings quite helpful (the msp430-gdbproxy sections +should of course be ignored as we are using our own openmsp430-gdbproxy +program :-) ):

-
• A Step By Step Guide To MSP430 Programming Under Linux (English)
-
• MSP430 eclipse helios mspgcc4 (German)
+ +
• A +Step By Step Guide To MSP430 Programming Under Linux (English)
+
• MSP430 +eclipse helios mspgcc4 (German)

- -

5. MSPGCC(4) Toolchain

+Tip 2: You probably want to install this excellent Eclipse +plugin (see screenshot above): EmbSysRegView
+
+ +

5. MSPGCC Toolchain

+

5.1 Compiler options

-The msp430-gcc compiler accepts the following MSP430 specific command line parameters (copied from the MSPGCC manual page): -

+The msp430-gcc compiler accepts the following MSP430 specific +command line parameters (copied from the MSPGCC manual page): +
+ +
+ - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

-mmcu=	Specify the MCU name
-mno-volatile-workaround	Do not perform a volatile workaround for bitwise operations.
-mno-stack-init	Do not initialize the stack as main()starts.
-minit-stack=	Specify the initial stack address.
-mendup-at=	Jump to the specified routine at the end of main().
-mforce-hwmul	Force use of a hardware multiplier.
-mdisable-hwmul	Do not use the hardware multiplier.
-minline-hwmul	Issue inline code for 32-bit integer operations for devices with a hardware multiplier.
-mnoint-hwmul	Do not disable and enable interrupts around hardware multiplier operations. This makes - multiplication faster when you are certain no hardware multiplier operations will occur - at deeper interrupt levels.
-mcall-shifts	Use subroutine calls for shift operations. This may save some space for shift intensive - applications.
-mmcu=	Specify the MCU name
-mno-volatile-workaround	Do not perform a volatile workaround for bitwise operations.
-mno-stack-init	Do not initialize the stack as main()starts.
-minit-stack=	Specify the initial stack address.
-mendup-at=	Jump to the specified routine at the end of main().
-mforce-hwmul	Force use of a hardware multiplier.
-mdisable-hwmul	Do not use the hardware multiplier.
-minline-hwmul	Issue inline code for 32-bit integer operations for devices +with a hardware multiplier.
-mnoint-hwmul	Do not disable and enable +interrupts around hardware multiplier operations. This makes +multiplication faster when you are certain no hardware multiplier +operations will occur at deeper interrupt levels.
-mcall-shifts	Use subroutine calls for shift +operations. This may save some space for shift intensive applications.

+
-

5.2 MCU selection

-The following table aims to help selecting the proper MCU name for the -mmcu option during the msp430-gcc call: -

+The following table aims to help selecting the proper MCU name for the -mmcu +option +during the msp430-gcc call: +
+ +
+ - + + + + + - - - + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + + + + - - + + + + + - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + + + + - + - + - + @@ -252,55 +581,130 @@ - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + + + + - - - - + + + + + + + + + + + - - - - - - + + + + + + + + + + + + + + + + + - - + + + + + - + - + - - - - - - + + + + + + + + + + + + + + + + + + + - - + + + + + - - - - + + + + + + + + + + + - - - - - - + + + + + + + + + + + + + + + + + - - - - + + + + + + + + + + + - - + + + + + - - + + + + + - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + + + + - - + + + + + - - + + + + + - + + @@ -425,7 +916,8 @@ - + - + - + - + - + - + - + - + - + - + - - + + - + - - + + - - + + - - + + - - + + - - + + - - + + - + - + - + - + - + - + - @@ -651,11 +1116,11 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + + +

-mmcu option	Program   Memory	Data    Memory	Hardware + +
-mmcu option	Program   +Memory	Data +   Memory	Hardware   Multiplier
Program Memory Size: 1 kB
msp430x110	1 kB	128 B	No +
Program Memory Size: 1 kB
msp430x110	1 kB	128 B	No
msp430x1101	1 kB	128 B	No
msp430x2001	1 kB	128 B	No
msp430x2002	1 kB	128 B	No
msp430x2003	1 kB	128 B	No
msp430x2101	1 kB	128 B	No
Program Memory Size: 2 kB
msp430x1111	2 kB	128 B	No
msp430x2011	2 kB	128 B	No
msp430x2012	2 kB	128 B	No
msp430x2013	2 kB	128 B	No
msp430x2111	2 kB	128 B	No
msp430x2112	2 kB	128 B	No
msp430x311	2 kB	128 B	No
Program Memory Size: 4 kB
msp430x112	4 kB	256 B	No
msp430x1121	4 kB	256 B	No
msp430x1122	4 kB	256 B	No
msp430x122	4 kB	256 B	No
msp430x1222	4 kB	256 B	No
msp430x2122	4 kB	256 B	No
msp430x2121	4 kB	256 B	No
msp430x312	4 kB	256 B	No
msp430x412	4 kB	256 B	No
Program Memory Size: 8 kB
msp430x123	8 kB	256 B	No
msp430x133	8 kB	256 B	No
msp430x313	8 kB	256 B	No
msp430x323	8 kB	256 B	No
msp430x413	8 kB	256 B	No
msp430x423	8 kB	256 B	Yes +
msp430x1101	1 kB	128 B	No
msp430x2001	1 kB	128 B	No
msp430x2002	1 kB	128 B	No
msp430x2003	1 kB	128 B	No
msp430x2101	1 kB	128 B	No
Program Memory Size: 2 kB
msp430x1111	2 kB	128 B	No
msp430x2011	2 kB	128 B	No
msp430x2012	2 kB	128 B	No
msp430x2013	2 kB	128 B	No
msp430x2111	2 kB	128 B	No
msp430x2112	2 kB	128 B	No
msp430x311	2 kB	128 B	No
Program Memory Size: 4 kB
msp430x112	4 kB	256 B	No
msp430x1121	4 kB	256 B	No
msp430x1122	4 kB	256 B	No
msp430x122	4 kB	256 B	No
msp430x1222	4 kB	256 B	No
msp430x2122	4 kB	256 B	No
msp430x2121	4 kB	256 B	No
msp430x312	4 kB	256 B	No
msp430x412	4 kB	256 B	No
Program Memory Size: 8 kB
msp430x123	8 kB	256 B	No
msp430x133	8 kB	256 B	No
msp430x313	8 kB	256 B	No
msp430x323	8 kB	256 B	No
msp430x413	8 kB	256 B	No
msp430x423	8 kB	256 B	Yes
msp430xE423	8 kB	256 B	Yes +
msp430xE423	8 kB	256 B	Yes
msp430xE4232	8 kB	256 B	Yes +
msp430xE4232	8 kB	256 B	Yes
msp430xW423	8 kB	256 B	No
msp430x1132	8 kB	256 B	No
msp430x1232	8 kB	256 B	No
msp430x1331	8 kB	256 B	No
msp430x2131	8 kB	256 B	No
msp430x2132	8 kB	256 B	No
msp430x2232	8 kB	512 B	No
msp430x2234	8 kB	512 B	No
msp430x233	8 kB	1024 B	Yes +
msp430xW423	8 kB	256 B	No
msp430x1132	8 kB	256 B	No
msp430x1232	8 kB	256 B	No
msp430x1331	8 kB	256 B	No
msp430x2131	8 kB	256 B	No
msp430x2132	8 kB	256 B	No
msp430x2232	8 kB	512 B	No
msp430x2234	8 kB	512 B	No
msp430x233	8 kB	1024 B	Yes
msp430x2330	8 kB	1024 B	Yes +
msp430x2330	8 kB	1024 B	Yes
Program Memory Size: 12 kB				Program +Memory Size: 12 kB
msp430xE4242	12 kB	512 B	512 B	Yes
msp430x314	12 kB	512 B +	512 B	No
Program Memory Size: 16 kB
msp430x4250	16 kB	256 B	No
msp430xG4250	16 kB	256 B	No
msp430x135	16 kB	512 B	No
msp430x1351	16 kB	512 B	No
msp430x155	16 kB	512 B	No
msp430x2252	16 kB	512 B	No
msp430x2254	16 kB	512 B	No
msp430x315	16 kB	512 B	No
msp430x325	16 kB	512 B	No
msp430x415	16 kB	512 B	No
msp430x425	16 kB	512 B	Yes +
Program Memory Size: 16 kB
msp430x4250	16 kB	256 B	No
msp430xG4250	16 kB	256 B	No
msp430x135	16 kB	512 B	No
msp430x1351	16 kB	512 B	No
msp430x155	16 kB	512 B	No
msp430x2252	16 kB	512 B	No
msp430x2254	16 kB	512 B	No
msp430x315	16 kB	512 B	No
msp430x325	16 kB	512 B	No
msp430x415	16 kB	512 B	No
msp430x425	16 kB	512 B	Yes
msp430xE425	16 kB	512 B	Yes +
msp430xE425	16 kB	512 B	Yes
msp430xW425	16 kB	512 B	No
msp430xE4252	16 kB	512 B	Yes +
msp430xW425	16 kB	512 B	No
msp430xE4252	16 kB	512 B	Yes
msp430x435	16 kB	512 B	No
msp430x4351	16 kB	512 B	No
msp430x235	16 kB	2048 B	Yes +
msp430x435	16 kB	512 B	No
msp430x4351	16 kB	512 B	No
msp430x235	16 kB	2048 B	Yes
msp430x2350	16 kB	2048 B	Yes +
msp430x2350	16 kB	2048 B	Yes
Program Memory Size: 24 kB				Program +Memory Size: 24 kB
msp430x4260 @@ -362,60 +766,147 @@	Yes
Program Memory Size: 32 kB
msp430x4270	32 kB	256 B	No
msp430xG4270	32 kB	256 B	No
msp430x147	32 kB	1024 B	Yes +
Program Memory Size: 32 kB
msp430x4270	32 kB	256 B	No
msp430xG4270	32 kB	256 B	No
msp430x147	32 kB	1024 B	Yes
msp430x1471	32 kB	1024 B	Yes +
msp430x1471	32 kB	1024 B	Yes
msp430x157	32 kB	1024 B	No
msp430x167	32 kB	1024 B	Yes +
msp430x157	32 kB	1024 B	No
msp430x167	32 kB	1024 B	Yes
msp430x2272	32 kB	1024 B	No
msp430x2274	32 kB	1024 B	No
msp430x337	32 kB	1024 B	Yes +
msp430x2272	32 kB	1024 B	No
msp430x2274	32 kB	1024 B	No
msp430x337	32 kB	1024 B	Yes
msp430x417	32 kB	1024 B	No
msp430x427	32 kB	1024 B	Yes +
msp430x417	32 kB	1024 B	No
msp430x427	32 kB	1024 B	Yes
msp430xE427	32 kB	1024 B	Yes +
msp430xE427	32 kB	1024 B	Yes
msp430xE4272	32 kB	1024 B	Yes +
msp430xE4272	32 kB	1024 B	Yes
msp430xW427	32 kB	1024 B	No
msp430x437	32 kB	1024 B	No
msp430xG437	32 kB	1024 B	No
msp430x4371	32 kB	1024 B	No
msp430x447	32 kB	1024 B	Yes +
msp430xW427	32 kB	1024 B	No
msp430x437	32 kB	1024 B	No
msp430xG437	32 kB	1024 B	No
msp430x4371	32 kB	1024 B	No
msp430x447	32 kB	1024 B	Yes
msp430x2370	32 kB	2048 B	Yes +
msp430x2370	32 kB	2048 B	Yes
msp430x247	32 kB	4096 B	Yes +
msp430x247	32 kB	4096 B	Yes
msp430x2471	32 kB	4096 B	Yes +
msp430x2471	32 kB	4096 B	Yes
msp430x1610	32 kB
Program Memory Size: 41 kB				Program +Memory Size: 41 kB
msp430x5438 @@ -434,8 +926,7 @@	16384 B	No -	No
msp430x5437 @@ -444,8 +935,7 @@	16384 B	No -	No
msp430x5436 @@ -454,8 +944,7 @@	16384 B	No -	No
msp430x5435 @@ -464,8 +953,7 @@	16384 B	No -	No
msp430x5419 @@ -474,8 +962,7 @@	16384 B	No -	No
msp430x5418 @@ -484,11 +971,11 @@	16384 B	No -	No
Program Memory Size: 48 kB				Program +Memory Size: 48 kB
msp430x1611 @@ -497,8 +984,7 @@	10240 B	Yes -	Yes
msp430x248 @@ -507,8 +993,7 @@	4096 B	Yes -	Yes
msp430x2481 @@ -515,10 +1000,8 @@	48 kB	4096 B -	Yes -	4096 B	Yes
msp430x4783 @@ -527,8 +1010,7 @@	2048 B	Yes -	Yes
msp430xG438 @@ -535,10 +1017,8 @@	48 kB	2048 B -	No -	2048 B	No
msp430x4784 @@ -545,10 +1025,8 @@	48 kB	2048 B -	Yes -	2048 B	Yes
msp430x148 @@ -555,10 +1033,8 @@	48 kB	2048 B -	Yes -	2048 B	Yes
msp430x168 @@ -565,10 +1041,8 @@	48 kB	2048 B -	Yes -	2048 B	Yes
msp430x1481 @@ -575,10 +1049,8 @@	48 kB	2048 B -	Yes -	2048 B	Yes
msp430x448 @@ -585,13 +1057,12 @@	48 kB	2048 B -	Yes -	2048 B	Yes
Program Memory Size: 51 kB				Program +Memory Size: 51 kB
msp430xG4617 @@ -600,8 +1071,7 @@	8192 B	Yes -	Yes
msp430x2418 @@ -610,8 +1080,7 @@	8192 B	Yes -	Yes
msp430x2618 @@ -620,8 +1089,7 @@	8192 B	Yes -	Yes
msp430x2417 @@ -630,8 +1098,7 @@	8192 B	Yes -	Yes
msp430xG4618 @@ -640,10 +1107,8 @@	8192 B	Yes -	Yes
msp430x2617	8192 B	Yes -	Yes
Program Memory Size: 54 kB				Program +Memory Size: 54 kB
msp430x1612 @@ -664,11 +1129,11 @@	5120 B	Yes -	Yes
Program Memory Size: 55 kB				Program +Memory Size: 55 kB
msp430x2619 @@ -677,8 +1142,7 @@	4096 B	Yes -	Yes
msp430xG4619 @@ -687,8 +1151,7 @@	4096 B	Yes -	Yes
msp430xG4616 @@ -697,8 +1160,7 @@	4096 B	Yes -	Yes
msp430x2416 @@ -707,8 +1169,7 @@	4096 B	Yes -	Yes
msp430x2419 @@ -717,8 +1178,7 @@	4096 B	Yes -	Yes
msp430x2616 @@ -727,8 +1187,7 @@	4096 B	Yes -	Yes
msp430x2410 @@ -737,11 +1196,11 @@	4096 B	Yes -	Yes
Program Memory Size: 59 kB				Program +Memory Size: 59 kB
msp430x4794 @@ -750,8 +1209,7 @@	2560 B	Yes -	Yes
msp430x4793 @@ -760,8 +1218,7 @@	2560 B	Yes -	Yes
msp430x2491 @@ -770,8 +1227,7 @@	2048 B	Yes -	Yes
msp430x1491 @@ -780,8 +1236,7 @@	2048 B	Yes -	Yes
msp430x149 @@ -790,8 +1245,7 @@	2048 B	Yes -	Yes
msp430xG439 @@ -810,8 +1264,7 @@	2048 B	Yes -	Yes
msp430x449 @@ -820,8 +1273,7 @@	2048 B	Yes -	Yes
msp430x169 @@ -830,33 +1282,66 @@	2048 B	Yes -	Yes

-
-Note: the program memory size should imperatively match the openMSP430 configuration.
+
+Note: the program +memory size should imperatively match the openMSP430 configuration.
+
+

5.3 Custom linker script

-The use of the -mmcu switch is of course NOT mandatory. It is simply a convenient way to use the pre-existing linker scripts provided with the MSPGCC4 toolchain.
+ +The use of the -mmcu switch is of course NOT mandatory. +It is simply a convenient way to use the pre-existing linker scripts +provided with the MSPGCC4 toolchain.
+
-However, if the peripheral address space is larger than the standard 512B of the original MSP430 (see the Advanced System Configuration section), a customized linker script MUST be provided.
+ +However, if the peripheral address space is larger than the standard +512B of the original MSP430 (see the Advanced +System Configuration section), a customized linker script MUST +be provided.
+
-To create a custom linker script, the simplest way is to start from an existing one: + +To create a custom linker script, the simplest way is to start from an +existing one:

-
• the MSPGCC(4) toolchain provides a wide range of examples for all supported MSP430 models (see "msp430/lib/ldscripts/" sub-directory, in the MSPGCC(4) installation directory).
-
• the openMSP430 project also provide a simple linker script example: ldscript_example.x
+ +
• the MSPGCC toolchain provides a wide range of examples for all +supported MSP430 models (see "msp430/lib/ldscripts/" +sub-directory, in the MSPGCC installation directory).
+
• the openMSP430 project also provide a simple linker script +example: ldscript_example.x

+
-From there, the script can be modified to match YOUR openMSP430 configuration: + +From there, the script can be modified to match YOUR openMSP430 +configuration:

-
• In the text (rx) section definition, update the ORIGIN and LENGTH fields to match the PROGRAM MEMORY configuration.
-
• In the data (rwx) section definition, update the ORIGIN field to match the PERIPHERAL SPACE configuration and the LENGTH field to match the DATA MEMORY configuration.
-
• At last, update the stack pointer initialization value (look for the "PROVIDE (__stack =" section) and make sure that it falls in the data memory space (the stack size should also matches your application requirements, i.e. not to small... and not to big :-P ).
+ +
• In the text (rx) section definition, update the ORIGIN +and LENGTH fields to match the PROGRAM MEMORY +configuration.
+
• In the data (rwx) section definition, update the ORIGIN +field to match the PERIPHERAL SPACE configuration and the LENGTH +field to match the DATA MEMORY configuration.
+
• At last, update the stack pointer initialization value (look for +the "PROVIDE (__stack =" +section) and make sure that it falls in the data memory space (the +stack size should also matches your application requirements, i.e. not +to small... and not to big :-P ).

-

+
+
+ \ No newline at end of file

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Table of content

-
• 1. Overview
-
• 2. Clocks
-
• 3. Resets
-
• 4. Program Memory
-
• 5. Data Memory
-
• 6. Peripherals
-
• 7. Interrupts
-
• 8. Serial Debug Interface
+
• 1. Overview
+
• 2. Clocks
+
• 3. Resets
+
• 4. Program Memory
+
• 5. Data Memory
+
• 6. Peripherals
+
• 7. Interrupts
+
• 8. Serial Debug Interface

1. Overview

- -This chapter aims to give a comprehensive description of all openMSP430 core interfaces in order to facilitates its integration within an ASIC or FPGA.

- -The following diagram shows an overview of the openMSP430 core connectivity:

- -

-The full pinout of the core is summarized in the following table.
-
+This chapter aims to give a comprehensive description of all openMSP430 +core interfaces in order to facilitate its integration within an ASIC +or FPGA.

The +following diagram shows an overview of the openMSP430 core connectivity +in an FPGA system (i.e. all ASIC specific pins are left unused):

+ +

+The full pinout of the core is summarized in the following table.
+
- + + - + - - - - + + + + + - - - - + + + + + - - - - + + + + + - - - - + + + + + - - - - + + + + + - - - - + + + + + - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - + + + + + - + - - - - + + + + + - - - - + + + + + - - - - + + + + + - - - - + + + + + - - - - + + + + + - + - - - - + + + + + - - - - + + + + + - - - - + + + + + - - - - + + + + + - - - - + + + + + - + - - - - + + + + + - - - - + + + + + - - - - + + + + + - - - - + + + + + - - - - + + + + + - + - - - - + + + + + - - - - + + + + + - - - - + + + + + - + - - - - + + + + + - - - - + + + + + - - - - + + + + + - - - - - -

Port Name	Direction	Width	Description
Port Name	Direction	Width	Clock + Domain +	Description
Clocks
Clocks
cpu_en	Input	1	Enable CPU code execution (asynchronous)	cpu_en	Input	1	<async> + +or mclk4	Enable CPU code execution (asynchronous and non-glitchy). Set to 1 if unused.
dco_clk	Input	1	Fast oscillator (fast clock), CPU clock	dco_clk	Input	1	- +	Fast oscillator (fast clock)
lfxt_clk	Input	1	Low frequency oscillator (typ. 32kHz)	lfxt_clk	Input	1	- +	Low frequency oscillator (typ. 32kHz) Set to 0 if unused.
mclk	Output	1	Main system clock	mclk	Output	1	- +	Main system clock
aclk_en	Output	1	ACLK enable	aclk_en	Output	1	mclk +	FPGA ONLY: ACLK enable
smclk_en	Output	1	SMCLK enable	smclk_en	Output	1	mclk +	FPGA ONLY: SMCLK enable
Resets
puc_rst	Output	1	Main system reset	dco_enable	Output +	1 +	dco_clk +	ASIC ONLY: Fast oscillator enable
dco_wkup	Output	1 +	<async> +	ASIC ONLY: Fast oscillator wakeup (asynchronous)
lfxt_enable	Output	1 +	lfxt_clk +	ASIC ONLY: Low frequency oscillator enable
lfxt_wkup	Output	1 +	<async> +	ASIC ONLY: Low frequency oscillator wakeup (asynchronous)
aclk	Output	1 +	- +	ASIC ONLY: ACLK
smclk	Output	1 +	- +	ASIC ONLY: SMCLK
wkup	Input +	1 +	<async> +	ASIC ONLY: System Wake-up (asynchronous and non-glitchy) Set to 0 if unused.
Resets
puc_rst	Output	1	mclk +	Main system reset
reset_n	Input	1	Reset Pin (low active, asynchronous)	reset_n	Input	1	<async> +	Reset Pin (active low, asynchronous and non-glitchy)
Program Memory interface
Program Memory interface
pmem_addr	Output	`PMEM_AWIDTH1	Program Memory address	pmem_addr	Output	`PMEM_AWIDTH1	mclk +	Program Memory address
pmem_cen	Output	1	Program Memory chip enable (low active)	pmem_cen	Output	1	mclk	Program Memory chip enable (low active)
pmem_din	Output	16	Program Memory data input	pmem_din	Output	16	mclk	Program Memory data input (optional 2)
pmem_dout	Input	16	Program Memory data output	pmem_dout	Input	16	mclk	Program Memory data output
pmem_wen	Output	2	Program Memory write byte enable (low active)	pmem_wen	Output	2	mclk	Program Memory write byte enable (low active) (optional 2)
Data Memory interface
Data Memory interface
dmem_addr	Output	`DMEM_AWIDTH1	Data Memory address	dmem_addr	Output	`DMEM_AWIDTH1	mclk	Data Memory address
dmem_cen	Output	1	Data Memory chip enable (low active)	dmem_cen	Output	1	mclk	Data Memory chip enable (low active)
dmem_din	Output	16	Data Memory data input	dmem_din	Output	16	mclk	Data Memory data input
dmem_dout	Input	16	Data Memory data output	dmem_dout	Input	16	mclk	Data Memory data output
dmem_wen	Output	2	Data Memory write byte enable (low active)	dmem_wen	Output	2	mclk	Data Memory write byte enable (low active)
External Peripherals interface
External Peripherals interface
per_addr	Output	14	Peripheral address	per_addr	Output	14	mclk	Peripheral address
per_din	Output	16	Peripheral data input	per_din	Output	16	mclk	Peripheral data input
per_dout	Input	16	Peripheral data output	per_dout	Input	16	mclk	Peripheral data output
per_en	Output	1	Peripheral enable (high active)	per_en	Output	1	mclk	Peripheral enable (high active)
per_we	Output	2	Peripheral write byte enable (high active)	per_we	Output	2	mclk	Peripheral write byte enable (high active)
Interrupts
Interrupts
irq	Input	14	Maskable interrupts (one-hot signal)	irq	Input	14	mclk	Maskable interrupts (one-hot signal)
nmi	Input	1	Non-maskable interrupt (asynchronous)	nmi	Input	1	<async> + +or mclk4	Non-maskable interrupt (asynchronous)
irq_acc	Output	14	Interrupt request accepted (one-hot signal)	irq_acc	Output	14	mclk	Interrupt request accepted (one-hot signal)
Serial Debug interface
Serial Debug interface
dbg_en	Input	1	Debug interface enable (asynchronous)	dbg_en	Input	1	<async> + +or mclk4	Debug interface enable (asynchronous) 3
dbg_freeze	Output	1	Freeze peripherals	dbg_freeze	Output	1	mclk	Freeze peripherals
dbg_uart_txd	Output	1	Debug interface: UART TXD	dbg_uart_txd	Output	1	mclk	Debug interface: UART TXD
dbg_uart_rxd	Input	1	Debug interface: UART RXD (asynchronous)

-
-¹: This parameter is declared in the "openMSP430_defines.v" file and defines the RAM/ROM size.
-
+ dbg_uart_rxd + Input + 1 + <async>
+ + Debug interface: UART RXD (asynchronous) + + Scan + + + scan_enable
+ + Input
+ + 1
+ + dco_clk
+ + ASIC ONLY: Scan enable (active during scan shifting) + + + scan_mode
+ + Input
+ + 1
+ + <stable>
+ + ASIC ONLY: Scan mode + + +
+¹: This parameter is declared in the "openMSP430_defines.v" file and defines the RAM/ROM size.
²: +These two optional ports can be connected whenever the program memory +is a RAM. This will allow the user to load a program through the serial +debug interface and to use software breakpoints.
³: When disabled, the debug interface is hold into reset (and clock gated in ASIC mode). As a consequence, the dbg_en port can be used to reset the debug interface without disrupting the CPU execution.
⁴: Clock domain is selectable through configuration in the "openMSP430_defines.v" file (see Advanced System Configuration).
+
+ - +

2. Clocks

-The different clocks in the design are managed by the Basic Clock Module: -

- -
+The different clocks in the design are managed by the Basic Clock Module as following in the FPGA configuration: +

+ +
+
+or as following in the ASIC configuration:
+
+ +

• - CPU_EN: this input port provide a hardware mean to stop or resume CPU execution. When unused, this port should be set to 1. -
  
  + CPU_EN: this input port provides a hardware mean to stop or resume CPU execution. When unused, this port should be set to 1. +
  
  
• - DCO_CLK: this input port is typically connected to a PLL, RC oscillator or any clock resource the target FPGA might provide.
  - From a synthesis tool perspective (ISE, Quartus, Libero, Design Compiler...), this the only port where a clock needs to be declared. -
  
  + DCO_CLK: this input port is typically connected to a PLL, RC oscillator or any clock resource the target FPGA/ASIC might provide.
  For the FPGA configuration, from a synthesis tool perspective (ISE, Quartus, Libero, Design +Compiler...), this the only port where a clock needs to be declared.
  
  
-
• - LFXT_CLK: if ACLK_EN or SMCLK_EN are going to be used in the project (for example through the Watchdog or TimerA peripherals), then this port needs to be connected to a clock running at least two time slower as DCO_CLK (typically 32kHz). It can be connected to 0 or 1 otherwise. -
  
  + +
• + LFXT_CLK: +in an FPGA system, if ACLK_EN or SMCLK_EN are going to be used in the project (for example +through the Watchdog or TimerA peripherals), then this port needs to be +connected to a clock running at least two time slower as DCO_CLK +(typically 32kHz). It can be connected to 0 or 1 otherwise.
  + +In an ASIC, if ACLK or SMCLK are used and if the clock muxes are +included, then this port can be connected to any kind of clock source +(it doesn't need to be low-frequency. The name was just +kept to be consistent with TI's documentation).
  
  
+
• - MCLK: the main system clock drives the complete openMSP430 clock domain, including program/data memories and the peripheral interfaces. -
  
  + MCLK: +the main system clock drives the complete openMSP430 clock domain, +including program/data memories and the peripheral interfaces.
  
  
• - ACLK_EN / SMCLK_EN: these two clock enable signals can be used in order to emulate the original ACLK and SMCLK from the MSP430 specification.
  - An example of this can be found in the Watchdog and TimerA modules, where it is implemented as following:
  
  - -
  
  -
+ ACLK_EN / SMCLK_EN: +these two clock enable signals can be used in order to emulate the +original ACLK and SMCLK from the MSP430 specification when the core is +targeting an FPGA.
+ An example of this can be found in the Watchdog and TimerA modules, where it is implemented as following:

+
+

- -As an illustration, the following waveform shows the different clocks where the software running on the openMSP430 configures the BCSCTL1 and BCSCTL2 registers so that ACLK_EN and SMCLK_EN are respectively running at LFXT_CLK/2 and DCO_CLK/4.

- -

+

+
• + ACLK / SMCLK: ACLK and MCLK are available through these two ports when targeting an ASIC.
   
+
• + DCO_ENABLE / DCO_WKUP: ASIC specific signals controlling the fast clock generator for low power mode support (SCG0 bit in the status register).
  
  
+
• + LFXT_ENABLE / LFXT_WKUP: +ASIC specific signals controlling the low frequency clock generator for +low power mode support (OSCOFF bit in the status register).
   
+
• WKUP: +When activated, this signal allows a peripheral to restore all CPU +clocks (i.e. wakeup the cpu) prior IRQ generation.  Note that IRQs +MUST always be generated from the MCLK clock domain.
+

+As an FPGA system illustration, the following waveform shows the different +clocks where the software running on the openMSP430 configures the +BCSCTL1 and BCSCTL2 registers so that ACLK_EN and SMCLK_EN are respectively running at LFXT_CLK/2 and DCO_CLK/4.

+ +

+ - +

3. Resets

• RESET_N: this input port is typically connected to a board push button and is generally combined with the system power-on-reset. -
  
  +
  
  
• - PUC_RST: the Power-Up-Clear signal is asynchronously set with the reset pin (RESET_N), the watchdog reset or the serial debug interface reset. In order to get clean timings, it is synchronously cleared with MCLK's falling edge. As a general rule, this signal should be used as the reset of the MCLK clock domain. -
  
  + PUC_RST: the Power-Up-Clear signal is asynchronously set with the reset pin (RESET_N), +the watchdog reset or the serial debug interface reset. In order to get +clean timings, it is synchronously cleared with MCLK. As +a general rule, this signal should be used as the reset of the MCLK clock domain. +
  
  

-The following waveform illustrates this:

- -

+The following waveform illustrates this:

+ +

- +

4. Program Memory

-Depending on the project needs, the program memory can be either implemented as a ROM or RAM.
-
-If a ROM is selected then the PMEM_DIN and PMEM_WEN ports won't be connected. In that case, the software debug capabilities are limited because the serial debug interface can only use hardware breakpoints in order to stop the program execution. In addition, updating the software will require a reprogramming of the FPGA.
-
-If the program memory is a RAM, the developer gets full flexibility regarding software debugging. The serial debug interface can be used to update the program memory and software breakpoints can be used.
-

+Depending on the project needs, the program memory can be either implemented as a ROM or RAM.
+
+If a ROM is selected then the PMEM_DIN and PMEM_WEN +ports won't be connected. In that case, the software debug capabilities +are limited because the serial debug interface can only use hardware +breakpoints in order to stop the program execution. In addition, +updating the software will require a reprogramming of the FPGA... or a new ROM mask for an ASIC.
+
+If the program memory is a RAM, the developer gets full flexibility +regarding software debugging. The serial debug interface can be used to +update the program memory and software breakpoints can be used.
+

That said, the protocol between the openMSP430 and the program memory is quite standard. Signal description goes as following:

• PMEM_CEN: when this signal is active, the read/write access will be executed with the next MCLK rising edge. Note that this signal is LOW ACTIVE. -
  
  +
  
  
• - PMEM_ADDR: Memory address of the 16 bit word which is going to be accessed.
  + PMEM_ADDR: Memory address of the 16 bit word which is going to be accessed.
  Note: in order to calculate the core logical address from the program memory physical address, the formula goes as following: LOGICAL@=2*PHYSICAL@+0x10000-PMEM_SIZE -
  
  +
  
  
• PMEM_DOUT: the memory output word will be updated with every valid read/write access (i.e. PMEM_DOUT is not updated if PMEM_CEN=1). -
  
  +
  
  
• - PMEM_WEN: this signal selects which byte should be written during a valid access. PMEM_WEN[0] will activate a write on the lower byte, PMEM_WEN[1] a write on the upper byte. Note that these signals are LOW ACTIVE. -
  
  + PMEM_WEN: +this signal selects which byte should be written during a valid access. +PMEM_WEN[0] will activate a write on the lower byte, PMEM_WEN[1] a +write on the upper byte. Note that these signals are LOW ACTIVE.
  
  
• PMEM_DIN: the memory input word will be written with the valid write access according to the PMEM_WEN value. -
  
  +
  
  

-The following waveform illustrates some read accesses of the program memory (write access are illustrated in the data memory section):

- -

+The following waveform illustrates some read accesses of the program +memory (write access are illustrated in the data memory section):

+ +

- +

5. Data Memory

-The data memory is always implemented as a RAM.
-
-The protocol between the openMSP430 and the data memory is the same as the one of the program memory. Therefore, the signal description is the same: +The data memory is always implemented as a RAM.
+
+The protocol between the openMSP430 and the data memory is the same as +the one of the program memory. Therefore, the signal description is the +same:

• DMEM_CEN: when this signal is active, the read/write access will be executed with the next MCLK rising edge. Note that this signal is LOW ACTIVE. -
  
  +
  
  
• - DMEM_ADDR: Memory address of the 16 bit word which is going to be accessed.
  + DMEM_ADDR: Memory address of the 16 bit word which is going to be accessed.
  Note: in order to calculate the core logical address from the data memory physical address, the formula goes as following: LOGICAL@=2*PHYSICAL@+0x200 -
  
  +
  
  
• DMEM_DOUT: the memory output word will be updated with every valid read/write access (i.e. DMEM_DOUT is not updated if DMEM_CEN=1). -
  
  +
  
  
• - DMEM_WEN: this signal selects which byte should be written during a valid access. DMEM_WEN[0] will activate a write on the lower byte, DMEM_WEN[1] a write on the upper byte. Note that these signals are LOW ACTIVE. -
  
  + DMEM_WEN: +this signal selects which byte should be written during a valid access. +DMEM_WEN[0] will activate a write on the lower byte, DMEM_WEN[1] a +write on the upper byte. Note that these signals are LOW ACTIVE.
  
  
• DMEM_DIN: the memory input word will be written with the valid write access according to the DMEM_WEN value. -
  
  +
  
  

-The following waveform illustrates some read/write access to the data memory:

- -

+The following waveform illustrates some read/write access to the data memory:

+ +

- +

6. Peripherals

- -The protocol between the openMSP430 core and its peripherals is the exactly same as the one with the data and program memories in regards to write access and differs slightly for read access.
-
-On the connectivity side, the specificity is that the read data bus of all peripherals should be ORed together before being connected to the core, as showed in the diagram of the Overview section.
-From the logical point of view, during a read access, each peripheral outputs the combinatorial value of its read mux and returns 0 if it doesn't contain the addressed register. On the waveforms, this translates by seeing the register value on PER_DOUT while PER_EN is valid and not one clock cycle afterwards as it is the case with the program and data memories.
-In any case, it is recommended to use the templates provided with the core in order to develop your own custom peripherals.
+The protocol between the openMSP430 core and its peripherals is the +exactly same as the one with the data and program memories in regard +to write access and differs slightly for read access.
+
+On the connectivity side, the specificity is that the read data bus of +all peripherals should be ORed together before being connected to the +core, as showed in the diagram of the Overview section.
+From the logical point of view, during a read access, each peripheral +outputs the combinatorial value of its read mux and returns 0 if it +doesn't contain the addressed register. On the waveforms, this +translates by seeing the register value on PER_DOUT while PER_EN is valid and not one clock cycle afterward as it is the case with the program and data memories.
+In any case, it is recommended to use the templates provided with the core in order to develop your own custom peripherals.
The signal description therefore goes as following:

• PER_EN: when this signal is active, read access are executed during the current MCLK cycle while write access will be executed with the next MCLK rising edge. Note that this signal is HIGH ACTIVE. -
  
  +
  
  
• - PER_ADDR: peripheral register address of the 16 bit word which is currently accessed. It is to be noted that a 14 bit address will always be provided from the openMSP430 to the peripheral in order to accommodate the biggest possible PER_SIZE Verilog configuration option (i.e. 32kB as opposed to 512B by default).
  + PER_ADDR: +peripheral register address of the 16 bit word which is currently +accessed. It is to be noted that a 14 bit address will always be +provided from the openMSP430 to the peripheral in order to accommodate +the biggest possible PER_SIZE Verilog configuration option (i.e. 32kB +as opposed to 512B by default).
  Note: in order to calculate the core logical address from the peripheral register physical address, the formula goes as following: LOGICAL@=2*PHYSICAL@ -
  
  +
  
  
• PER_DOUT: the peripheral output word will be updated with every valid read/write access, it will be set to 0 otherwise. -
  
  +
  
  
• - PER_WE: this signal selects which byte should be written during a valid access. PER_WE[0] will activate a write on the lower byte, PER_WE[1] a write on the upper byte. Note that these signals are HIGH ACTIVE. -
  
  + PER_WE: +this signal selects which byte should be written during a valid access. +PER_WE[0] will activate a write on the lower byte, PER_WE[1] a write on +the upper byte. Note that these signals are HIGH ACTIVE.
  
  
• PER_DIN: the peripheral input word will be written with the valid write access according to the PER_WEN value. -
  
  +
  
  

-The following waveform illustrates some read/write access to the peripheral registers:

- -

+The following waveform illustrates some read/write access to the peripheral registers:

+ +

- -

7. Interrupts

- -As with the original MSP430, the interrupt priorities of the openMSP430 are fixed in hardware accordingly to the connectivity of the NMI and IRQ ports.
-If two interrupts are pending simultaneously, the higher priority interrupt will be serviced first.
-The following table summarize this:

+ +

7. Interrupts

As with the original MSP430, the interrupt +priorities of the openMSP430 are fixed in hardware accordingly to the +connectivity of the NMI and IRQ ports.
+If two interrupts are pending simultaneously, the higher priority interrupt will be serviced first.
+The following table summarize this:

- + @@ -484,54 +691,64 @@ -

Interrupt Port	Vector address	Priority	0xFFE0	0 (lowest)

-

+ +

The signal description goes as following:

• - NMI: The Non-Maskable Interrupt has higher priority than other IRQs and is masked by the NMIIE bit instead of GIE.
  -It is internally synchronized to the MCLK domain and can therefore be connected to any asynchronous signal of the chip (which could for example be a pin of the FPGA). If unused, this signal should be connected to 0. -
  
  + NMI: The Non-Maskable Interrupt has higher priority than other IRQs and is masked by the NMIIE bit instead of GIE.
  +It is internally synchronized to the MCLK +domain and can therefore be connected to any asynchronous signal of the +chip (which could for example be a pin of the FPGA). If unused, this +signal should be connected to 0.
  
  
• - IRQ: The standard interrupts can be connected to any signal coming from the MCLK domain (typically a peripheral). Priorities can be chosen by selecting the proper bit of the IRQ bus as shown in the table above. Unused interrupts should be connected to 0.
  -Note: IRQ[10] is internally connected to the Watchdog interrupt. If this bit is also used by an external peripheral, they will both share the same interrupt vector. -
  
  + IRQ: The standard interrupts can be connected to any signal coming from the MCLK domain (typically a peripheral). Priorities can be chosen by selecting the proper bit of the IRQ bus as shown in the table above. Unused interrupts should be connected to 0.
  +Note: IRQ[10] is internally connected to the Watchdog +interrupt. If this bit is also used by an external peripheral, they +will both share the same interrupt vector.
  
  
• - IRQ_ACC: Whenever an interrupt request is serviced, some peripheral automatically clear their pending flag in hardware. In order to do so, the IRQ_ACC bus can be used by using the bit matching the corresponding IRQ bit. An example of this is shown in the implementation of the TACCR0 Timer A interrupt. -
  
  + IRQ_ACC: +Whenever an interrupt request is serviced, some peripheral +automatically clear their pending flag in hardware. In order to do so, +the IRQ_ACC bus can be used by using the bit matching the corresponding IRQ bit. An example of this is shown in the implementation of the TACCR0 Timer A interrupt. +
  
  

-The following waveform illustrates a TAIV interrupt issued by the Timer-A, which is connected to IRQ[8] :

- +The following waveform illustrates a TAIV interrupt issued by the Timer-A, which is connected to IRQ[8] :

+ -

+

- +

8. Serial Debug Interface

- -The serial debug interface module provides a two-wires communication bus for remote debugging and an additional freeze signal which might be useful for some peripherals.
-
+The serial debug interface module provides a two-wires communication +bus for remote debugging and an additional freeze signal which might be +useful for some peripherals (typically timers).
+

• - DBG_EN: this signal allows the user to enable or disable the serial debug interface without interfering with the CPU execution. It is to be noted that when disabled (i.e. DBG_EN=0), the debug interface is held into reset. -
  
  + DBG_EN: this signal +allows the user to enable or disable the serial debug interface without +interfering with the CPU execution. It is to be noted that when +disabled (i.e. DBG_EN=0), the debug interface is held into reset.
  
  
• - DBG_FREEZE: this signal will be set whenever the debug interface stops the CPU (and if the FRZ_BRK_EN field of the CPU_CTL debug register is set). As its name implies, the purpose of DBG_FREEZE is to freeze a peripheral whenever the CPU is stopped by the software debugger.
  -For example, it is used by the Watchdog timer in order to stop its free-running counter. This prevents the CPU from being reseted by the watchdog every times the user stops the CPU during a debugging session. -
  
  + DBG_FREEZE: this signal will be set whenever the debug interface stops the CPU (and if the FRZ_BRK_EN field of the CPU_CTL debug register is set). As its name implies, the purpose of DBG_FREEZE is to freeze a peripheral whenever the CPU is stopped by the software debugger.
  +For example, it is used by the Watchdog timer in order to stop its +free-running counter. This prevents the CPU from being reseted by the +watchdog every times the user stops the CPU during a debugging session. +
  
  
• DBG_UART_TXD / DBG_UART_RXD: these signals are typically connected to an RS-232 transceiver and will allow a PC to communicate with the openMSP430 core. -
  
  +
  
  

-The following waveform shows some communication traffic on the serial bus :

- -

- - \ No newline at end of file +The following waveform shows some communication traffic on the serial bus :

+ +

+ \ No newline at end of file

/openmsp430/trunk/doc/html/asic_implementation.html

openmsp430/trunk/doc/html/asic_implementation.html Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/doc/html/serial_debug_interface.html =================================================================== --- openmsp430/trunk/doc/html/serial_debug_interface.html (revision 134) +++ openmsp430/trunk/doc/html/serial_debug_interface.html (revision 135) @@ -1,71 +1,75 @@ - - - - - +

Table of content

-
• 1. Introduction
-
• 2. Debug Unit +
• 1. Introduction
+
• 2. Debug Unit
  -
  • 2.1 Register Mapping
  -
  • 2.2 CPU Control/Status Registers
  +
  • 2.1 Register Mapping
  +
  • 2.2 CPU Control/Status Registers
  -
  • 2.2.1 CPU_ID
  -
  • 2.2.2 CPU_CTL
  -
  • 2.2.3 CPU_STAT
  +
  • 2.2.1 CPU_ID
  +
  • 2.2.2 CPU_CTL
  +
  • 2.2.3 CPU_STAT
  -
  • 2.3 Memory Access Registers
  +
  • 2.3 Memory Access Registers
  -
  • 2.3.1 MEM_CTL
  -
  • 2.3.2 MEM_ADDR
  -
  • 2.3.3 MEM_DATA
  -
  • 2.3.4 MEM_CNT
  +
  • 2.3.1 MEM_CTL
  +
  • 2.3.2 MEM_ADDR
  +
  • 2.3.3 MEM_DATA
  +
  • 2.3.4 MEM_CNT
  -
  • 2.4 Hardware Breakpoint Unit Registers
  +
  • 2.4 Hardware Breakpoint Unit Registers
  -
  • 2.4.1 BRKx_CTL
  -
  • 2.4.2 BRKx_STAT
  -
  • 2.4.3 BRKx_ADDR0
  -
  • 2.4.4 BRKx_ADDR1
  +
  • 2.4.1 BRKx_CTL
  +
  • 2.4.2 BRKx_STAT
  +
  • 2.4.3 BRKx_ADDR0
  +
  • 2.4.4 BRKx_ADDR1
-
• 3. Debug Communication Interface: UART +
• 3. Debug Communication Interface: UART
  -
  • 3.1 Serial communication protocol: 8N1
  -
  • 3.2 Synchronization frame
  -
  • 3.3 Read/Write access to the debug registers
  +
  • 3.1 Serial communication protocol: 8N1
  +
  • 3.2 Synchronization frame
  +
  • 3.3 Read/Write access to the debug registers
  -
  • 3.3.1 Command Frame
  -
  • 3.3.2 Write access
  -
  • 3.3.3 Read access
  +
  • 3.3.1 Command Frame
  +
  • 3.3.2 Write access
  +
  • 3.3.3 Read access
  -
  • 3.4 Read/Write burst implementation for the CPU Memory access
  +
  • 3.4 Read/Write burst implementation for the CPU Memory access
  -
  • 3.4.1 Write Burst access
  -
  • 3.4.2 Read Burst access
  +
  • 3.4.1 Write Burst access
  +
  • 3.4.2 Read Burst access
  -

+

1. Introduction

+The original MSP430 from TI provides a serial debug interface to allow +in-system software debugging. In that case, the communication +with the host computer is typically built on a JTAG or Spy-Bi-Wire +serial protocol. However, the global debug architecture from the MSP430 +is unfortunately poorly documented on the web (and is also probably +tightly linked with the internal core architecture). +

A custom module has therefore been implemented for the +openMSP430. The communication with the host is done with a simple two-wire RS232 +cable (8N1 serial protocol) and the debug unit provides all the +required features for Nexus Class 3 debugging (beside trace), namely:

+
• CPU control (run, stop, step, reset).
+
• Software & hardware breakpoint support.
+
• Hardware watchpoint support.
  +
-The original MSP430 from TI provides a serial debug interface to give a simple path to software development. In that case, the communication with the host computer is typically build on a JTAG or Spy-Bi-Wire serial protocol. However, the global debug architecture from the MSP430 is unfortunately poorly documented on the web (and is also probably tightly linked with the internal core architecture). -

-A custom module has therefore been implemented for the openMSP430. The communication with the host is done with a simple RS232 cable (8N1 serial protocol) and the debug unit provides all the required features for Nexus Class 3 debugging (beside trace), namely: -
-
• CPU control (run, stop, step, reset).
-
• Software & hardware breakpoint support.
• Memory read/write on-the-fly (no need to halt execution).
• CPU registers read/write on-the-fly (no need to halt execution).
-
Top
+
Top

2. Debug Unit

@@ -72,26 +76,26 @@

2.1 Register Mapping

The following table summarize the complete debug register set accessible through the debug communication interface: -

+

- - - - + + + + - - - - - - - - + + + + + + + + - - + + @@ -98,15 +102,15 @@ - - + + - - + + @@ -117,8 +121,8 @@ - - + + @@ -130,8 +134,8 @@ - - + + @@ -139,23 +143,23 @@ - - + + - - + + - - + + - - + + @@ -163,8 +167,8 @@ - - + + @@ -174,18 +178,18 @@ - - + + - - + + - - + + @@ -193,8 +197,8 @@ - - + + @@ -204,18 +208,18 @@ - - + + - - + + - - + + @@ -223,8 +227,8 @@ - - + + @@ -234,18 +238,18 @@ - - + + - - + + - - + + @@ -253,8 +257,8 @@ - - + + @@ -264,44 +268,44 @@ - - + + - - + + -

Register Name

Address

Bit Field

Register Name

Address

Bit Field

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CPU_ID_LO

0x00

CPU_ID_LO

0x00

PER_SPACE

USER_VERSION

ASIC

CPU_VERSION

CPU_ID_HI

0x01

CPU_ID_HI

0x01

PMEM_SIZE

DMEM_SIZE

MPY

CPU_CTL

0x02

CPU_CTL

0x02

Reserved

CPU_RST

RST_BRK_EN

HALT

CPU_STAT

0x03

CPU_STAT

0x03

Reserved

HWBRK3_PND

HWBRK2_PND

HALT_RUN

MEM_CTL

0x04

MEM_CTL

0x04

Reserved

B/W

MEM/REG

START

MEM_ADDR

0x05

MEM_ADDR

0x05

MEM_ADDR[15:0]

MEM_DATA

0x06

MEM_DATA

0x06

MEM_DATA[15:0]

MEM_CNT

0x07

MEM_CNT

0x07

MEM_CNT[15:0]

BRK0_CTL

0x08

BRK0_CTL

0x08

Reserved

RANGE_MODE

INST_EN

ACCESS_MODE

BRK0_STAT

0x09

BRK0_STAT

0x09

Reserved

RANGE_WR

RANGE_RD

ADDR0_RD

BRK0_ADDR0

0x0A

BRK0_ADDR0

0x0A

BRK_ADDR0[15:0]

BRK0_ADDR1

0x0B

BRK0_ADDR1

0x0B

BRK_ADDR1[15:0]

BRK1_CTL

0x0C

BRK1_CTL

0x0C

Reserved

RANGE_MODE

INST_EN

ACCESS_MODE

BRK1_STAT

0x0D

BRK1_STAT

0x0D

Reserved

RANGE_WR

RANGE_RD

ADDR0_RD

BRK1_ADDR0

0x0E

BRK1_ADDR0

0x0E

BRK_ADDR0[15:0]

BRK1_ADDR1

0x0F

BRK1_ADDR1

0x0F

BRK_ADDR1[15:0]

BRK2_CTL

0x10

BRK2_CTL

0x10

Reserved

RANGE_MODE

INST_EN

ACCESS_MODE

BRK2_STAT

0x11

BRK2_STAT

0x11

Reserved

RANGE_WR

RANGE_RD

ADDR0_RD

BRK2_ADDR0

0x12

BRK2_ADDR0

0x12

BRK_ADDR0[15:0]

BRK2_ADDR1

0x13

BRK2_ADDR1

0x13

BRK_ADDR1[15:0]

BRK3_CTL

0x14

BRK3_CTL

0x14

Reserved

RANGE_MODE

INST_EN

ACCESS_MODE

BRK3_STAT

0x15

BRK3_STAT

0x15

Reserved

RANGE_WR

RANGE_RD

ADDR0_RD

BRK3_ADDR0

0x16

BRK3_ADDR0

0x16

BRK_ADDR0[15:0]

BRK3_ADDR1

0x17

BRK3_ADDR1

0x17

BRK_ADDR1[15:0]

+ -
Top
+
Top

2.2 CPU Control/Status Registers

2.2.1 CPU_ID

This 32 bit read-only register holds the program and data memory size information of the implemented openMSP430. -

+

- - - - + + + + - - - - - - - - + + + + + + + + - - + + @@ -308,18 +312,19 @@ - - + + -

Register Name	Address	Bit Field
		Register Name	Address	Bit Field
15	14			13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CPU_ID_LO	0x00	CPU_ID_LO	0x00	PER_SPACE							USER_VERSION					ASIC	CPU_VERSION
CPU_ID_HI	0x01	CPU_ID_HI	0x01	PMEM_SIZE						DMEM_SIZE									MPY

-
+ +
- + - + @@ -345,28 +350,28 @@ -

	CPU_VERSION	: Current CPU version (currently 1)	: Current CPU version +
	ASIC		PMEM_SIZE	: Progam memory size for the current implementation (byte size = PMEM_SIZE*1024)

+ -

2.2.2 CPU_CTL

- -This 8 bit read-write register is used to control the CPU and to configure some basic debug features. After a POR, this register is set to 0x00. -

+

2.2.2 CPU_CTL

This 8 bit read-write register is used to +control the CPU and to configure some basic debug features. After a +POR, this register is set to 0x10 or 0x30 (depending on the DBG_RST_BRK_EN configuration option). +

- - - - + + + + - - - - + + + + - - + + @@ -376,10 +381,10 @@ -

Register Name	Address	Bit Field
		Register Name	Address	Bit Field
7	6			5	4	3	2	1	0	7	6	5	4	3	2	1	0
CPU_CTL	0x02	CPU_CTL	0x02	Res.	CPU_RST	RST_BRK_EN	RUN	HALT

-
+ +
- + @@ -407,29 +412,29 @@ -

	CPU_RST	: Setting this bit to 1 will activate the PUC reset. Setting it back to 0 will release it.
	HALT1	: Writing 1 to this bit will put the CPU in halt state.

-
¹:this field is write-only and always reads back 0. -
+ +
¹:this field is write-only and always reads back 0. +


2.2.3 CPU_STAT

This 8 bit read-write register gives the global status of the debug interface. After a POR, this register is set to 0x00. -

+

- - - - + + + + - - - - + + + + - - + + @@ -439,24 +444,24 @@ -

Register Name	Address	Bit Field
		Register Name	Address	Bit Field
7	6			5	4	3	2	1	0	7	6	5	4	3	2	1	0
CPU_STAT	0x03	CPU_STAT	0x03	HWBRK3_PND	HWBRK2_PND	HWBRK1_PND	Res.	HALT_RUN

-
+ +
- + - + - + - + - + @@ -474,17 +479,17 @@ -

	HWBRK3_PND	: This bit reflects if one of the Hardware Breakpoint Unit 3 status bit is set (i.e. BRK3_STAT≠0).	: This bit reflects if one of the Hardware Breakpoint Unit 3 status bit is set (i.e. BRK3_STAT≠0).
	HWBRK2_PND	: This bit reflects if one of the Hardware Breakpoint Unit 2 status bit is set (i.e. BRK2_STAT≠0).	: This bit reflects if one of the Hardware Breakpoint Unit 2 status bit is set (i.e. BRK2_STAT≠0).
	HWBRK1_PND	: This bit reflects if one of the Hardware Breakpoint Unit 1 status bit is set (i.e. BRK1_STAT≠0).	: This bit reflects if one of the Hardware Breakpoint Unit 1 status bit is set (i.e. BRK1_STAT≠0).
	HWBRK0_PND	: This bit reflects if one of the Hardware Breakpoint Unit 0 status bit is set (i.e. BRK0_STAT≠0).	: This bit reflects if one of the Hardware Breakpoint Unit 0 status bit is set (i.e. BRK0_STAT≠0).
	SWBRK_PND
		0 - CPU is running. -    1 - CPU is stopped. +    1 - CPU is stopped.

+ -
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+
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2.3 Memory Access Registers

The following four registers enable single and burst read/write access to both CPU-Registers and full memory address range. -
In order to perform an access, the following sequences are typically done: +
In order to perform an access, the following sequences are typically done:
• single read access (MEM_CNT=0):
@@ -498,32 +503,32 @@
1. set MEM_DATA with the data to be written
2. set MEM_CTL (in particular RD/WR=1 and START=1)
-
• burst read/write access (MEM_CNT≠0):
+
• burst read/write access (MEM_CNT≠0):
• burst access are optimized for the communication interface used (i.e. for the UART). - The burst sequence are therefore described in the corresponding section (3.4 Read/Write burst implementation for the CPU Memory access)
+ The burst sequence are therefore described in the corresponding section (3.4 Read/Write burst implementation for the CPU Memory access)
-

2.3.1 MEM_CTL

- -This 8 bit read-write register is used to control the Memory and CPU-Register read/write access. After a POR, this register is set to 0x00. -

+

2.3.1 MEM_CTL

This 8 bit read-write register is used to control +the Memory and CPU-Register read/write access. After a POR, this +register is set to 0x00. +

- - - - + + + + - - - - + + + + - - + + @@ -530,10 +535,10 @@ -

Register Name	Address	Bit Field
		Register Name	Address	Bit Field
7	6			5	4	3	2	1	0	7	6	5	4	3	2	1	0
MEM_CTL	0x04	MEM_CTL	0x04	Reserved				B/W	MEM/REG	RD/WR	START

-
+ +
- + @@ -565,75 +570,78 @@ -

	B/W	: 0 - 16 bit access.
		1 - Initiate memory transfer.

+ -

2.3.2 MEM_ADDR

- -This 16 bit read-write register specifies the Memory or CPU-Register address to be used for the next read/write transfer. After a POR, this register is set to 0x0000. -
-Note: in case of burst (i.e. MEM_CNT≠0), this register specifies the first address of the burst transfer and will be incremented automatically as the burst goes (by 1 for 8-bit access and by 2 for 16-bit access). -

+

2.3.2 MEM_ADDR

This 16 bit read-write register specifies the +Memory or CPU-Register address to be used for the next read/write +transfer. After a POR, this register is set to 0x0000. +
+Note: in case of burst (i.e. MEM_CNT≠0), this register +specifies the first address of the burst transfer and will be +incremented automatically as the burst goes (by 1 for 8-bit access and +by 2 for 16-bit access). +

- - - - + + + + - - - - - - - - + + + + + + + + - - + + -

Register Name	Address	Bit Field
		Register Name	Address	Bit Field
15	14			13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MEM_ADDR	0x05	MEM_ADDR	0x05	MEM_ADDR[15:0]

-
+ +
- + -

	MEM_ADDR	: Memory or CPU-Register address to be used for the next read/write transfer.

+ -

2.3.3 MEM_DATA

- -This 16 bit read-write register specifies (wr) or receive (rd) the Memory or CPU-Register data for the the next transfer. After a POR, this register is set to 0x0000. -

+

2.3.3 MEM_DATA

This 16 bit read-write register gives (wr) +or receive (rd) the Memory or CPU-Register data for the next +transfer. After a POR, this register is set to 0x0000. +

- - - - + + + + - - - - - - - - + + + + + + + + - - + + -

Register Name	Address	Bit Field
		Register Name	Address	Bit Field
15	14			13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MEM_DATA	0x06	MEM_DATA	0x06	MEM_DATA[15:0]

-
+ +
- + @@ -641,71 +649,78 @@ -

	MEM_DATA	: if MEM_CTL.WR - data to be written during the next write transfer.
		if MEM_CTL.RD - updated with the data from the read transfer

+ -

2.3.4 MEM_CNT

- -This 16 bit read-write register controls the burst access to the Memory or CPU-Registers. If set to 0, a single access will occur, otherwise, a burst will be performed. The burst being optimized for the communication interface, more details are given there. After a POR, this register is set to 0x0000. -

+

2.3.4 MEM_CNT

This 16 bit read-write register controls the +burst access to the Memory or CPU-Registers. If set to 0, a single +access will occur, otherwise, a burst will be performed. The burst +being optimized for the communication interface, more details are given +there. After a POR, this register is set to 0x0000. +

- - - - + + + + - - - - - - - - + + + + + + + + - - + + -

Register Name	Address	Bit Field
		Register Name	Address	Bit Field
15	14			13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MEM_CNT	0x07	MEM_CNT	0x07	MEM_CNT[15:0]

-
+ +
- + - + -

	MEM_CNT	: =0 - a single access will be performed with the next transfer.
		≠0 - specifies the burst size for the next transfer (i.e number of data access). This field will be automatically decremented as the burst goes.	≠0 - +specifies the burst size for the next transfer (i.e number of data +access). This field will be automatically decremented as the burst goes.

+ -
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+
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2.4 Hardware Breakpoint Unit Registers

-Depending on the defines located in the "openmsp430_defines.v" file, up to four hardware breakpoint units can be included in the design. These units can be individually controlled with the following registers. +Depending on the defines +located in the "openmsp430_defines.v" file, up to four hardware +breakpoint units can be included in the design. These units can be +individually controlled with the following registers.

2.4.1 BRKx_CTL

This 8 bit read-write register controls the hardware breakpoint unit x. After a POR, this register is set to 0x00. -

+

- - - - + + + + - - - - + + + + - - + + @@ -712,18 +727,18 @@ -

Register Name	Address	Bit Field
		Register Name	Address	Bit Field
7	6			5	4	3	2	1	0	7	6	5	4	3	2	1	0
BRKx_CTL	0x08, 0x0C, 0x10, 0x14	BRKx_CTL	0x08, 0x0C, 0x10, 0x14	Reserved			RANGE_MODE	INST_EN	BREAK_EN	ACCESS_MODE

-
+ +
- + - - + + @@ -750,32 +765,32 @@ +
  10 - Detect write access. +
  11 - Detect read/write access +
Note: '10' & '11' modes are not supported on the instruction flow -

	RANGE_MODE	: 0 - Address match on BRK_ADDR0 or BRK_ADDR1 (normal mode)
		1 - Address match on BRK_ADDR0→BRK_ADDR1 range (range mode) - Note: range mode is not supported by the core unless the `DBG_HWBRK_RANGE define is set to 1'b1 in the openMSP430_define.v file.	1 - Address match on BRK_ADDR0→BRK_ADDR1 range (range mode) + Note: range mode is not supported by the core unless the `DBG_HWBRK_RANGE define is set to 1'b1 in the openMSP430_define.v file.
	INST_EN
		01 - Detect read access. -   10 - Detect write access. -   11 - Detect read/write access - Note: '10' & '11' modes are not supported on the instruction flow

+ -

2.4.2 BRKx_STAT

- -This 8 bit read-write register gives the status of the hardware breakpoint unit x. Each status bit can be cleared by writing 1 to it. After a POR, this register is set to 0x00. -

+

2.4.2 BRKx_STAT

This 8 bit read-write register gives the status +of the hardware breakpoint unit x. Each status bit can be cleared by +writing 1 to it. After a POR, this register is set to 0x00. +

- - - - + + + + - - - - + + + + - - + + @@ -784,186 +799,211 @@ -

Register Name	Address	Bit Field
		Register Name	Address	Bit Field
7	6			5	4	3	2	1	0	7	6	5	4	3	2	1	0
BRKx_STAT	0x09, 0x0D, 0x11, 0x15	BRKx_STAT	0x09, 0x0D, 0x11, 0x15	Reserved		RANGE_WR	RANGE_RD	ADDR0_WR	ADDR0_RD

-
+ +
- + - + - + - + - + - + - + -

	RANGE_WR	: This bit is set whenever the CPU performs a write access within the BRKx_ADDR0→BRKx_ADDR1 range (valid if RANGE_MODE=1 and ACCESS_MODE[1]=1).	: +This bit is set whenever the CPU performs a write access within the +BRKx_ADDR0→BRKx_ADDR1 range (valid if RANGE_MODE=1 and +ACCESS_MODE[1]=1).
	RANGE_RD	: This bit is set whenever the CPU performs a read access within the BRKx_ADDR0→BRKx_ADDR1 range (valid if RANGE_MODE=1 and ACCESS_MODE[0]=1). - Note: range mode is not supported by the core unless the `DBG_HWBRK_RANGE define is set to 1'b1 in the openMSP430_define.v file.	: +This bit is set whenever the CPU performs a read access within the +BRKx_ADDR0→BRKx_ADDR1 range (valid if RANGE_MODE=1 and +ACCESS_MODE[0]=1). Note: range mode is not supported by the core unless the `DBG_HWBRK_RANGE define is set to 1'b1 in the openMSP430_define.v file.
	ADDR1_WR	: This bit is set whenever the CPU performs a write access at the BRKx_ADDR1 address (valid if RANGE_MODE=0 and ACCESS_MODE[1]=1).	: +This bit is set whenever the CPU performs a write access at the +BRKx_ADDR1 address (valid if RANGE_MODE=0 and ACCESS_MODE[1]=1).
	ADDR1_RD	: This bit is set whenever the CPU performs a read access at the BRKx_ADDR1 address (valid if RANGE_MODE=0 and ACCESS_MODE[0]=1).	: +This bit is set whenever the CPU performs a read access at the +BRKx_ADDR1 address (valid if RANGE_MODE=0 and ACCESS_MODE[0]=1).
	ADDR0_WR	: This bit is set whenever the CPU performs a write access at the BRKx_ADDR0 address (valid if RANGE_MODE=0 and ACCESS_MODE[1]=1).	: +This bit is set whenever the CPU performs a write access at the +BRKx_ADDR0 address (valid if RANGE_MODE=0 and ACCESS_MODE[1]=1).
	ADDR0_RD	: This bit is set whenever the CPU performs a read access at the BRKx_ADDR0 address (valid if RANGE_MODE=0 and ACCESS_MODE[0]=1).	: +This bit is set whenever the CPU performs a read access at the +BRKx_ADDR0 address (valid if RANGE_MODE=0 and ACCESS_MODE[0]=1).

+

2.4.3 BRKx_ADDR0

- -This 16 bit read-write register holds the value which is compared against the address value currently present on the program or data address bus. After a POR, this register is set to 0x0000. -

+This 16 bit read-write register holds the value which is compared +against the address value currently present on the program or data +address bus. After a POR, this register is set to 0x0000. +

- - - - + + + + - - - - - - - - + + + + + + + + - - + + -

Register Name	Address	Bit Field
		Register Name	Address	Bit Field
15	14			13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRKx_ADDR0	0x0A, 0x0E, 0x12, 0x16	BRKx_ADDR0	0x0A, 0x0E, 0x12, 0x16	BRK_ADDR0[15:0]

-
+ +
- + -

	BRK_ADDR0	: Value compared against the address value currently present on the program or data address bus.

+ -

2.4.4 BRKx_ADDR1

- -This 16 bit read-write register holds the value which is compared against the address value currently present on the program or data address bus. After a POR, this register is set to 0x0000. -

+

2.4.4 BRKx_ADDR1

This 16 bit read-write register holds the +value which is compared against the address value currently present on +the program or data address bus. After a POR, this register is set to +0x0000. +

- - - - + + + + - - - - - - - - + + + + + + + + - - + + -

Register Name	Addresses	Bit Field
		Register Name	Addresses	Bit Field
15	14			13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRKx_ADDR1	0x0B, 0x0F, 0x13, 0x17	BRKx_ADDR1	0x0B, 0x0F, 0x13, 0x17	BRK_ADDR1[15:0]

-
+ +
- + -

	BRK_ADDR1	: Value compared against the address value currently present on the program or data address bus.

+ -
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-

3. Debug Communication Interface: UART

-With its UART interface, the openMSP430 debug unit can communicate with the host computer using a simple RS232 cable (connected to the dbg_uart_txd and dbg_uart_rxd ports of the IP).
-Using an standard USB to RS232 adaptor, the interface provides a reliable communication link up to 1,5Mbps. - +
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+

3. Debug Communication Interface: UART

With its UART interface, +the openMSP430 debug unit can communicate with the host computer using +a simple RS232 cable (connected to the dbg_uart_txd and dbg_uart_rxd ports of the IP).
Typically, a USB to RS232 or USB to serial TTL +cable will provide a reliable communication link between your host PC +and the openMSP430 (speed being typically limited by the cable length).

3.1 Serial communication protocol: 8N1

-There are plenty tutorials on Internet regarding RS232 based protocols. However, here is quick recap about 8N1 (1 Start bit, 8 Data bits, No Parity, 1 Stop bit):
-
- -
-As you can see in the above diagram, data transmission starts with a Start bit, followed by the data bits (LSB sent first and MSB sent last), and ends with a "Stop" bit. - +There are plenty tutorials on Internet regarding RS232 based protocols. +However, here is quick recap about 8N1 (1 Start bit, 8 Data bits, No +Parity, 1 Stop bit):
+
+ +
+As you can see in the above diagram, data transmission starts with a +Start bit, followed by the data bits (LSB sent first and MSB sent +last), and ends with a "Stop" bit. -

3.2 Synchronization frame

-After a POR, the Serial Debug Interface expects a synchronization frame from the host computer in order to determine the communication speed (i.e. the baud rate).
+

3.2 Synchronization frame

After a POR, the Serial Debug +Interface expects a synchronization frame from the host computer in +order to determine the communication speed (i.e. the baud rate).
The synchronization frame looks as following: -
- -
-As you can see, the host simply sends the 0x80 value. The openMSP430 will then measure the time between the falling and rising edge, divide it by 8 and automatically deduce the baud rate it should use to properly communicate with the host. -

-Important note: if you want to change the communication speed between two debugging sessions, the openMSP430 needs to go over a POR cycle and a new synchronization frame needs to be send. - +
+ +
+As you can see, the host simply sends the 0x80 value. The openMSP430 +will then measure the time between the falling and rising edge, divide +it by 8 and automatically deduce the baud rate it should use to +properly communicate with the host. +

+Important note: if you want to change the communication speed +between two debugging sessions, the Serial Debug Interface needs to go through a reset cycle (i.e. through the reset_n or dbg_en pins) and a new synchronization frame needs to be send. +


3.3 Read/Write access to the debug registers

-In order to perform a read / write access to a debug register, the host needs to send a command frame to the openMSP430.
-In case of write access, this command frame will be followed by 1 or 2 data frames and in case of read access, the openMSP430 will send 1 or 2 data frames after receiving the command. - +In order to perform a read / write access to a debug register, the host needs to send a command frame to the openMSP430.
In +case of write access, this command frame will be followed by 1 or 2 +data frames and in case of read access, the openMSP430 will send 1 or 2 +data frames after receiving the command.

3.3.1 Command Frame

The command frame looks as following: -
- -
+
+ +
- + - + - + -

	WR	: Perform a Write access when set. Read otherwise.
	B/W	: Perform a 8-bit data access when set (one data frame). 16-bit otherwise (two data frame).
: Perform a 8-bit data access when set (one data frame). 16-bit otherwise (two data frame).
	Address	: Debug register address.
: Debug register address.

+

3.3.2 Write access

A write access transaction looks like this: -
- +
+

3.3.3 Read access

A read access transaction looks like this: -
- +
+ -

3.4 Read/Write burst implementation for the CPU Memory access

-In order to optimize the data burst transactions for the UART, read/write access are not done by reading or writing the MEM_DATA register.
+

3.4 Read/Write burst implementation for the CPU Memory access

In +order to optimize the data burst transactions for the UART, read/write +access are not done by reading or writing the MEM_DATA register.
Instead, the data transfer starts immediately after the MEM_CTL.START bit has been set.

3.4.1 Write Burst access

A write burst transaction looks like this: -
- +
+

3.4.2 Read Burst access

A read burst transaction looks like this: -
- +
+ -
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- - \ No newline at end of file +
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+ \ No newline at end of file