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Rev 135 → Rev 136

/trunk/rtl/verilog/pci_conf_space.v
43,6 → 43,12
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2003/12/19 11:11:30 mihad
// Compact PCI Hot Swap support added.
// New testcases added.
// Specification updated.
// Test application changed to support WB B3 cycles.
//
// Revision 1.3 2003/08/14 13:06:02 simons
// synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.
//
1593,6 → 1599,7
assign w_conf_wdata_reduced[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = w_conf_data_in[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
assign w_conf_wdata_reduced[(31-`WB_NUM_OF_DEC_ADDR_LINES): 0] = 0 ;
 
 
always@(posedge w_clock or posedge reset)
begin
// Here are implemented all registers that are reset with RESET signal otherwise they can be normaly written!!!
1608,11 → 1615,15
`ifdef HOST
`ifdef NO_CNF_IMAGE // if PCI bridge is HOST and IMAGE0 is assigned as general image space
`ifdef PCI_IMAGE0
pci_img_ctrl0_bit2_1 <= 2'h0 ;
`ifdef ADDR_TRAN_IMPL
pci_img_ctrl0_bit2_1 <= 2'h2 ; //FR2201 when defined enabled
`else
pci_img_ctrl0_bit2_1 <= 2'h0 ;
`endif
pci_ba0_bit31_12 <= 20'h0000_0 ;
pci_ba0_bit0 <= `PCI_BA0_MEM_IO ;
pci_am0 <= `PCI_AM0 ;
pci_ta0 <= 20'h0000_0 ;
pci_ta0 <= `PCI_TA0 ;//fr2201 translation address
`endif
`else
pci_ba0_bit31_12 <= 20'h0000_0 ;
1621,80 → 1632,125
pci_ba0_bit31_12 <= 20'h0000_0 ;
`endif
 
pci_img_ctrl1_bit2_1 <= 2'h0 ;
`ifdef ADDR_TRAN_IMPL
pci_img_ctrl1_bit2_1 <= 2'h2 ; //FR2201 when defined enabled
`else
pci_img_ctrl1_bit2_1 <= 2'h0 ;
`endif
pci_ba1_bit31_12 <= 20'h0000_0 ;
`ifdef HOST
pci_ba1_bit0 <= `PCI_BA1_MEM_IO ;
`endif
pci_am1 <= `PCI_AM1;
pci_ta1 <= 20'h0000_0 ;
pci_ta1 <= `PCI_TA1 ;//FR2201 translation address ;
`ifdef PCI_IMAGE2
pci_img_ctrl2_bit2_1 <= 2'h0 ;
`ifdef ADDR_TRAN_IMPL
pci_img_ctrl2_bit2_1 <= 2'h2 ; //FR2201 when defined enabled
`else
pci_img_ctrl2_bit2_1 <= 2'h0 ;
`endif
pci_ba2_bit31_12 <= 20'h0000_0 ;
`ifdef HOST
pci_ba2_bit0 <= `PCI_BA2_MEM_IO ;
`endif
pci_am2 <= `PCI_AM2;
pci_ta2 <= 20'h0000_0 ;
pci_ta2 <= `PCI_TA2 ;//FR2201 translation address ;
`endif
`ifdef PCI_IMAGE3
pci_img_ctrl3_bit2_1 <= 2'h0 ;
`ifdef ADDR_TRAN_IMPL
pci_img_ctrl3_bit2_1 <= 2'h2 ; //FR2201 when defined enabled
`else
pci_img_ctrl3_bit2_1 <= 2'h0 ;
`endif
pci_ba3_bit31_12 <= 20'h0000_0 ;
`ifdef HOST
pci_ba3_bit0 <= `PCI_BA3_MEM_IO ;
`endif
pci_am3 <= `PCI_AM3;
pci_ta3 <= 20'h0000_0 ;
pci_ta3 <= `PCI_TA3 ;//FR2201 translation address ;
`endif
`ifdef PCI_IMAGE4
pci_img_ctrl4_bit2_1 <= 2'h0 ;
`ifdef ADDR_TRAN_IMPL
pci_img_ctrl4_bit2_1 <= 2'h2 ; //FR2201 when defined enabled
`else
pci_img_ctrl4_bit2_1 <= 2'h0 ;
`endif
pci_ba4_bit31_12 <= 20'h0000_0 ;
`ifdef HOST
pci_ba4_bit0 <= `PCI_BA4_MEM_IO ;
`endif
pci_am4 <= `PCI_AM4;
pci_ta4 <= 20'h0000_0 ;
pci_ta4 <= `PCI_TA4 ;//FR2201 translation address ;
`endif
`ifdef PCI_IMAGE5
pci_img_ctrl5_bit2_1 <= 2'h0 ;
`ifdef ADDR_TRAN_IMPL
pci_img_ctrl5_bit2_1 <= 2'h2 ; //FR2201 when defined enabled
`else
pci_img_ctrl5_bit2_1 <= 2'h0 ;
`endif
pci_ba5_bit31_12 <= 20'h0000_0 ;
`ifdef HOST
pci_ba5_bit0 <= `PCI_BA5_MEM_IO ;
`endif
pci_am5 <= `PCI_AM5;
pci_ta5 <= 20'h0000_0 ;
pci_am5 <= `PCI_AM5; //FR2201 pci_am0
pci_ta5 <= `PCI_TA5 ;//FR2201 translation address ;
`endif
/*pci_err_cs_bit31_24 ; pci_err_cs_bit10; pci_err_cs_bit9 ; pci_err_cs_bit8 ;*/ pci_err_cs_bit0 <= 1'h0 ;
/*pci_err_addr ;*/
/*pci_err_data ;*/
//
wb_img_ctrl1_bit2_0 <= 3'h0 ;
wb_ba1_bit31_12 <= 20'h0000_0 ; wb_ba1_bit0 <= 1'h0 ;
wb_am1 <= 20'h0000_0 ;
wb_ta1 <= 20'h0000_0 ;
`ifdef ADDR_TRAN_IMPL
wb_img_ctrl1_bit2_0 <= 3'h4 ; //FR2201 when defined enabled
`else
wb_img_ctrl1_bit2_0 <= 3'h0 ;
`endif
wb_ba1_bit31_12 <=`WB_BA1; //FR2201 Address bar
wb_ba1_bit0 <=`WB_BA1_MEM_IO;//
wb_am1 <= `WB_AM1 ;//FR2201 Address mask
wb_ta1 <= `WB_TA1 ;//FR2201 20'h0000_0 ;
`ifdef WB_IMAGE2
wb_img_ctrl2_bit2_0 <= 3'h0 ;
wb_ba2_bit31_12 <= 20'h0000_0 ; wb_ba2_bit0 <= 1'h0 ;
wb_am2 <= 20'h0000_0 ;
wb_ta2 <= 20'h0000_0 ;
`ifdef ADDR_TRAN_IMPL
wb_img_ctrl2_bit2_0 <= 3'h4 ; //FR2201 when defined enabled
`else
wb_img_ctrl2_bit2_0 <= 3'h0 ;
`endif
wb_ba2_bit31_12 <=`WB_BA2; //FR2201 Address bar
wb_ba2_bit0 <=`WB_BA2_MEM_IO;//
wb_am2 <=`WB_AM2 ;//FR2201 Address mask
wb_ta2 <=`WB_TA2 ;//FR2201 translation address ;
`endif
`ifdef WB_IMAGE3
wb_img_ctrl3_bit2_0 <= 3'h0 ;
wb_ba3_bit31_12 <= 20'h0000_0 ; wb_ba3_bit0 <= 1'h0 ;
wb_am3 <= 20'h0000_0 ;
wb_ta3 <= 20'h0000_0 ;
`ifdef ADDR_TRAN_IMPL
wb_img_ctrl3_bit2_0 <= 3'h4 ; //FR2201 when defined enabled
`else
wb_img_ctrl3_bit2_0 <= 3'h0 ;
`endif
wb_ba3_bit31_12 <=`WB_BA3; //FR2201 Address bar
wb_ba3_bit0 <=`WB_BA3_MEM_IO;//
wb_am3 <=`WB_AM3 ;//FR2201 Address mask
wb_ta3 <=`WB_TA3 ;//FR2201 translation address ;
`endif
`ifdef WB_IMAGE4
wb_img_ctrl4_bit2_0 <= 3'h0 ;
wb_ba4_bit31_12 <= 20'h0000_0 ; wb_ba4_bit0 <= 1'h0 ;
wb_am4 <= 20'h0000_0 ;
wb_ta4 <= 20'h0000_0 ;
`ifdef ADDR_TRAN_IMPL
wb_img_ctrl4_bit2_0 <= 3'h4 ; //FR2201 when defined enabled
`else
wb_img_ctrl4_bit2_0 <= 3'h0 ;
`endif
wb_ba4_bit31_12 <=`WB_BA4; //FR2201 Address bar
wb_ba4_bit0 <=`WB_BA4_MEM_IO;//
wb_am4 <=`WB_AM4 ;//FR2201 Address mask
wb_ta4 <=`WB_TA4 ;//FR2201 translation address ;
`endif
`ifdef WB_IMAGE5
wb_img_ctrl5_bit2_0 <= 3'h0 ;
wb_ba5_bit31_12 <= 20'h0000_0 ; wb_ba5_bit0 <= 1'h0 ;
wb_am5 <= 20'h0000_0 ;
wb_ta5 <= 20'h0000_0 ;
`ifdef ADDR_TRAN_IMPL
wb_img_ctrl5_bit2_0 <= 3'h4 ; //FR2201 when defined enabled
`else
wb_img_ctrl5_bit2_0 <= 3'h0 ;
`endif
wb_ba5_bit31_12 <=`WB_BA5; //FR2201 Address bar ;
wb_ba5_bit0 <=`WB_BA5_MEM_IO;//FR2201 1'h0 ;
wb_am5 <=`WB_AM5 ;//FR2201 Address mask
wb_ta5 <=`WB_TA5 ;//FR2201 translation address ;
`endif
/*wb_err_cs_bit31_24 ; wb_err_cs_bit10 ; wb_err_cs_bit9 ; wb_err_cs_bit8 ;*/ wb_err_cs_bit0 <= 1'h0 ;
/*wb_err_addr ;*/
/trunk/rtl/verilog/pci_user_constants.v
39,6 → 39,12
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10 2003/12/19 11:11:30 mihad
// Compact PCI Hot Swap support added.
// New testcases added.
// Specification updated.
// Test application changed to support WB B3 cycles.
//
// Revision 1.9 2003/08/03 18:05:06 mihad
// Added limited WISHBONE B3 support for WISHBONE Slave Unit.
// Doesn't support full speed bursts yet.
175,6 → 181,16
`define PCI_BA4_MEM_IO 1'b0
`define PCI_BA5_MEM_IO 1'b1
 
// initial value for PCI translation addresses. The initial values
// are set after reset. When ADDR_TRAN_IMPL is defined then then Images
// are transleted to this adresses whithout access to pci_ta registers.
`define PCI_TA0 20'h1000_0
`define PCI_TA1 20'h2000_0
`define PCI_TA2 20'h3000_0
`define PCI_TA3 20'h4000_0
`define PCI_TA4 20'h5000_0
`define PCI_TA5 20'h6000_0
 
// number defined here specifies how many MS bits in WB address are compared with base address, to decode
// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images,
191,10 → 207,42
`define WB_IMAGE3
`define WB_IMAGE4
`define WB_IMAGE5
//Address bar register defines the base address for each image.
//To asccess bus without Software configuration.
`define WB_BA1 20'h1000_0
`define WB_BA2 20'h2000_0
`define WB_BA3 20'h3000_0
`define WB_BA4 20'h4000_0
`define WB_BA5 20'h5000_0
 
// initial value for WB image maping to MEMORY or IO spaces. If initial define is set to 0,
// then IMAGE with that base address points to MEMORY space, othervise it points ti IO space.
`define WB_BA1_MEM_IO 1'b0
`define WB_BA2_MEM_IO 1'b0
`define WB_BA3_MEM_IO 1'b0
`define WB_BA4_MEM_IO 1'b0
`define WB_BA5_MEM_IO 1'b0
 
// initial value for WB image address masks.
`define WB_AM1 20'hffff_f
`define WB_AM2 20'hffff_f
`define WB_AM3 20'hffff_f
`define WB_AM4 20'hffff_f
`define WB_AM5 20'hffff_f
 
// initial value for WB translation addresses. The initial values
// are set after reset. When ADDR_TRAN_IMPL is defined then then Images
// are transleted to this adresses whithout access to pci_ta registers.
`define WB_TA1 20'h2000_0
`define WB_TA2 20'h3000_0
`define WB_TA3 20'h4000_0
`define WB_TA4 20'h5000_0
`define WB_TA5 20'h6000_0
 
// If this define is commented out, then address translation will not be implemented.
// addresses will pass through bridge unchanged, regardles of address translation enable bits.
// Address translation also slows down the decoding
//When ADDR_TRAN_IMPL this define is present then adress translation is enabled after reset.
`define ADDR_TRAN_IMPL
 
// decode speed for WISHBONE definition - initial cycle on WISHBONE bus will take 1 WS for FAST, 2 WSs for MEDIUM and 3 WSs for slow.

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