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Rev 138 → Rev 139

/trunk/rtl/verilog/oc8051_defines.v
90,7 → 90,7
`define OC8051_ALU_RLC 4'b1011
`define OC8051_ALU_RR 4'b1100
`define OC8051_ALU_RRC 4'b1101
`define OC8051_ALU_PCS 4'b1110
`define OC8051_ALU_INC 4'b1110
`define OC8051_ALU_XCH 4'b1111
 
//
/trunk/rtl/verilog/oc8051_indi_addr.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2003/01/13 14:14:41 simont
// replace some modules
//
// Revision 1.4 2002/09/30 17:33:59 simont
// prepared header
//
55,95 → 58,64
// synopsys translate_on
 
 
module oc8051_indi_addr (clk, rst, rd_addr, wr_addr, data_in, wr, wr_bit, rn_out, ri_out, sel, bank);
module oc8051_indi_addr (clk, rst, wr_addr, data_in, wr, wr_bit, ri_out, sel, bank);
//
// clk (in) clock
// rst (in) reset
// addr (in) write address [oc8051_ram_wr_sel.out]
// data_in (in) data input (alu destination1) [oc8051_alu.des1]
// wr (in) write [oc8051_decoder.wr -r]
// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]
// data_out (out) data output [oc8051_ram_rd_sel.ri, oc8051_ram_wr_sel.ri -r]
// sel (in) select register [oc8051_op_select.op1_out[0] ]
// bank (in) select register bank: [oc8051_psw.data_out[4:3] ]
//
 
 
input clk, rst, wr, wr_bit;
input [1:0] bank;
input [2:0] sel;
input [7:0] data_in;
input [7:0] rd_addr, wr_addr;
input clk, // clock
rst, // reset
wr, // write
sel, // select register
wr_bit; // write bit addressable
input [1:0] bank; // select register bank
input [7:0] data_in; // data input
input [7:0] wr_addr; // write address
 
output [7:0] rn_out, ri_out;
output [7:0] ri_out;
 
reg [7:0] rn_out;
 
reg [7:0] buff [31:0];
//reg [7:0] buff [31:0];
reg wr_bit_r;
wire rd_ram, rd_ind;
 
 
wire tmp;
assign tmp = ~|wr_addr[7:5];
reg [7:0] buff [0:7];
 
//
//write to buffer
always @(posedge clk or posedge rst)
begin
if (rst) begin
buff[0] <= #1 8'h00;
buff[1] <= #1 8'h00;
buff[2] <= #1 8'h00;
buff[3] <= #1 8'h00;
buff[4] <= #1 8'h00;
buff[5] <= #1 8'h00;
buff[6] <= #1 8'h00;
buff[7] <= #1 8'h00;
buff[8] <= #1 8'h00;
buff[9] <= #1 8'h00;
buff[10] <= #1 8'h00;
buff[11] <= #1 8'h00;
buff[12] <= #1 8'h00;
buff[13] <= #1 8'h00;
buff[14] <= #1 8'h00;
buff[15] <= #1 8'h00;
buff[16] <= #1 8'h00;
buff[17] <= #1 8'h00;
buff[18] <= #1 8'h00;
buff[19] <= #1 8'h00;
buff[20] <= #1 8'h00;
buff[21] <= #1 8'h00;
buff[22] <= #1 8'h00;
buff[23] <= #1 8'h00;
buff[24] <= #1 8'h00;
buff[25] <= #1 8'h00;
buff[26] <= #1 8'h00;
buff[27] <= #1 8'h00;
buff[28] <= #1 8'h00;
buff[29] <= #1 8'h00;
buff[30] <= #1 8'h00;
buff[31] <= #1 8'h00;
end else if ((wr) && !(wr_bit_r) && (tmp)) begin
buff[wr_addr[4:0]] <= #1 data_in;
buff[3'b000] <= #1 8'h00;
buff[3'b001] <= #1 8'h00;
buff[3'b010] <= #1 8'h00;
buff[3'b011] <= #1 8'h00;
buff[3'b100] <= #1 8'h00;
buff[3'b101] <= #1 8'h00;
buff[3'b110] <= #1 8'h00;
buff[3'b111] <= #1 8'h00;
end else begin
if ((wr) & !(wr_bit_r)) begin
case (wr_addr)
8'h00: buff[3'b000] <= #1 data_in;
8'h01: buff[3'b001] <= #1 data_in;
8'h08: buff[3'b010] <= #1 data_in;
8'h09: buff[3'b011] <= #1 data_in;
8'h10: buff[3'b100] <= #1 data_in;
8'h11: buff[3'b101] <= #1 data_in;
8'h18: buff[3'b110] <= #1 data_in;
8'h19: buff[3'b111] <= #1 data_in;
endcase
end
end
end
 
//
//read from buffer
assign rd_ram = (rd_addr== wr_addr);
assign rd_ind = ({3'h0, bank, 2'b00, sel[0]}==wr_addr);
assign ri_out = ( rd_ind & (wr) & !wr_bit) ? data_in : buff[{bank, 2'b00, sel[0]}];
 
always @(posedge clk or posedge rst)
if (rst) begin
rn_out <= #1 8'h00;
end else if ( rd_ram & (wr) & !wr_bit) begin
rn_out <= #1 data_in;
end else begin
rn_out <= #1 buff[rd_addr[4:0]];
end
assign ri_out = (({3'b000, bank, 2'b00, sel}==wr_addr) & (wr) & !wr_bit_r) ?
data_in : buff[{bank, sel}];
 
 
 
always @(posedge clk or posedge rst)
if (rst) begin
wr_bit_r <= #1 1'b0;
/trunk/rtl/verilog/oc8051_alu.v
46,6 → 46,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.13 2003/04/29 08:35:12 simont
// fix bug in substraction.
//
// Revision 1.12 2003/04/25 17:15:51 simont
// change branch instruction execution (reduse needed clock periods).
//
68,8 → 71,8
 
 
 
module oc8051_alu (clk, rst, op_code, src1, src2, src3, srcCy, srcAc, bit_in, des1, des2, desCy,
desAc, desOv);
module oc8051_alu (clk, rst, op_code, src1, src2, src3, srcCy, srcAc, bit_in,
des1, des2, des_acc, desCy, desAc, desOv);
//
// op_code (in) operation code [oc8051_decoder.alu_op -r]
// src1 (in) first operand [oc8051_alu_src1_sel.des]
85,14 → 88,14
// desOv (out) Overflow output [oc8051_psw.ov_in]
//
 
input srcCy, srcAc, bit_in, clk, rst;
input [3:0] op_code;
input [7:0] src1, src2, src3;
output desCy, desAc, desOv;
output [7:0] des1, des2;
input srcCy, srcAc, bit_in, clk, rst;
input [3:0] op_code;
input [7:0] src1, src2, src3;
output desCy, desAc, desOv;
output [7:0] des1, des2, des_acc;
 
reg desCy, desAc, desOv;
reg [7:0] des1, des2;
reg [7:0] des1, des2, des_acc;
 
 
//
129,6 → 132,11
reg da_tmp;
//reg [8:0] da1;
 
//
// inc
//
wire [15:0] inc, dec;
 
oc8051_multiply oc8051_mul1(.clk(clk), .rst(rst), .enable(enable_mul), .src1(src1), .src2(src2), .des1(mulsrc1), .des2(mulsrc2), .desOv(mulOv));
oc8051_divide oc8051_div1(.clk(clk), .rst(rst), .enable(enable_div), .src1(src1), .src2(src2), .des1(divsrc1), .des2(divsrc2), .desOv(divOv));
 
164,14 → 172,20
assign subb = {1'b0,!sub8[3]};
assign subc = sub9-suba-subb;
 
/* inc */
assign inc = {src2, src1} + {15'h0, 1'b1};
assign dec = {src2, src1} - {15'h0, 1'b1};
 
always @(op_code or src1 or src2 or srcCy or srcAc or bit_in or src3 or mulsrc1 or mulsrc2 or mulOv or divsrc1 or divsrc2 or divOv or addc or add8 or add4 or sub4 or sub8 or subc or da_tmp)
always @(op_code or src1 or src2 or srcCy or srcAc or bit_in or src3 or mulsrc1
or mulsrc2 or mulOv or divsrc1 or divsrc2 or divOv or addc or add8 or add4
or sub4 or sub8 or subc or da_tmp or inc or dec)
begin
 
case (op_code)
//operation add
`OC8051_ALU_ADD: begin
des1 = {addc[0],add8[2:0],add4[3:0]};
des_acc = {addc[0],add8[2:0],add4[3:0]};
des1 = src1;
des2 = src3+ {7'b0, addc[1]};
desCy = addc[1];
desAc = add4[4];
182,7 → 196,8
end
//operation subtract
`OC8051_ALU_SUB: begin
des1 = {subc[0],sub8[2:0],sub4[3:0]};
des_acc = {subc[0],sub8[2:0],sub4[3:0]};
des1 = src1;
des2 = 8'h00;
desCy = !subc[1];
desAc = !sub4[4];
193,7 → 208,8
end
//operation multiply
`OC8051_ALU_MUL: begin
des1 = mulsrc1;
des_acc = mulsrc1;
des1 = src1;
des2 = mulsrc2;
desOv = mulOv;
desCy = 1'b0;
203,7 → 219,8
end
//operation divide
`OC8051_ALU_DIV: begin
des1 = divsrc1;
des_acc = divsrc1;
des1 = src1;
des2 = divsrc2;
desOv = divOv;
desAc = 1'bx;
214,13 → 231,15
//operation decimal adjustment
`OC8051_ALU_DA: begin
 
if (srcAc==1'b1 | src1[3:0]>4'b1001) {da_tmp, des1[3:0]} = {1'b0, src1[3:0]}+ 5'b00110;
else {da_tmp, des1[3:0]} = {1'b0, src1[3:0]};
if (srcAc==1'b1 | src1[3:0]>4'b1001) {da_tmp, des_acc[3:0]} = {1'b0, src1[3:0]}+ 5'b00110;
else {da_tmp, des_acc[3:0]} = {1'b0, src1[3:0]};
 
if (srcCy==1'b1 | src1[7:4]>4'b1001)
{desCy, des1[7:4]} = {srcCy, src1[7:4]}+ 5'b00110 + {4'b0, da_tmp};
else {desCy, des1[7:4]} = {srcCy, src1[7:4]} + {4'b0, da_tmp};
{desCy, des_acc[7:4]} = {srcCy, src1[7:4]}+ 5'b00110 + {4'b0, da_tmp};
else {desCy, des_acc[7:4]} = {srcCy, src1[7:4]} + {4'b0, da_tmp};
 
des1 = src1;
 
des2 = 8'h00;
desAc = 1'b0;
desOv = 1'b0;
230,6 → 249,7
//operation not
// bit operation not
`OC8051_ALU_NOT: begin
des_acc = ~src1;
des1 = ~src1;
des2 = 8'h00;
desCy = !srcCy;
241,6 → 261,7
//operation and
//bit operation and
`OC8051_ALU_AND: begin
des_acc = src1 & src2;
des1 = src1 & src2;
des2 = 8'h00;
desCy = srcCy & bit_in;
252,6 → 273,7
//operation xor
// bit operation xor
`OC8051_ALU_XOR: begin
des_acc = src1 ^ src2;
des1 = src1 ^ src2;
des2 = 8'h00;
desCy = srcCy ^ bit_in;
263,6 → 285,7
//operation or
// bit operation or
`OC8051_ALU_OR: begin
des_acc = src1 | src2;
des1 = src1 | src2;
des2 = 8'h00;
desCy = srcCy | bit_in;
274,7 → 297,8
//operation rotate left
// bit operation cy= cy or (not ram)
`OC8051_ALU_RL: begin
des1 = {src1[6:0], src1[7]};
des_acc = {src1[6:0], src1[7]};
des1 = src1 ;
des2 = 8'h00;
desCy = srcCy | !bit_in;
desAc = 1'bx;
284,7 → 308,8
end
//operation rotate left with carry and swap nibbles
`OC8051_ALU_RLC: begin
des1 = {src1[6:0], srcCy};
des_acc = {src1[6:0], srcCy};
des1 = src1 ;
des2 = {src1[3:0], src1[7:4]};
desCy = src1[7];
desAc = 1'b0;
294,7 → 319,8
end
//operation rotate right
`OC8051_ALU_RR: begin
des1 = {src1[0], src1[7:1]};
des_acc = {src1[0], src1[7:1]};
des1 = src1 ;
des2 = 8'h00;
desCy = srcCy & !bit_in;
desAc = 1'b0;
304,7 → 330,8
end
//operation rotate right with carry
`OC8051_ALU_RRC: begin
des1 = {srcCy, src1[7:1]};
des_acc = {srcCy, src1[7:1]};
des1 = src1 ;
des2 = 8'h00;
desCy = src1[0];
desAc = 1'b0;
313,25 → 340,32
enable_div = 1'b0;
end
//operation pcs Add
/* `OC8051_ALU_PCS: begin
if (src1[7]) begin
{desCy, des1} = {1'b0, src2} + {1'b0, src1};
des2 = {1'b0, src3} - {8'h0, !desCy};
end else {des2, des1} = {src3,src2} + {8'h00, src1};
`OC8051_ALU_INC: begin
if (srcCy) begin
des_acc = dec[7:0];
des1 = dec[7:0];
des2 = dec[15:8];
end else begin
des_acc = inc[7:0];
des1 = inc[7:0];
des2 = inc[15:8];
end
desCy = 1'b0;
desAc = 1'b0;
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end*/
end
//operation exchange
//if carry = 0 exchange low order digit
`OC8051_ALU_XCH: begin
if (srcCy)
begin
des_acc = src2;
des1 = src2;
des2 = src1;
end else begin
des_acc = {src1[7:4],src2[3:0]};
des1 = {src1[7:4],src2[3:0]};
des2 = {src2[7:4],src1[3:0]};
end
342,6 → 376,7
enable_div = 1'b0;
end
default: begin
des_acc = src1;
des1 = src1;
des2 = src2;
desCy = srcCy;
/trunk/rtl/verilog/oc8051_memory_interface.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2003/04/25 17:15:51 simont
// change branch instruction execution (reduse needed clock periods).
//
// Revision 1.4 2003/04/16 10:04:09 simont
// chance idat_ir to 24 bit wide
//
89,10 → 92,10
intr, int_v, int_ack,
 
//alu
des1, des2,
des_acc, des1, des2,
 
//sfr's
dptr, ri, rn_mem, sp, sp_w, rn, acc, reti);
dptr, ri, sp, sp_w, rn, acc, reti);
 
input bit_in, sfr_bit, dack_i;
input [2:0] mem_act;
104,7 → 107,7
 
reg bit_out, reti;
reg [7:0] iram_out, sp_r;
reg [2:0] rd_addr_r;
reg rd_addr_r;
input clk, rst, wr_i, wr_bit_i;
output wr_o, wr_bit_o;
 
119,7 → 122,7
//
/////////////////////////////
input iack_i;
input [7:0] des1, des2;
input [7:0] des_acc, des1, des2;
output [15:0] iadr_o;
 
wire ea_rom_sel;
129,7 → 132,7
// ext_addr_sel
//
/////////////////////////////
input [7:0] ri, rn_mem, ddat_i;
input [7:0] ri, ddat_i;
input [15:0] dptr;
 
output dstb_o, dwe_o;
216,7 → 219,7
assign bank = rn[4:3];
assign imm = op2_out;
assign imm2 = op3_out;
assign alu = {des2,des1};
assign alu = {des2, des_acc};
assign ea_rom_sel = ea && ea_int;
assign wr_o = wr_i;
assign wr_bit_o = wr_bit_i;
234,15 → 237,12
//
// ram_select
//
/////////////////////////////
always @(rd_addr_r or in_ram or sfr or bit_in or sfr_bit or rn_mem or rd_ind)
///////////////////////////// ??????????????????????
always @(rd_addr_r or in_ram or sfr or bit_in or sfr_bit or rd_ind)
begin
if (rd_addr_r[2] && !rd_ind) begin
if (rd_addr_r && !rd_ind) begin
iram_out = sfr;
bit_out = sfr_bit;
end else if (~|rd_addr_r[2:0]) begin
iram_out = rn_mem;
bit_out = bit_in;
end else begin
iram_out = in_ram;
bit_out = bit_in;
257,18 → 257,18
 
always @(rd_sel or sp or ri or rn or imm or op1_out or dadr_o[15:0] or bank)
begin
case (rd_sel)
`OC8051_RRS_RN : rd_addr = {3'h0, rn};
`OC8051_RRS_I : rd_addr = ri;
`OC8051_RRS_D : rd_addr = imm;
`OC8051_RRS_SP : rd_addr = sp;
case (rd_sel)
`OC8051_RRS_RN : rd_addr = {3'h0, rn};
`OC8051_RRS_I : rd_addr = ri;
`OC8051_RRS_D : rd_addr = imm;
`OC8051_RRS_SP : rd_addr = sp;
 
`OC8051_RRS_B : rd_addr = `OC8051_SFR_B;
`OC8051_RRS_DPTR : rd_addr = `OC8051_SFR_DPTR_LO;
`OC8051_RRS_PSW : rd_addr = `OC8051_SFR_PSW;
`OC8051_RRS_ACC : rd_addr = `OC8051_SFR_ACC;
default : rd_addr = 2'bxx;
endcase
`OC8051_RRS_B : rd_addr = `OC8051_SFR_B;
`OC8051_RRS_DPTR : rd_addr = `OC8051_SFR_DPTR_LO;
`OC8051_RRS_PSW : rd_addr = `OC8051_SFR_PSW;
`OC8051_RRS_ACC : rd_addr = `OC8051_SFR_ACC;
default : rd_addr = 2'bxx;
endcase
 
end
 
277,15 → 277,15
//
always @(wr_sel or sp_w or rn_r or imm_r or ri_r or imm2_r or op1_r or dadr_o[15:0])
begin
case (wr_sel)
`OC8051_RWS_RN : wr_addr = {3'h0, rn_r};
`OC8051_RWS_I : wr_addr = ri_r;
`OC8051_RWS_D : wr_addr = imm_r;
`OC8051_RWS_SP : wr_addr = sp_w;
`OC8051_RWS_D3 : wr_addr = imm2_r;
`OC8051_RWS_B : wr_addr = `OC8051_SFR_B;
default : wr_addr = 2'bxx;
endcase
case (wr_sel)
`OC8051_RWS_RN : wr_addr = {3'h0, rn_r};
`OC8051_RWS_I : wr_addr = ri_r;
`OC8051_RWS_D : wr_addr = imm_r;
`OC8051_RWS_SP : wr_addr = sp_w;
`OC8051_RWS_D3 : wr_addr = imm2_r;
`OC8051_RWS_B : wr_addr = `OC8051_SFR_B;
default : wr_addr = 2'bxx;
endcase
end
 
always @(posedge clk or posedge rst)
312,7 → 312,7
// output address is alu destination
// (instructions MOVC)
 
assign iadr_ot = istb_t ? iadr_t : pc;
assign iadr_ot = (istb_t & !iack_i) ? iadr_t : pc;
assign iadr_o = iadr_ot;
 
 
332,7 → 332,7
end else if (ea_rom_sel && !imem_wait && istb_t) begin
istb_t <= #1 1'b0;
end else if (mem_act==`OC8051_MAS_CODE) begin
iadr_t <= #1 {des2, des1};
iadr_t <= #1 alu;
istb_t <= #1 1'b1;
imem_wait <= #1 1'b1;
end
497,7 → 497,7
//
/////////////////////////////
 
always @(pc_buf or op1_out or pc_wait or int_buff or int_buff1 or alu[7:0] or ea_rom_sel or iack_i)
always @(pc_buf or op1_out or pc_wait or int_buff or int_buff1 or ea_rom_sel or iack_i)
begin
if (int_buff || int_buff1) begin
//
655,7 → 655,7
ri_r <= #1 8'h00;
imm_r <= #1 8'h00;
imm2_r <= #1 8'h00;
rd_addr_r <= #1 3'h0;
rd_addr_r <= #1 1'b0;
op1_r <= #1 8'h0;
dack_ir <= #1 1'b0;
sp_r <= #1 1'b0;
664,7 → 664,7
ri_r <= #1 ri;
imm_r <= #1 imm;
imm2_r <= #1 imm2;
rd_addr_r <= #1 rd_addr[7:5];
rd_addr_r <= #1 rd_addr[7];
op1_r <= #1 op1_out;
dack_ir <= #1 dack_i;
sp_r <= #1 sp;
/trunk/rtl/verilog/oc8051_sfr.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12 2003/04/29 11:24:31 simont
// fix bug in case execution of two data dependent instructions.
//
// Revision 1.11 2003/04/25 17:15:51 simont
// change branch instruction execution (reduse needed clock periods).
//
89,6 → 92,7
module oc8051_sfr (rst, clk,
adr0, adr1, dat0,
dat1, dat2, bit_in,
des_acc,
we, wr_bit,
bit_out,
wr_sfr, acc,
95,7 → 99,7
ram_wr_sel, ram_rd_sel,
sp, sp_w,
bank_sel,
desAc, desOv,
desAc, desOv,
srcAc, cy,
psw_set, rmw,
comp_sel,
166,6 → 170,7
ram_wr_sel;
input [7:0] adr0, //address 0 input
adr1, //address 1 input
des_acc,
dat1, //data 1 input (des1)
dat2; //data 2 input (des2)
 
300,13 → 305,13
oc8051_acc oc8051_acc1(.clk(clk),
.rst(rst),
.bit_in(bit_in),
.data_in(dat1),
.data2_in(dat2),
.wr(we),
.wr_bit(wr_bit_r),
.data_in(des_acc),
.data2_in(dat2),
.wr(we),
.wr_bit(wr_bit_r),
.wr_sfr(wr_sfr),
.wr_addr(adr1),
.data_out(acc),
.wr_addr(adr1),
.data_out(acc),
.p(p));
 
 
313,10 → 318,10
//
// b register
// B
oc8051_b_register oc8051_b_register (.clk(clk),
.rst(rst),
oc8051_b_register oc8051_b_register (.clk(clk),
.rst(rst),
.bit_in(bit_in),
.data_in(dat1),
.data_in(des_acc),
.wr(we),
.wr_bit(wr_bit_r),
.wr_addr(adr1),
342,7 → 347,7
oc8051_dptr oc8051_dptr1(.clk(clk),
.rst(rst),
.addr(adr1),
.data_in(dat1),
.data_in(des_acc),
.data2_in(dat2),
.wr(we),
.wr_bit(wr_bit_r),
/trunk/rtl/verilog/oc8051_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.26 2003/04/29 11:24:31 simont
// fix bug in case execution of two data dependent instructions.
//
// Revision 1.25 2003/04/25 17:15:51 simont
// change branch instruction execution (reduse needed clock periods).
//
230,7 → 233,6
dptr_hi,
dptr_lo,
ri,
rn_mem,
data_out,
op1,
op2,
282,6 → 284,7
wire [7:0] src1, //alu sources 1
src2, //alu sources 2
src3, //alu sources 3
des_acc,
des1, //alu destination 1
des2; //alu destinations 2
wire desCy, //carry out
357,7 → 360,7
//
//alu
oc8051_alu oc8051_alu1(.rst(wb_rst_i),
.clk(wb_clk_i),
.clk(wb_clk_i),
.op_code(alu_op),
.src1(src1),
.src2(src2),
364,6 → 367,7
.src3(src3),
.srcCy(alu_cy),
.srcAc(srcAc),
.des_acc(des_acc),
.des1(des1),
.des2(des2),
.desCy(desCy),
414,7 → 418,7
.b_in(bit_out),
.cy(cy),
.acc(acc),
.des(des1)
.des(des_acc)
);
 
 
445,14 → 449,12
//
oc8051_indi_addr oc8051_indi_addr1 (.clk(wb_clk_i),
.rst(wb_rst_i),
.rd_addr(rd_addr),
.wr_addr(wr_addr),
.data_in(wr_dat),
.data_in(wr_dat),
.wr(wr_o),
.wr_bit(bit_addr_o),
.rn_out(rn_mem),
.ri_out(ri),
.sel(op1_cur),
.ri_out(ri),
.sel(op1_cur[0]),
.bank(bank_sel));
 
 
468,15 → 470,16
.wr_bit_i(bit_addr),
.wr_bit_o(bit_addr_o),
.wr_dat(wr_dat),
.des_acc(des_acc),
.des1(des1),
.des2(des2),
.rd_addr(rd_addr),
.rd_addr(rd_addr),
.wr_addr(wr_addr),
.wr_ind(wr_ind),
.bit_in(bit_data),
.bit_in(bit_data),
.in_ram(ram_data),
.sfr(sfr_out),
.sfr_bit(sfr_bit),
.sfr(sfr_out),
.sfr_bit(sfr_bit),
.bit_out(bit_out),
.iram_out(ram_out),
 
487,34 → 490,34
.istb_o(istb_o),
 
// internal instruction rom
.op1_i(op1_i),
.op2_i(op2_i),
.op1_i(op1_i),
.op2_i(op2_i),
.op3_i(op3_i),
 
// data memory
.dadr_o(wbd_adr_o),
.dadr_o(wbd_adr_o),
.ddat_o(wbd_dat_o),
.dwe_o(wbd_we_o),
.dwe_o(wbd_we_o),
.dstb_o(wbd_stb_o),
.ddat_i(wbd_dat_i),
.ddat_i(wbd_dat_i),
.dack_i(wbd_ack_i),
 
// from decoder
.rd_sel(ram_rd_sel),
.wr_sel(ram_wr_sel),
.rd_sel(ram_rd_sel),
.wr_sel(ram_wr_sel),
.rn({bank_sel, op1_cur}),
.rd_ind(rd_ind),
.rd(rd),
.mem_act(mem_act),
.mem_act(mem_act),
.mem_wait(mem_wait),
 
// external access
.ea(ea_in),
.ea(ea_in),
.ea_int(ea_int),
 
// instructions outputs to cpu
.op1_out(op1_n),
.op2_out(op2_n),
.op1_out(op1_n),
.op2_out(op2_n),
.op3_out(op3_n),
 
// interrupt interface
533,8 → 536,7
.sp_w(sp_w),
.dptr({dptr_hi, dptr_lo}),
.ri(ri),
.rn_mem(rn_mem),
.acc(acc),
.acc(acc),
.sp(sp)
);
 
546,10 → 548,11
.clk(wb_clk_i),
.adr0(rd_addr[7:0]),
.adr1(wr_addr[7:0]),
.dat0(sfr_out),
.dat1(wr_dat),
.dat2(des2),
.we(wr_o && !wr_ind),
.dat0(sfr_out),
.dat1(wr_dat),
.dat2(des2),
.des_acc(des_acc),
.we(wr_o && !wr_ind),
.bit_in(desCy),
.bit_out(sfr_bit),
.wr_bit(bit_addr_o),
/trunk/rtl/verilog/oc8051_decoder.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.17 2003/04/25 17:15:51 simont
// change branch instruction execution (reduse needed clock periods).
//
// Revision 1.16 2003/04/09 16:24:03 simont
// change wr_sft to 2 bit wire.
//
1039,7 → 1042,7
pc_sel = `OC8051_PIS_SO2;
comp_sel = `OC8051_CSS_BIT;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
stb_i = 1'b0;
bit_addr = 1'b1;
end
`OC8051_JBC : begin
1048,7 → 1051,7
pc_sel = `OC8051_PIS_DC;
comp_sel = `OC8051_CSS_BIT;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
stb_i = 1'b0;
bit_addr = 1'b1;
end
`OC8051_JC : begin
1057,7 → 1060,7
pc_sel = `OC8051_PIS_SO1;
comp_sel = `OC8051_CSS_CY;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
stb_i = 1'b0;
bit_addr = 1'b0;
end
`OC8051_JMP_D : begin
1076,7 → 1079,7
pc_sel = `OC8051_PIS_SO2;
comp_sel = `OC8051_CSS_BIT;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
stb_i = 1'b0;
bit_addr = 1'b1;
end
`OC8051_JNC : begin
1085,7 → 1088,7
pc_sel = `OC8051_PIS_SO1;
comp_sel = `OC8051_CSS_CY;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
stb_i = 1'b0;
bit_addr = 1'b0;
end
`OC8051_JNZ : begin
1094,7 → 1097,7
pc_sel = `OC8051_PIS_SO1;
comp_sel = `OC8051_CSS_AZ;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
stb_i = 1'b0;
bit_addr = 1'b0;
end
`OC8051_JZ : begin
1103,7 → 1106,7
pc_sel = `OC8051_PIS_SO1;
comp_sel = `OC8051_CSS_AZ;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
stb_i = 1'b0;
bit_addr = 1'b0;
end
`OC8051_LCALL :begin
1392,7 → 1395,7
pc_sel = `OC8051_PIS_SO1;
comp_sel = `OC8051_CSS_DC;
rmw = `OC8051_RMW_N;
stb_i = 1'b1;
stb_i = 1'b0;
bit_addr = 1'b0;
end
`OC8051_SUBB_D : begin
1800,7 → 1803,7
ram_wr_sel <= #1 `OC8051_RWS_RN;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ZERO;
alu_op <= #1 `OC8051_ALU_SUB;
alu_op <= #1 `OC8051_ALU_INC;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_1;
1811,7 → 1814,7
ram_wr_sel <= #1 `OC8051_RWS_RN;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ZERO;
alu_op <= #1 `OC8051_ALU_SUB;
alu_op <= #1 `OC8051_ALU_INC;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_1;
1822,10 → 1825,10
ram_wr_sel <= #1 `OC8051_RWS_RN;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ZERO;
alu_op <= #1 `OC8051_ALU_ADD;
alu_op <= #1 `OC8051_ALU_INC;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_1;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
1978,7 → 1981,7
ram_wr_sel <= #1 `OC8051_RWS_I;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ZERO;
alu_op <= #1 `OC8051_ALU_SUB;
alu_op <= #1 `OC8051_ALU_INC;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_1;
1989,10 → 1992,10
ram_wr_sel <= #1 `OC8051_RWS_I;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ZERO;
alu_op <= #1 `OC8051_ALU_ADD;
alu_op <= #1 `OC8051_ALU_INC;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_1;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
2343,7 → 2346,7
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_ZERO;
alu_op <= #1 `OC8051_ALU_SUB;
alu_op <= #1 `OC8051_ALU_INC;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_1;
2354,7 → 2357,7
ram_wr_sel <= #1 `OC8051_RWS_D;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ZERO;
alu_op <= #1 `OC8051_ALU_SUB;
alu_op <= #1 `OC8051_ALU_INC;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_1;
2376,7 → 2379,7
ram_wr_sel <= #1 `OC8051_RWS_D;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ZERO;
alu_op <= #1 `OC8051_ALU_SUB;
alu_op <= #1 `OC8051_ALU_INC;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_1;
2387,10 → 2390,10
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_ACC;
src_sel2 <= #1 `OC8051_AS2_ZERO;
alu_op <= #1 `OC8051_ALU_ADD;
alu_op <= #1 `OC8051_ALU_INC;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_1;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_ACC1;
end
2398,10 → 2401,10
ram_wr_sel <= #1 `OC8051_RWS_D;
src_sel1 <= #1 `OC8051_AS1_RAM;
src_sel2 <= #1 `OC8051_AS2_ZERO;
alu_op <= #1 `OC8051_ALU_ADD;
alu_op <= #1 `OC8051_ALU_INC;
wr <= #1 1'b1;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_1;
cy_sel <= #1 `OC8051_CY_0;
src_sel3 <= #1 `OC8051_AS3_DC;
wr_sfr <= #1 `OC8051_WRS_N;
end
2418,9 → 2421,9
end
`OC8051_JB : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP3;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
2429,9 → 2432,9
end
`OC8051_JBC :begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP3;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
2440,9 → 2443,9
end
`OC8051_JC : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP2;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
2462,9 → 2465,9
end
`OC8051_JNB : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP3;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
2473,9 → 2476,9
end
`OC8051_JNC : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP2;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
2484,9 → 2487,9
end
`OC8051_JNZ :begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP2;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;
2495,9 → 2498,9
end
`OC8051_JZ : begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_OP2;
src_sel2 <= #1 `OC8051_AS2_PCL;
alu_op <= #1 `OC8051_ALU_PCS;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
alu_op <= #1 `OC8051_ALU_NOP;
wr <= #1 1'b0;
psw_set <= #1 `OC8051_PS_NOT;
cy_sel <= #1 `OC8051_CY_0;

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