OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /
    from Rev 1386 to Rev 1387
    Reverse comparison

Rev 1386 → Rev 1387

/trunk/or1ksim/pic/pic.h
19,5 → 19,4
 
/* Prototypes */
void pic_reset();
inline void pic_clock();
void report_interrupt(int line);
/trunk/or1ksim/pic/pic.c
39,6 → 39,7
#include "except.h"
#include "sprs.h"
#include "debug.h"
#include "sched.h"
 
extern int cont_run;
 
51,16 → 52,19
mtspr(SPR_PICSR, 0);
}
 
/* Simulation hook. Must be called every clock cycle to simulate PIC
It does internal functional PIC simulation. */
inline void pic_clock()
/* Simulation hook. Called when interrupts are masked. */
void pic_clock(int i)
{
/* Don't do anything if interrupts not currently enabled or
higher priority exception was allready reported */
if(mfspr(SPR_PICSR) && testsprbits (SPR_SR, SPR_SR_IEE) && !pending.valid)
/* Don't do anything if interrupts not currently enabled */
if(testsprbits (SPR_SR, SPR_SR_IEE))
except_handle(EXCEPT_INT, mfspr(SPR_EEAR_BASE));
else
SCHED_ADD(pic_clock, 0, 1);
}
 
/* WARNING: Don't eaven try and call this function *during* a simulated
* instruction!! (as in during a read_mem or write_mem callback). except_handle
* assumes that this is the case, it breaks otherwise. */
/* Asserts interrupt to the PIC. */
void report_interrupt(int line)
{
69,6 → 73,13
 
debug(4, "Asserting interrupt %d (%s).\n", line, getsprbit(SPR_PICMR, line) ? "Unmasked" : "Masked");
 
if (getsprbit(SPR_PICMR, line) || line < 2)
if (getsprbit(SPR_PICMR, line) || line < 2) {
setsprbit(SPR_PICSR, line, 1);
/* Don't do anything if interrupts not currently enabled */
if (testsprbits (SPR_SR, SPR_SR_IEE))
except_handle(EXCEPT_INT, mfspr(SPR_EEAR_BASE));
else
/* Interrupts not currently enabled, retry next clock cycle */
SCHED_ADD(pic_clock, 0, runtime.sim.cycles + 1);
}
}
/trunk/or1ksim/toplevel.c
68,7 → 68,7
#include "cuc.h"
 
/* CVS revision number. */
const char rcsrev[] = "$Revision: 1.116 $";
const char rcsrev[] = "$Revision: 1.117 $";
 
inline void debug(int level, const char *format, ...)
{
419,7 → 419,6
runtime.sim.mem_cycles = 0;
if (!config.pm.enabled || !testsprbits(SPR_PMR, SPR_PMR_DME | SPR_PMR_SME)) {
if (runtime.sim.cont_run > 0) runtime.sim.cont_run--;
pic_clock ();
if (cpu_clock ()) break;
if (config.dc.enabled) dc_clock();
if (config.ic.enabled) ic_clock();

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.