Rev 14 → Rev 15
tags/REL/images/tbschematic.jpg
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: tags/REL/images/timing.jpg
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/REL/images/timing.jpg
===================================================================
--- tags/REL/images/timing.jpg (revision 14)
+++ tags/REL/images/timing.jpg (nonexistent)
tags/REL/images/timing.jpg
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: tags/REL/doc/single_port.html
===================================================================
--- tags/REL/doc/single_port.html (revision 14)
+++ tags/REL/doc/single_port.html (nonexistent)
@@ -1,213 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B"H
-
Description
-of single_port memory and test environment.
-
Abstract:
-
A single port memory with testbench is described. The memory is
-implemented as three different architectures.
-
Port Interface:
-
-
-
- Port Name
- |
-
- Type
- |
-
- Description
- |
-
-
-
-
- rnwtQ
- |
-
- Time
- |
-
- Time delay from rnw = read until data appears on q data bus.
- |
-
-
-
- d
- |
-
- data_inter_typ
- |
-
- Input data bus, type specified in single_port_pkg
- |
-
-
-
- q
- |
-
- data_inter_typ
- |
-
- Output data bus, type specified in single_port_pkg
- |
-
-
-
- a
- |
-
- addr_inter_typ
- |
-
- Address bus, type specified in single_port_pkg
- |
-
-
-
- rnw
- |
-
- STD_LOGIC
- |
-
- Read not write port
- |
-
-
-
- dealloc_mem
- |
-
- BOOLEAN
- |
-
- When set to true, deallocate linked list memory.
- |
-
-
-
-
-
Functional Description:
-
The single_port memory is implemented as three different
-architecures. The first architecture is called ArrayMemNoFlag, and
-implements the memory core as an array of STD_LOGIC_VECTOR. The memory
-is asynchronous and triggered on rnw'transaction. When rnw = '0', the
-data on bus "d" is loaded into the memory at the location specified by
-the addres bus "a". When rnw = '1', the data located in memory address
-"a" is loaded onto the output data bus "q". If a memory location is read
-which was not written to during the current simulation, 'U' are loaded
-onto the memory bus.
-
The second architecture is called ArrayMem, and implements the
-memory core as an array of BIT_VECTOR. This arrangement allows less
-workstation memory to be used than the ArrayMemNoFlag architecture. The
-memory is asynchronous and triggered on rnw'transaction. When rnw = '0',
-the data on bus "d" is loaded into the memory at the location specified
-by the addres bus "a". When rnw = '1', the data located in memory
-address "a" is loaded onto the output data bus "q". If a memory location
-is read which was not written to during the current simulation, 'U' are
-loaded onto the memory bus.
-
The third architecture is called LinkedList, and implements the
-memory core as a linked list of arrays of BIT_VECTOR. Each array in the
-linked list is a page of memory whose size is specified in
-single_port_pkg. This arrangement allows less workstation memory to be
-used than either the ArrayMemNoFlag or ArrayMem architectures. The
-memory is asynchronous and triggered on rnw'transaction. When rnw = '0',
-the data on bus "d" is loaded into the memory at the location specified
-by the addres bus "a". When rnw = '1', the data located in memory
-address "a" is loaded onto the output data bus "q". If a memory location
-is read which was not written to during the current simulation, 'U' are
-loaded onto the memory bus. To de-allocate the memory in the linked
-list, set dealloc_mem to true.
-
Functional Timing:
-
The single port memory is asynchronous and is triggered on
-rnw'transaction. When rnw is cleared to '0', the write occurs at the
-same time as rnw'transaction. When a read occurs, with rnw = '1' , data
-appears on the Q bus rnwtQ ns after rnw is set to '1'. The below sample
-timing diagram illustrates both a read and write operation.
-
-
-
Testbench Description:
-
The test bench is arranged as a client server architecture as
-specified by Bergeron. A diagram illustrating the
-testbench is given below.
-
-
-Two tests are specified in tc_single_port component. The first test
-writes data to two logical memory pages, and then reads them back
-verifying the correct data. The test case writes an error message to the
-console for every miscompare. The second case verifies that the
-single_port memory model outputs unknowns to the q bus if a read occurs
-for an unwritten memory location. Six configurations are specified in
-the test bench architecture tb_single_port, running both tests for each
-single_port architecture.
-
-
Usage:
-
A Makefile is used to compile and run all of the tests in a Unix or
-like environment, such as Cygwin. The compilation and simulation is
-targetted to the SymphonyEDA tool available at www.symphonyeda.com .
-
The source files and Makefile are located in {top}/VHDL
-
-To compile: make com
-
To simulate all of the tests: make sim
-
-
To clean the compiled library: make clean
-
The tests are labeled :
-
- - ll_error
- - ll_main
- - mem_main
-
- - mem_error
-
- - memnoflag_main
-
- - memnoflag_error
-
-
-
To simulate any of these tests, type make {testname}
-
Please contact Robert Paley at rpaley_yid@opencores.org
-if you have any questions or comments.
-
-
-
Index: tags/REL/VHDL/single_port.vhd
===================================================================
--- tags/REL/VHDL/single_port.vhd (revision 14)
+++ tags/REL/VHDL/single_port.vhd (nonexistent)
@@ -1,131 +0,0 @@
--- $Author: rpaley_yid $
--- $Date: 2003-01-14 21:48:11 $
--- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/single_port.vhd,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $
--- $Locker
--- $Revision: 1.1.1.1 $
--- $State: Exp $
-
--- --------------------------------------------------------------------------
---
--- Purpose: This is a single port asynchronous memory. This files
--- describes three architectures. Two architectures are traditional
--- array based memories. One describes the memory as an array of
--- STD_LOGIC_VECTOR, and the other describes the ARRAY as BIT_VECTOR.
--- The third architecture describes the memory arranged as a linked
--- list in order to conserve computer memory usage. The memory
--- is organized as a linked list of BIT_VECTOR arrays whose size
--- is defined PAGEDEPTH in single_port_pkg.vhd.
---
---
--- References:
--- 1. The Designer's Guide to VHDL by Peter Ashenden
--- ISBN: 1-55860-270-4 (pbk.)
--- 2. Writing Testbenches - Functional Verification of HDL models by
--- Janick Bergeron | ISBN: 0-7923-7766-4
---
--- Notes:
---
--- --------------------------------------------------------------------------
-LIBRARY IEEE;
-LIBRARY WORK;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE WORK.single_port_pkg.ALL;
-USE WORK.linked_list_mem_pkg.ALL;
-
-ENTITY single_port IS
- GENERIC (
- rnwtQ : TIME := 1 NS
- );
- PORT (
- d : IN data_inter_typ;
- q : OUT data_inter_typ;
- a : IN addr_inter_typ;
- rnw : IN STD_LOGIC;
- dealloc_mem : IN BOOLEAN
- );
-END ENTITY single_port;
-
-ARCHITECTURE ArrayMemNoFlag OF single_port IS
-BEGIN
-
- mem_proc : PROCESS
- TYPE mem_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1) OF data_inter_typ;
- VARIABLE mem : mem_typ;
- BEGIN
- WAIT on rnw'transaction;
- IF ( rnw = '0') THEN -- Write
- mem(TO_INTEGER(unsigned(a))) := d;
- ELSE -- Read
- q <= mem(TO_INTEGER(unsigned(a))) AFTER rnwtQ;
- END IF;
- END PROCESS mem_proc;
-
-END ArrayMemNoFlag;
-
-ARCHITECTURE ArrayMem OF single_port IS
-BEGIN
-
- mem_proc : PROCESS
- TYPE mem_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1 ) OF data_typ;
- TYPE flag_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1 ) OF BOOLEAN;
- VARIABLE mem : mem_typ;
- VARIABLE flag : flag_typ;
- BEGIN
- WAIT ON rnw'transaction;
- IF ( rnw = '0') THEN -- Write
- mem(TO_INTEGER(unsigned(a))) := TO_BITVECTOR(d);
- flag(TO_INTEGER(unsigned(a))) := true; -- set valid memory location flag
- ELSE -- read data, either valid or 'U'
- IF ( flag(TO_INTEGER(unsigned(a))) = true ) THEN
- q <= TO_STDLOGICVECTOR(mem(TO_INTEGER(unsigned(a)))) AFTER rnwtQ;
- ELSE -- reading invalid memory location
- q <= (OTHERS => 'U') after rnwtQ;
- END IF;
- END IF;
- END PROCESS mem_proc;
-END ArrayMem;
-
-ARCHITECTURE LinkedList OF single_port IS
- BEGIN
-
- mem_proc : PROCESS
- VARIABLE mem_page_v : mem_page_ptr;
- VARIABLE d_v : data_inter_typ;
- VARIABLE a_v : addr_typ;
- VARIABLE WRITE_MEM_v : BOOLEAN := true;
- VARIABLE READ_MEM_v : BOOLEAN := false;
- BEGIN
- WAIT ON dealloc_mem'transaction , rnw'TRANSACTION;
- IF NOT dealloc_mem THEN
- d_v := d;
- a_v := TO_INTEGER(unsigned(a));
- IF ( rnw = '0' ) THEN -- write to linked list memory
- rw_mem( data => d_v,
- addr => a_v,
- write_flag => WRITE_MEM_v,
- next_cell => mem_page_v
- );
- ELSE -- read from linked list memory
- rw_mem( data => d_v,
- addr => a_v,
- write_flag => READ_MEM_v,
- next_cell => mem_page_v
- );
- q <= d_v after rnwtQ;
- END IF;
- ELSE -- Deallocate memory from work station memory.
- deallocate_mem(mem_page_v);
- END IF;
- END PROCESS mem_proc;
-
-END LinkedList;
-
--- $Log: not supported by cvs2svn $
--- Revision 1.1 2003/01/14 17:48:31 Default
--- Initial revision
---
--- Revision 1.1 2002/12/24 18:09:05 Default
--- Initial revision
---
-
Index: tags/REL/VHDL/single_port_pkg.vhd
===================================================================
--- tags/REL/VHDL/single_port_pkg.vhd (revision 14)
+++ tags/REL/VHDL/single_port_pkg.vhd (nonexistent)
@@ -1,70 +0,0 @@
--- $Author: rpaley_yid $
--- $Date: 2003-01-14 21:48:11 $
--- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/single_port_pkg.vhd,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $
--- $Locker: $
--- $Revision: 1.1.1.1 $
--- $State: Exp $
-
--- --------------------------------------------------------------------------
---
--- Purpose: Package file for single_port memory and testbench
---
--- References:
--- 1. The Designer's Guide to VHDL by Peter Ashenden
--- ISBN: 1-55860-270-4 (pbk.)
--- 2. Writing Testbenches - Functional Verification of HDL models by
--- Janick Bergeron | ISBN: 0-7923-7766-4
---
--- Notes:
---
--- --------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-PACKAGE single_port_pkg IS
-CONSTANT PAGEDEPTH : INTEGER := 256; -- memory page depth
-CONSTANT PAGENUM : INTEGER := 4096; -- number of pages in memory.
-CONSTANT DATA_WIDTH : INTEGER := 32; -- memory data bus width
-CONSTANT ADDRESS_WIDTH : INTEGER := 16; -- memory address bus width
--- Data bus type for memory interface
-SUBTYPE data_inter_typ IS STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
--- Data bus type for internal memory
-SUBTYPE data_typ IS BIT_VECTOR(DATA_WIDTH-1 DOWNTO 0);
--- Address bus type for memory interface
-SUBTYPE addr_inter_typ IS STD_LOGIC_VECTOR(ADDRESS_WIDTH-1 DOWNTO 0);
--- Address bus type for internal memory
-SUBTYPE addr_typ IS NATURAL;
--- Operations testbench can do.
-TYPE do_typ IS ( init , read , write , dealloc , end_test );
-
-TYPE to_srv_typ IS RECORD -- Record passed from test case to test bench
- do : do_typ;
- addr : addr_inter_typ;
- data : data_inter_typ;
- event : BOOLEAN;
-END RECORD to_srv_typ;
-
-TYPE frm_srv_typ IS RECORD -- Record passed from test bench to test case
- data : data_inter_typ;
- event : BOOLEAN;
-END RECORD frm_srv_typ;
-
-
-END PACKAGE single_port_pkg;
-
-PACKAGE BODY single_port_pkg IS
-
-END PACKAGE BODY single_port_pkg;
-
--- $Log: not supported by cvs2svn $
--- Revision 1.1 2003/01/14 17:48:44 Default
--- Initial revision
---
--- Revision 1.1 2002/12/24 17:58:49 Default
--- Initial revision
---
-
-
-
Index: tags/REL/VHDL/tb_single_port.vhd
===================================================================
--- tags/REL/VHDL/tb_single_port.vhd (revision 14)
+++ tags/REL/VHDL/tb_single_port.vhd (nonexistent)
@@ -1,191 +0,0 @@
--- $Author: rpaley_yid $
--- $Date: 2003-01-14 21:48:11 $
--- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/tb_single_port.vhd,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $
--- $Locker
--- $Revision: 1.1.1.1 $
--- $State: Exp $
-
--- --------------------------------------------------------------------------
---
--- Purpose: This file specifies test bench harness for the single_port
--- Memory. It also contains the configuration files for all the
--- tests.
---
---
--- References:
--- 1. The Designer's Guide to VHDL by Peter Ashenden
--- ISBN: 1-55860-270-4 (pbk.)
--- 2. Writing Testbenches - Functional Verification of HDL models by
--- Janick Bergeron | ISBN: 0-7923-7766-4
---
--- Notes:
---
--- --------------------------------------------------------------------------
-LIBRARY IEEE;
-LIBRARY WORK;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE WORK.linked_list_mem_pkg.ALL;
-USE WORK.single_port_pkg.all;
-USE STD.TEXTIO.ALL;
-
-ENTITY tb_single_port IS
-END ENTITY tb_single_port;
-
-ARCHITECTURE BHV of tb_single_port IS
-
-COMPONENT single_port IS
- GENERIC (
- rnwtQ : TIME := 1 NS
- );
- PORT (
- d : IN data_inter_typ;
- q : OUT data_inter_typ;
- a : IN addr_inter_typ;
- rnw : IN STD_LOGIC;
- dealloc_mem : BOOLEAN
-);
-END COMPONENT single_port;
-
-COMPONENT tc_single_port IS
- PORT (
- to_srv : OUT to_srv_typ;
- frm_srv : IN frm_srv_typ
-);
-END COMPONENT tc_single_port;
-
-SIGNAL d : data_inter_typ;
-SIGNAL q : data_inter_typ;
-SIGNAL a : addr_inter_typ;
-SIGNAL rnw : STD_LOGIC;
-SIGNAL dealloc_mem : BOOLEAN;
-SIGNAL to_srv : to_srv_typ;
-SIGNAL frm_srv : frm_srv_typ;
-SIGNAL tie_vdd : STD_LOGIC := '1';
-BEGIN
- dut : single_port
- PORT MAP (
- d => d,
- a => a,
- q => q,
- rnw => rnw,
- dealloc_mem => dealloc_mem
- );
-
- tc : tc_single_port
- PORT MAP (
- to_srv => to_srv,
- frm_srv => frm_srv
- );
-
- single_port_server : PROCESS
- VARIABLE frm_srv_v : frm_srv_typ;
- CONSTANT ACCESS_DELAY : TIME := 5 NS;
- BEGIN
- -- Wait until the test case is finished setting up the next memory access.
- WAIT ON to_srv'TRANSACTION;
- CASE to_srv.do IS
- WHEN init =>
- ASSERT FALSE
- REPORT "initialized"
- SEVERITY NOTE;
- WHEN read => -- perform memory read
- d <= to_srv.data;
- a <= to_srv.addr;
- rnw <= '1';
- -- Wait for data to appear
- WAIT FOR ACCESS_DELAY;
- WHEN write => -- perform memory write
- d <= to_srv.data;
- a <= to_srv.addr;
- rnw <= '0';
- WAIT FOR ACCESS_DELAY;
- WHEN dealloc => -- deallocate the linked list for the LL architecture
- dealloc_mem <= true;
- WHEN end_test => -- reached the end of the test case
- WAIT;
- END CASE;
- frm_srv_v.data := q;
- -- Send message to test case to continue the test.
- frm_srv <= frm_srv_v ; WAIT FOR 0 NS;
- END PROCESS single_port_server;
-END BHV;
-
-CONFIGURATION ll_main_cfg OF TB_SINGLE_PORT IS
- FOR BHV
- FOR dut : single_port
- USE ENTITY work.single_port(LinkedList);
- END FOR; -- dut
- FOR tc : tc_single_port
- USE ENTITY work.tc_single_port(TC0);
- END FOR; -- tc;
- END FOR; -- BHV
-END CONFIGURATION ll_main_cfg;
-
-CONFIGURATION ll_error_cfg OF TB_SINGLE_PORT IS
- FOR BHV
- FOR dut : single_port
- USE ENTITY work.single_port(LinkedList);
- END FOR; -- dut
- FOR tc : tc_single_port
- USE ENTITY work.tc_single_port(TC1);
- END FOR; -- tc;
- END FOR; -- BHV
-END CONFIGURATION ll_error_cfg ;
-
-CONFIGURATION mem_main_cfg of TB_SINGLE_PORT IS
- FOR BHV
- FOR dut : single_port
- USE ENTITY work.single_port(ArrayMem);
- END FOR; -- dut
- FOR tc : tc_single_port
- USE ENTITY work.tc_single_port(TC0);
- END FOR; -- tc;
- END FOR; -- BHV
-END CONFIGURATION mem_main_cfg;
-
-CONFIGURATION mem_error_cfg of TB_SINGLE_PORT IS
- FOR BHV
- FOR dut : single_port
- USE ENTITY work.single_port(ArrayMem);
- END FOR; -- dut
- FOR tc : tc_single_port
- USE ENTITY work.tc_single_port(TC1);
- END FOR; -- tc;
- END FOR; -- BHV
-END CONFIGURATION mem_error_cfg;
-
-CONFIGURATION memnoflag_main_cfg of TB_SINGLE_PORT IS
- FOR BHV
- FOR dut : single_port
- USE ENTITY work.single_port(ArrayMemNoFlag);
- END FOR; -- dut
- FOR tc : tc_single_port
- USE ENTITY work.tc_single_port(TC0);
- END FOR; -- tc;
- END FOR; -- BHV
-END CONFIGURATION memnoflag_main_cfg;
-
-CONFIGURATION memnoflag_error_cfg of TB_SINGLE_PORT IS
- FOR BHV
- FOR dut : single_port
- USE ENTITY work.single_port(ArrayMemNoFlag);
- END FOR; -- dut
- FOR tc : tc_single_port
- USE ENTITY work.tc_single_port(TC1);
- END FOR; -- tc;
- END FOR; -- BHV
-END CONFIGURATION memnoflag_error_cfg;
-
--- $Log: not supported by cvs2svn $
--- Revision 1.1 2003/01/14 17:49:04 Default
--- Initial revision
---
--- Revision 1.2 2002/12/31 19:19:43 Default
--- Updated 'transaction statements for fixed simulator.
---
--- Revision 1.1 2002/12/24 18:10:18 Default
--- Initial revision
---
-
-
Index: tags/REL/VHDL/tc_single_port.vhd
===================================================================
--- tags/REL/VHDL/tc_single_port.vhd (revision 14)
+++ tags/REL/VHDL/tc_single_port.vhd (nonexistent)
@@ -1,194 +0,0 @@
--- $Author: rpaley_yid $
--- $Date: 2003-01-14 21:48:11 $
--- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/tc_single_port.vhd,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $
--- $Locker
--- $Revision: 1.1.1.1 $
--- $State: Exp $
-
--- --------------------------------------------------------------------------
---
--- Purpose: This file specifies test cases for the single_port
--- Memory.
---
---
--- References:
--- 1. The Designer's Guide to VHDL by Peter Ashenden
--- ISBN: 1-55860-270-4 (pbk.)
--- 2. Writing Testbenches - Functional Verification of HDL models by
--- Janick Bergeron | ISBN: 0-7923-7766-4
---
--- Notes:
---
--- --------------------------------------------------------------------------
-LIBRARY IEEE;
-LIBRARY WORK;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE WORK.SINGLE_PORT_PKG.ALL;
-USE WORK.PKG_IMAGE.ALL;
-
-ENTITY tc_single_port IS
-PORT (
- to_srv : OUT to_srv_typ;
- frm_srv : IN frm_srv_typ
-);
-END ENTITY tc_single_port;
-
--- --------------------------------------------------
--- Test Case TC0
--- This test case is to check two pages of memory
--- Starting at physical address 0x0 ,
--- Write a '1' to bit position 0, leaving all other bits 0.
--- Increment the address,
--- Write a '1' to bit position 1, leaving all other bits 0.
--- Increment the address.
--- Write a '1' to bit position 2, leaving all other bits 0.
--- Continue in this fasion, until write a 1 to the MSB.
--- increment the address,
--- Write a '1' to bit position 0, leaving all other bits 0.
--- Continue until the entire page is written to.
--- Read back all addresses in the page, ensuring the
--- correct data is read back.
--- --------------------------------------------------
-
-
-ARCHITECTURE TC0 OF tc_single_port IS
-BEGIN
- MAIN : PROCESS
- VARIABLE to_srv_v : to_srv_typ;
- VARIABLE frm_srv_v : frm_srv_typ;
- VARIABLE dv : data_inter_typ :=
- STD_LOGIC_VECTOR(TO_UNSIGNED(1,data_inter_typ'length));
- VARIABLE offset_v : INTEGER;
- BEGIN
- offset_v := 0;
- -- Run this write/read test 10 times for benchmark
- -- purposes.
- for i in 0 to 9 loop
- for index in 0 to 2*PAGEDEPTH-1 loop
- -- Specify to testbench server to perform write operation;
- to_srv_v.do := write;
- to_srv_v.data := dv; -- specify data to write
- dv := To_StdLogicVector(TO_BitVector(dv) rol 1); -- ROL 1 for next write
- -- Specify physical address.
- to_srv_v.addr := STD_LOGIC_VECTOR(TO_UNSIGNED(index+offset_v,
- ADDRESS_WIDTH));
- to_srv <= to_srv_v ; WAIT FOR 0 NS;
- WAIT ON frm_srv'TRANSACTION;
- end loop;
- -- Reset data to 1.
- dv := STD_LOGIC_VECTOR(TO_UNSIGNED(1,data_inter_typ'length));
- for index in 0 to 2*PAGEDEPTH-1 loop
- -- Perform read operation.
- to_srv_v.do := read;
- -- Specify physical address.
- to_srv_v.addr := STD_LOGIC_VECTOR(TO_UNSIGNED(index+offset_v,
- ADDRESS_WIDTH));
- to_srv <= to_srv_v ; WAIT FOR 0 NS;
- WAIT ON frm_srv'TRANSACTION;
- -- Compare actual with expected read back data, if the
- -- the expected and actual to not compare, print the
- -- expected and actual values.
- ASSERT frm_srv.data = dv
- REPORT "Expected: " & HexImage(frm_srv.data) &
- " did not equal Actual: " & HexImage(dv)
- SEVERITY ERROR;
- -- Set expected data for next read.
- dv := TO_STDLOGICVECTOR(TO_BITVECTOR(dv) rol 1);
- end loop;
- end loop;
- to_srv_v.do := dealloc; -- Deallocate memory
- --
- to_srv <= to_srv_v ; WAIT FOR 0 NS;
- -- Tell test bench server process test completed.
- to_srv_v.do := end_test;
- to_srv <= to_srv_v;
- ASSERT FALSE
- REPORT "Completed Test TC0"
- SEVERITY NOTE;
- WAIT;
- END PROCESS main;
-END TC0;
-
--- --------------------------------------------------
--- Test Case TC1
--- This test case is to check if the test bench will
--- return 'U' for invalid memory locations for
--- single_port architectures ArrayMEm and LinkedList
--- --------------------------------------------------
-ARCHITECTURE TC1 OF tc_single_port IS
-BEGIN
- MAIN : PROCESS
- VARIABLE to_srv_v : to_srv_typ;
- VARIABLE frm_srv_v : frm_srv_typ;
- VARIABLE dv : data_inter_typ := (OTHERS => 'U');
- BEGIN
- -- Perform read operation.
- to_srv_v.do := read;
- -- Specify physical address.
- to_srv_v.addr := STD_LOGIC_VECTOR(TO_UNSIGNED(0,
- ADDRESS_WIDTH));
- to_srv <= to_srv_v; WAIT FOR 0 NS;
- WAIT ON frm_srv'TRANSACTION;
- -- Compare actual with expected read back data, if the
- -- the expected and actual to not compare, print the
- -- expected and actual values.
- ASSERT frm_srv.data = dv
- REPORT "Expected: " & HexImage(frm_srv.data) &
- " did not equal Actual: " & HexImage(dv)
- SEVERITY ERROR;
-
- -- Write and read back from same address.
-
- -- Specify to testbench server to perform write operation;
- to_srv_v.do := write;
- dv := X"a5a5a5a5";
- to_srv_v.data := dv; -- specify data to write
- -- Specify physical address.
- to_srv_v.addr := STD_LOGIC_VECTOR(TO_UNSIGNED(0,
- ADDRESS_WIDTH));
- to_srv <= to_srv_v; WAIT FOR 0 NS;
- -- Wait until the test bench server finished with the write.
- -- WAIT UNTIL frm_srv.event = true;
- WAIT ON frm_srv'transaction;
-
- to_srv_v.do := read;
- -- Specify physical address.
- to_srv_v.addr := STD_LOGIC_VECTOR(TO_UNSIGNED(0,
- ADDRESS_WIDTH));
- to_srv <= to_srv_v; WAIT FOR 0 NS;
- WAIT ON frm_srv'transaction;
-
- -- Compare actual with expected read back data, if the
- -- the expected and actual to not compare, print the
- -- expected and actual values.
- ASSERT frm_srv.data = dv
- REPORT "Expected: " & HexImage(frm_srv.data) &
- " did not equal Actual: " & HexImage(dv)
- SEVERITY ERROR;
-
- to_srv_v.do := dealloc; -- Deallocate memory
- --
- to_srv <= to_srv_v; WAIT FOR 0 NS;
- -- Tell test bench server process test completed.
- to_srv_v.do := end_test;
- to_srv <= to_srv_v; WAIT FOR 0 NS;
-
- ASSERT FALSE
- REPORT "Completed Test TC1"
- SEVERITY NOTE;
- WAIT;
- END PROCESS main;
-END TC1;
-
--- $Log: not supported by cvs2svn $
--- Revision 1.1 2003/01/14 17:49:04 Default
--- Initial revision
---
--- Revision 1.2 2002/12/31 19:19:43 Default
--- Updated 'transaction statements for fixed simulator.
---
--- Revision 1.1 2002/12/24 18:13:50 Default
--- Initial revision
---
-
Index: tags/REL/VHDL/Makefile
===================================================================
--- tags/REL/VHDL/Makefile (revision 14)
+++ tags/REL/VHDL/Makefile (nonexistent)
@@ -1,161 +0,0 @@
-#
-# Description: Top level make file for single_port test project.
-# make com to compile
-# make sim to simulate all tests
-# make ll_error to run this test only
-# make ll_main to run this test only
-# make mem_main to run this test only
-# make mem_error to run this test only
-# make memnoflag_main to run this test
-# make memnoflag_error to run this test
-# $Author: rpaley_yid $
-# $Date: 2003-01-14 21:48:11 $
-# $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/Makefile,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $
-# $Locker: $
-# $Revision: 1.1.1.1 $
-# $State: Exp $
-
-# VCOM , VSIM , and WORK variables are set for Sonata simulator,
-# Change appropriately for your simulator. Ex.for Modeltech,
-# VCOM = vcom
-# VSIM = vsim
-# WORK = work
-
-SHELL = /bin/sh
-VCOM = vhdlp
-VCOMOPT = -s
-VSIM = vhdle
-VSIMOPT =
-WORK = work.sym
-## Need to figure out how to put Bourne shell stuff in Makefile
-## will do so to generate log files in
-## LOGDIR = ../LOG/
-## For now, log files are in VHDL directory.
-
-
-# List of main compiled objects, does not include configurations,
-# which are included in the tb_single_port.vhd file.
-# These targets are for the Sonata simulator, adjust accordingly for
-# your simulator.
-
-SINGLE_PORT_PKG_OBJ = $(WORK)/single_port_pkg/prim.var
-LINKED_LIST_MEM_OBJ = $(WORK)/linked_list_mem_pkg/prim.var
-PKG_IMAGE_OBJ = $(WORK)/pkg_image/prim.var
-SINGLE_PORT_OBJ = $(WORK)/single_port/prim.var
-TC_SINGLE_PORT_OBJ = $(WORK)/tc_single_port/prim.var
-TB_SINGLE_PORT_OBJ = $(WORK)/tb_single_port/prim.var
-LL_ERROR_DEP = $(WORK)/ll_error_cfg/prim.var
-LL_MAIN_DEP = $(WORK)/ll_main_cfg/prim.var
-MEM_MAIN_DEP = $(WORK)/mem_main_cfg/prim.var
-MEM_ERROR_DEP = $(WORK)/mem_error_cfg/prim.var
-MEMNOFLAG_MAIN_DEP = $(WORK)/memnoflag_main_cfg/prim.var
-MEMNOFLAG_ERROR_DEP = $(WORK)/memnoflag_error_cfg/prim.var
-
-LL_ERROR = $(LOGDIR)ll_error.log
-LL_MAIN = ll_main.log
-MEM_MAIN = mem_main.log
-MEM_ERROR = mem_error.log
-MEMNOFLAG_MAIN = memnoflag_main.log
-MEMNOFLAG_ERROR = memnoflag_error.log
-
-OBJS = $(SINGLE_PORT_PKG_OBJ) \
- $(LINKED_LIST_MEM_OBJ) \
- $(PKG_IMAGE_OBJ) \
- $(SINGLE_PORT_OBJ) \
- $(TC_SINGLE_PORT_OBJ) \
- $(TB_SINGLE_PORT_OBJ)
-
-SIMOBJS = $(LL_ERROR) \
- $(LL_MAIN) \
- $(MEM_MAIN) \
- $(MEM_ERROR) \
- $(MEMNOFLAG_MAIN) \
- $(MEMNOFLAG_ERROR)
-
-# Compile the project
-com: $(OBJS)
-
-# Clean the library
-clean:: $(WORK)
-
-# Simulate all tests
-sim: $(SIMOBJS)
-
-## Run only ll_error test
-ll_error: $(LL_ERROR)
-
-# Run onle ll_main test
-ll_main: $(LL_MAIN)
-
-# Run only mem_main test
-mem_main: $(MEM_MAIN)
-
-# Run only mem_error test
-mem_error: $(MEM_ERROR)
-
-# Run only memnoflag_main test
-memnoflag_main: $(MEMNOFLAG_MAIN)
-
-# Run only memnoflag_error test
-memnoflag_error: $(MEMNOFLAG_ERROR)
-
-# Target dependency rules to run tests
-$(LL_ERROR) : $(LL_ERROR_DEP)
- $(VSIM) $(VSIMOPT) ll_error_cfg | tee $@
-
-$(LL_MAIN) : $(LL_MAIN_DEP)
- $(VSIM) $(VSIMOPT) ll_main_cfg | tee $@
-
-$(MEM_MAIN) : $(MEM_MAIN_DEP)
- $(VSIM) $(VSIMOPT) mem_main_cfg | tee $@
-
-$(MEM_ERROR) : $(MEM_ERROR_DEP)
- $(VSIM) $(VSIMOPT) mem_error_cfg | tee $@
-
-$(MEMNOFLAG_MAIN) : $(MEMNOFLAG_MAIN_DEP)
- $(VSIM) $(VSIMOPT) memnoflag_main_cfg | tee $@
-
-$(MEMNOFLAG_ERROR) : $(MEMNOFLAG_ERROR_DEP)
- $(VSIM) $(VSIMOPT) memnoflag_error_cfg | tee $@
-
-# Target dependency rules to compile tests
-
-$(SINGLE_PORT_PKG_OBJ) : single_port_pkg.vhd
- $(VCOM) $(VCOMOPT) $<
-
-$(LINKED_LIST_MEM_OBJ) : linked_list_mem_pkg.vhd \
- $(SINGLE_PORT_PKG_OBJ)
- $(VCOM) $(VCOMOPT) $<
-
-$(PKG_IMAGE_OBJ) : pkg_image.vhd
- $(VCOM) $(VCOMOPT) $<
-
-$(SINGLE_PORT_OBJ) : single_port.vhd \
- $(SINGLE_PORT_PKG_OBJ) \
- $(LINKED_LIST_MEM_OBJ)
- $(VCOM) $(VCOMOPT) $<
-
-$(TC_SINGLE_PORT_OBJ) : tc_single_port.vhd \
- $(SINGLE_PORT_PKG_OBJ) \
- $(PKG_IMAGE_OBJ) \
- $(SINGLE_PORT_OBJ)
- $(VCOM) $(VCOMOPT) $<
-
-$(TB_SINGLE_PORT_OBJ) : tb_single_port.vhd \
- $(SINGLE_PORT_PKG_OBJ) \
- $(LINKED_LIST_MEM_OBJ) \
- $(SINGLE_PORT_OBJ) \
- $(TC_SINGLE_PORT_OBJ)
- $(VCOM) $(VCOMOPT) $<
-
-$(WORK) ::
- rm -rf $(WORK)/*
-
-
-####################################################################
-# $Log: not supported by cvs2svn $
-# Revision 1.1 2002/12/31 19:21:59 Default
-# Initial revision
-#
-#
-
Index: tags/REL/VHDL/linked_list_mem_pkg.vhd
===================================================================
--- tags/REL/VHDL/linked_list_mem_pkg.vhd (revision 14)
+++ tags/REL/VHDL/linked_list_mem_pkg.vhd (nonexistent)
@@ -1,147 +0,0 @@
--- $Author: rpaley_yid $
--- $Date: 2003-01-14 21:48:10 $
--- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/linked_list_mem_pkg.vhd,v 1.1.1.1 2003-01-14 21:48:10 rpaley_yid Exp $
--- $Locker
--- $Revision: 1.1.1.1 $
--- $State: Exp $
-
--- --------------------------------------------------------------------------
---
--- Purpose: This package implements functions to allocate, write, read, and
--- deallocate a linked list based memory.
---
---
--- References:
--- 1. The Designer's Guide to VHDL by Peter Ashenden
--- ISBN: 1-55860-270-4 (pbk.)
--- 2. Writing Testbenches - Functional Verification of HDL models by
--- Janick Bergeron | ISBN: 0-7923-7766-4
---
--- Notes:
---
--- --------------------------------------------------------------------------
-
-LIBRARY IEEE;
-LIBRARY WORK;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE WORK.single_port_pkg.all;
-
-PACKAGE linked_list_mem_pkg IS
- -- data memory array type definition
- TYPE mem_array_typ IS ARRAY (0 TO PAGEDEPTH-1) OF data_typ;
- -- Define memory page linked list cell. This cell contains,
- -- the mem_array, starting page address, valid data array, and
- -- the pointer to the next element in the linked list.
- TYPE mem_page_typ;
- -- pointer to next item in the linked list.
- TYPE mem_page_ptr IS ACCESS mem_page_typ;
- TYPE mem_page_typ IS RECORD
- mem_array : mem_array_typ; -- data memory
- -- This array is a flag which indicates if the corresponding
- -- address location inside mem_array contains valid data.
- data_valid_array : BIT_VECTOR( 0 TO PAGEDEPTH-1);
- page_address : addr_typ;
- next_cell : mem_page_ptr;
- END RECORD mem_page_typ;
- PROCEDURE rw_mem (
- VARIABLE data : INOUT data_inter_typ;
- VARIABLE addr : addr_typ;
- VARIABLE write_flag : BOOLEAN;
- VARIABLE next_cell : INOUT mem_page_ptr
- );
- PROCEDURE deallocate_mem (
- VARIABLE next_cell : INOUT mem_page_ptr
- );
-
-END PACKAGE linked_list_mem_pkg;
-
-PACKAGE BODY LINKED_LIST_MEM_PKG IS
- -- --------------------------------------------------
- -- The purpose of this procedure is to write a memory location from
- -- the linked list, if the particular page does not exist, create it.
- -- --------------------------------------------------
- PROCEDURE rw_mem (
- VARIABLE data : INOUT data_inter_typ;
- VARIABLE addr : addr_typ;
- VARIABLE write_flag : BOOLEAN;
- VARIABLE next_cell : INOUT mem_page_ptr
- ) IS
- VARIABLE current_cell_v : mem_page_ptr; -- current page pointer
- VARIABLE page_address_v : addr_typ; -- calculated page address
- VARIABLE index_v : INTEGER; -- address within the memory page
- VARIABLE mem_array_v : mem_array_typ;
- VARIABLE data_valid_array_v : BIT_VECTOR(0 TO PAGEDEPTH-1);
- BEGIN
- -- Copy the top of the linked list pointer to a working pointer
- current_cell_v := next_cell;
- -- Calculate the index within the page from the given address
- index_v := addr MOD PAGEDEPTH;
- -- Calculate the page address from the given address
- page_address_v := addr - index_v;
- -- Search through the memory to determine if the calculated
- -- memory page exists. Stop searching when reach the end of
- -- the linked list.
- WHILE ( current_cell_v /= NULL
- AND current_cell_v.page_address /= page_address_v) LOOP
- current_cell_v := current_cell_v.next_cell;
- END LOOP;
-
- IF write_flag THEN
- IF ( current_cell_v /= NULL AND -- Check if address exists in memory.
- current_cell_v.page_address = page_address_v
- ) THEN
- -- Found the memory page the particular address belongs to
- current_cell_v.mem_array(index_v) := TO_BITVECTOR(data);
- -- set memory location valid flag
- current_cell_v.data_valid_array(index_v) := '1';
- ELSE
- -- The memory page the address belongs to was not allocated in memory.
- -- Allocate page here and assign data.
- mem_array_v(index_v) := TO_BITVECTOR(data);
- data_valid_array_v(index_v) := '1';
- next_cell := NEW mem_page_typ'( mem_array => mem_array_v,
- data_valid_array => data_valid_array_v,
- page_address => page_address_v,
- next_cell => next_cell
- );
- END IF;
- ELSE -- Read memory
- IF ( current_cell_v /= NULL AND -- Check if address exists in memory.
- current_cell_v.page_address = page_address_v AND
- current_cell_v.data_valid_array(index_v) = '1'
- ) THEN
- -- Found the memory page the particular address belongs to,
- -- and the memory location has valid data.
- data := TO_STDLOGICVECTOR(current_cell_v.mem_array(index_v));
- ELSE
- -- Trying to read from unwritten or unallocated
- -- memory location, return 'U';
- data := (OTHERS => 'U');
- END IF;
- END IF;
- END PROCEDURE rw_mem;
-
- PROCEDURE deallocate_mem (
- VARIABLE next_cell : INOUT mem_page_ptr
- ) IS
- VARIABLE delete_cell_v : mem_page_ptr;
- BEGIN
- -- Deallocate the linked link memory from work station memory.
- WHILE next_cell /= NULL LOOP -- while not reached the end of the LL
- delete_cell_v := next_cell; -- Copy pointer to record for deleting
- next_cell := next_cell.next_cell; -- set pointer to next cell in LL
- deallocate(delete_cell_v); -- Deallocate current cell from memory.
- END LOOP;
- END PROCEDURE deallocate_mem;
-END PACKAGE BODY LINKED_LIST_MEM_PKG;
-
--- $Log: not supported by cvs2svn $
--- Revision 1.1 2003/01/14 17:47:32 Default
--- Initial revision
---
--- Revision 1.1 2002/12/24 18:03:50 Default
--- Initial revision
---
-
-
-
Index: tags/REL/VHDL/pkg_image.vhd
===================================================================
--- tags/REL/VHDL/pkg_image.vhd (revision 14)
+++ tags/REL/VHDL/pkg_image.vhd (nonexistent)
@@ -1,307 +0,0 @@
--- $Author: rpaley_yid $
--- $Date: 2003-01-14 21:48:10 $
--- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/pkg_image.vhd,v 1.1.1.1 2003-01-14 21:48:10 rpaley_yid Exp $
--- $Locker
--- $Revision: 1.1.1.1 $
--- $State: Exp $
-
--- Copyright (c) 1997 Ben Cohen. All rights reserved.
--- This model can be used in conjunction with the Kluwer Academic books
--- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0
--- "VHDL Amswers to Frequently Asked Questions", Kluwer Academic
--- by Ben Cohen. email: vhdlcohen@aol.com
---
--- This source file for the Image Package
--- may be used and distributed without restriction provided
--- that this copyright statement is not removed from the file
--- and that any derivative work contains this copyright notice.
---
---
--- Original Author: Ben Cohen
--- Description:
--- Convert VHDL types to string for printing. This is especially useful when
--- compiling with VHDL-87
-
----------------------------------------------------------------
-LIBRARY IEEE;
- USE IEEE.STD_LOGIC_1164.ALL;
- USE IEEE.STD_LOGIC_TEXTIO.ALL;
- USE IEEE.NUMERIC_STD.ALL;
-
-LIBRARY STD;
- USE STD.TEXTIO.ALL;
-
-package pkg_image is
- function Image(In_Image : Time) return String;
- function Image(In_Image : Bit) return String;
- function Image(In_Image : Bit_Vector) return String;
- function Image(In_Image : Integer) return String;
- function Image(In_Image : Real) return String;
- function Image(In_Image : Std_uLogic) return String;
- function Image(In_Image : Std_uLogic_Vector) return String;
- function Image(In_Image : Std_Logic_Vector) return String;
- function Image(In_Image : Signed) return String;
- function Image(In_Image : UnSigned) return String;
-
- function HexImage(InStrg : String) return String;
- function HexImage(In_Image : Bit_Vector) return String;
- function HexImage(In_Image : Std_uLogic_Vector) return String;
- function HexImage(In_Image : Std_Logic_Vector) return String;
- function HexImage(In_Image : Signed) return String;
- function HexImage(In_Image : UnSigned) return String;
-
- function DecImage(In_Image : Bit_Vector) return String;
- function DecImage(In_Image : Std_uLogic_Vector) return String;
- function DecImage(In_Image : Std_Logic_Vector) return String;
- function DecImage(In_Image : Signed) return String;
- function DecImage(In_Image : UnSigned) return String;
-end pkg_image;
-
-package body pkg_image is
- function Image(In_Image : Time) return String is
- variable L : Line; -- access type
- variable W : String(1 to 14) := (others => ' ');
- -- Long enough to hold a time string
- begin
- -- the WRITE procedure creates an object with "NEW".
- -- L is passed as an output of the procedure.
- Std.TextIO.WRITE(L, in_image);
- -- Copy L.all onto W
- W(L.all'range) := L.all;
- Deallocate(L);
- return W;
- end Image;
-
- function Image(In_Image : Bit) return String is
- variable L : Line; -- access type
- variable W : String(1 to 3) := (others => ' ');
- begin
- Std.TextIO.WRITE(L, in_image);
- W(L.all'range) := L.all;
- Deallocate(L);
- return W;
- end Image;
-
- function Image(In_Image : Bit_Vector) return String is
- variable L : Line; -- access type
- variable W : String(1 to In_Image'length) := (others => ' ');
- begin
- Std.TextIO.WRITE(L, in_image);
- W(L.all'range) := L.all;
- Deallocate(L);
- return W;
- end Image;
-
- function Image(In_Image : Integer) return String is
- variable L : Line; -- access type
- variable W : String(1 to 32) := (others => ' ');
- -- Long enough to hold a time string
- begin
- Std.TextIO.WRITE(L, in_image);
- W(L.all'range) := L.all;
- Deallocate(L);
- return W;
- end Image;
-
- function Image(In_Image : Real) return String is
- variable L : Line; -- access type
- variable W : String(1 to 32) := (others => ' ');
- -- Long enough to hold a time string
- begin
- Std.TextIO.WRITE(L, in_image);
- W(L.all'range) := L.all;
- Deallocate(L);
- return W;
- end Image;
-
- function Image(In_Image : Std_uLogic) return String is
- variable L : Line; -- access type
- variable W : String(1 to 3) := (others => ' ');
- begin
- IEEE.Std_Logic_Textio.WRITE(L, in_image);
- W(L.all'range) := L.all;
- Deallocate(L);
- return W;
- end Image;
-
- function Image(In_Image : Std_uLogic_Vector) return String is
- variable L : Line; -- access type
- variable W : String(1 to In_Image'length) := (others => ' ');
- begin
- IEEE.Std_Logic_Textio.WRITE(L, in_image);
- W(L.all'range) := L.all;
- Deallocate(L);
- return W;
- end Image;
-
- function Image(In_Image : Std_Logic_Vector) return String is
- variable L : Line; -- access type
- variable W : String(1 to In_Image'length) := (others => ' ');
- begin
- IEEE.Std_Logic_TextIO.WRITE(L, In_Image);
- W(L.all'range) := L.all;
- Deallocate(L);
- return W;
- end Image;
-
- function Image(In_Image : Signed) return String is
- begin
- return Image(Std_Logic_Vector(In_Image));
- end Image;
-
- function Image(In_Image : UnSigned) return String is
- begin
- return Image(Std_Logic_Vector(In_Image));
- end Image;
-
- function HexImage(InStrg : String) return String is
- subtype Int03_Typ is Integer range 0 to 3;
- variable Result : string(1 to ((InStrg'length - 1)/4)+1) :=
- (others => '0');
- variable StrTo4 : string(1 to Result'length * 4) :=
- (others => '0');
- variable MTspace : Int03_Typ; -- Empty space to fill in
- variable Str4 : String(1 to 4);
- variable Group_v : Natural := 0;
- begin
- MTspace := Result'length * 4 - InStrg'length;
- StrTo4(MTspace + 1 to StrTo4'length) := InStrg; -- padded with '0'
- Cnvrt_Lbl : for I in Result'range loop
- Group_v := Group_v + 4; -- identifies end of bit # in a group of 4
- Str4 := StrTo4(Group_v - 3 to Group_v); -- get next 4 characters
- case Str4 is
- when "0000" => Result(I) := '0';
- when "0001" => Result(I) := '1';
- when "0010" => Result(I) := '2';
- when "0011" => Result(I) := '3';
- when "0100" => Result(I) := '4';
- when "0101" => Result(I) := '5';
- when "0110" => Result(I) := '6';
- when "0111" => Result(I) := '7';
- when "1000" => Result(I) := '8';
- when "1001" => Result(I) := '9';
- when "1010" => Result(I) := 'A';
- when "1011" => Result(I) := 'B';
- when "1100" => Result(I) := 'C';
- when "1101" => Result(I) := 'D';
- when "1110" => Result(I) := 'E';
- when "1111" => Result(I) := 'F';
- when others => Result(I) := 'X';
- end case; -- Str4
- end loop Cnvrt_Lbl;
-
- return Result;
- end HexImage;
-
-
- function HexImage(In_Image : Bit_Vector) return String is
- begin
- return HexImage(Image(In_Image));
- end HexImage;
-
- function HexImage(In_Image : Std_uLogic_Vector) return String is
- begin
- return HexImage(Image(In_Image));
- end HexImage;
-
- function HexImage(In_Image : Std_Logic_Vector) return String is
- begin
- return HexImage(Image(In_Image));
- end HexImage;
-
- function HexImage(In_Image : Signed) return String is
- begin
- return HexImage(Image(In_Image));
- end HexImage;
-
- function HexImage(In_Image : UnSigned) return String is
- begin
- return HexImage(Image(In_Image));
- end HexImage;
-
- function DecImage(In_Image : Bit_Vector) return String is
- variable In_Image_v : Bit_Vector(In_Image'length downto 1) := In_Image;
- begin
- if In_Image'length > 31 then
- assert False
- report "Number too large for Integer, clipping to 31 bits"
- severity Warning;
- return Image(To_Integer
- (Unsigned(To_StdLogicVector
- (In_Image_v(31 downto 1)))));
- else
- return Image(To_Integer(Unsigned(To_StdLogicVector(In_Image))));
- end if;
- end DecImage;
-
- function DecImage(In_Image : Std_uLogic_Vector) return String is
- variable In_Image_v : Std_uLogic_Vector(In_Image'length downto 1)
- := In_Image;
- begin
- if In_Image'length > 31 then
- assert False
- report "Number too large for Integer, clipping to 31 bits"
- severity Warning;
- return Image(To_Integer(Unsigned(In_Image_v(31 downto 1))));
- else
- return Image(To_Integer(Unsigned(In_Image)));
- end if;
- end DecImage;
-
- function DecImage(In_Image : Std_Logic_Vector) return String is
- variable In_Image_v : Std_Logic_Vector(In_Image'length downto 1)
- := In_Image;
- begin
- if In_Image'length > 31 then
- assert False
- report "Number too large for Integer, clipping to 31 bits"
- severity Warning;
- return Image(To_Integer(Unsigned(In_Image_v(31 downto 1))));
- else
- return Image(To_Integer(Unsigned(In_Image)));
- end if;
- end DecImage;
-
- function DecImage(In_Image : Signed) return String is
- variable In_Image_v : Signed(In_Image'length downto 1) := In_Image;
- begin
- if In_Image'length > 31 then
- assert False
- report "Number too large for Integer, clipping to 31 bits"
- severity Warning;
- return Image(To_Integer(In_Image_v(31 downto 1)));
- else
- return Image(To_Integer(In_Image));
- end if;
- end DecImage;
-
- function DecImage(In_Image : UnSigned) return String is
- variable In_Image_v : UnSigned(In_Image'length downto 1) := In_Image;
- begin
- if In_Image'length > 31 then
- assert False
- report "Number too large for Integer, clipping to 31 bits"
- severity Warning;
- return Image(To_Integer(In_Image_v(31 downto 1)));
- else
- return Image(To_Integer(In_Image));
- end if;
- end DecImage;
-
-end pkg_image;
-
--- $Log: not supported by cvs2svn $
--- Revision 1.1 2003/01/14 17:48:44 Default
--- Initial revision
---
--- Revision 1.1 2002/12/24 18:07:50 Default
--- Initial revision
---
-
-
-
-
-
-
-
-
Index: trunk/images/timing.dia
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/images/timing.dia
===================================================================
--- trunk/images/timing.dia (revision 14)
+++ trunk/images/timing.dia (nonexistent)
trunk/images/timing.dia
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: trunk/images/tbschematic.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/images/tbschematic.png
===================================================================
--- trunk/images/tbschematic.png (revision 14)
+++ trunk/images/tbschematic.png (nonexistent)
trunk/images/tbschematic.png
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: trunk/images/timing.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/images/timing.png
===================================================================
--- trunk/images/timing.png (revision 14)
+++ trunk/images/timing.png (nonexistent)
trunk/images/timing.png
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: trunk/images/tbschematic.fig
===================================================================
--- trunk/images/tbschematic.fig (revision 14)
+++ trunk/images/tbschematic.fig (nonexistent)
@@ -1,62 +0,0 @@
-#FIG 3.2 Produced by xfig version 3.2.5-alpha5
-Landscape
-Center
-Metric
-A4
-100.00
-Single
--2
-1200 2
-2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
- 1 1 1.00 60.00 120.00
- 8325 540 6300 540
-2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
- 1 1 1.00 60.00 120.00
- 6300 225 8325 225
-2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
- 1 1 1.00 60.00 120.00
- 6300 855 8325 855
-2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
- 1 1 1.00 60.00 120.00
- 6300 1170 8325 1170
-2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
- 1 1 1.00 60.00 120.00
- 6300 1485 8325 1485
-2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
- 1 1 1.00 60.00 120.00
- 6300 1800 8325 1800
-2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
- 1 1 1.00 60.00 120.00
- 6300 2115 8325 2115
-2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
- 5490 450 6030 450 6030 2925 5490 2925 5490 450
-2 2 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
- 3375 0 6300 0 6300 3375 3375 3375 3375 0
-2 2 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
- 8325 0 10125 0 10125 2340 8325 2340 8325 0
-2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
- 1 1 1.00 60.00 120.00
- 3375 270 2025 270
-2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
- 1 1 1.00 60.00 120.00
- 2025 855 3375 855
-2 2 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
- 0 0 2025 0 2025 1125 0 1125 0 0
-4 1 0 50 -1 0 16 1.5708 4 255 2070 5805 1710 single_port_server\001
-4 0 0 50 -1 1 16 0.0000 4 195 465 3645 1440 Test\001
-4 0 0 50 -1 1 16 0.0000 4 195 945 3645 1755 Harness\001
-4 0 0 50 -1 1 16 0.0000 4 270 1575 3645 2070 tb_single_port\001
-4 0 0 50 -1 0 16 0.0000 4 195 600 3600 405 Arch\001
-4 0 0 50 -1 0 16 0.0000 4 255 1455 8505 1350 (single_port)\001
-4 0 0 50 -1 0 16 0.0000 4 195 570 8505 945 DUT\001
-4 1 0 50 -1 0 16 0.0000 4 195 135 7290 495 q\001
-4 1 0 50 -1 0 16 0.0000 4 195 135 7290 180 d\001
-4 1 0 50 -1 0 16 0.0000 4 135 120 7290 810 a\001
-4 1 0 50 -1 0 16 0.0000 4 135 390 7290 1125 nce\001
-4 1 0 50 -1 0 16 0.0000 4 135 450 7290 1440 nwe\001
-4 1 0 50 -1 0 16 0.0000 4 135 405 7290 1755 noe\001
-4 1 0 50 -1 0 16 0.0000 4 255 1485 7290 2070 dealloc_mem\001
-4 1 0 50 -1 0 16 0.0000 4 255 900 2700 180 frm_srv\001
-4 1 0 50 -1 0 16 0.0000 4 225 705 2700 765 to_srv\001
-4 0 0 50 -1 0 16 0.0000 4 255 1590 225 765 tc_single_port\001
-4 0 0 50 -1 0 16 0.0000 4 195 960 225 450 Testcase\001
Index: trunk/doc/single_port.html
===================================================================
--- trunk/doc/single_port.html (revision 14)
+++ trunk/doc/single_port.html (nonexistent)
@@ -1,366 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Description
- of single_port memory and test environment.
-
-
Abstract:
-
-
A VHDL simulation model for an asynchronous static single
- port memory is described. The memory is implemented as three different
- architectures, a simple one and 2 ones which are optimized for efficient
- use of simulator memory. Data and address buses are unconstrained, so
-multiple instances with different address and data bus widths can be implemented
-in one single design. A testbench is also provided.
-
-
-
Port Interface:
-
-
-
-
-
-
- Port Name
- |
-
-
- Type
- |
-
-
- Description
- |
-
-
-
-
-
- rnwtQ
- |
-
-
- Time
- |
-
-
- Time delay until data or tristate appears on q data bus.
- |
-
-
-
-
- d
- |
- STD_LOGIC_VECTOR
- |
-
-
- Input data bus, unconstrained
- |
-
-
-
-
- q
- |
-
-
- STD_LOGIC_VECTOR
-
- |
-
-
- Output data bus, unconstrained
- |
-
-
-
-
- a
- |
-
-
- STD_LOGIC_VECTOR
-
- |
-
-
- Address bus, unconstrained
- |
-
-
-
-
- nce
- |
-
-
- STD_LOGIC
- |
-
-
- not chip enable
- |
-
-
- nwe
- |
- STD_LOGIC
- |
- not write enable
- |
-
-
- noe
- |
- STD_LOGIC
- |
- not output enable
- |
-
-
-
-
- dealloc_mem
- |
-
-
- BOOLEAN
- |
-
-
- When set to true, deallocate linked list memory.
- |
-
-
-
-
-
-
Functional Description:
-
-
All 3 architectures functionally behave like commercially
- available asynchronous SRAMs if you connect d and q to the same bus. If a memory location is read which was not written to during the
- current simulation, 'U's are loaded onto the memory bus.
-
-
-
-
- nce
- |
- nwe
- |
- noe
- |
- d
- |
- q
- |
- Mode
- |
-
-
- 1
- |
- don't care
- |
- don't care
- |
- don't care
- |
- high Z
- |
- deselected
- |
-
-
- 0
- |
- 1
- |
- 1
- |
- don't care
- |
- high Z
- |
- output disabled
- |
-
-
- 0
- |
- 0
- |
- don't care
- |
- input data
- |
- high Z
- |
- write
- |
-
-
- 0
- |
- 1
- |
- 0
- |
- don't care
- |
- RAM content
- |
- read
- |
-
-
-
-
-
-
Architecture ArrayMemNoFlag
-
-
This architecture implements the memory core as an array
- of STD_LOGIC_VECTOR. This is the simplest architecture. It is provided
- for comparison with the models below but not recommended for use in your
- design.
-
-
-
-
Architecture ArrayMem
-
-
This architecture implements the
- memory core as an array of BIT_VECTOR. This arrangement allows less workstation
- memory to be used than the ArrayMemNoFlag architecture. Use this architecture
- if most addresses in the simulated memory are written at least once.
-
-
-
Architecture LinkedList
-
-
-
This architecture implements the memory core as a linked
- list of arrays of BIT_VECTOR. Each array in the linked list is a page
-of memory whose size is specified with the constant PAGEDEPTH in the package
- linked_list_mem_pkg. This arrangement allows less workstation memory
-to be used than either the ArrayMemNoFlag or ArrayMem architectures because
- memory representing the array data is only allocated if the memory is
-actually written to. To de-allocate the memory in the linked list, set
-dealloc_mem to true. A short pulse is sufficient. Use this architecture
- if a significant portion of your simulated memory (which need not be
-contiguous) is never written to.
-
Example Timing:
-
-
Clearing both nce and nwe to to '0' immediately causes
-a write operation. Changing the address while nce and nwe are asserted causes
- a write to the new address, too (But don't do that with real RAMs because
- you could destroy more memory locations while the address bus settles).
-Every read (and tristate) operation is delayed rnwtQ ns. The below sample
- timing diagram illustrates both a read and write operation.
-
-
-
-
-
-
Testbench Description:
-
-
The test bench is arranged as a client server architecture as specified
- by Bergeron. A diagram illustrating the testbench
- is given below.
-
-
-
- Two tests are specified in tc_single_port component. The first test
- writes data to two logical memory pages, and then reads them back verifying
- the correct data. The test case writes an error message to the console
-for every miscompare. The second case verifies that the single_port memory
-model outputs unknowns to the q bus if a read occurs for an unwritten memory
-location. Six configurations are specified in the test bench architecture
-tb_single_port, running both tests for each single_port architecture.
-
-
-
Usage:
-
-
A Makefile is used to compile and run all of the tests in a Unix or like
- environment, such as Cygwin. The compilation and simulation is targetted
- to the SymphonyEDA tool available at www.symphonyeda.com.
-
-
The source files and Makefile are located in {top}/VHDL
-
- To compile: make com
-
-
To simulate all of the tests: make sim
-
-
-
To clean the compiled library: make clean
-
-
The tests are labeled :
-
-
- - ll_error
- - ll_main
- - mem_main
-
- - mem_error
-
- - memnoflag_main
-
- - memnoflag_error
-
-
-
-
-
To simulate any of these tests, type make {testname}
-
-
Please contact Robert Paley at rpaley_yid@opencores.org
- or Michael Geng at vhdl@michaelgeng.de
- if you have any questions or comments.
-
-
-
-
-
-
-
Index: trunk/doc/copying.txt
===================================================================
--- trunk/doc/copying.txt (revision 14)
+++ trunk/doc/copying.txt (nonexistent)
@@ -1,504 +0,0 @@
- GNU LESSER GENERAL PUBLIC LICENSE
- Version 2.1, February 1999
-
- Copyright (C) 1991, 1999 Free Software Foundation, Inc.
- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- Everyone is permitted to copy and distribute verbatim copies
- of this license document, but changing it is not allowed.
-
-[This is the first released version of the Lesser GPL. It also counts
- as the successor of the GNU Library Public License, version 2, hence
- the version number 2.1.]
-
- Preamble
-
- The licenses for most software are designed to take away your
-freedom to share and change it. By contrast, the GNU General Public
-Licenses are intended to guarantee your freedom to share and change
-free software--to make sure the software is free for all its users.
-
- This license, the Lesser General Public License, applies to some
-specially designated software packages--typically libraries--of the
-Free Software Foundation and other authors who decide to use it. You
-can use it too, but we suggest you first think carefully about whether
-this license or the ordinary General Public License is the better
-strategy to use in any particular case, based on the explanations below.
-
- When we speak of free software, we are referring to freedom of use,
-not price. Our General Public Licenses are designed to make sure that
-you have the freedom to distribute copies of free software (and charge
-for this service if you wish); that you receive source code or can get
-it if you want it; that you can change the software and use pieces of
-it in new free programs; and that you are informed that you can do
-these things.
-
- To protect your rights, we need to make restrictions that forbid
-distributors to deny you these rights or to ask you to surrender these
-rights. These restrictions translate to certain responsibilities for
-you if you distribute copies of the library or if you modify it.
-
- For example, if you distribute copies of the library, whether gratis
-or for a fee, you must give the recipients all the rights that we gave
-you. You must make sure that they, too, receive or can get the source
-code. If you link other code with the library, you must provide
-complete object files to the recipients, so that they can relink them
-with the library after making changes to the library and recompiling
-it. And you must show them these terms so they know their rights.
-
- We protect your rights with a two-step method: (1) we copyright the
-library, and (2) we offer you this license, which gives you legal
-permission to copy, distribute and/or modify the library.
-
- To protect each distributor, we want to make it very clear that
-there is no warranty for the free library. Also, if the library is
-modified by someone else and passed on, the recipients should know
-that what they have is not the original version, so that the original
-author's reputation will not be affected by problems that might be
-introduced by others.
-
- Finally, software patents pose a constant threat to the existence of
-any free program. We wish to make sure that a company cannot
-effectively restrict the users of a free program by obtaining a
-restrictive license from a patent holder. Therefore, we insist that
-any patent license obtained for a version of the library must be
-consistent with the full freedom of use specified in this license.
-
- Most GNU software, including some libraries, is covered by the
-ordinary GNU General Public License. This license, the GNU Lesser
-General Public License, applies to certain designated libraries, and
-is quite different from the ordinary General Public License. We use
-this license for certain libraries in order to permit linking those
-libraries into non-free programs.
-
- When a program is linked with a library, whether statically or using
-a shared library, the combination of the two is legally speaking a
-combined work, a derivative of the original library. The ordinary
-General Public License therefore permits such linking only if the
-entire combination fits its criteria of freedom. The Lesser General
-Public License permits more lax criteria for linking other code with
-the library.
-
- We call this license the "Lesser" General Public License because it
-does Less to protect the user's freedom than the ordinary General
-Public License. It also provides other free software developers Less
-of an advantage over competing non-free programs. These disadvantages
-are the reason we use the ordinary General Public License for many
-libraries. However, the Lesser license provides advantages in certain
-special circumstances.
-
- For example, on rare occasions, there may be a special need to
-encourage the widest possible use of a certain library, so that it becomes
-a de-facto standard. To achieve this, non-free programs must be
-allowed to use the library. A more frequent case is that a free
-library does the same job as widely used non-free libraries. In this
-case, there is little to gain by limiting the free library to free
-software only, so we use the Lesser General Public License.
-
- In other cases, permission to use a particular library in non-free
-programs enables a greater number of people to use a large body of
-free software. For example, permission to use the GNU C Library in
-non-free programs enables many more people to use the whole GNU
-operating system, as well as its variant, the GNU/Linux operating
-system.
-
- Although the Lesser General Public License is Less protective of the
-users' freedom, it does ensure that the user of a program that is
-linked with the Library has the freedom and the wherewithal to run
-that program using a modified version of the Library.
-
- The precise terms and conditions for copying, distribution and
-modification follow. Pay close attention to the difference between a
-"work based on the library" and a "work that uses the library". The
-former contains code derived from the library, whereas the latter must
-be combined with the library in order to run.
-
- GNU LESSER GENERAL PUBLIC LICENSE
- TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
-
- 0. This License Agreement applies to any software library or other
-program which contains a notice placed by the copyright holder or
-other authorized party saying it may be distributed under the terms of
-this Lesser General Public License (also called "this License").
-Each licensee is addressed as "you".
-
- A "library" means a collection of software functions and/or data
-prepared so as to be conveniently linked with application programs
-(which use some of those functions and data) to form executables.
-
- The "Library", below, refers to any such software library or work
-which has been distributed under these terms. A "work based on the
-Library" means either the Library or any derivative work under
-copyright law: that is to say, a work containing the Library or a
-portion of it, either verbatim or with modifications and/or translated
-straightforwardly into another language. (Hereinafter, translation is
-included without limitation in the term "modification".)
-
- "Source code" for a work means the preferred form of the work for
-making modifications to it. For a library, complete source code means
-all the source code for all modules it contains, plus any associated
-interface definition files, plus the scripts used to control compilation
-and installation of the library.
-
- Activities other than copying, distribution and modification are not
-covered by this License; they are outside its scope. The act of
-running a program using the Library is not restricted, and output from
-such a program is covered only if its contents constitute a work based
-on the Library (independent of the use of the Library in a tool for
-writing it). Whether that is true depends on what the Library does
-and what the program that uses the Library does.
-
- 1. You may copy and distribute verbatim copies of the Library's
-complete source code as you receive it, in any medium, provided that
-you conspicuously and appropriately publish on each copy an
-appropriate copyright notice and disclaimer of warranty; keep intact
-all the notices that refer to this License and to the absence of any
-warranty; and distribute a copy of this License along with the
-Library.
-
- You may charge a fee for the physical act of transferring a copy,
-and you may at your option offer warranty protection in exchange for a
-fee.
-
- 2. You may modify your copy or copies of the Library or any portion
-of it, thus forming a work based on the Library, and copy and
-distribute such modifications or work under the terms of Section 1
-above, provided that you also meet all of these conditions:
-
- a) The modified work must itself be a software library.
-
- b) You must cause the files modified to carry prominent notices
- stating that you changed the files and the date of any change.
-
- c) You must cause the whole of the work to be licensed at no
- charge to all third parties under the terms of this License.
-
- d) If a facility in the modified Library refers to a function or a
- table of data to be supplied by an application program that uses
- the facility, other than as an argument passed when the facility
- is invoked, then you must make a good faith effort to ensure that,
- in the event an application does not supply such function or
- table, the facility still operates, and performs whatever part of
- its purpose remains meaningful.
-
- (For example, a function in a library to compute square roots has
- a purpose that is entirely well-defined independent of the
- application. Therefore, Subsection 2d requires that any
- application-supplied function or table used by this function must
- be optional: if the application does not supply it, the square
- root function must still compute square roots.)
-
-These requirements apply to the modified work as a whole. If
-identifiable sections of that work are not derived from the Library,
-and can be reasonably considered independent and separate works in
-themselves, then this License, and its terms, do not apply to those
-sections when you distribute them as separate works. But when you
-distribute the same sections as part of a whole which is a work based
-on the Library, the distribution of the whole must be on the terms of
-this License, whose permissions for other licensees extend to the
-entire whole, and thus to each and every part regardless of who wrote
-it.
-
-Thus, it is not the intent of this section to claim rights or contest
-your rights to work written entirely by you; rather, the intent is to
-exercise the right to control the distribution of derivative or
-collective works based on the Library.
-
-In addition, mere aggregation of another work not based on the Library
-with the Library (or with a work based on the Library) on a volume of
-a storage or distribution medium does not bring the other work under
-the scope of this License.
-
- 3. You may opt to apply the terms of the ordinary GNU General Public
-License instead of this License to a given copy of the Library. To do
-this, you must alter all the notices that refer to this License, so
-that they refer to the ordinary GNU General Public License, version 2,
-instead of to this License. (If a newer version than version 2 of the
-ordinary GNU General Public License has appeared, then you can specify
-that version instead if you wish.) Do not make any other change in
-these notices.
-
- Once this change is made in a given copy, it is irreversible for
-that copy, so the ordinary GNU General Public License applies to all
-subsequent copies and derivative works made from that copy.
-
- This option is useful when you wish to copy part of the code of
-the Library into a program that is not a library.
-
- 4. You may copy and distribute the Library (or a portion or
-derivative of it, under Section 2) in object code or executable form
-under the terms of Sections 1 and 2 above provided that you accompany
-it with the complete corresponding machine-readable source code, which
-must be distributed under the terms of Sections 1 and 2 above on a
-medium customarily used for software interchange.
-
- If distribution of object code is made by offering access to copy
-from a designated place, then offering equivalent access to copy the
-source code from the same place satisfies the requirement to
-distribute the source code, even though third parties are not
-compelled to copy the source along with the object code.
-
- 5. A program that contains no derivative of any portion of the
-Library, but is designed to work with the Library by being compiled or
-linked with it, is called a "work that uses the Library". Such a
-work, in isolation, is not a derivative work of the Library, and
-therefore falls outside the scope of this License.
-
- However, linking a "work that uses the Library" with the Library
-creates an executable that is a derivative of the Library (because it
-contains portions of the Library), rather than a "work that uses the
-library". The executable is therefore covered by this License.
-Section 6 states terms for distribution of such executables.
-
- When a "work that uses the Library" uses material from a header file
-that is part of the Library, the object code for the work may be a
-derivative work of the Library even though the source code is not.
-Whether this is true is especially significant if the work can be
-linked without the Library, or if the work is itself a library. The
-threshold for this to be true is not precisely defined by law.
-
- If such an object file uses only numerical parameters, data
-structure layouts and accessors, and small macros and small inline
-functions (ten lines or less in length), then the use of the object
-file is unrestricted, regardless of whether it is legally a derivative
-work. (Executables containing this object code plus portions of the
-Library will still fall under Section 6.)
-
- Otherwise, if the work is a derivative of the Library, you may
-distribute the object code for the work under the terms of Section 6.
-Any executables containing that work also fall under Section 6,
-whether or not they are linked directly with the Library itself.
-
- 6. As an exception to the Sections above, you may also combine or
-link a "work that uses the Library" with the Library to produce a
-work containing portions of the Library, and distribute that work
-under terms of your choice, provided that the terms permit
-modification of the work for the customer's own use and reverse
-engineering for debugging such modifications.
-
- You must give prominent notice with each copy of the work that the
-Library is used in it and that the Library and its use are covered by
-this License. You must supply a copy of this License. If the work
-during execution displays copyright notices, you must include the
-copyright notice for the Library among them, as well as a reference
-directing the user to the copy of this License. Also, you must do one
-of these things:
-
- a) Accompany the work with the complete corresponding
- machine-readable source code for the Library including whatever
- changes were used in the work (which must be distributed under
- Sections 1 and 2 above); and, if the work is an executable linked
- with the Library, with the complete machine-readable "work that
- uses the Library", as object code and/or source code, so that the
- user can modify the Library and then relink to produce a modified
- executable containing the modified Library. (It is understood
- that the user who changes the contents of definitions files in the
- Library will not necessarily be able to recompile the application
- to use the modified definitions.)
-
- b) Use a suitable shared library mechanism for linking with the
- Library. A suitable mechanism is one that (1) uses at run time a
- copy of the library already present on the user's computer system,
- rather than copying library functions into the executable, and (2)
- will operate properly with a modified version of the library, if
- the user installs one, as long as the modified version is
- interface-compatible with the version that the work was made with.
-
- c) Accompany the work with a written offer, valid for at
- least three years, to give the same user the materials
- specified in Subsection 6a, above, for a charge no more
- than the cost of performing this distribution.
-
- d) If distribution of the work is made by offering access to copy
- from a designated place, offer equivalent access to copy the above
- specified materials from the same place.
-
- e) Verify that the user has already received a copy of these
- materials or that you have already sent this user a copy.
-
- For an executable, the required form of the "work that uses the
-Library" must include any data and utility programs needed for
-reproducing the executable from it. However, as a special exception,
-the materials to be distributed need not include anything that is
-normally distributed (in either source or binary form) with the major
-components (compiler, kernel, and so on) of the operating system on
-which the executable runs, unless that component itself accompanies
-the executable.
-
- It may happen that this requirement contradicts the license
-restrictions of other proprietary libraries that do not normally
-accompany the operating system. Such a contradiction means you cannot
-use both them and the Library together in an executable that you
-distribute.
-
- 7. You may place library facilities that are a work based on the
-Library side-by-side in a single library together with other library
-facilities not covered by this License, and distribute such a combined
-library, provided that the separate distribution of the work based on
-the Library and of the other library facilities is otherwise
-permitted, and provided that you do these two things:
-
- a) Accompany the combined library with a copy of the same work
- based on the Library, uncombined with any other library
- facilities. This must be distributed under the terms of the
- Sections above.
-
- b) Give prominent notice with the combined library of the fact
- that part of it is a work based on the Library, and explaining
- where to find the accompanying uncombined form of the same work.
-
- 8. You may not copy, modify, sublicense, link with, or distribute
-the Library except as expressly provided under this License. Any
-attempt otherwise to copy, modify, sublicense, link with, or
-distribute the Library is void, and will automatically terminate your
-rights under this License. However, parties who have received copies,
-or rights, from you under this License will not have their licenses
-terminated so long as such parties remain in full compliance.
-
- 9. You are not required to accept this License, since you have not
-signed it. However, nothing else grants you permission to modify or
-distribute the Library or its derivative works. These actions are
-prohibited by law if you do not accept this License. Therefore, by
-modifying or distributing the Library (or any work based on the
-Library), you indicate your acceptance of this License to do so, and
-all its terms and conditions for copying, distributing or modifying
-the Library or works based on it.
-
- 10. Each time you redistribute the Library (or any work based on the
-Library), the recipient automatically receives a license from the
-original licensor to copy, distribute, link with or modify the Library
-subject to these terms and conditions. You may not impose any further
-restrictions on the recipients' exercise of the rights granted herein.
-You are not responsible for enforcing compliance by third parties with
-this License.
-
- 11. If, as a consequence of a court judgment or allegation of patent
-infringement or for any other reason (not limited to patent issues),
-conditions are imposed on you (whether by court order, agreement or
-otherwise) that contradict the conditions of this License, they do not
-excuse you from the conditions of this License. If you cannot
-distribute so as to satisfy simultaneously your obligations under this
-License and any other pertinent obligations, then as a consequence you
-may not distribute the Library at all. For example, if a patent
-license would not permit royalty-free redistribution of the Library by
-all those who receive copies directly or indirectly through you, then
-the only way you could satisfy both it and this License would be to
-refrain entirely from distribution of the Library.
-
-If any portion of this section is held invalid or unenforceable under any
-particular circumstance, the balance of the section is intended to apply,
-and the section as a whole is intended to apply in other circumstances.
-
-It is not the purpose of this section to induce you to infringe any
-patents or other property right claims or to contest validity of any
-such claims; this section has the sole purpose of protecting the
-integrity of the free software distribution system which is
-implemented by public license practices. Many people have made
-generous contributions to the wide range of software distributed
-through that system in reliance on consistent application of that
-system; it is up to the author/donor to decide if he or she is willing
-to distribute software through any other system and a licensee cannot
-impose that choice.
-
-This section is intended to make thoroughly clear what is believed to
-be a consequence of the rest of this License.
-
- 12. If the distribution and/or use of the Library is restricted in
-certain countries either by patents or by copyrighted interfaces, the
-original copyright holder who places the Library under this License may add
-an explicit geographical distribution limitation excluding those countries,
-so that distribution is permitted only in or among countries not thus
-excluded. In such case, this License incorporates the limitation as if
-written in the body of this License.
-
- 13. The Free Software Foundation may publish revised and/or new
-versions of the Lesser General Public License from time to time.
-Such new versions will be similar in spirit to the present version,
-but may differ in detail to address new problems or concerns.
-
-Each version is given a distinguishing version number. If the Library
-specifies a version number of this License which applies to it and
-"any later version", you have the option of following the terms and
-conditions either of that version or of any later version published by
-the Free Software Foundation. If the Library does not specify a
-license version number, you may choose any version ever published by
-the Free Software Foundation.
-
- 14. If you wish to incorporate parts of the Library into other free
-programs whose distribution conditions are incompatible with these,
-write to the author to ask for permission. For software which is
-copyrighted by the Free Software Foundation, write to the Free
-Software Foundation; we sometimes make exceptions for this. Our
-decision will be guided by the two goals of preserving the free status
-of all derivatives of our free software and of promoting the sharing
-and reuse of software generally.
-
- NO WARRANTY
-
- 15. BECAUSE THE LIBRARY IS LICENSED FREE OF CHARGE, THERE IS NO
-WARRANTY FOR THE LIBRARY, TO THE EXTENT PERMITTED BY APPLICABLE LAW.
-EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR
-OTHER PARTIES PROVIDE THE LIBRARY "AS IS" WITHOUT WARRANTY OF ANY
-KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE
-LIBRARY IS WITH YOU. SHOULD THE LIBRARY PROVE DEFECTIVE, YOU ASSUME
-THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
-
- 16. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN
-WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY
-AND/OR REDISTRIBUTE THE LIBRARY AS PERMITTED ABOVE, BE LIABLE TO YOU
-FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR
-CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE
-LIBRARY (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING
-RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A
-FAILURE OF THE LIBRARY TO OPERATE WITH ANY OTHER SOFTWARE), EVEN IF
-SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
-DAMAGES.
-
- END OF TERMS AND CONDITIONS
-
- How to Apply These Terms to Your New Libraries
-
- If you develop a new library, and you want it to be of the greatest
-possible use to the public, we recommend making it free software that
-everyone can redistribute and change. You can do so by permitting
-redistribution under these terms (or, alternatively, under the terms of the
-ordinary General Public License).
-
- To apply these terms, attach the following notices to the library. It is
-safest to attach them to the start of each source file to most effectively
-convey the exclusion of warranty; and each file should have at least the
-"copyright" line and a pointer to where the full notice is found.
-
-
- Copyright (C)
-
- This library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- This library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with this library; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-
-Also add information on how to contact you by electronic and paper mail.
-
-You should also get your employer (if you work as a programmer) or your
-school, if any, to sign a "copyright disclaimer" for the library, if
-necessary. Here is a sample; alter the names:
-
- Yoyodyne, Inc., hereby disclaims all copyright interest in the
- library `Frob' (a library for tweaking knobs) written by James Random Hacker.
-
- , 1 April 1990
- Ty Coon, President of Vice
-
-That's all there is to it!
-
-
Index: trunk/VHDL/single_port.vhd
===================================================================
--- trunk/VHDL/single_port.vhd (revision 14)
+++ trunk/VHDL/single_port.vhd (nonexistent)
@@ -1,178 +0,0 @@
-----------------------------------------------------------------------
----- ----
----- Single port asynchronous RAM simulation model ----
----- ----
----- This file is part of the single_port project ----
----- ----
----- Description ----
----- This is a single port asynchronous memory. This files ----
----- describes three architectures. Two architectures are ----
----- traditional array based memories. One describes the memory ----
----- as an array of STD_LOGIC_VECTOR, and the other describes ----
----- the ARRAY as BIT_VECTOR. ----
----- The third architecture describes the memory arranged as a ----
----- linked list in order to conserve computer memory usage. The ----
----- memory is organized as a linked list of BIT_VECTOR arrays ----
----- whose size is defined by the constant PAGEDEPTH in ----
----- single_port_pkg.vhd. ----
----- ----
----- Authors: ----
----- - Robert Paley, rpaley_yid@yahoo.com ----
----- - Michael Geng, vhdl@MichaelGeng.de ----
----- ----
----- References: ----
----- 1. The Designer's Guide to VHDL by Peter Ashenden ----
----- ISBN: 1-55860-270-4 (pbk.) ----
----- 2. Writing Testbenches - Functional Verification of HDL ----
----- models by Janick Bergeron | ISBN: 0-7923-7766-4 ----
----- ----
-----------------------------------------------------------------------
----- ----
----- Copyright (C) 2005 Authors and OPENCORES.ORG ----
----- ----
----- This source file may be used and distributed without ----
----- restriction provided that this copyright statement is not ----
----- removed from the file and that any derivative work contains ----
----- the original copyright notice and the associated disclaimer. ----
----- ----
----- This source file is free software; you can redistribute it ----
----- and/or modify it under the terms of the GNU Lesser General ----
----- Public License as published by the Free Software Foundation; ----
----- either version 2.1 of the License, or (at your option) any ----
----- later version. ----
----- ----
----- This source is distributed in the hope that it will be ----
----- useful, but WITHOUT ANY WARRANTY; without even the implied ----
----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
----- PURPOSE. See the GNU Lesser General Public License for more ----
----- details. ----
----- ----
----- You should have received a copy of the GNU Lesser General ----
----- Public License along with this source; if not, download it ----
----- from http://www.opencores.org/lgpl.shtml ----
----- ----
-----------------------------------------------------------------------
---
--- CVS Revision History
---
--- $Log: not supported by cvs2svn $
--- Revision 1.4 2005/11/19 15:18:54 mgeng
--- rnw replaced by nce, nwe and noe, tristate drivers added
---
--- Revision 1.3 2005/10/25 18:26:52 mgeng
--- PAGENUM constant removed because the address bus width provides this information
---
--- Revision 1.2 2005/10/12 19:39:27 mgeng
--- Buses unconstrained, LGPL header added
---
--- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid
--- initial checkin
---
--- Revision 1.1 2003/01/14 17:48:31 Default
--- Initial revision
---
--- Revision 1.1 2002/12/24 18:09:05 Default
--- Initial revision
---
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE WORK.single_port_pkg.ALL;
-USE WORK.linked_list_mem_pkg.ALL;
-
-ENTITY single_port IS
- GENERIC (
- rnwtQ : TIME := 1 NS);
- PORT (
- d : IN STD_LOGIC_VECTOR; -- data bus input
- q : OUT STD_LOGIC_VECTOR; -- data bus output
- a : IN STD_LOGIC_VECTOR; -- address bus
- nce : IN STD_LOGIC; -- not chip enable
- nwe : IN STD_LOGIC; -- not write enable
- noe : IN STD_LOGIC; -- not output enable
- dealloc_mem : IN BOOLEAN := FALSE); -- control signal for deallocating memory,
- -- only used in the linked list implementation
-END ENTITY single_port;
-
-ARCHITECTURE ArrayMemNoFlag OF single_port IS
-BEGIN
-
- mem_proc : PROCESS(d, a, nce, nwe, noe)
- TYPE mem_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF STD_LOGIC_VECTOR(d'RANGE);
- VARIABLE mem : mem_typ;
- BEGIN
- IF ( nce = '0' ) AND ( nwe = '0' ) THEN -- Write
- mem(TO_INTEGER(unsigned(a))) := d;
- END IF;
-
- IF ( nce = '0' ) AND ( noe = '0' ) THEN -- Read
- q <= mem(TO_INTEGER(unsigned(a))) AFTER rnwtQ;
- ELSE
- q <= (q'RANGE => 'Z') AFTER rnwtQ;
- END IF;
- END PROCESS mem_proc;
-
-END ArrayMemNoFlag;
-
-ARCHITECTURE ArrayMem OF single_port IS
-BEGIN
-
- mem_proc : PROCESS(d, a, nce, nwe, noe)
- TYPE mem_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF BIT_VECTOR(d'RANGE);
- TYPE flag_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF BOOLEAN;
- VARIABLE mem : mem_typ;
- VARIABLE flag : flag_typ;
- BEGIN
- IF ( nce = '0' ) AND ( nwe = '0' ) THEN -- Write
- mem( TO_INTEGER(unsigned(a))) := TO_BITVECTOR(d);
- flag(TO_INTEGER(unsigned(a))) := true; -- set valid memory location flag
- END IF;
-
- IF ( nce = '0' ) AND ( noe = '0' ) THEN -- Read
- IF ( flag(TO_INTEGER(unsigned(a))) = true ) THEN -- read data, either valid or 'U'
- q <= TO_STDLOGICVECTOR(mem(TO_INTEGER(unsigned(a)))) AFTER rnwtQ;
- ELSE -- reading invalid memory location
- q <= (q'RANGE => 'U') AFTER rnwtQ;
- END IF;
- ELSE
- q <= (q'RANGE => 'Z') AFTER rnwtQ;
- END IF;
- END PROCESS mem_proc;
-END ArrayMem;
-
-ARCHITECTURE LinkedList OF single_port IS
- CONSTANT WRITE_MEM : BOOLEAN := true;
- CONSTANT READ_MEM : BOOLEAN := false;
-BEGIN
-
- mem_proc : PROCESS(d, a, nce, nwe, noe, dealloc_mem)
- VARIABLE mem_page_v : mem_page_ptr;
- VARIABLE d_v : STD_LOGIC_VECTOR(d'RANGE);
- VARIABLE a_v : addr_typ;
- BEGIN
- IF NOT dealloc_mem THEN
- d_v := d;
- if (nce = '0') then
- a_v := TO_INTEGER(unsigned(a));
- end if;
- IF ( nce = '0' ) AND ( nwe = '0' ) THEN -- Write
- rw_mem( data => d_v,
- addr => a_v,
- next_cell => mem_page_v,
- write_flag => WRITE_MEM);
- END IF;
-
- IF ( nce = '0' ) AND ( noe = '0' ) THEN -- Read
- rw_mem( data => d_v,
- addr => a_v,
- next_cell => mem_page_v,
- write_flag => READ_MEM);
- q <= d_v AFTER rnwtQ;
- ELSE
- q <= (q'RANGE => 'Z') AFTER rnwtQ;
- END IF;
- ELSE -- Deallocate memory from work station memory.
- deallocate_mem(mem_page_v);
- END IF;
- END PROCESS mem_proc;
-END LinkedList;
Index: trunk/VHDL/single_port_pkg.vhd
===================================================================
--- trunk/VHDL/single_port_pkg.vhd (revision 14)
+++ trunk/VHDL/single_port_pkg.vhd (nonexistent)
@@ -1,84 +0,0 @@
-----------------------------------------------------------------------
----- ----
----- Single port asynchronous RAM simulation model ----
----- ----
----- This file is part of the single_port project ----
----- ----
----- Description ----
----- Package file for single_port memory and testbench ----
----- ----
----- Authors: ----
----- - Robert Paley, rpaley_yid@yahoo.com ----
----- - Michael Geng, vhdl@MichaelGeng.de ----
----- ----
----- References: ----
----- 1. The Designer's Guide to VHDL by Peter Ashenden ----
----- ISBN: 1-55860-270-4 (pbk.) ----
----- 2. Writing Testbenches - Functional Verification of HDL ----
----- models by Janick Bergeron | ISBN: 0-7923-7766-4 ----
----- ----
-----------------------------------------------------------------------
----- ----
----- Copyright (C) 2005 Authors and OPENCORES.ORG ----
----- ----
----- This source file may be used and distributed without ----
----- restriction provided that this copyright statement is not ----
----- removed from the file and that any derivative work contains ----
----- the original copyright notice and the associated disclaimer. ----
----- ----
----- This source file is free software; you can redistribute it ----
----- and/or modify it under the terms of the GNU Lesser General ----
----- Public License as published by the Free Software Foundation; ----
----- either version 2.1 of the License, or (at your option) any ----
----- later version. ----
----- ----
----- This source is distributed in the hope that it will be ----
----- useful, but WITHOUT ANY WARRANTY; without even the implied ----
----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
----- PURPOSE. See the GNU Lesser General Public License for more ----
----- details. ----
----- ----
----- You should have received a copy of the GNU Lesser General ----
----- Public License along with this source; if not, download it ----
----- from http://www.opencores.org/lgpl.shtml ----
----- ----
-----------------------------------------------------------------------
---
--- CVS Revision History
---
--- $Log: not supported by cvs2svn $
--- Revision 1.3 2005/10/25 18:26:52 mgeng
--- PAGENUM constant removed because the address bus width provides this information
---
--- Revision 1.2 2005/10/12 19:39:27 mgeng
--- Buses unconstrained, LGPL header added
---
--- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid
--- initial checkin
---
--- Revision 1.1 2003/01/14 17:48:44 Default
--- Initial revision
---
--- Revision 1.1 2002/12/24 17:58:49 Default
--- Initial revision
---
-LIBRARY IEEE;
- USE IEEE.STD_LOGIC_1164.ALL;
- USE IEEE.NUMERIC_STD.ALL;
-
-PACKAGE single_port_pkg IS
- -- Address bus type for internal memory
- SUBTYPE addr_typ IS NATURAL;
- -- Operations testbench can do.
- TYPE do_typ IS ( init , read , write , dealloc , end_test );
-
- TYPE to_srv_typ IS RECORD -- Record passed from test case to test bench
- do : do_typ;
- addr : INTEGER;
- data : INTEGER;
- event : BOOLEAN;
- END RECORD to_srv_typ;
-END PACKAGE single_port_pkg;
-
-PACKAGE BODY single_port_pkg IS
-END PACKAGE BODY single_port_pkg;
Index: trunk/VHDL/tb_single_port.vhd
===================================================================
--- trunk/VHDL/tb_single_port.vhd (revision 14)
+++ trunk/VHDL/tb_single_port.vhd (nonexistent)
@@ -1,225 +0,0 @@
-----------------------------------------------------------------------
----- ----
----- Single port asynchronous RAM simulation model ----
----- ----
----- This file is part of the single_port project ----
----- ----
----- Description ----
----- This file specifies test bench harness for the single_port ----
----- Memory. It also contains the configuration files for all the ----
----- tests. ----
----- ----
----- Authors: ----
----- - Robert Paley, rpaley_yid@yahoo.com ----
----- - Michael Geng, vhdl@MichaelGeng.de ----
----- ----
----- References: ----
----- 1. The Designer's Guide to VHDL by Peter Ashenden ----
----- ISBN: 1-55860-270-4 (pbk.) ----
----- 2. Writing Testbenches - Functional Verification of HDL ----
----- models by Janick Bergeron | ISBN: 0-7923-7766-4 ----
----- ----
-----------------------------------------------------------------------
----- ----
----- Copyright (C) 2005 Authors and OPENCORES.ORG ----
----- ----
----- This source file may be used and distributed without ----
----- restriction provided that this copyright statement is not ----
----- removed from the file and that any derivative work contains ----
----- the original copyright notice and the associated disclaimer. ----
----- ----
----- This source file is free software; you can redistribute it ----
----- and/or modify it under the terms of the GNU Lesser General ----
----- Public License as published by the Free Software Foundation; ----
----- either version 2.1 of the License, or (at your option) any ----
----- later version. ----
----- ----
----- This source is distributed in the hope that it will be ----
----- useful, but WITHOUT ANY WARRANTY; without even the implied ----
----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
----- PURPOSE. See the GNU Lesser General Public License for more ----
----- details. ----
----- ----
----- You should have received a copy of the GNU Lesser General ----
----- Public License along with this source; if not, download it ----
----- from http://www.opencores.org/lgpl.shtml ----
----- ----
-----------------------------------------------------------------------
---
--- CVS Revision History
---
--- $Log: not supported by cvs2svn $
--- Revision 1.2 2005/10/12 19:39:27 mgeng
--- Buses unconstrained, LGPL header added
---
--- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid
--- initial checkin
---
--- Revision 1.1 2003/01/14 17:49:04 Default
--- Initial revision
---
--- Revision 1.2 2002/12/31 19:19:43 Default
--- Updated 'transaction statements for fixed simulator.
---
--- Revision 1.1 2002/12/24 18:10:18 Default
--- Initial revision
---
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE WORK.linked_list_mem_pkg.ALL;
-USE WORK.single_port_pkg.all;
-USE STD.TEXTIO.ALL;
-
-ENTITY tb_single_port IS
-END ENTITY tb_single_port;
-
-ARCHITECTURE BHV of tb_single_port IS
-
-COMPONENT single_port IS
- GENERIC (
- rnwtQ : TIME := 1 NS);
- PORT (
- d : IN STD_LOGIC_VECTOR;
- q : OUT STD_LOGIC_VECTOR;
- a : IN STD_LOGIC_VECTOR;
- nce : IN STD_LOGIC;
- nwe : IN STD_LOGIC;
- noe : IN STD_LOGIC;
- dealloc_mem : BOOLEAN);
-END COMPONENT single_port;
-
-COMPONENT tc_single_port IS
- PORT (
- to_srv : OUT to_srv_typ;
- frm_srv : IN STD_LOGIC_VECTOR);
-END COMPONENT tc_single_port;
- CONSTANT DATA_WIDTH : INTEGER := 32;
- CONSTANT ADDR_WIDTH : INTEGER := 16;
-
- SIGNAL d : STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0);
- SIGNAL q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0);
- SIGNAL a : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
- SIGNAL nce, nwe, noe : STD_LOGIC;
- SIGNAL dealloc_mem : BOOLEAN;
- SIGNAL to_srv : to_srv_typ;
- SIGNAL frm_srv : STD_LOGIC_VECTOR(d'RANGE);
- SIGNAL tie_vdd : STD_LOGIC := '1';
-BEGIN
- dut : single_port
- PORT MAP (
- d => d,
- a => a,
- q => q,
- nce => nce,
- nwe => nwe,
- noe => noe,
- dealloc_mem => dealloc_mem);
-
- tc : tc_single_port
- PORT MAP (
- to_srv => to_srv,
- frm_srv => frm_srv);
-
- single_port_server : PROCESS
- VARIABLE frm_srv_v : STD_LOGIC_VECTOR(d'RANGE);
- CONSTANT ACCESS_DELAY : TIME := 5 NS;
- BEGIN
- -- Wait until the test case is finished setting up the next memory access.
- WAIT ON to_srv'TRANSACTION;
- CASE to_srv.do IS
- WHEN init =>
- ASSERT FALSE
- REPORT "initialized"
- SEVERITY NOTE;
- WHEN read => -- perform memory read
- d <= STD_LOGIC_VECTOR(TO_SIGNED(to_srv.data, d'length));
- a <= STD_LOGIC_VECTOR(TO_UNSIGNED(to_srv.addr, a'length));
- nce <= '0';
- noe <= '0';
- nwe <= '1';
- -- Wait for data to appear
- WAIT FOR ACCESS_DELAY;
- WHEN write => -- perform memory write
- d <= STD_LOGIC_VECTOR(TO_SIGNED(to_srv.data, d'length));
- a <= STD_LOGIC_VECTOR(TO_UNSIGNED(to_srv.addr, a'length));
- nce <= '0';
- noe <= '1';
- nwe <= '0';
- WAIT FOR ACCESS_DELAY;
- WHEN dealloc => -- deallocate the linked list for the LL architecture
- dealloc_mem <= true;
- WHEN end_test => -- reached the end of the test case
- WAIT;
- END CASE;
- frm_srv_v := q;
- -- Send message to test case to continue the test.
- frm_srv <= frm_srv_v ; WAIT FOR 0 NS;
- END PROCESS single_port_server;
-END BHV;
-
-CONFIGURATION ll_main_cfg OF TB_SINGLE_PORT IS
- FOR BHV
- FOR dut : single_port
- USE ENTITY work.single_port(LinkedList);
- END FOR; -- dut
- FOR tc : tc_single_port
- USE ENTITY work.tc_single_port(TC0);
- END FOR; -- tc;
- END FOR; -- BHV
-END CONFIGURATION ll_main_cfg;
-
-CONFIGURATION ll_error_cfg OF TB_SINGLE_PORT IS
- FOR BHV
- FOR dut : single_port
- USE ENTITY work.single_port(LinkedList);
- END FOR; -- dut
- FOR tc : tc_single_port
- USE ENTITY work.tc_single_port(TC1);
- END FOR; -- tc;
- END FOR; -- BHV
-END CONFIGURATION ll_error_cfg ;
-
-CONFIGURATION mem_main_cfg of TB_SINGLE_PORT IS
- FOR BHV
- FOR dut : single_port
- USE ENTITY work.single_port(ArrayMem);
- END FOR; -- dut
- FOR tc : tc_single_port
- USE ENTITY work.tc_single_port(TC0);
- END FOR; -- tc;
- END FOR; -- BHV
-END CONFIGURATION mem_main_cfg;
-
-CONFIGURATION mem_error_cfg of TB_SINGLE_PORT IS
- FOR BHV
- FOR dut : single_port
- USE ENTITY work.single_port(ArrayMem);
- END FOR; -- dut
- FOR tc : tc_single_port
- USE ENTITY work.tc_single_port(TC1);
- END FOR; -- tc;
- END FOR; -- BHV
-END CONFIGURATION mem_error_cfg;
-
-CONFIGURATION memnoflag_main_cfg of TB_SINGLE_PORT IS
- FOR BHV
- FOR dut : single_port
- USE ENTITY work.single_port(ArrayMemNoFlag);
- END FOR; -- dut
- FOR tc : tc_single_port
- USE ENTITY work.tc_single_port(TC0);
- END FOR; -- tc;
- END FOR; -- BHV
-END CONFIGURATION memnoflag_main_cfg;
-
-CONFIGURATION memnoflag_error_cfg of TB_SINGLE_PORT IS
- FOR BHV
- FOR dut : single_port
- USE ENTITY work.single_port(ArrayMemNoFlag);
- END FOR; -- dut
- FOR tc : tc_single_port
- USE ENTITY work.tc_single_port(TC1);
- END FOR; -- tc;
- END FOR; -- BHV
-END CONFIGURATION memnoflag_error_cfg;
Index: trunk/VHDL/tc_single_port.vhd
===================================================================
--- trunk/VHDL/tc_single_port.vhd (revision 14)
+++ trunk/VHDL/tc_single_port.vhd (nonexistent)
@@ -1,214 +0,0 @@
-----------------------------------------------------------------------
----- ----
----- Single port asynchronous RAM simulation model ----
----- ----
----- This file is part of the single_port project ----
----- ----
----- Description ----
----- This file specifies test cases for the single_port Memory. ----
----- ----
----- Authors: ----
----- - Robert Paley, rpaley_yid@yahoo.com ----
----- - Michael Geng, vhdl@MichaelGeng.de ----
----- ----
----- References: ----
----- 1. The Designer's Guide to VHDL by Peter Ashenden ----
----- ISBN: 1-55860-270-4 (pbk.) ----
----- 2. Writing Testbenches - Functional Verification of HDL ----
----- models by Janick Bergeron | ISBN: 0-7923-7766-4 ----
----- ----
-----------------------------------------------------------------------
----- ----
----- Copyright (C) 2005 Authors and OPENCORES.ORG ----
----- ----
----- This source file may be used and distributed without ----
----- restriction provided that this copyright statement is not ----
----- removed from the file and that any derivative work contains ----
----- the original copyright notice and the associated disclaimer. ----
----- ----
----- This source file is free software; you can redistribute it ----
----- and/or modify it under the terms of the GNU Lesser General ----
----- Public License as published by the Free Software Foundation; ----
----- either version 2.1 of the License, or (at your option) any ----
----- later version. ----
----- ----
----- This source is distributed in the hope that it will be ----
----- useful, but WITHOUT ANY WARRANTY; without even the implied ----
----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
----- PURPOSE. See the GNU Lesser General Public License for more ----
----- details. ----
----- ----
----- You should have received a copy of the GNU Lesser General ----
----- Public License along with this source; if not, download it ----
----- from http://www.opencores.org/lgpl.shtml ----
----- ----
-----------------------------------------------------------------------
---
--- CVS Revision History
---
--- $Log: not supported by cvs2svn $
--- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid
--- initial checkin
---
--- Revision 1.1 2003/01/14 17:49:04 Default
--- Initial revision
---
--- Revision 1.2 2002/12/31 19:19:43 Default
--- Updated 'transaction statements for fixed simulator.
---
--- Revision 1.1 2002/12/24 18:13:50 Default
--- Initial revision
---
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE WORK.SINGLE_PORT_PKG.ALL;
-USE WORK.PKG_IMAGE.ALL;
-
-ENTITY tc_single_port IS
-PORT (
- to_srv : OUT to_srv_typ;
- frm_srv : IN STD_LOGIC_VECTOR);
-END ENTITY tc_single_port;
-
--- --------------------------------------------------
--- Test Case TC0
--- This test case is to check two pages of memory
--- Starting at physical address 0x0 ,
--- Write a '1' to bit position 0, leaving all other bits 0.
--- Increment the address,
--- Write a '1' to bit position 1, leaving all other bits 0.
--- Increment the address.
--- Write a '1' to bit position 2, leaving all other bits 0.
--- Continue in this fasion, until write a 1 to the MSB.
--- increment the address,
--- Write a '1' to bit position 0, leaving all other bits 0.
--- Continue until the entire page is written to.
--- Read back all addresses in the page, ensuring the
--- correct data is read back.
--- --------------------------------------------------
-
-
-ARCHITECTURE TC0 OF tc_single_port IS
-BEGIN
- MAIN : PROCESS
- VARIABLE to_srv_v : to_srv_typ;
- VARIABLE frm_srv_v : STD_LOGIC_VECTOR(frm_srv'RANGE);
- VARIABLE dv : STD_LOGIC_VECTOR(frm_srv'RANGE) :=
- STD_LOGIC_VECTOR(TO_UNSIGNED(1, frm_srv'length));
- VARIABLE offset_v : INTEGER;
- BEGIN
- offset_v := 0;
- -- Run this write/read test 10 times for benchmark
- -- purposes.
- FOR i IN 0 to 9 LOOP
- FOR index IN 0 to 2*PAGEDEPTH-1 LOOP
- -- Specify to testbench server to perform write operation;
- to_srv_v.do := write;
- to_srv_v.data := TO_INTEGER(SIGNED(dv)); -- specify data to write
- dv := To_StdLogicVector(TO_BitVector(dv) ROL 1); -- ROL 1 for next write
- -- Specify physical address.
- to_srv_v.addr := index+offset_v;
- to_srv <= to_srv_v;
- WAIT ON frm_srv'TRANSACTION;
- END LOOP;
- -- Reset data to 1.
- dv := STD_LOGIC_VECTOR(TO_UNSIGNED(1,frm_srv'length));
- FOR index IN 0 to 2*PAGEDEPTH-1 LOOP
- -- Perform read operation.
- to_srv_v.do := read;
- -- Specify physical address.
- to_srv_v.addr := index+offset_v;
- to_srv <= to_srv_v;
- WAIT ON frm_srv'TRANSACTION;
- -- Compare actual with expected read back data, if the
- -- the expected and actual to not compare, print the
- -- expected and actual values.
- ASSERT frm_srv = dv
- REPORT "Expected: " & HexImage(frm_srv) &
- " did not equal Actual: " & HexImage(dv)
- SEVERITY ERROR;
- -- Set expected data for next read.
- dv := TO_STDLOGICVECTOR(TO_BITVECTOR(dv) ROL 1);
- END LOOP;
- END LOOP;
- to_srv_v.do := dealloc; -- Deallocate memory
- --
- to_srv <= to_srv_v;
- -- Tell test bench server process test completed.
- to_srv_v.do := end_test;
- to_srv <= to_srv_v;
- ASSERT FALSE
- REPORT "Completed Test TC0"
- SEVERITY NOTE;
- WAIT;
- END PROCESS main;
-END TC0;
-
--- --------------------------------------------------
--- Test Case TC1
--- This test case is to check if the test bench will
--- return 'U' for invalid memory locations for
--- single_port architectures ArrayMem and LinkedList
--- --------------------------------------------------
-ARCHITECTURE TC1 OF tc_single_port IS
-BEGIN
- MAIN : PROCESS
- VARIABLE to_srv_v : to_srv_typ;
- VARIABLE frm_srv_v : STD_LOGIC_VECTOR(frm_srv'RANGE);
- VARIABLE dv : STD_LOGIC_VECTOR(frm_srv'RANGE) := (OTHERS => 'U');
- BEGIN
- -- Perform read operation.
- to_srv_v.do := read;
- -- Specify physical address.
- to_srv_v.addr := 0;
- to_srv <= to_srv_v;
- WAIT ON frm_srv'TRANSACTION;
- -- Compare actual with expected read back data, if the
- -- the expected and actual to not compare, print the
- -- expected and actual values.
- ASSERT frm_srv = dv
- REPORT "Expected: " & HexImage(frm_srv) &
- " did not equal Actual: " & HexImage(dv)
- SEVERITY ERROR;
-
- -- Write and read back from same address.
-
- -- Specify to testbench server to perform write operation;
- to_srv_v.do := write;
- dv := X"a5a5a5a5";
- to_srv_v.data := TO_INTEGER(SIGNED(dv)); -- specify data to write
- -- Specify physical address.
- to_srv_v.addr := 0;
- to_srv <= to_srv_v;
- -- Wait until the test bench server finished with the write.
- -- WAIT UNTIL frm_srv.event = true;
- WAIT ON frm_srv'TRANSACTION;
-
- to_srv_v.do := read;
- -- Specify physical address.
- to_srv_v.addr := 0;
- to_srv <= to_srv_v;
- WAIT ON frm_srv'TRANSACTION;
-
- -- Compare actual with expected read back data, if the
- -- the expected and actual to not compare, print the
- -- expected and actual values.
- ASSERT frm_srv = dv
- REPORT "Expected: " & HexImage(frm_srv) &
- " did not equal Actual: " & HexImage(dv)
- SEVERITY ERROR;
-
- to_srv_v.do := dealloc; -- Deallocate memory
- --
- to_srv <= to_srv_v;
- -- Tell test bench server process test completed.
- to_srv_v.do := end_test;
- to_srv <= to_srv_v;
-
- ASSERT FALSE
- REPORT "Completed Test TC1"
- SEVERITY NOTE;
- WAIT;
- END PROCESS main;
-END TC1;
Index: trunk/VHDL/Makefile
===================================================================
--- trunk/VHDL/Makefile (revision 14)
+++ trunk/VHDL/Makefile (nonexistent)
@@ -1,161 +0,0 @@
-#
-# Description: Top level make file for single_port test project.
-# make com to compile
-# make sim to simulate all tests
-# make ll_error to run this test only
-# make ll_main to run this test only
-# make mem_main to run this test only
-# make mem_error to run this test only
-# make memnoflag_main to run this test
-# make memnoflag_error to run this test
-# $Author: rpaley_yid $
-# $Date: 2003-01-14 21:48:11 $
-# $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/Makefile,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $
-# $Locker: $
-# $Revision: 1.1.1.1 $
-# $State: Exp $
-
-# VCOM , VSIM , and WORK variables are set for Sonata simulator,
-# Change appropriately for your simulator. Ex.for Modeltech,
-# VCOM = vcom
-# VSIM = vsim
-# WORK = work
-
-SHELL = /bin/sh
-VCOM = vhdlp
-VCOMOPT = -s
-VSIM = vhdle
-VSIMOPT =
-WORK = work.sym
-## Need to figure out how to put Bourne shell stuff in Makefile
-## will do so to generate log files in
-## LOGDIR = ../LOG/
-## For now, log files are in VHDL directory.
-
-
-# List of main compiled objects, does not include configurations,
-# which are included in the tb_single_port.vhd file.
-# These targets are for the Sonata simulator, adjust accordingly for
-# your simulator.
-
-SINGLE_PORT_PKG_OBJ = $(WORK)/single_port_pkg/prim.var
-LINKED_LIST_MEM_OBJ = $(WORK)/linked_list_mem_pkg/prim.var
-PKG_IMAGE_OBJ = $(WORK)/pkg_image/prim.var
-SINGLE_PORT_OBJ = $(WORK)/single_port/prim.var
-TC_SINGLE_PORT_OBJ = $(WORK)/tc_single_port/prim.var
-TB_SINGLE_PORT_OBJ = $(WORK)/tb_single_port/prim.var
-LL_ERROR_DEP = $(WORK)/ll_error_cfg/prim.var
-LL_MAIN_DEP = $(WORK)/ll_main_cfg/prim.var
-MEM_MAIN_DEP = $(WORK)/mem_main_cfg/prim.var
-MEM_ERROR_DEP = $(WORK)/mem_error_cfg/prim.var
-MEMNOFLAG_MAIN_DEP = $(WORK)/memnoflag_main_cfg/prim.var
-MEMNOFLAG_ERROR_DEP = $(WORK)/memnoflag_error_cfg/prim.var
-
-LL_ERROR = $(LOGDIR)ll_error.log
-LL_MAIN = ll_main.log
-MEM_MAIN = mem_main.log
-MEM_ERROR = mem_error.log
-MEMNOFLAG_MAIN = memnoflag_main.log
-MEMNOFLAG_ERROR = memnoflag_error.log
-
-OBJS = $(SINGLE_PORT_PKG_OBJ) \
- $(LINKED_LIST_MEM_OBJ) \
- $(PKG_IMAGE_OBJ) \
- $(SINGLE_PORT_OBJ) \
- $(TC_SINGLE_PORT_OBJ) \
- $(TB_SINGLE_PORT_OBJ)
-
-SIMOBJS = $(LL_ERROR) \
- $(LL_MAIN) \
- $(MEM_MAIN) \
- $(MEM_ERROR) \
- $(MEMNOFLAG_MAIN) \
- $(MEMNOFLAG_ERROR)
-
-# Compile the project
-com: $(OBJS)
-
-# Clean the library
-clean:: $(WORK)
-
-# Simulate all tests
-sim: $(SIMOBJS)
-
-## Run only ll_error test
-ll_error: $(LL_ERROR)
-
-# Run onle ll_main test
-ll_main: $(LL_MAIN)
-
-# Run only mem_main test
-mem_main: $(MEM_MAIN)
-
-# Run only mem_error test
-mem_error: $(MEM_ERROR)
-
-# Run only memnoflag_main test
-memnoflag_main: $(MEMNOFLAG_MAIN)
-
-# Run only memnoflag_error test
-memnoflag_error: $(MEMNOFLAG_ERROR)
-
-# Target dependency rules to run tests
-$(LL_ERROR) : $(LL_ERROR_DEP)
- $(VSIM) $(VSIMOPT) ll_error_cfg | tee $@
-
-$(LL_MAIN) : $(LL_MAIN_DEP)
- $(VSIM) $(VSIMOPT) ll_main_cfg | tee $@
-
-$(MEM_MAIN) : $(MEM_MAIN_DEP)
- $(VSIM) $(VSIMOPT) mem_main_cfg | tee $@
-
-$(MEM_ERROR) : $(MEM_ERROR_DEP)
- $(VSIM) $(VSIMOPT) mem_error_cfg | tee $@
-
-$(MEMNOFLAG_MAIN) : $(MEMNOFLAG_MAIN_DEP)
- $(VSIM) $(VSIMOPT) memnoflag_main_cfg | tee $@
-
-$(MEMNOFLAG_ERROR) : $(MEMNOFLAG_ERROR_DEP)
- $(VSIM) $(VSIMOPT) memnoflag_error_cfg | tee $@
-
-# Target dependency rules to compile tests
-
-$(SINGLE_PORT_PKG_OBJ) : single_port_pkg.vhd
- $(VCOM) $(VCOMOPT) $<
-
-$(LINKED_LIST_MEM_OBJ) : linked_list_mem_pkg.vhd \
- $(SINGLE_PORT_PKG_OBJ)
- $(VCOM) $(VCOMOPT) $<
-
-$(PKG_IMAGE_OBJ) : pkg_image.vhd
- $(VCOM) $(VCOMOPT) $<
-
-$(SINGLE_PORT_OBJ) : single_port.vhd \
- $(SINGLE_PORT_PKG_OBJ) \
- $(LINKED_LIST_MEM_OBJ)
- $(VCOM) $(VCOMOPT) $<
-
-$(TC_SINGLE_PORT_OBJ) : tc_single_port.vhd \
- $(SINGLE_PORT_PKG_OBJ) \
- $(PKG_IMAGE_OBJ) \
- $(SINGLE_PORT_OBJ)
- $(VCOM) $(VCOMOPT) $<
-
-$(TB_SINGLE_PORT_OBJ) : tb_single_port.vhd \
- $(SINGLE_PORT_PKG_OBJ) \
- $(LINKED_LIST_MEM_OBJ) \
- $(SINGLE_PORT_OBJ) \
- $(TC_SINGLE_PORT_OBJ)
- $(VCOM) $(VCOMOPT) $<
-
-$(WORK) ::
- rm -rf $(WORK)/*
-
-
-####################################################################
-# $Log: not supported by cvs2svn $
-# Revision 1.1 2002/12/31 19:21:59 Default
-# Initial revision
-#
-#
-
Index: trunk/VHDL/linked_list_mem_pkg.vhd
===================================================================
--- trunk/VHDL/linked_list_mem_pkg.vhd (revision 14)
+++ trunk/VHDL/linked_list_mem_pkg.vhd (nonexistent)
@@ -1,174 +0,0 @@
-----------------------------------------------------------------------
----- ----
----- Single port asynchronous RAM simulation model ----
----- ----
----- This file is part of the single_port project ----
----- ----
----- Description ----
----- This package implements functions to allocate, write, read ----
----- and deallocate a linked list based memory. ----
----- ----
----- Authors: ----
----- - Robert Paley, rpaley_yid@yahoo.com ----
----- - Michael Geng, vhdl@MichaelGeng.de ----
----- ----
----- References: ----
----- 1. The Designer's Guide to VHDL by Peter Ashenden ----
----- ISBN: 1-55860-270-4 (pbk.) ----
----- 2. Writing Testbenches - Functional Verification of HDL ----
----- models by Janick Bergeron | ISBN: 0-7923-7766-4 ----
----- ----
-----------------------------------------------------------------------
----- ----
----- Copyright (C) 2005 Authors and OPENCORES.ORG ----
----- ----
----- This source file may be used and distributed without ----
----- restriction provided that this copyright statement is not ----
----- removed from the file and that any derivative work contains ----
----- the original copyright notice and the associated disclaimer. ----
----- ----
----- This source file is free software; you can redistribute it ----
----- and/or modify it under the terms of the GNU Lesser General ----
----- Public License as published by the Free Software Foundation; ----
----- either version 2.1 of the License, or (at your option) any ----
----- later version. ----
----- ----
----- This source is distributed in the hope that it will be ----
----- useful, but WITHOUT ANY WARRANTY; without even the implied ----
----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
----- PURPOSE. See the GNU Lesser General Public License for more ----
----- details. ----
----- ----
----- You should have received a copy of the GNU Lesser General ----
----- Public License along with this source; if not, download it ----
----- from http://www.opencores.org/lgpl.shtml ----
----- ----
-----------------------------------------------------------------------
---
--- CVS Revision History
---
--- $Log: not supported by cvs2svn $
--- Revision 1.2 2005/10/12 19:39:27 mgeng
--- Buses unconstrained, LGPL header added
---
--- Revision 1.1.1.1 2003/01/14 21:48:10 rpaley_yid
--- initial checkin
---
--- Revision 1.1 2003/01/14 17:47:32 Default
--- Initial revision
---
--- Revision 1.1 2002/12/24 18:03:50 Default
--- Initial revision
---
-LIBRARY IEEE;
-LIBRARY WORK;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE WORK.single_port_pkg.all;
-
-PACKAGE linked_list_mem_pkg IS
- CONSTANT PAGEDEPTH : INTEGER := 256; -- memory page depth
- -- pointer to one data word in the memory
- -- The reason for using a pointer here is that it seems to be the only way to keep the model
- -- independent of the data width
- TYPE data_ptr IS ACCESS BIT_VECTOR;
- -- data memory array type definition
- TYPE mem_array_typ IS ARRAY (0 TO PAGEDEPTH-1) OF data_ptr;
- -- Define memory page linked list cell. This cell contains
- -- the mem_array, starting page address, valid data array and
- -- the pointer to the next element in the linked list.
- TYPE mem_page_typ;
- -- pointer to next item in the linked list.
- TYPE mem_page_ptr IS ACCESS mem_page_typ;
- TYPE mem_page_typ IS RECORD
- mem_array : mem_array_typ; -- data memory
- page_address : addr_typ;
- next_cell : mem_page_ptr;
- END RECORD mem_page_typ;
- PROCEDURE rw_mem (
- VARIABLE data : INOUT STD_LOGIC_VECTOR;
- VARIABLE addr : IN addr_typ;
- VARIABLE next_cell : INOUT mem_page_ptr;
- CONSTANT write_flag : IN BOOLEAN);
- PROCEDURE deallocate_mem (
- VARIABLE next_cell : INOUT mem_page_ptr);
-
-END PACKAGE linked_list_mem_pkg;
-
-PACKAGE BODY linked_list_mem_pkg IS
- -- --------------------------------------------------
- -- The purpose of this procedure is to write a memory location from
- -- the linked list, if the particular page does not exist, create it.
- -- --------------------------------------------------
- PROCEDURE rw_mem (
- VARIABLE data : INOUT STD_LOGIC_VECTOR;
- VARIABLE addr : IN addr_typ;
- VARIABLE next_cell : INOUT mem_page_ptr;
- CONSTANT write_flag : IN BOOLEAN) IS
- VARIABLE current_cell_v : mem_page_ptr; -- current page pointer
- VARIABLE page_address_v : addr_typ; -- calculated page address
- VARIABLE index_v : INTEGER; -- address within the memory page
- VARIABLE mem_array_v : mem_array_typ;
- BEGIN
- -- Copy the top of the linked list pointer to a working pointer
- current_cell_v := next_cell;
- -- Calculate the index within the page from the given address
- index_v := addr MOD PAGEDEPTH;
- -- Calculate the page address from the given address
- page_address_v := addr - index_v;
- -- Search through the memory to determine if the calculated
- -- memory page exists. Stop searching when reach the end of
- -- the linked list.
- WHILE ( current_cell_v /= NULL AND
- current_cell_v.page_address /= page_address_v) LOOP
- current_cell_v := current_cell_v.next_cell;
- END LOOP;
-
- IF write_flag THEN
- IF ( current_cell_v /= NULL AND -- Check if address exists in memory.
- current_cell_v.page_address = page_address_v ) THEN
- -- Found the memory page the particular address belongs to
- IF ( current_cell_v.mem_array(index_v) /= NULL ) THEN
- current_cell_v.mem_array(index_v).ALL := TO_BITVECTOR(data);
- ELSE
- current_cell_v.mem_array(index_v) := NEW BIT_VECTOR'(TO_BITVECTOR(data));
- END IF;
- ELSE
- -- The memory page the address belongs to was not allocated in memory.
- -- Allocate page here and assign data.
- mem_array_v(index_v) := NEW BIT_VECTOR'(TO_BITVECTOR(data));
- next_cell := NEW mem_page_typ'( mem_array => mem_array_v,
- page_address => page_address_v,
- next_cell => next_cell);
- END IF;
- ELSE -- Read memory
- IF ( current_cell_v /= NULL AND -- Check if address exists in memory.
- current_cell_v.page_address = page_address_v AND
- current_cell_v.mem_array(index_v) /= NULL ) THEN
- -- Found the memory page the particular address belongs to,
- -- and the memory location has valid data.
- data := TO_STDLOGICVECTOR(current_cell_v.mem_array(index_v).ALL);
- ELSE
- -- Trying to read from unwritten or unallocated
- -- memory location, return 'U';
- data := (data'RANGE => 'U');
- END IF;
- END IF;
- END PROCEDURE rw_mem;
-
- PROCEDURE deallocate_mem (
- VARIABLE next_cell : INOUT mem_page_ptr) IS
- VARIABLE delete_cell_v : mem_page_ptr;
- BEGIN
- -- Deallocate the linked link memory from work station memory.
- WHILE next_cell /= NULL LOOP -- while not reached the end of the LL
- delete_cell_v := next_cell; -- Copy pointer to record for deleting
- FOR i IN 0 TO PAGEDEPTH-1 LOOP
- IF delete_cell_v.mem_array(i) /= NULL THEN
- deallocate(delete_cell_v.mem_array(i));
- END IF;
- END LOOP;
- next_cell := next_cell.next_cell; -- set pointer to next cell in LL
- deallocate(delete_cell_v); -- Deallocate current cell from memory.
- END LOOP;
- END PROCEDURE deallocate_mem;
-END PACKAGE BODY linked_list_mem_pkg;
Index: trunk/VHDL/pkg_image.vhd
===================================================================
--- trunk/VHDL/pkg_image.vhd (revision 14)
+++ trunk/VHDL/pkg_image.vhd (nonexistent)
@@ -1,307 +0,0 @@
--- $Author: rpaley_yid $
--- $Date: 2003-01-14 21:48:10 $
--- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/pkg_image.vhd,v 1.1.1.1 2003-01-14 21:48:10 rpaley_yid Exp $
--- $Locker
--- $Revision: 1.1.1.1 $
--- $State: Exp $
-
--- Copyright (c) 1997 Ben Cohen. All rights reserved.
--- This model can be used in conjunction with the Kluwer Academic books
--- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0
--- "VHDL Amswers to Frequently Asked Questions", Kluwer Academic
--- by Ben Cohen. email: vhdlcohen@aol.com
---
--- This source file for the Image Package
--- may be used and distributed without restriction provided
--- that this copyright statement is not removed from the file
--- and that any derivative work contains this copyright notice.
---
---
--- Original Author: Ben Cohen
--- Description:
--- Convert VHDL types to string for printing. This is especially useful when
--- compiling with VHDL-87
-
----------------------------------------------------------------
-LIBRARY IEEE;
- USE IEEE.STD_LOGIC_1164.ALL;
- USE IEEE.STD_LOGIC_TEXTIO.ALL;
- USE IEEE.NUMERIC_STD.ALL;
-
-LIBRARY STD;
- USE STD.TEXTIO.ALL;
-
-package pkg_image is
- function Image(In_Image : Time) return String;
- function Image(In_Image : Bit) return String;
- function Image(In_Image : Bit_Vector) return String;
- function Image(In_Image : Integer) return String;
- function Image(In_Image : Real) return String;
- function Image(In_Image : Std_uLogic) return String;
- function Image(In_Image : Std_uLogic_Vector) return String;
- function Image(In_Image : Std_Logic_Vector) return String;
- function Image(In_Image : Signed) return String;
- function Image(In_Image : UnSigned) return String;
-
- function HexImage(InStrg : String) return String;
- function HexImage(In_Image : Bit_Vector) return String;
- function HexImage(In_Image : Std_uLogic_Vector) return String;
- function HexImage(In_Image : Std_Logic_Vector) return String;
- function HexImage(In_Image : Signed) return String;
- function HexImage(In_Image : UnSigned) return String;
-
- function DecImage(In_Image : Bit_Vector) return String;
- function DecImage(In_Image : Std_uLogic_Vector) return String;
- function DecImage(In_Image : Std_Logic_Vector) return String;
- function DecImage(In_Image : Signed) return String;
- function DecImage(In_Image : UnSigned) return String;
-end pkg_image;
-
-package body pkg_image is
- function Image(In_Image : Time) return String is
- variable L : Line; -- access type
- variable W : String(1 to 14) := (others => ' ');
- -- Long enough to hold a time string
- begin
- -- the WRITE procedure creates an object with "NEW".
- -- L is passed as an output of the procedure.
- Std.TextIO.WRITE(L, in_image);
- -- Copy L.all onto W
- W(L.all'range) := L.all;
- Deallocate(L);
- return W;
- end Image;
-
- function Image(In_Image : Bit) return String is
- variable L : Line; -- access type
- variable W : String(1 to 3) := (others => ' ');
- begin
- Std.TextIO.WRITE(L, in_image);
- W(L.all'range) := L.all;
- Deallocate(L);
- return W;
- end Image;
-
- function Image(In_Image : Bit_Vector) return String is
- variable L : Line; -- access type
- variable W : String(1 to In_Image'length) := (others => ' ');
- begin
- Std.TextIO.WRITE(L, in_image);
- W(L.all'range) := L.all;
- Deallocate(L);
- return W;
- end Image;
-
- function Image(In_Image : Integer) return String is
- variable L : Line; -- access type
- variable W : String(1 to 32) := (others => ' ');
- -- Long enough to hold a time string
- begin
- Std.TextIO.WRITE(L, in_image);
- W(L.all'range) := L.all;
- Deallocate(L);
- return W;
- end Image;
-
- function Image(In_Image : Real) return String is
- variable L : Line; -- access type
- variable W : String(1 to 32) := (others => ' ');
- -- Long enough to hold a time string
- begin
- Std.TextIO.WRITE(L, in_image);
- W(L.all'range) := L.all;
- Deallocate(L);
- return W;
- end Image;
-
- function Image(In_Image : Std_uLogic) return String is
- variable L : Line; -- access type
- variable W : String(1 to 3) := (others => ' ');
- begin
- IEEE.Std_Logic_Textio.WRITE(L, in_image);
- W(L.all'range) := L.all;
- Deallocate(L);
- return W;
- end Image;
-
- function Image(In_Image : Std_uLogic_Vector) return String is
- variable L : Line; -- access type
- variable W : String(1 to In_Image'length) := (others => ' ');
- begin
- IEEE.Std_Logic_Textio.WRITE(L, in_image);
- W(L.all'range) := L.all;
- Deallocate(L);
- return W;
- end Image;
-
- function Image(In_Image : Std_Logic_Vector) return String is
- variable L : Line; -- access type
- variable W : String(1 to In_Image'length) := (others => ' ');
- begin
- IEEE.Std_Logic_TextIO.WRITE(L, In_Image);
- W(L.all'range) := L.all;
- Deallocate(L);
- return W;
- end Image;
-
- function Image(In_Image : Signed) return String is
- begin
- return Image(Std_Logic_Vector(In_Image));
- end Image;
-
- function Image(In_Image : UnSigned) return String is
- begin
- return Image(Std_Logic_Vector(In_Image));
- end Image;
-
- function HexImage(InStrg : String) return String is
- subtype Int03_Typ is Integer range 0 to 3;
- variable Result : string(1 to ((InStrg'length - 1)/4)+1) :=
- (others => '0');
- variable StrTo4 : string(1 to Result'length * 4) :=
- (others => '0');
- variable MTspace : Int03_Typ; -- Empty space to fill in
- variable Str4 : String(1 to 4);
- variable Group_v : Natural := 0;
- begin
- MTspace := Result'length * 4 - InStrg'length;
- StrTo4(MTspace + 1 to StrTo4'length) := InStrg; -- padded with '0'
- Cnvrt_Lbl : for I in Result'range loop
- Group_v := Group_v + 4; -- identifies end of bit # in a group of 4
- Str4 := StrTo4(Group_v - 3 to Group_v); -- get next 4 characters
- case Str4 is
- when "0000" => Result(I) := '0';
- when "0001" => Result(I) := '1';
- when "0010" => Result(I) := '2';
- when "0011" => Result(I) := '3';
- when "0100" => Result(I) := '4';
- when "0101" => Result(I) := '5';
- when "0110" => Result(I) := '6';
- when "0111" => Result(I) := '7';
- when "1000" => Result(I) := '8';
- when "1001" => Result(I) := '9';
- when "1010" => Result(I) := 'A';
- when "1011" => Result(I) := 'B';
- when "1100" => Result(I) := 'C';
- when "1101" => Result(I) := 'D';
- when "1110" => Result(I) := 'E';
- when "1111" => Result(I) := 'F';
- when others => Result(I) := 'X';
- end case; -- Str4
- end loop Cnvrt_Lbl;
-
- return Result;
- end HexImage;
-
-
- function HexImage(In_Image : Bit_Vector) return String is
- begin
- return HexImage(Image(In_Image));
- end HexImage;
-
- function HexImage(In_Image : Std_uLogic_Vector) return String is
- begin
- return HexImage(Image(In_Image));
- end HexImage;
-
- function HexImage(In_Image : Std_Logic_Vector) return String is
- begin
- return HexImage(Image(In_Image));
- end HexImage;
-
- function HexImage(In_Image : Signed) return String is
- begin
- return HexImage(Image(In_Image));
- end HexImage;
-
- function HexImage(In_Image : UnSigned) return String is
- begin
- return HexImage(Image(In_Image));
- end HexImage;
-
- function DecImage(In_Image : Bit_Vector) return String is
- variable In_Image_v : Bit_Vector(In_Image'length downto 1) := In_Image;
- begin
- if In_Image'length > 31 then
- assert False
- report "Number too large for Integer, clipping to 31 bits"
- severity Warning;
- return Image(To_Integer
- (Unsigned(To_StdLogicVector
- (In_Image_v(31 downto 1)))));
- else
- return Image(To_Integer(Unsigned(To_StdLogicVector(In_Image))));
- end if;
- end DecImage;
-
- function DecImage(In_Image : Std_uLogic_Vector) return String is
- variable In_Image_v : Std_uLogic_Vector(In_Image'length downto 1)
- := In_Image;
- begin
- if In_Image'length > 31 then
- assert False
- report "Number too large for Integer, clipping to 31 bits"
- severity Warning;
- return Image(To_Integer(Unsigned(In_Image_v(31 downto 1))));
- else
- return Image(To_Integer(Unsigned(In_Image)));
- end if;
- end DecImage;
-
- function DecImage(In_Image : Std_Logic_Vector) return String is
- variable In_Image_v : Std_Logic_Vector(In_Image'length downto 1)
- := In_Image;
- begin
- if In_Image'length > 31 then
- assert False
- report "Number too large for Integer, clipping to 31 bits"
- severity Warning;
- return Image(To_Integer(Unsigned(In_Image_v(31 downto 1))));
- else
- return Image(To_Integer(Unsigned(In_Image)));
- end if;
- end DecImage;
-
- function DecImage(In_Image : Signed) return String is
- variable In_Image_v : Signed(In_Image'length downto 1) := In_Image;
- begin
- if In_Image'length > 31 then
- assert False
- report "Number too large for Integer, clipping to 31 bits"
- severity Warning;
- return Image(To_Integer(In_Image_v(31 downto 1)));
- else
- return Image(To_Integer(In_Image));
- end if;
- end DecImage;
-
- function DecImage(In_Image : UnSigned) return String is
- variable In_Image_v : UnSigned(In_Image'length downto 1) := In_Image;
- begin
- if In_Image'length > 31 then
- assert False
- report "Number too large for Integer, clipping to 31 bits"
- severity Warning;
- return Image(To_Integer(In_Image_v(31 downto 1)));
- else
- return Image(To_Integer(In_Image));
- end if;
- end DecImage;
-
-end pkg_image;
-
--- $Log: not supported by cvs2svn $
--- Revision 1.1 2003/01/14 17:48:44 Default
--- Initial revision
---
--- Revision 1.1 2002/12/24 18:07:50 Default
--- Initial revision
---
-
-
-
-
-
-
-
-
Index: single_port/trunk/VHDL/single_port.vhd
===================================================================
--- single_port/trunk/VHDL/single_port.vhd (nonexistent)
+++ single_port/trunk/VHDL/single_port.vhd (revision 15)
@@ -0,0 +1,178 @@
+----------------------------------------------------------------------
+---- ----
+---- Single port asynchronous RAM simulation model ----
+---- ----
+---- This file is part of the single_port project ----
+---- ----
+---- Description ----
+---- This is a single port asynchronous memory. This files ----
+---- describes three architectures. Two architectures are ----
+---- traditional array based memories. One describes the memory ----
+---- as an array of STD_LOGIC_VECTOR, and the other describes ----
+---- the ARRAY as BIT_VECTOR. ----
+---- The third architecture describes the memory arranged as a ----
+---- linked list in order to conserve computer memory usage. The ----
+---- memory is organized as a linked list of BIT_VECTOR arrays ----
+---- whose size is defined by the constant PAGEDEPTH in ----
+---- single_port_pkg.vhd. ----
+---- ----
+---- Authors: ----
+---- - Robert Paley, rpaley_yid@yahoo.com ----
+---- - Michael Geng, vhdl@MichaelGeng.de ----
+---- ----
+---- References: ----
+---- 1. The Designer's Guide to VHDL by Peter Ashenden ----
+---- ISBN: 1-55860-270-4 (pbk.) ----
+---- 2. Writing Testbenches - Functional Verification of HDL ----
+---- models by Janick Bergeron | ISBN: 0-7923-7766-4 ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors and OPENCORES.ORG ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+--
+-- CVS Revision History
+--
+-- $Log: not supported by cvs2svn $
+-- Revision 1.4 2005/11/19 15:18:54 mgeng
+-- rnw replaced by nce, nwe and noe, tristate drivers added
+--
+-- Revision 1.3 2005/10/25 18:26:52 mgeng
+-- PAGENUM constant removed because the address bus width provides this information
+--
+-- Revision 1.2 2005/10/12 19:39:27 mgeng
+-- Buses unconstrained, LGPL header added
+--
+-- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid
+-- initial checkin
+--
+-- Revision 1.1 2003/01/14 17:48:31 Default
+-- Initial revision
+--
+-- Revision 1.1 2002/12/24 18:09:05 Default
+-- Initial revision
+--
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE WORK.single_port_pkg.ALL;
+USE WORK.linked_list_mem_pkg.ALL;
+
+ENTITY single_port IS
+ GENERIC (
+ rnwtQ : TIME := 1 NS);
+ PORT (
+ d : IN STD_LOGIC_VECTOR; -- data bus input
+ q : OUT STD_LOGIC_VECTOR; -- data bus output
+ a : IN STD_LOGIC_VECTOR; -- address bus
+ nce : IN STD_LOGIC; -- not chip enable
+ nwe : IN STD_LOGIC; -- not write enable
+ noe : IN STD_LOGIC; -- not output enable
+ dealloc_mem : IN BOOLEAN := FALSE); -- control signal for deallocating memory,
+ -- only used in the linked list implementation
+END ENTITY single_port;
+
+ARCHITECTURE ArrayMemNoFlag OF single_port IS
+BEGIN
+
+ mem_proc : PROCESS(d, a, nce, nwe, noe)
+ TYPE mem_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF STD_LOGIC_VECTOR(d'RANGE);
+ VARIABLE mem : mem_typ;
+ BEGIN
+ IF ( nce = '0' ) AND ( nwe = '0' ) THEN -- Write
+ mem(TO_INTEGER(unsigned(a))) := d;
+ END IF;
+
+ IF ( nce = '0' ) AND ( noe = '0' ) THEN -- Read
+ q <= mem(TO_INTEGER(unsigned(a))) AFTER rnwtQ;
+ ELSE
+ q <= (q'RANGE => 'Z') AFTER rnwtQ;
+ END IF;
+ END PROCESS mem_proc;
+
+END ArrayMemNoFlag;
+
+ARCHITECTURE ArrayMem OF single_port IS
+BEGIN
+
+ mem_proc : PROCESS(d, a, nce, nwe, noe)
+ TYPE mem_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF BIT_VECTOR(d'RANGE);
+ TYPE flag_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF BOOLEAN;
+ VARIABLE mem : mem_typ;
+ VARIABLE flag : flag_typ;
+ BEGIN
+ IF ( nce = '0' ) AND ( nwe = '0' ) THEN -- Write
+ mem( TO_INTEGER(unsigned(a))) := TO_BITVECTOR(d);
+ flag(TO_INTEGER(unsigned(a))) := true; -- set valid memory location flag
+ END IF;
+
+ IF ( nce = '0' ) AND ( noe = '0' ) THEN -- Read
+ IF ( flag(TO_INTEGER(unsigned(a))) = true ) THEN -- read data, either valid or 'U'
+ q <= TO_STDLOGICVECTOR(mem(TO_INTEGER(unsigned(a)))) AFTER rnwtQ;
+ ELSE -- reading invalid memory location
+ q <= (q'RANGE => 'U') AFTER rnwtQ;
+ END IF;
+ ELSE
+ q <= (q'RANGE => 'Z') AFTER rnwtQ;
+ END IF;
+ END PROCESS mem_proc;
+END ArrayMem;
+
+ARCHITECTURE LinkedList OF single_port IS
+ CONSTANT WRITE_MEM : BOOLEAN := true;
+ CONSTANT READ_MEM : BOOLEAN := false;
+BEGIN
+
+ mem_proc : PROCESS(d, a, nce, nwe, noe, dealloc_mem)
+ VARIABLE mem_page_v : mem_page_ptr;
+ VARIABLE d_v : STD_LOGIC_VECTOR(d'RANGE);
+ VARIABLE a_v : addr_typ;
+ BEGIN
+ IF NOT dealloc_mem THEN
+ d_v := d;
+ if (nce = '0') then
+ a_v := TO_INTEGER(unsigned(a));
+ end if;
+ IF ( nce = '0' ) AND ( nwe = '0' ) THEN -- Write
+ rw_mem( data => d_v,
+ addr => a_v,
+ next_cell => mem_page_v,
+ write_flag => WRITE_MEM);
+ END IF;
+
+ IF ( nce = '0' ) AND ( noe = '0' ) THEN -- Read
+ rw_mem( data => d_v,
+ addr => a_v,
+ next_cell => mem_page_v,
+ write_flag => READ_MEM);
+ q <= d_v AFTER rnwtQ;
+ ELSE
+ q <= (q'RANGE => 'Z') AFTER rnwtQ;
+ END IF;
+ ELSE -- Deallocate memory from work station memory.
+ deallocate_mem(mem_page_v);
+ END IF;
+ END PROCESS mem_proc;
+END LinkedList;
Index: single_port/trunk/VHDL/tb_single_port.vhd
===================================================================
--- single_port/trunk/VHDL/tb_single_port.vhd (nonexistent)
+++ single_port/trunk/VHDL/tb_single_port.vhd (revision 15)
@@ -0,0 +1,225 @@
+----------------------------------------------------------------------
+---- ----
+---- Single port asynchronous RAM simulation model ----
+---- ----
+---- This file is part of the single_port project ----
+---- ----
+---- Description ----
+---- This file specifies test bench harness for the single_port ----
+---- Memory. It also contains the configuration files for all the ----
+---- tests. ----
+---- ----
+---- Authors: ----
+---- - Robert Paley, rpaley_yid@yahoo.com ----
+---- - Michael Geng, vhdl@MichaelGeng.de ----
+---- ----
+---- References: ----
+---- 1. The Designer's Guide to VHDL by Peter Ashenden ----
+---- ISBN: 1-55860-270-4 (pbk.) ----
+---- 2. Writing Testbenches - Functional Verification of HDL ----
+---- models by Janick Bergeron | ISBN: 0-7923-7766-4 ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors and OPENCORES.ORG ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+--
+-- CVS Revision History
+--
+-- $Log: not supported by cvs2svn $
+-- Revision 1.2 2005/10/12 19:39:27 mgeng
+-- Buses unconstrained, LGPL header added
+--
+-- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid
+-- initial checkin
+--
+-- Revision 1.1 2003/01/14 17:49:04 Default
+-- Initial revision
+--
+-- Revision 1.2 2002/12/31 19:19:43 Default
+-- Updated 'transaction statements for fixed simulator.
+--
+-- Revision 1.1 2002/12/24 18:10:18 Default
+-- Initial revision
+--
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE WORK.linked_list_mem_pkg.ALL;
+USE WORK.single_port_pkg.all;
+USE STD.TEXTIO.ALL;
+
+ENTITY tb_single_port IS
+END ENTITY tb_single_port;
+
+ARCHITECTURE BHV of tb_single_port IS
+
+COMPONENT single_port IS
+ GENERIC (
+ rnwtQ : TIME := 1 NS);
+ PORT (
+ d : IN STD_LOGIC_VECTOR;
+ q : OUT STD_LOGIC_VECTOR;
+ a : IN STD_LOGIC_VECTOR;
+ nce : IN STD_LOGIC;
+ nwe : IN STD_LOGIC;
+ noe : IN STD_LOGIC;
+ dealloc_mem : BOOLEAN);
+END COMPONENT single_port;
+
+COMPONENT tc_single_port IS
+ PORT (
+ to_srv : OUT to_srv_typ;
+ frm_srv : IN STD_LOGIC_VECTOR);
+END COMPONENT tc_single_port;
+ CONSTANT DATA_WIDTH : INTEGER := 32;
+ CONSTANT ADDR_WIDTH : INTEGER := 16;
+
+ SIGNAL d : STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0);
+ SIGNAL q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0);
+ SIGNAL a : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+ SIGNAL nce, nwe, noe : STD_LOGIC;
+ SIGNAL dealloc_mem : BOOLEAN;
+ SIGNAL to_srv : to_srv_typ;
+ SIGNAL frm_srv : STD_LOGIC_VECTOR(d'RANGE);
+ SIGNAL tie_vdd : STD_LOGIC := '1';
+BEGIN
+ dut : single_port
+ PORT MAP (
+ d => d,
+ a => a,
+ q => q,
+ nce => nce,
+ nwe => nwe,
+ noe => noe,
+ dealloc_mem => dealloc_mem);
+
+ tc : tc_single_port
+ PORT MAP (
+ to_srv => to_srv,
+ frm_srv => frm_srv);
+
+ single_port_server : PROCESS
+ VARIABLE frm_srv_v : STD_LOGIC_VECTOR(d'RANGE);
+ CONSTANT ACCESS_DELAY : TIME := 5 NS;
+ BEGIN
+ -- Wait until the test case is finished setting up the next memory access.
+ WAIT ON to_srv'TRANSACTION;
+ CASE to_srv.do IS
+ WHEN init =>
+ ASSERT FALSE
+ REPORT "initialized"
+ SEVERITY NOTE;
+ WHEN read => -- perform memory read
+ d <= STD_LOGIC_VECTOR(TO_SIGNED(to_srv.data, d'length));
+ a <= STD_LOGIC_VECTOR(TO_UNSIGNED(to_srv.addr, a'length));
+ nce <= '0';
+ noe <= '0';
+ nwe <= '1';
+ -- Wait for data to appear
+ WAIT FOR ACCESS_DELAY;
+ WHEN write => -- perform memory write
+ d <= STD_LOGIC_VECTOR(TO_SIGNED(to_srv.data, d'length));
+ a <= STD_LOGIC_VECTOR(TO_UNSIGNED(to_srv.addr, a'length));
+ nce <= '0';
+ noe <= '1';
+ nwe <= '0';
+ WAIT FOR ACCESS_DELAY;
+ WHEN dealloc => -- deallocate the linked list for the LL architecture
+ dealloc_mem <= true;
+ WHEN end_test => -- reached the end of the test case
+ WAIT;
+ END CASE;
+ frm_srv_v := q;
+ -- Send message to test case to continue the test.
+ frm_srv <= frm_srv_v ; WAIT FOR 0 NS;
+ END PROCESS single_port_server;
+END BHV;
+
+CONFIGURATION ll_main_cfg OF TB_SINGLE_PORT IS
+ FOR BHV
+ FOR dut : single_port
+ USE ENTITY work.single_port(LinkedList);
+ END FOR; -- dut
+ FOR tc : tc_single_port
+ USE ENTITY work.tc_single_port(TC0);
+ END FOR; -- tc;
+ END FOR; -- BHV
+END CONFIGURATION ll_main_cfg;
+
+CONFIGURATION ll_error_cfg OF TB_SINGLE_PORT IS
+ FOR BHV
+ FOR dut : single_port
+ USE ENTITY work.single_port(LinkedList);
+ END FOR; -- dut
+ FOR tc : tc_single_port
+ USE ENTITY work.tc_single_port(TC1);
+ END FOR; -- tc;
+ END FOR; -- BHV
+END CONFIGURATION ll_error_cfg ;
+
+CONFIGURATION mem_main_cfg of TB_SINGLE_PORT IS
+ FOR BHV
+ FOR dut : single_port
+ USE ENTITY work.single_port(ArrayMem);
+ END FOR; -- dut
+ FOR tc : tc_single_port
+ USE ENTITY work.tc_single_port(TC0);
+ END FOR; -- tc;
+ END FOR; -- BHV
+END CONFIGURATION mem_main_cfg;
+
+CONFIGURATION mem_error_cfg of TB_SINGLE_PORT IS
+ FOR BHV
+ FOR dut : single_port
+ USE ENTITY work.single_port(ArrayMem);
+ END FOR; -- dut
+ FOR tc : tc_single_port
+ USE ENTITY work.tc_single_port(TC1);
+ END FOR; -- tc;
+ END FOR; -- BHV
+END CONFIGURATION mem_error_cfg;
+
+CONFIGURATION memnoflag_main_cfg of TB_SINGLE_PORT IS
+ FOR BHV
+ FOR dut : single_port
+ USE ENTITY work.single_port(ArrayMemNoFlag);
+ END FOR; -- dut
+ FOR tc : tc_single_port
+ USE ENTITY work.tc_single_port(TC0);
+ END FOR; -- tc;
+ END FOR; -- BHV
+END CONFIGURATION memnoflag_main_cfg;
+
+CONFIGURATION memnoflag_error_cfg of TB_SINGLE_PORT IS
+ FOR BHV
+ FOR dut : single_port
+ USE ENTITY work.single_port(ArrayMemNoFlag);
+ END FOR; -- dut
+ FOR tc : tc_single_port
+ USE ENTITY work.tc_single_port(TC1);
+ END FOR; -- tc;
+ END FOR; -- BHV
+END CONFIGURATION memnoflag_error_cfg;
Index: single_port/trunk/VHDL/linked_list_mem_pkg.vhd
===================================================================
--- single_port/trunk/VHDL/linked_list_mem_pkg.vhd (nonexistent)
+++ single_port/trunk/VHDL/linked_list_mem_pkg.vhd (revision 15)
@@ -0,0 +1,174 @@
+----------------------------------------------------------------------
+---- ----
+---- Single port asynchronous RAM simulation model ----
+---- ----
+---- This file is part of the single_port project ----
+---- ----
+---- Description ----
+---- This package implements functions to allocate, write, read ----
+---- and deallocate a linked list based memory. ----
+---- ----
+---- Authors: ----
+---- - Robert Paley, rpaley_yid@yahoo.com ----
+---- - Michael Geng, vhdl@MichaelGeng.de ----
+---- ----
+---- References: ----
+---- 1. The Designer's Guide to VHDL by Peter Ashenden ----
+---- ISBN: 1-55860-270-4 (pbk.) ----
+---- 2. Writing Testbenches - Functional Verification of HDL ----
+---- models by Janick Bergeron | ISBN: 0-7923-7766-4 ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors and OPENCORES.ORG ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+--
+-- CVS Revision History
+--
+-- $Log: not supported by cvs2svn $
+-- Revision 1.2 2005/10/12 19:39:27 mgeng
+-- Buses unconstrained, LGPL header added
+--
+-- Revision 1.1.1.1 2003/01/14 21:48:10 rpaley_yid
+-- initial checkin
+--
+-- Revision 1.1 2003/01/14 17:47:32 Default
+-- Initial revision
+--
+-- Revision 1.1 2002/12/24 18:03:50 Default
+-- Initial revision
+--
+LIBRARY IEEE;
+LIBRARY WORK;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE WORK.single_port_pkg.all;
+
+PACKAGE linked_list_mem_pkg IS
+ CONSTANT PAGEDEPTH : INTEGER := 256; -- memory page depth
+ -- pointer to one data word in the memory
+ -- The reason for using a pointer here is that it seems to be the only way to keep the model
+ -- independent of the data width
+ TYPE data_ptr IS ACCESS BIT_VECTOR;
+ -- data memory array type definition
+ TYPE mem_array_typ IS ARRAY (0 TO PAGEDEPTH-1) OF data_ptr;
+ -- Define memory page linked list cell. This cell contains
+ -- the mem_array, starting page address, valid data array and
+ -- the pointer to the next element in the linked list.
+ TYPE mem_page_typ;
+ -- pointer to next item in the linked list.
+ TYPE mem_page_ptr IS ACCESS mem_page_typ;
+ TYPE mem_page_typ IS RECORD
+ mem_array : mem_array_typ; -- data memory
+ page_address : addr_typ;
+ next_cell : mem_page_ptr;
+ END RECORD mem_page_typ;
+ PROCEDURE rw_mem (
+ VARIABLE data : INOUT STD_LOGIC_VECTOR;
+ VARIABLE addr : IN addr_typ;
+ VARIABLE next_cell : INOUT mem_page_ptr;
+ CONSTANT write_flag : IN BOOLEAN);
+ PROCEDURE deallocate_mem (
+ VARIABLE next_cell : INOUT mem_page_ptr);
+
+END PACKAGE linked_list_mem_pkg;
+
+PACKAGE BODY linked_list_mem_pkg IS
+ -- --------------------------------------------------
+ -- The purpose of this procedure is to write a memory location from
+ -- the linked list, if the particular page does not exist, create it.
+ -- --------------------------------------------------
+ PROCEDURE rw_mem (
+ VARIABLE data : INOUT STD_LOGIC_VECTOR;
+ VARIABLE addr : IN addr_typ;
+ VARIABLE next_cell : INOUT mem_page_ptr;
+ CONSTANT write_flag : IN BOOLEAN) IS
+ VARIABLE current_cell_v : mem_page_ptr; -- current page pointer
+ VARIABLE page_address_v : addr_typ; -- calculated page address
+ VARIABLE index_v : INTEGER; -- address within the memory page
+ VARIABLE mem_array_v : mem_array_typ;
+ BEGIN
+ -- Copy the top of the linked list pointer to a working pointer
+ current_cell_v := next_cell;
+ -- Calculate the index within the page from the given address
+ index_v := addr MOD PAGEDEPTH;
+ -- Calculate the page address from the given address
+ page_address_v := addr - index_v;
+ -- Search through the memory to determine if the calculated
+ -- memory page exists. Stop searching when reach the end of
+ -- the linked list.
+ WHILE ( current_cell_v /= NULL AND
+ current_cell_v.page_address /= page_address_v) LOOP
+ current_cell_v := current_cell_v.next_cell;
+ END LOOP;
+
+ IF write_flag THEN
+ IF ( current_cell_v /= NULL AND -- Check if address exists in memory.
+ current_cell_v.page_address = page_address_v ) THEN
+ -- Found the memory page the particular address belongs to
+ IF ( current_cell_v.mem_array(index_v) /= NULL ) THEN
+ current_cell_v.mem_array(index_v).ALL := TO_BITVECTOR(data);
+ ELSE
+ current_cell_v.mem_array(index_v) := NEW BIT_VECTOR'(TO_BITVECTOR(data));
+ END IF;
+ ELSE
+ -- The memory page the address belongs to was not allocated in memory.
+ -- Allocate page here and assign data.
+ mem_array_v(index_v) := NEW BIT_VECTOR'(TO_BITVECTOR(data));
+ next_cell := NEW mem_page_typ'( mem_array => mem_array_v,
+ page_address => page_address_v,
+ next_cell => next_cell);
+ END IF;
+ ELSE -- Read memory
+ IF ( current_cell_v /= NULL AND -- Check if address exists in memory.
+ current_cell_v.page_address = page_address_v AND
+ current_cell_v.mem_array(index_v) /= NULL ) THEN
+ -- Found the memory page the particular address belongs to,
+ -- and the memory location has valid data.
+ data := TO_STDLOGICVECTOR(current_cell_v.mem_array(index_v).ALL);
+ ELSE
+ -- Trying to read from unwritten or unallocated
+ -- memory location, return 'U';
+ data := (data'RANGE => 'U');
+ END IF;
+ END IF;
+ END PROCEDURE rw_mem;
+
+ PROCEDURE deallocate_mem (
+ VARIABLE next_cell : INOUT mem_page_ptr) IS
+ VARIABLE delete_cell_v : mem_page_ptr;
+ BEGIN
+ -- Deallocate the linked link memory from work station memory.
+ WHILE next_cell /= NULL LOOP -- while not reached the end of the LL
+ delete_cell_v := next_cell; -- Copy pointer to record for deleting
+ FOR i IN 0 TO PAGEDEPTH-1 LOOP
+ IF delete_cell_v.mem_array(i) /= NULL THEN
+ deallocate(delete_cell_v.mem_array(i));
+ END IF;
+ END LOOP;
+ next_cell := next_cell.next_cell; -- set pointer to next cell in LL
+ deallocate(delete_cell_v); -- Deallocate current cell from memory.
+ END LOOP;
+ END PROCEDURE deallocate_mem;
+END PACKAGE BODY linked_list_mem_pkg;
Index: single_port/trunk/VHDL/single_port_pkg.vhd
===================================================================
--- single_port/trunk/VHDL/single_port_pkg.vhd (nonexistent)
+++ single_port/trunk/VHDL/single_port_pkg.vhd (revision 15)
@@ -0,0 +1,84 @@
+----------------------------------------------------------------------
+---- ----
+---- Single port asynchronous RAM simulation model ----
+---- ----
+---- This file is part of the single_port project ----
+---- ----
+---- Description ----
+---- Package file for single_port memory and testbench ----
+---- ----
+---- Authors: ----
+---- - Robert Paley, rpaley_yid@yahoo.com ----
+---- - Michael Geng, vhdl@MichaelGeng.de ----
+---- ----
+---- References: ----
+---- 1. The Designer's Guide to VHDL by Peter Ashenden ----
+---- ISBN: 1-55860-270-4 (pbk.) ----
+---- 2. Writing Testbenches - Functional Verification of HDL ----
+---- models by Janick Bergeron | ISBN: 0-7923-7766-4 ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors and OPENCORES.ORG ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+--
+-- CVS Revision History
+--
+-- $Log: not supported by cvs2svn $
+-- Revision 1.3 2005/10/25 18:26:52 mgeng
+-- PAGENUM constant removed because the address bus width provides this information
+--
+-- Revision 1.2 2005/10/12 19:39:27 mgeng
+-- Buses unconstrained, LGPL header added
+--
+-- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid
+-- initial checkin
+--
+-- Revision 1.1 2003/01/14 17:48:44 Default
+-- Initial revision
+--
+-- Revision 1.1 2002/12/24 17:58:49 Default
+-- Initial revision
+--
+LIBRARY IEEE;
+ USE IEEE.STD_LOGIC_1164.ALL;
+ USE IEEE.NUMERIC_STD.ALL;
+
+PACKAGE single_port_pkg IS
+ -- Address bus type for internal memory
+ SUBTYPE addr_typ IS NATURAL;
+ -- Operations testbench can do.
+ TYPE do_typ IS ( init , read , write , dealloc , end_test );
+
+ TYPE to_srv_typ IS RECORD -- Record passed from test case to test bench
+ do : do_typ;
+ addr : INTEGER;
+ data : INTEGER;
+ event : BOOLEAN;
+ END RECORD to_srv_typ;
+END PACKAGE single_port_pkg;
+
+PACKAGE BODY single_port_pkg IS
+END PACKAGE BODY single_port_pkg;
Index: single_port/trunk/VHDL/tc_single_port.vhd
===================================================================
--- single_port/trunk/VHDL/tc_single_port.vhd (nonexistent)
+++ single_port/trunk/VHDL/tc_single_port.vhd (revision 15)
@@ -0,0 +1,214 @@
+----------------------------------------------------------------------
+---- ----
+---- Single port asynchronous RAM simulation model ----
+---- ----
+---- This file is part of the single_port project ----
+---- ----
+---- Description ----
+---- This file specifies test cases for the single_port Memory. ----
+---- ----
+---- Authors: ----
+---- - Robert Paley, rpaley_yid@yahoo.com ----
+---- - Michael Geng, vhdl@MichaelGeng.de ----
+---- ----
+---- References: ----
+---- 1. The Designer's Guide to VHDL by Peter Ashenden ----
+---- ISBN: 1-55860-270-4 (pbk.) ----
+---- 2. Writing Testbenches - Functional Verification of HDL ----
+---- models by Janick Bergeron | ISBN: 0-7923-7766-4 ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors and OPENCORES.ORG ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+--
+-- CVS Revision History
+--
+-- $Log: not supported by cvs2svn $
+-- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid
+-- initial checkin
+--
+-- Revision 1.1 2003/01/14 17:49:04 Default
+-- Initial revision
+--
+-- Revision 1.2 2002/12/31 19:19:43 Default
+-- Updated 'transaction statements for fixed simulator.
+--
+-- Revision 1.1 2002/12/24 18:13:50 Default
+-- Initial revision
+--
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE WORK.SINGLE_PORT_PKG.ALL;
+USE WORK.PKG_IMAGE.ALL;
+
+ENTITY tc_single_port IS
+PORT (
+ to_srv : OUT to_srv_typ;
+ frm_srv : IN STD_LOGIC_VECTOR);
+END ENTITY tc_single_port;
+
+-- --------------------------------------------------
+-- Test Case TC0
+-- This test case is to check two pages of memory
+-- Starting at physical address 0x0 ,
+-- Write a '1' to bit position 0, leaving all other bits 0.
+-- Increment the address,
+-- Write a '1' to bit position 1, leaving all other bits 0.
+-- Increment the address.
+-- Write a '1' to bit position 2, leaving all other bits 0.
+-- Continue in this fasion, until write a 1 to the MSB.
+-- increment the address,
+-- Write a '1' to bit position 0, leaving all other bits 0.
+-- Continue until the entire page is written to.
+-- Read back all addresses in the page, ensuring the
+-- correct data is read back.
+-- --------------------------------------------------
+
+
+ARCHITECTURE TC0 OF tc_single_port IS
+BEGIN
+ MAIN : PROCESS
+ VARIABLE to_srv_v : to_srv_typ;
+ VARIABLE frm_srv_v : STD_LOGIC_VECTOR(frm_srv'RANGE);
+ VARIABLE dv : STD_LOGIC_VECTOR(frm_srv'RANGE) :=
+ STD_LOGIC_VECTOR(TO_UNSIGNED(1, frm_srv'length));
+ VARIABLE offset_v : INTEGER;
+ BEGIN
+ offset_v := 0;
+ -- Run this write/read test 10 times for benchmark
+ -- purposes.
+ FOR i IN 0 to 9 LOOP
+ FOR index IN 0 to 2*PAGEDEPTH-1 LOOP
+ -- Specify to testbench server to perform write operation;
+ to_srv_v.do := write;
+ to_srv_v.data := TO_INTEGER(SIGNED(dv)); -- specify data to write
+ dv := To_StdLogicVector(TO_BitVector(dv) ROL 1); -- ROL 1 for next write
+ -- Specify physical address.
+ to_srv_v.addr := index+offset_v;
+ to_srv <= to_srv_v;
+ WAIT ON frm_srv'TRANSACTION;
+ END LOOP;
+ -- Reset data to 1.
+ dv := STD_LOGIC_VECTOR(TO_UNSIGNED(1,frm_srv'length));
+ FOR index IN 0 to 2*PAGEDEPTH-1 LOOP
+ -- Perform read operation.
+ to_srv_v.do := read;
+ -- Specify physical address.
+ to_srv_v.addr := index+offset_v;
+ to_srv <= to_srv_v;
+ WAIT ON frm_srv'TRANSACTION;
+ -- Compare actual with expected read back data, if the
+ -- the expected and actual to not compare, print the
+ -- expected and actual values.
+ ASSERT frm_srv = dv
+ REPORT "Expected: " & HexImage(frm_srv) &
+ " did not equal Actual: " & HexImage(dv)
+ SEVERITY ERROR;
+ -- Set expected data for next read.
+ dv := TO_STDLOGICVECTOR(TO_BITVECTOR(dv) ROL 1);
+ END LOOP;
+ END LOOP;
+ to_srv_v.do := dealloc; -- Deallocate memory
+ --
+ to_srv <= to_srv_v;
+ -- Tell test bench server process test completed.
+ to_srv_v.do := end_test;
+ to_srv <= to_srv_v;
+ ASSERT FALSE
+ REPORT "Completed Test TC0"
+ SEVERITY NOTE;
+ WAIT;
+ END PROCESS main;
+END TC0;
+
+-- --------------------------------------------------
+-- Test Case TC1
+-- This test case is to check if the test bench will
+-- return 'U' for invalid memory locations for
+-- single_port architectures ArrayMem and LinkedList
+-- --------------------------------------------------
+ARCHITECTURE TC1 OF tc_single_port IS
+BEGIN
+ MAIN : PROCESS
+ VARIABLE to_srv_v : to_srv_typ;
+ VARIABLE frm_srv_v : STD_LOGIC_VECTOR(frm_srv'RANGE);
+ VARIABLE dv : STD_LOGIC_VECTOR(frm_srv'RANGE) := (OTHERS => 'U');
+ BEGIN
+ -- Perform read operation.
+ to_srv_v.do := read;
+ -- Specify physical address.
+ to_srv_v.addr := 0;
+ to_srv <= to_srv_v;
+ WAIT ON frm_srv'TRANSACTION;
+ -- Compare actual with expected read back data, if the
+ -- the expected and actual to not compare, print the
+ -- expected and actual values.
+ ASSERT frm_srv = dv
+ REPORT "Expected: " & HexImage(frm_srv) &
+ " did not equal Actual: " & HexImage(dv)
+ SEVERITY ERROR;
+
+ -- Write and read back from same address.
+
+ -- Specify to testbench server to perform write operation;
+ to_srv_v.do := write;
+ dv := X"a5a5a5a5";
+ to_srv_v.data := TO_INTEGER(SIGNED(dv)); -- specify data to write
+ -- Specify physical address.
+ to_srv_v.addr := 0;
+ to_srv <= to_srv_v;
+ -- Wait until the test bench server finished with the write.
+ -- WAIT UNTIL frm_srv.event = true;
+ WAIT ON frm_srv'TRANSACTION;
+
+ to_srv_v.do := read;
+ -- Specify physical address.
+ to_srv_v.addr := 0;
+ to_srv <= to_srv_v;
+ WAIT ON frm_srv'TRANSACTION;
+
+ -- Compare actual with expected read back data, if the
+ -- the expected and actual to not compare, print the
+ -- expected and actual values.
+ ASSERT frm_srv = dv
+ REPORT "Expected: " & HexImage(frm_srv) &
+ " did not equal Actual: " & HexImage(dv)
+ SEVERITY ERROR;
+
+ to_srv_v.do := dealloc; -- Deallocate memory
+ --
+ to_srv <= to_srv_v;
+ -- Tell test bench server process test completed.
+ to_srv_v.do := end_test;
+ to_srv <= to_srv_v;
+
+ ASSERT FALSE
+ REPORT "Completed Test TC1"
+ SEVERITY NOTE;
+ WAIT;
+ END PROCESS main;
+END TC1;
Index: single_port/trunk/VHDL/pkg_image.vhd
===================================================================
--- single_port/trunk/VHDL/pkg_image.vhd (nonexistent)
+++ single_port/trunk/VHDL/pkg_image.vhd (revision 15)
@@ -0,0 +1,307 @@
+-- $Author: rpaley_yid $
+-- $Date: 2003-01-14 21:48:10 $
+-- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/pkg_image.vhd,v 1.1.1.1 2003-01-14 21:48:10 rpaley_yid Exp $
+-- $Locker
+-- $Revision: 1.1.1.1 $
+-- $State: Exp $
+
+-- Copyright (c) 1997 Ben Cohen. All rights reserved.
+-- This model can be used in conjunction with the Kluwer Academic books
+-- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0
+-- "VHDL Amswers to Frequently Asked Questions", Kluwer Academic
+-- by Ben Cohen. email: vhdlcohen@aol.com
+--
+-- This source file for the Image Package
+-- may be used and distributed without restriction provided
+-- that this copyright statement is not removed from the file
+-- and that any derivative work contains this copyright notice.
+--
+--
+-- Original Author: Ben Cohen
+-- Description:
+-- Convert VHDL types to string for printing. This is especially useful when
+-- compiling with VHDL-87
+
+---------------------------------------------------------------
+LIBRARY IEEE;
+ USE IEEE.STD_LOGIC_1164.ALL;
+ USE IEEE.STD_LOGIC_TEXTIO.ALL;
+ USE IEEE.NUMERIC_STD.ALL;
+
+LIBRARY STD;
+ USE STD.TEXTIO.ALL;
+
+package pkg_image is
+ function Image(In_Image : Time) return String;
+ function Image(In_Image : Bit) return String;
+ function Image(In_Image : Bit_Vector) return String;
+ function Image(In_Image : Integer) return String;
+ function Image(In_Image : Real) return String;
+ function Image(In_Image : Std_uLogic) return String;
+ function Image(In_Image : Std_uLogic_Vector) return String;
+ function Image(In_Image : Std_Logic_Vector) return String;
+ function Image(In_Image : Signed) return String;
+ function Image(In_Image : UnSigned) return String;
+
+ function HexImage(InStrg : String) return String;
+ function HexImage(In_Image : Bit_Vector) return String;
+ function HexImage(In_Image : Std_uLogic_Vector) return String;
+ function HexImage(In_Image : Std_Logic_Vector) return String;
+ function HexImage(In_Image : Signed) return String;
+ function HexImage(In_Image : UnSigned) return String;
+
+ function DecImage(In_Image : Bit_Vector) return String;
+ function DecImage(In_Image : Std_uLogic_Vector) return String;
+ function DecImage(In_Image : Std_Logic_Vector) return String;
+ function DecImage(In_Image : Signed) return String;
+ function DecImage(In_Image : UnSigned) return String;
+end pkg_image;
+
+package body pkg_image is
+ function Image(In_Image : Time) return String is
+ variable L : Line; -- access type
+ variable W : String(1 to 14) := (others => ' ');
+ -- Long enough to hold a time string
+ begin
+ -- the WRITE procedure creates an object with "NEW".
+ -- L is passed as an output of the procedure.
+ Std.TextIO.WRITE(L, in_image);
+ -- Copy L.all onto W
+ W(L.all'range) := L.all;
+ Deallocate(L);
+ return W;
+ end Image;
+
+ function Image(In_Image : Bit) return String is
+ variable L : Line; -- access type
+ variable W : String(1 to 3) := (others => ' ');
+ begin
+ Std.TextIO.WRITE(L, in_image);
+ W(L.all'range) := L.all;
+ Deallocate(L);
+ return W;
+ end Image;
+
+ function Image(In_Image : Bit_Vector) return String is
+ variable L : Line; -- access type
+ variable W : String(1 to In_Image'length) := (others => ' ');
+ begin
+ Std.TextIO.WRITE(L, in_image);
+ W(L.all'range) := L.all;
+ Deallocate(L);
+ return W;
+ end Image;
+
+ function Image(In_Image : Integer) return String is
+ variable L : Line; -- access type
+ variable W : String(1 to 32) := (others => ' ');
+ -- Long enough to hold a time string
+ begin
+ Std.TextIO.WRITE(L, in_image);
+ W(L.all'range) := L.all;
+ Deallocate(L);
+ return W;
+ end Image;
+
+ function Image(In_Image : Real) return String is
+ variable L : Line; -- access type
+ variable W : String(1 to 32) := (others => ' ');
+ -- Long enough to hold a time string
+ begin
+ Std.TextIO.WRITE(L, in_image);
+ W(L.all'range) := L.all;
+ Deallocate(L);
+ return W;
+ end Image;
+
+ function Image(In_Image : Std_uLogic) return String is
+ variable L : Line; -- access type
+ variable W : String(1 to 3) := (others => ' ');
+ begin
+ IEEE.Std_Logic_Textio.WRITE(L, in_image);
+ W(L.all'range) := L.all;
+ Deallocate(L);
+ return W;
+ end Image;
+
+ function Image(In_Image : Std_uLogic_Vector) return String is
+ variable L : Line; -- access type
+ variable W : String(1 to In_Image'length) := (others => ' ');
+ begin
+ IEEE.Std_Logic_Textio.WRITE(L, in_image);
+ W(L.all'range) := L.all;
+ Deallocate(L);
+ return W;
+ end Image;
+
+ function Image(In_Image : Std_Logic_Vector) return String is
+ variable L : Line; -- access type
+ variable W : String(1 to In_Image'length) := (others => ' ');
+ begin
+ IEEE.Std_Logic_TextIO.WRITE(L, In_Image);
+ W(L.all'range) := L.all;
+ Deallocate(L);
+ return W;
+ end Image;
+
+ function Image(In_Image : Signed) return String is
+ begin
+ return Image(Std_Logic_Vector(In_Image));
+ end Image;
+
+ function Image(In_Image : UnSigned) return String is
+ begin
+ return Image(Std_Logic_Vector(In_Image));
+ end Image;
+
+ function HexImage(InStrg : String) return String is
+ subtype Int03_Typ is Integer range 0 to 3;
+ variable Result : string(1 to ((InStrg'length - 1)/4)+1) :=
+ (others => '0');
+ variable StrTo4 : string(1 to Result'length * 4) :=
+ (others => '0');
+ variable MTspace : Int03_Typ; -- Empty space to fill in
+ variable Str4 : String(1 to 4);
+ variable Group_v : Natural := 0;
+ begin
+ MTspace := Result'length * 4 - InStrg'length;
+ StrTo4(MTspace + 1 to StrTo4'length) := InStrg; -- padded with '0'
+ Cnvrt_Lbl : for I in Result'range loop
+ Group_v := Group_v + 4; -- identifies end of bit # in a group of 4
+ Str4 := StrTo4(Group_v - 3 to Group_v); -- get next 4 characters
+ case Str4 is
+ when "0000" => Result(I) := '0';
+ when "0001" => Result(I) := '1';
+ when "0010" => Result(I) := '2';
+ when "0011" => Result(I) := '3';
+ when "0100" => Result(I) := '4';
+ when "0101" => Result(I) := '5';
+ when "0110" => Result(I) := '6';
+ when "0111" => Result(I) := '7';
+ when "1000" => Result(I) := '8';
+ when "1001" => Result(I) := '9';
+ when "1010" => Result(I) := 'A';
+ when "1011" => Result(I) := 'B';
+ when "1100" => Result(I) := 'C';
+ when "1101" => Result(I) := 'D';
+ when "1110" => Result(I) := 'E';
+ when "1111" => Result(I) := 'F';
+ when others => Result(I) := 'X';
+ end case; -- Str4
+ end loop Cnvrt_Lbl;
+
+ return Result;
+ end HexImage;
+
+
+ function HexImage(In_Image : Bit_Vector) return String is
+ begin
+ return HexImage(Image(In_Image));
+ end HexImage;
+
+ function HexImage(In_Image : Std_uLogic_Vector) return String is
+ begin
+ return HexImage(Image(In_Image));
+ end HexImage;
+
+ function HexImage(In_Image : Std_Logic_Vector) return String is
+ begin
+ return HexImage(Image(In_Image));
+ end HexImage;
+
+ function HexImage(In_Image : Signed) return String is
+ begin
+ return HexImage(Image(In_Image));
+ end HexImage;
+
+ function HexImage(In_Image : UnSigned) return String is
+ begin
+ return HexImage(Image(In_Image));
+ end HexImage;
+
+ function DecImage(In_Image : Bit_Vector) return String is
+ variable In_Image_v : Bit_Vector(In_Image'length downto 1) := In_Image;
+ begin
+ if In_Image'length > 31 then
+ assert False
+ report "Number too large for Integer, clipping to 31 bits"
+ severity Warning;
+ return Image(To_Integer
+ (Unsigned(To_StdLogicVector
+ (In_Image_v(31 downto 1)))));
+ else
+ return Image(To_Integer(Unsigned(To_StdLogicVector(In_Image))));
+ end if;
+ end DecImage;
+
+ function DecImage(In_Image : Std_uLogic_Vector) return String is
+ variable In_Image_v : Std_uLogic_Vector(In_Image'length downto 1)
+ := In_Image;
+ begin
+ if In_Image'length > 31 then
+ assert False
+ report "Number too large for Integer, clipping to 31 bits"
+ severity Warning;
+ return Image(To_Integer(Unsigned(In_Image_v(31 downto 1))));
+ else
+ return Image(To_Integer(Unsigned(In_Image)));
+ end if;
+ end DecImage;
+
+ function DecImage(In_Image : Std_Logic_Vector) return String is
+ variable In_Image_v : Std_Logic_Vector(In_Image'length downto 1)
+ := In_Image;
+ begin
+ if In_Image'length > 31 then
+ assert False
+ report "Number too large for Integer, clipping to 31 bits"
+ severity Warning;
+ return Image(To_Integer(Unsigned(In_Image_v(31 downto 1))));
+ else
+ return Image(To_Integer(Unsigned(In_Image)));
+ end if;
+ end DecImage;
+
+ function DecImage(In_Image : Signed) return String is
+ variable In_Image_v : Signed(In_Image'length downto 1) := In_Image;
+ begin
+ if In_Image'length > 31 then
+ assert False
+ report "Number too large for Integer, clipping to 31 bits"
+ severity Warning;
+ return Image(To_Integer(In_Image_v(31 downto 1)));
+ else
+ return Image(To_Integer(In_Image));
+ end if;
+ end DecImage;
+
+ function DecImage(In_Image : UnSigned) return String is
+ variable In_Image_v : UnSigned(In_Image'length downto 1) := In_Image;
+ begin
+ if In_Image'length > 31 then
+ assert False
+ report "Number too large for Integer, clipping to 31 bits"
+ severity Warning;
+ return Image(To_Integer(In_Image_v(31 downto 1)));
+ else
+ return Image(To_Integer(In_Image));
+ end if;
+ end DecImage;
+
+end pkg_image;
+
+-- $Log: not supported by cvs2svn $
+-- Revision 1.1 2003/01/14 17:48:44 Default
+-- Initial revision
+--
+-- Revision 1.1 2002/12/24 18:07:50 Default
+-- Initial revision
+--
+
+
+
+
+
+
+
+
Index: single_port/trunk/VHDL/Makefile
===================================================================
--- single_port/trunk/VHDL/Makefile (nonexistent)
+++ single_port/trunk/VHDL/Makefile (revision 15)
@@ -0,0 +1,161 @@
+#
+# Description: Top level make file for single_port test project.
+# make com to compile
+# make sim to simulate all tests
+# make ll_error to run this test only
+# make ll_main to run this test only
+# make mem_main to run this test only
+# make mem_error to run this test only
+# make memnoflag_main to run this test
+# make memnoflag_error to run this test
+# $Author: rpaley_yid $
+# $Date: 2003-01-14 21:48:11 $
+# $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/Makefile,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $
+# $Locker: $
+# $Revision: 1.1.1.1 $
+# $State: Exp $
+
+# VCOM , VSIM , and WORK variables are set for Sonata simulator,
+# Change appropriately for your simulator. Ex.for Modeltech,
+# VCOM = vcom
+# VSIM = vsim
+# WORK = work
+
+SHELL = /bin/sh
+VCOM = vhdlp
+VCOMOPT = -s
+VSIM = vhdle
+VSIMOPT =
+WORK = work.sym
+## Need to figure out how to put Bourne shell stuff in Makefile
+## will do so to generate log files in
+## LOGDIR = ../LOG/
+## For now, log files are in VHDL directory.
+
+
+# List of main compiled objects, does not include configurations,
+# which are included in the tb_single_port.vhd file.
+# These targets are for the Sonata simulator, adjust accordingly for
+# your simulator.
+
+SINGLE_PORT_PKG_OBJ = $(WORK)/single_port_pkg/prim.var
+LINKED_LIST_MEM_OBJ = $(WORK)/linked_list_mem_pkg/prim.var
+PKG_IMAGE_OBJ = $(WORK)/pkg_image/prim.var
+SINGLE_PORT_OBJ = $(WORK)/single_port/prim.var
+TC_SINGLE_PORT_OBJ = $(WORK)/tc_single_port/prim.var
+TB_SINGLE_PORT_OBJ = $(WORK)/tb_single_port/prim.var
+LL_ERROR_DEP = $(WORK)/ll_error_cfg/prim.var
+LL_MAIN_DEP = $(WORK)/ll_main_cfg/prim.var
+MEM_MAIN_DEP = $(WORK)/mem_main_cfg/prim.var
+MEM_ERROR_DEP = $(WORK)/mem_error_cfg/prim.var
+MEMNOFLAG_MAIN_DEP = $(WORK)/memnoflag_main_cfg/prim.var
+MEMNOFLAG_ERROR_DEP = $(WORK)/memnoflag_error_cfg/prim.var
+
+LL_ERROR = $(LOGDIR)ll_error.log
+LL_MAIN = ll_main.log
+MEM_MAIN = mem_main.log
+MEM_ERROR = mem_error.log
+MEMNOFLAG_MAIN = memnoflag_main.log
+MEMNOFLAG_ERROR = memnoflag_error.log
+
+OBJS = $(SINGLE_PORT_PKG_OBJ) \
+ $(LINKED_LIST_MEM_OBJ) \
+ $(PKG_IMAGE_OBJ) \
+ $(SINGLE_PORT_OBJ) \
+ $(TC_SINGLE_PORT_OBJ) \
+ $(TB_SINGLE_PORT_OBJ)
+
+SIMOBJS = $(LL_ERROR) \
+ $(LL_MAIN) \
+ $(MEM_MAIN) \
+ $(MEM_ERROR) \
+ $(MEMNOFLAG_MAIN) \
+ $(MEMNOFLAG_ERROR)
+
+# Compile the project
+com: $(OBJS)
+
+# Clean the library
+clean:: $(WORK)
+
+# Simulate all tests
+sim: $(SIMOBJS)
+
+## Run only ll_error test
+ll_error: $(LL_ERROR)
+
+# Run onle ll_main test
+ll_main: $(LL_MAIN)
+
+# Run only mem_main test
+mem_main: $(MEM_MAIN)
+
+# Run only mem_error test
+mem_error: $(MEM_ERROR)
+
+# Run only memnoflag_main test
+memnoflag_main: $(MEMNOFLAG_MAIN)
+
+# Run only memnoflag_error test
+memnoflag_error: $(MEMNOFLAG_ERROR)
+
+# Target dependency rules to run tests
+$(LL_ERROR) : $(LL_ERROR_DEP)
+ $(VSIM) $(VSIMOPT) ll_error_cfg | tee $@
+
+$(LL_MAIN) : $(LL_MAIN_DEP)
+ $(VSIM) $(VSIMOPT) ll_main_cfg | tee $@
+
+$(MEM_MAIN) : $(MEM_MAIN_DEP)
+ $(VSIM) $(VSIMOPT) mem_main_cfg | tee $@
+
+$(MEM_ERROR) : $(MEM_ERROR_DEP)
+ $(VSIM) $(VSIMOPT) mem_error_cfg | tee $@
+
+$(MEMNOFLAG_MAIN) : $(MEMNOFLAG_MAIN_DEP)
+ $(VSIM) $(VSIMOPT) memnoflag_main_cfg | tee $@
+
+$(MEMNOFLAG_ERROR) : $(MEMNOFLAG_ERROR_DEP)
+ $(VSIM) $(VSIMOPT) memnoflag_error_cfg | tee $@
+
+# Target dependency rules to compile tests
+
+$(SINGLE_PORT_PKG_OBJ) : single_port_pkg.vhd
+ $(VCOM) $(VCOMOPT) $<
+
+$(LINKED_LIST_MEM_OBJ) : linked_list_mem_pkg.vhd \
+ $(SINGLE_PORT_PKG_OBJ)
+ $(VCOM) $(VCOMOPT) $<
+
+$(PKG_IMAGE_OBJ) : pkg_image.vhd
+ $(VCOM) $(VCOMOPT) $<
+
+$(SINGLE_PORT_OBJ) : single_port.vhd \
+ $(SINGLE_PORT_PKG_OBJ) \
+ $(LINKED_LIST_MEM_OBJ)
+ $(VCOM) $(VCOMOPT) $<
+
+$(TC_SINGLE_PORT_OBJ) : tc_single_port.vhd \
+ $(SINGLE_PORT_PKG_OBJ) \
+ $(PKG_IMAGE_OBJ) \
+ $(SINGLE_PORT_OBJ)
+ $(VCOM) $(VCOMOPT) $<
+
+$(TB_SINGLE_PORT_OBJ) : tb_single_port.vhd \
+ $(SINGLE_PORT_PKG_OBJ) \
+ $(LINKED_LIST_MEM_OBJ) \
+ $(SINGLE_PORT_OBJ) \
+ $(TC_SINGLE_PORT_OBJ)
+ $(VCOM) $(VCOMOPT) $<
+
+$(WORK) ::
+ rm -rf $(WORK)/*
+
+
+####################################################################
+# $Log: not supported by cvs2svn $
+# Revision 1.1 2002/12/31 19:21:59 Default
+# Initial revision
+#
+#
+
Index: single_port/trunk/doc/single_port.html
===================================================================
--- single_port/trunk/doc/single_port.html (nonexistent)
+++ single_port/trunk/doc/single_port.html (revision 15)
@@ -0,0 +1,366 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+Description
+ of single_port memory and test environment.
+
+Abstract:
+
+A VHDL simulation model for an asynchronous static single
+ port memory is described. The memory is implemented as three different
+ architectures, a simple one and 2 ones which are optimized for efficient
+ use of simulator memory. Data and address buses are unconstrained, so
+multiple instances with different address and data bus widths can be implemented
+in one single design. A testbench is also provided.
+
+
+Port Interface:
+
+
+
+
+
+
+ Port Name
+ |
+
+
+ Type
+ |
+
+
+ Description
+ |
+
+
+
+
+
+ rnwtQ
+ |
+
+
+ Time
+ |
+
+
+ Time delay until data or tristate appears on q data bus.
+ |
+
+
+
+
+ d
+ |
+ STD_LOGIC_VECTOR
+ |
+
+
+ Input data bus, unconstrained
+ |
+
+
+
+
+ q
+ |
+
+
+ STD_LOGIC_VECTOR
+
+ |
+
+
+ Output data bus, unconstrained
+ |
+
+
+
+
+ a
+ |
+
+
+ STD_LOGIC_VECTOR
+
+ |
+
+
+ Address bus, unconstrained
+ |
+
+
+
+
+ nce
+ |
+
+
+ STD_LOGIC
+ |
+
+
+ not chip enable
+ |
+
+
+ nwe
+ |
+ STD_LOGIC
+ |
+ not write enable
+ |
+
+
+ noe
+ |
+ STD_LOGIC
+ |
+ not output enable
+ |
+
+
+
+
+ dealloc_mem
+ |
+
+
+ BOOLEAN
+ |
+
+
+ When set to true, deallocate linked list memory.
+ |
+
+
+
+
+
+Functional Description:
+
+All 3 architectures functionally behave like commercially
+ available asynchronous SRAMs if you connect d and q to the same bus. If a memory location is read which was not written to during the
+ current simulation, 'U's are loaded onto the memory bus.
+
+
+
+
+ nce
+ |
+ nwe
+ |
+ noe
+ |
+ d
+ |
+ q
+ |
+ Mode
+ |
+
+
+ 1
+ |
+ don't care
+ |
+ don't care
+ |
+ don't care
+ |
+ high Z
+ |
+ deselected
+ |
+
+
+ 0
+ |
+ 1
+ |
+ 1
+ |
+ don't care
+ |
+ high Z
+ |
+ output disabled
+ |
+
+
+ 0
+ |
+ 0
+ |
+ don't care
+ |
+ input data
+ |
+ high Z
+ |
+ write
+ |
+
+
+ 0
+ |
+ 1
+ |
+ 0
+ |
+ don't care
+ |
+ RAM content
+ |
+ read
+ |
+
+
+
+
+
+Architecture ArrayMemNoFlag
+
+This architecture implements the memory core as an array
+ of STD_LOGIC_VECTOR. This is the simplest architecture. It is provided
+ for comparison with the models below but not recommended for use in your
+ design.
+
+
+
+Architecture ArrayMem
+
+This architecture implements the
+ memory core as an array of BIT_VECTOR. This arrangement allows less workstation
+ memory to be used than the ArrayMemNoFlag architecture. Use this architecture
+ if most addresses in the simulated memory are written at least once.
+
+
+Architecture LinkedList
+
+
+ This architecture implements the memory core as a linked
+ list of arrays of BIT_VECTOR. Each array in the linked list is a page
+of memory whose size is specified with the constant PAGEDEPTH in the package
+ linked_list_mem_pkg. This arrangement allows less workstation memory
+to be used than either the ArrayMemNoFlag or ArrayMem architectures because
+ memory representing the array data is only allocated if the memory is
+actually written to. To de-allocate the memory in the linked list, set
+dealloc_mem to true. A short pulse is sufficient. Use this architecture
+ if a significant portion of your simulated memory (which need not be
+contiguous) is never written to.
+Example Timing:
+
+Clearing both nce and nwe to to '0' immediately causes
+a write operation. Changing the address while nce and nwe are asserted causes
+ a write to the new address, too (But don't do that with real RAMs because
+ you could destroy more memory locations while the address bus settles).
+Every read (and tristate) operation is delayed rnwtQ ns. The below sample
+ timing diagram illustrates both a read and write operation.
+
+
+
+
+
+Testbench Description:
+
+The test bench is arranged as a client server architecture as specified
+ by Bergeron. A diagram illustrating the testbench
+ is given below.
+
+
+
+ Two tests are specified in tc_single_port component. The first test
+ writes data to two logical memory pages, and then reads them back verifying
+ the correct data. The test case writes an error message to the console
+for every miscompare. The second case verifies that the single_port memory
+model outputs unknowns to the q bus if a read occurs for an unwritten memory
+location. Six configurations are specified in the test bench architecture
+tb_single_port, running both tests for each single_port architecture.
+
+
+Usage:
+
+A Makefile is used to compile and run all of the tests in a Unix or like
+ environment, such as Cygwin. The compilation and simulation is targetted
+ to the SymphonyEDA tool available at www.symphonyeda.com.
+
+The source files and Makefile are located in {top}/VHDL
+
+ To compile: make com
+
+To simulate all of the tests: make sim
+
+
+To clean the compiled library: make clean
+
+The tests are labeled :
+
+
+ - ll_error
+ - ll_main
+ - mem_main
+
+ - mem_error
+
+ - memnoflag_main
+
+ - memnoflag_error
+
+
+
+
+To simulate any of these tests, type make {testname}
+
+Please contact Robert Paley at rpaley_yid@opencores.org
+ or Michael Geng at vhdl@michaelgeng.de
+ if you have any questions or comments.
+
+
+
+
+
+
+
Index: single_port/trunk/doc/copying.txt
===================================================================
--- single_port/trunk/doc/copying.txt (nonexistent)
+++ single_port/trunk/doc/copying.txt (revision 15)
@@ -0,0 +1,504 @@
+ GNU LESSER GENERAL PUBLIC LICENSE
+ Version 2.1, February 1999
+
+ Copyright (C) 1991, 1999 Free Software Foundation, Inc.
+ 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+[This is the first released version of the Lesser GPL. It also counts
+ as the successor of the GNU Library Public License, version 2, hence
+ the version number 2.1.]
+
+ Preamble
+
+ The licenses for most software are designed to take away your
+freedom to share and change it. By contrast, the GNU General Public
+Licenses are intended to guarantee your freedom to share and change
+free software--to make sure the software is free for all its users.
+
+ This license, the Lesser General Public License, applies to some
+specially designated software packages--typically libraries--of the
+Free Software Foundation and other authors who decide to use it. You
+can use it too, but we suggest you first think carefully about whether
+this license or the ordinary General Public License is the better
+strategy to use in any particular case, based on the explanations below.
+
+ When we speak of free software, we are referring to freedom of use,
+not price. Our General Public Licenses are designed to make sure that
+you have the freedom to distribute copies of free software (and charge
+for this service if you wish); that you receive source code or can get
+it if you want it; that you can change the software and use pieces of
+it in new free programs; and that you are informed that you can do
+these things.
+
+ To protect your rights, we need to make restrictions that forbid
+distributors to deny you these rights or to ask you to surrender these
+rights. These restrictions translate to certain responsibilities for
+you if you distribute copies of the library or if you modify it.
+
+ For example, if you distribute copies of the library, whether gratis
+or for a fee, you must give the recipients all the rights that we gave
+you. You must make sure that they, too, receive or can get the source
+code. If you link other code with the library, you must provide
+complete object files to the recipients, so that they can relink them
+with the library after making changes to the library and recompiling
+it. And you must show them these terms so they know their rights.
+
+ We protect your rights with a two-step method: (1) we copyright the
+library, and (2) we offer you this license, which gives you legal
+permission to copy, distribute and/or modify the library.
+
+ To protect each distributor, we want to make it very clear that
+there is no warranty for the free library. Also, if the library is
+modified by someone else and passed on, the recipients should know
+that what they have is not the original version, so that the original
+author's reputation will not be affected by problems that might be
+introduced by others.
+
+ Finally, software patents pose a constant threat to the existence of
+any free program. We wish to make sure that a company cannot
+effectively restrict the users of a free program by obtaining a
+restrictive license from a patent holder. Therefore, we insist that
+any patent license obtained for a version of the library must be
+consistent with the full freedom of use specified in this license.
+
+ Most GNU software, including some libraries, is covered by the
+ordinary GNU General Public License. This license, the GNU Lesser
+General Public License, applies to certain designated libraries, and
+is quite different from the ordinary General Public License. We use
+this license for certain libraries in order to permit linking those
+libraries into non-free programs.
+
+ When a program is linked with a library, whether statically or using
+a shared library, the combination of the two is legally speaking a
+combined work, a derivative of the original library. The ordinary
+General Public License therefore permits such linking only if the
+entire combination fits its criteria of freedom. The Lesser General
+Public License permits more lax criteria for linking other code with
+the library.
+
+ We call this license the "Lesser" General Public License because it
+does Less to protect the user's freedom than the ordinary General
+Public License. It also provides other free software developers Less
+of an advantage over competing non-free programs. These disadvantages
+are the reason we use the ordinary General Public License for many
+libraries. However, the Lesser license provides advantages in certain
+special circumstances.
+
+ For example, on rare occasions, there may be a special need to
+encourage the widest possible use of a certain library, so that it becomes
+a de-facto standard. To achieve this, non-free programs must be
+allowed to use the library. A more frequent case is that a free
+library does the same job as widely used non-free libraries. In this
+case, there is little to gain by limiting the free library to free
+software only, so we use the Lesser General Public License.
+
+ In other cases, permission to use a particular library in non-free
+programs enables a greater number of people to use a large body of
+free software. For example, permission to use the GNU C Library in
+non-free programs enables many more people to use the whole GNU
+operating system, as well as its variant, the GNU/Linux operating
+system.
+
+ Although the Lesser General Public License is Less protective of the
+users' freedom, it does ensure that the user of a program that is
+linked with the Library has the freedom and the wherewithal to run
+that program using a modified version of the Library.
+
+ The precise terms and conditions for copying, distribution and
+modification follow. Pay close attention to the difference between a
+"work based on the library" and a "work that uses the library". The
+former contains code derived from the library, whereas the latter must
+be combined with the library in order to run.
+
+ GNU LESSER GENERAL PUBLIC LICENSE
+ TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+ 0. This License Agreement applies to any software library or other
+program which contains a notice placed by the copyright holder or
+other authorized party saying it may be distributed under the terms of
+this Lesser General Public License (also called "this License").
+Each licensee is addressed as "you".
+
+ A "library" means a collection of software functions and/or data
+prepared so as to be conveniently linked with application programs
+(which use some of those functions and data) to form executables.
+
+ The "Library", below, refers to any such software library or work
+which has been distributed under these terms. A "work based on the
+Library" means either the Library or any derivative work under
+copyright law: that is to say, a work containing the Library or a
+portion of it, either verbatim or with modifications and/or translated
+straightforwardly into another language. (Hereinafter, translation is
+included without limitation in the term "modification".)
+
+ "Source code" for a work means the preferred form of the work for
+making modifications to it. For a library, complete source code means
+all the source code for all modules it contains, plus any associated
+interface definition files, plus the scripts used to control compilation
+and installation of the library.
+
+ Activities other than copying, distribution and modification are not
+covered by this License; they are outside its scope. The act of
+running a program using the Library is not restricted, and output from
+such a program is covered only if its contents constitute a work based
+on the Library (independent of the use of the Library in a tool for
+writing it). Whether that is true depends on what the Library does
+and what the program that uses the Library does.
+
+ 1. You may copy and distribute verbatim copies of the Library's
+complete source code as you receive it, in any medium, provided that
+you conspicuously and appropriately publish on each copy an
+appropriate copyright notice and disclaimer of warranty; keep intact
+all the notices that refer to this License and to the absence of any
+warranty; and distribute a copy of this License along with the
+Library.
+
+ You may charge a fee for the physical act of transferring a copy,
+and you may at your option offer warranty protection in exchange for a
+fee.
+
+ 2. You may modify your copy or copies of the Library or any portion
+of it, thus forming a work based on the Library, and copy and
+distribute such modifications or work under the terms of Section 1
+above, provided that you also meet all of these conditions:
+
+ a) The modified work must itself be a software library.
+
+ b) You must cause the files modified to carry prominent notices
+ stating that you changed the files and the date of any change.
+
+ c) You must cause the whole of the work to be licensed at no
+ charge to all third parties under the terms of this License.
+
+ d) If a facility in the modified Library refers to a function or a
+ table of data to be supplied by an application program that uses
+ the facility, other than as an argument passed when the facility
+ is invoked, then you must make a good faith effort to ensure that,
+ in the event an application does not supply such function or
+ table, the facility still operates, and performs whatever part of
+ its purpose remains meaningful.
+
+ (For example, a function in a library to compute square roots has
+ a purpose that is entirely well-defined independent of the
+ application. Therefore, Subsection 2d requires that any
+ application-supplied function or table used by this function must
+ be optional: if the application does not supply it, the square
+ root function must still compute square roots.)
+
+These requirements apply to the modified work as a whole. If
+identifiable sections of that work are not derived from the Library,
+and can be reasonably considered independent and separate works in
+themselves, then this License, and its terms, do not apply to those
+sections when you distribute them as separate works. But when you
+distribute the same sections as part of a whole which is a work based
+on the Library, the distribution of the whole must be on the terms of
+this License, whose permissions for other licensees extend to the
+entire whole, and thus to each and every part regardless of who wrote
+it.
+
+Thus, it is not the intent of this section to claim rights or contest
+your rights to work written entirely by you; rather, the intent is to
+exercise the right to control the distribution of derivative or
+collective works based on the Library.
+
+In addition, mere aggregation of another work not based on the Library
+with the Library (or with a work based on the Library) on a volume of
+a storage or distribution medium does not bring the other work under
+the scope of this License.
+
+ 3. You may opt to apply the terms of the ordinary GNU General Public
+License instead of this License to a given copy of the Library. To do
+this, you must alter all the notices that refer to this License, so
+that they refer to the ordinary GNU General Public License, version 2,
+instead of to this License. (If a newer version than version 2 of the
+ordinary GNU General Public License has appeared, then you can specify
+that version instead if you wish.) Do not make any other change in
+these notices.
+
+ Once this change is made in a given copy, it is irreversible for
+that copy, so the ordinary GNU General Public License applies to all
+subsequent copies and derivative works made from that copy.
+
+ This option is useful when you wish to copy part of the code of
+the Library into a program that is not a library.
+
+ 4. You may copy and distribute the Library (or a portion or
+derivative of it, under Section 2) in object code or executable form
+under the terms of Sections 1 and 2 above provided that you accompany
+it with the complete corresponding machine-readable source code, which
+must be distributed under the terms of Sections 1 and 2 above on a
+medium customarily used for software interchange.
+
+ If distribution of object code is made by offering access to copy
+from a designated place, then offering equivalent access to copy the
+source code from the same place satisfies the requirement to
+distribute the source code, even though third parties are not
+compelled to copy the source along with the object code.
+
+ 5. A program that contains no derivative of any portion of the
+Library, but is designed to work with the Library by being compiled or
+linked with it, is called a "work that uses the Library". Such a
+work, in isolation, is not a derivative work of the Library, and
+therefore falls outside the scope of this License.
+
+ However, linking a "work that uses the Library" with the Library
+creates an executable that is a derivative of the Library (because it
+contains portions of the Library), rather than a "work that uses the
+library". The executable is therefore covered by this License.
+Section 6 states terms for distribution of such executables.
+
+ When a "work that uses the Library" uses material from a header file
+that is part of the Library, the object code for the work may be a
+derivative work of the Library even though the source code is not.
+Whether this is true is especially significant if the work can be
+linked without the Library, or if the work is itself a library. The
+threshold for this to be true is not precisely defined by law.
+
+ If such an object file uses only numerical parameters, data
+structure layouts and accessors, and small macros and small inline
+functions (ten lines or less in length), then the use of the object
+file is unrestricted, regardless of whether it is legally a derivative
+work. (Executables containing this object code plus portions of the
+Library will still fall under Section 6.)
+
+ Otherwise, if the work is a derivative of the Library, you may
+distribute the object code for the work under the terms of Section 6.
+Any executables containing that work also fall under Section 6,
+whether or not they are linked directly with the Library itself.
+
+ 6. As an exception to the Sections above, you may also combine or
+link a "work that uses the Library" with the Library to produce a
+work containing portions of the Library, and distribute that work
+under terms of your choice, provided that the terms permit
+modification of the work for the customer's own use and reverse
+engineering for debugging such modifications.
+
+ You must give prominent notice with each copy of the work that the
+Library is used in it and that the Library and its use are covered by
+this License. You must supply a copy of this License. If the work
+during execution displays copyright notices, you must include the
+copyright notice for the Library among them, as well as a reference
+directing the user to the copy of this License. Also, you must do one
+of these things:
+
+ a) Accompany the work with the complete corresponding
+ machine-readable source code for the Library including whatever
+ changes were used in the work (which must be distributed under
+ Sections 1 and 2 above); and, if the work is an executable linked
+ with the Library, with the complete machine-readable "work that
+ uses the Library", as object code and/or source code, so that the
+ user can modify the Library and then relink to produce a modified
+ executable containing the modified Library. (It is understood
+ that the user who changes the contents of definitions files in the
+ Library will not necessarily be able to recompile the application
+ to use the modified definitions.)
+
+ b) Use a suitable shared library mechanism for linking with the
+ Library. A suitable mechanism is one that (1) uses at run time a
+ copy of the library already present on the user's computer system,
+ rather than copying library functions into the executable, and (2)
+ will operate properly with a modified version of the library, if
+ the user installs one, as long as the modified version is
+ interface-compatible with the version that the work was made with.
+
+ c) Accompany the work with a written offer, valid for at
+ least three years, to give the same user the materials
+ specified in Subsection 6a, above, for a charge no more
+ than the cost of performing this distribution.
+
+ d) If distribution of the work is made by offering access to copy
+ from a designated place, offer equivalent access to copy the above
+ specified materials from the same place.
+
+ e) Verify that the user has already received a copy of these
+ materials or that you have already sent this user a copy.
+
+ For an executable, the required form of the "work that uses the
+Library" must include any data and utility programs needed for
+reproducing the executable from it. However, as a special exception,
+the materials to be distributed need not include anything that is
+normally distributed (in either source or binary form) with the major
+components (compiler, kernel, and so on) of the operating system on
+which the executable runs, unless that component itself accompanies
+the executable.
+
+ It may happen that this requirement contradicts the license
+restrictions of other proprietary libraries that do not normally
+accompany the operating system. Such a contradiction means you cannot
+use both them and the Library together in an executable that you
+distribute.
+
+ 7. You may place library facilities that are a work based on the
+Library side-by-side in a single library together with other library
+facilities not covered by this License, and distribute such a combined
+library, provided that the separate distribution of the work based on
+the Library and of the other library facilities is otherwise
+permitted, and provided that you do these two things:
+
+ a) Accompany the combined library with a copy of the same work
+ based on the Library, uncombined with any other library
+ facilities. This must be distributed under the terms of the
+ Sections above.
+
+ b) Give prominent notice with the combined library of the fact
+ that part of it is a work based on the Library, and explaining
+ where to find the accompanying uncombined form of the same work.
+
+ 8. You may not copy, modify, sublicense, link with, or distribute
+the Library except as expressly provided under this License. Any
+attempt otherwise to copy, modify, sublicense, link with, or
+distribute the Library is void, and will automatically terminate your
+rights under this License. However, parties who have received copies,
+or rights, from you under this License will not have their licenses
+terminated so long as such parties remain in full compliance.
+
+ 9. You are not required to accept this License, since you have not
+signed it. However, nothing else grants you permission to modify or
+distribute the Library or its derivative works. These actions are
+prohibited by law if you do not accept this License. Therefore, by
+modifying or distributing the Library (or any work based on the
+Library), you indicate your acceptance of this License to do so, and
+all its terms and conditions for copying, distributing or modifying
+the Library or works based on it.
+
+ 10. Each time you redistribute the Library (or any work based on the
+Library), the recipient automatically receives a license from the
+original licensor to copy, distribute, link with or modify the Library
+subject to these terms and conditions. You may not impose any further
+restrictions on the recipients' exercise of the rights granted herein.
+You are not responsible for enforcing compliance by third parties with
+this License.
+
+ 11. If, as a consequence of a court judgment or allegation of patent
+infringement or for any other reason (not limited to patent issues),
+conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License. If you cannot
+distribute so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you
+may not distribute the Library at all. For example, if a patent
+license would not permit royalty-free redistribution of the Library by
+all those who receive copies directly or indirectly through you, then
+the only way you could satisfy both it and this License would be to
+refrain entirely from distribution of the Library.
+
+If any portion of this section is held invalid or unenforceable under any
+particular circumstance, the balance of the section is intended to apply,
+and the section as a whole is intended to apply in other circumstances.
+
+It is not the purpose of this section to induce you to infringe any
+patents or other property right claims or to contest validity of any
+such claims; this section has the sole purpose of protecting the
+integrity of the free software distribution system which is
+implemented by public license practices. Many people have made
+generous contributions to the wide range of software distributed
+through that system in reliance on consistent application of that
+system; it is up to the author/donor to decide if he or she is willing
+to distribute software through any other system and a licensee cannot
+impose that choice.
+
+This section is intended to make thoroughly clear what is believed to
+be a consequence of the rest of this License.
+
+ 12. If the distribution and/or use of the Library is restricted in
+certain countries either by patents or by copyrighted interfaces, the
+original copyright holder who places the Library under this License may add
+an explicit geographical distribution limitation excluding those countries,
+so that distribution is permitted only in or among countries not thus
+excluded. In such case, this License incorporates the limitation as if
+written in the body of this License.
+
+ 13. The Free Software Foundation may publish revised and/or new
+versions of the Lesser General Public License from time to time.
+Such new versions will be similar in spirit to the present version,
+but may differ in detail to address new problems or concerns.
+
+Each version is given a distinguishing version number. If the Library
+specifies a version number of this License which applies to it and
+"any later version", you have the option of following the terms and
+conditions either of that version or of any later version published by
+the Free Software Foundation. If the Library does not specify a
+license version number, you may choose any version ever published by
+the Free Software Foundation.
+
+ 14. If you wish to incorporate parts of the Library into other free
+programs whose distribution conditions are incompatible with these,
+write to the author to ask for permission. For software which is
+copyrighted by the Free Software Foundation, write to the Free
+Software Foundation; we sometimes make exceptions for this. Our
+decision will be guided by the two goals of preserving the free status
+of all derivatives of our free software and of promoting the sharing
+and reuse of software generally.
+
+ NO WARRANTY
+
+ 15. BECAUSE THE LIBRARY IS LICENSED FREE OF CHARGE, THERE IS NO
+WARRANTY FOR THE LIBRARY, TO THE EXTENT PERMITTED BY APPLICABLE LAW.
+EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR
+OTHER PARTIES PROVIDE THE LIBRARY "AS IS" WITHOUT WARRANTY OF ANY
+KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE
+LIBRARY IS WITH YOU. SHOULD THE LIBRARY PROVE DEFECTIVE, YOU ASSUME
+THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
+
+ 16. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN
+WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY
+AND/OR REDISTRIBUTE THE LIBRARY AS PERMITTED ABOVE, BE LIABLE TO YOU
+FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR
+CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE
+LIBRARY (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING
+RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A
+FAILURE OF THE LIBRARY TO OPERATE WITH ANY OTHER SOFTWARE), EVEN IF
+SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
+DAMAGES.
+
+ END OF TERMS AND CONDITIONS
+
+ How to Apply These Terms to Your New Libraries
+
+ If you develop a new library, and you want it to be of the greatest
+possible use to the public, we recommend making it free software that
+everyone can redistribute and change. You can do so by permitting
+redistribution under these terms (or, alternatively, under the terms of the
+ordinary General Public License).
+
+ To apply these terms, attach the following notices to the library. It is
+safest to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least the
+"copyright" line and a pointer to where the full notice is found.
+
+
+ Copyright (C)
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+Also add information on how to contact you by electronic and paper mail.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the library, if
+necessary. Here is a sample; alter the names:
+
+ Yoyodyne, Inc., hereby disclaims all copyright interest in the
+ library `Frob' (a library for tweaking knobs) written by James Random Hacker.
+
+ , 1 April 1990
+ Ty Coon, President of Vice
+
+That's all there is to it!
+
+
Index: single_port/trunk/images/timing.dia
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: single_port/trunk/images/timing.dia
===================================================================
--- single_port/trunk/images/timing.dia (nonexistent)
+++ single_port/trunk/images/timing.dia (revision 15)
single_port/trunk/images/timing.dia
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: single_port/trunk/images/tbschematic.fig
===================================================================
--- single_port/trunk/images/tbschematic.fig (nonexistent)
+++ single_port/trunk/images/tbschematic.fig (revision 15)
@@ -0,0 +1,62 @@
+#FIG 3.2 Produced by xfig version 3.2.5-alpha5
+Landscape
+Center
+Metric
+A4
+100.00
+Single
+-2
+1200 2
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 1.00 60.00 120.00
+ 8325 540 6300 540
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 1.00 60.00 120.00
+ 6300 225 8325 225
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 1.00 60.00 120.00
+ 6300 855 8325 855
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 1.00 60.00 120.00
+ 6300 1170 8325 1170
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 1.00 60.00 120.00
+ 6300 1485 8325 1485
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 1.00 60.00 120.00
+ 6300 1800 8325 1800
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 1.00 60.00 120.00
+ 6300 2115 8325 2115
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+ 5490 450 6030 450 6030 2925 5490 2925 5490 450
+2 2 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
+ 3375 0 6300 0 6300 3375 3375 3375 3375 0
+2 2 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
+ 8325 0 10125 0 10125 2340 8325 2340 8325 0
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 1.00 60.00 120.00
+ 3375 270 2025 270
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 1.00 60.00 120.00
+ 2025 855 3375 855
+2 2 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
+ 0 0 2025 0 2025 1125 0 1125 0 0
+4 1 0 50 -1 0 16 1.5708 4 255 2070 5805 1710 single_port_server\001
+4 0 0 50 -1 1 16 0.0000 4 195 465 3645 1440 Test\001
+4 0 0 50 -1 1 16 0.0000 4 195 945 3645 1755 Harness\001
+4 0 0 50 -1 1 16 0.0000 4 270 1575 3645 2070 tb_single_port\001
+4 0 0 50 -1 0 16 0.0000 4 195 600 3600 405 Arch\001
+4 0 0 50 -1 0 16 0.0000 4 255 1455 8505 1350 (single_port)\001
+4 0 0 50 -1 0 16 0.0000 4 195 570 8505 945 DUT\001
+4 1 0 50 -1 0 16 0.0000 4 195 135 7290 495 q\001
+4 1 0 50 -1 0 16 0.0000 4 195 135 7290 180 d\001
+4 1 0 50 -1 0 16 0.0000 4 135 120 7290 810 a\001
+4 1 0 50 -1 0 16 0.0000 4 135 390 7290 1125 nce\001
+4 1 0 50 -1 0 16 0.0000 4 135 450 7290 1440 nwe\001
+4 1 0 50 -1 0 16 0.0000 4 135 405 7290 1755 noe\001
+4 1 0 50 -1 0 16 0.0000 4 255 1485 7290 2070 dealloc_mem\001
+4 1 0 50 -1 0 16 0.0000 4 255 900 2700 180 frm_srv\001
+4 1 0 50 -1 0 16 0.0000 4 225 705 2700 765 to_srv\001
+4 0 0 50 -1 0 16 0.0000 4 255 1590 225 765 tc_single_port\001
+4 0 0 50 -1 0 16 0.0000 4 195 960 225 450 Testcase\001
Index: single_port/trunk/images/timing.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: single_port/trunk/images/timing.png
===================================================================
--- single_port/trunk/images/timing.png (nonexistent)
+++ single_port/trunk/images/timing.png (revision 15)
single_port/trunk/images/timing.png
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: single_port/trunk/images/tbschematic.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: single_port/trunk/images/tbschematic.png
===================================================================
--- single_port/trunk/images/tbschematic.png (nonexistent)
+++ single_port/trunk/images/tbschematic.png (revision 15)
single_port/trunk/images/tbschematic.png
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: single_port/trunk
===================================================================
--- single_port/trunk (nonexistent)
+++ single_port/trunk (revision 15)
single_port/trunk
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: single_port/web_uploads
===================================================================
--- single_port/web_uploads (nonexistent)
+++ single_port/web_uploads (revision 15)
single_port/web_uploads
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: single_port/branches
===================================================================
--- single_port/branches (nonexistent)
+++ single_port/branches (revision 15)
single_port/branches
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: single_port/tags/REL/doc/single_port.html
===================================================================
--- single_port/tags/REL/doc/single_port.html (nonexistent)
+++ single_port/tags/REL/doc/single_port.html (revision 15)
@@ -0,0 +1,213 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
B"H
+
Description
+of single_port memory and test environment.
+
Abstract:
+
A single port memory with testbench is described. The memory is
+implemented as three different architectures.
+
Port Interface:
+
+
+
+ Port Name
+ |
+
+ Type
+ |
+
+ Description
+ |
+
+
+
+
+ rnwtQ
+ |
+
+ Time
+ |
+
+ Time delay from rnw = read until data appears on q data bus.
+ |
+
+
+
+ d
+ |
+
+ data_inter_typ
+ |
+
+ Input data bus, type specified in single_port_pkg
+ |
+
+
+
+ q
+ |
+
+ data_inter_typ
+ |
+
+ Output data bus, type specified in single_port_pkg
+ |
+
+
+
+ a
+ |
+
+ addr_inter_typ
+ |
+
+ Address bus, type specified in single_port_pkg
+ |
+
+
+
+ rnw
+ |
+
+ STD_LOGIC
+ |
+
+ Read not write port
+ |
+
+
+
+ dealloc_mem
+ |
+
+ BOOLEAN
+ |
+
+ When set to true, deallocate linked list memory.
+ |
+
+
+
+
+
Functional Description:
+
The single_port memory is implemented as three different
+architecures. The first architecture is called ArrayMemNoFlag, and
+implements the memory core as an array of STD_LOGIC_VECTOR. The memory
+is asynchronous and triggered on rnw'transaction. When rnw = '0', the
+data on bus "d" is loaded into the memory at the location specified by
+the addres bus "a". When rnw = '1', the data located in memory address
+"a" is loaded onto the output data bus "q". If a memory location is read
+which was not written to during the current simulation, 'U' are loaded
+onto the memory bus.
+
The second architecture is called ArrayMem, and implements the
+memory core as an array of BIT_VECTOR. This arrangement allows less
+workstation memory to be used than the ArrayMemNoFlag architecture. The
+memory is asynchronous and triggered on rnw'transaction. When rnw = '0',
+the data on bus "d" is loaded into the memory at the location specified
+by the addres bus "a". When rnw = '1', the data located in memory
+address "a" is loaded onto the output data bus "q". If a memory location
+is read which was not written to during the current simulation, 'U' are
+loaded onto the memory bus.
+
The third architecture is called LinkedList, and implements the
+memory core as a linked list of arrays of BIT_VECTOR. Each array in the
+linked list is a page of memory whose size is specified in
+single_port_pkg. This arrangement allows less workstation memory to be
+used than either the ArrayMemNoFlag or ArrayMem architectures. The
+memory is asynchronous and triggered on rnw'transaction. When rnw = '0',
+the data on bus "d" is loaded into the memory at the location specified
+by the addres bus "a". When rnw = '1', the data located in memory
+address "a" is loaded onto the output data bus "q". If a memory location
+is read which was not written to during the current simulation, 'U' are
+loaded onto the memory bus. To de-allocate the memory in the linked
+list, set dealloc_mem to true.
+
Functional Timing:
+
The single port memory is asynchronous and is triggered on
+rnw'transaction. When rnw is cleared to '0', the write occurs at the
+same time as rnw'transaction. When a read occurs, with rnw = '1' , data
+appears on the Q bus rnwtQ ns after rnw is set to '1'. The below sample
+timing diagram illustrates both a read and write operation.
+
+
+
Testbench Description:
+
The test bench is arranged as a client server architecture as
+specified by Bergeron. A diagram illustrating the
+testbench is given below.
+
+
+Two tests are specified in tc_single_port component. The first test
+writes data to two logical memory pages, and then reads them back
+verifying the correct data. The test case writes an error message to the
+console for every miscompare. The second case verifies that the
+single_port memory model outputs unknowns to the q bus if a read occurs
+for an unwritten memory location. Six configurations are specified in
+the test bench architecture tb_single_port, running both tests for each
+single_port architecture.
+
+
Usage:
+
A Makefile is used to compile and run all of the tests in a Unix or
+like environment, such as Cygwin. The compilation and simulation is
+targetted to the SymphonyEDA tool available at www.symphonyeda.com .
+
The source files and Makefile are located in {top}/VHDL
+
+To compile: make com
+
To simulate all of the tests: make sim
+
+
To clean the compiled library: make clean
+
The tests are labeled :
+
+ - ll_error
+ - ll_main
+ - mem_main
+
+ - mem_error
+
+ - memnoflag_main
+
+ - memnoflag_error
+
+
+
To simulate any of these tests, type make {testname}
+
Please contact Robert Paley at rpaley_yid@opencores.org
+if you have any questions or comments.
+
+
+
Index: single_port/tags/REL/images/tbschematic.jpg
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: single_port/tags/REL/images/tbschematic.jpg
===================================================================
--- single_port/tags/REL/images/tbschematic.jpg (nonexistent)
+++ single_port/tags/REL/images/tbschematic.jpg (revision 15)
single_port/tags/REL/images/tbschematic.jpg
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: single_port/tags/REL/images/timing.jpg
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: single_port/tags/REL/images/timing.jpg
===================================================================
--- single_port/tags/REL/images/timing.jpg (nonexistent)
+++ single_port/tags/REL/images/timing.jpg (revision 15)
single_port/tags/REL/images/timing.jpg
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: single_port/tags/REL/VHDL/linked_list_mem_pkg.vhd
===================================================================
--- single_port/tags/REL/VHDL/linked_list_mem_pkg.vhd (nonexistent)
+++ single_port/tags/REL/VHDL/linked_list_mem_pkg.vhd (revision 15)
@@ -0,0 +1,147 @@
+-- $Author: rpaley_yid $
+-- $Date: 2003-01-14 21:48:10 $
+-- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/linked_list_mem_pkg.vhd,v 1.1.1.1 2003-01-14 21:48:10 rpaley_yid Exp $
+-- $Locker
+-- $Revision: 1.1.1.1 $
+-- $State: Exp $
+
+-- --------------------------------------------------------------------------
+--
+-- Purpose: This package implements functions to allocate, write, read, and
+-- deallocate a linked list based memory.
+--
+--
+-- References:
+-- 1. The Designer's Guide to VHDL by Peter Ashenden
+-- ISBN: 1-55860-270-4 (pbk.)
+-- 2. Writing Testbenches - Functional Verification of HDL models by
+-- Janick Bergeron | ISBN: 0-7923-7766-4
+--
+-- Notes:
+--
+-- --------------------------------------------------------------------------
+
+LIBRARY IEEE;
+LIBRARY WORK;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE WORK.single_port_pkg.all;
+
+PACKAGE linked_list_mem_pkg IS
+ -- data memory array type definition
+ TYPE mem_array_typ IS ARRAY (0 TO PAGEDEPTH-1) OF data_typ;
+ -- Define memory page linked list cell. This cell contains,
+ -- the mem_array, starting page address, valid data array, and
+ -- the pointer to the next element in the linked list.
+ TYPE mem_page_typ;
+ -- pointer to next item in the linked list.
+ TYPE mem_page_ptr IS ACCESS mem_page_typ;
+ TYPE mem_page_typ IS RECORD
+ mem_array : mem_array_typ; -- data memory
+ -- This array is a flag which indicates if the corresponding
+ -- address location inside mem_array contains valid data.
+ data_valid_array : BIT_VECTOR( 0 TO PAGEDEPTH-1);
+ page_address : addr_typ;
+ next_cell : mem_page_ptr;
+ END RECORD mem_page_typ;
+ PROCEDURE rw_mem (
+ VARIABLE data : INOUT data_inter_typ;
+ VARIABLE addr : addr_typ;
+ VARIABLE write_flag : BOOLEAN;
+ VARIABLE next_cell : INOUT mem_page_ptr
+ );
+ PROCEDURE deallocate_mem (
+ VARIABLE next_cell : INOUT mem_page_ptr
+ );
+
+END PACKAGE linked_list_mem_pkg;
+
+PACKAGE BODY LINKED_LIST_MEM_PKG IS
+ -- --------------------------------------------------
+ -- The purpose of this procedure is to write a memory location from
+ -- the linked list, if the particular page does not exist, create it.
+ -- --------------------------------------------------
+ PROCEDURE rw_mem (
+ VARIABLE data : INOUT data_inter_typ;
+ VARIABLE addr : addr_typ;
+ VARIABLE write_flag : BOOLEAN;
+ VARIABLE next_cell : INOUT mem_page_ptr
+ ) IS
+ VARIABLE current_cell_v : mem_page_ptr; -- current page pointer
+ VARIABLE page_address_v : addr_typ; -- calculated page address
+ VARIABLE index_v : INTEGER; -- address within the memory page
+ VARIABLE mem_array_v : mem_array_typ;
+ VARIABLE data_valid_array_v : BIT_VECTOR(0 TO PAGEDEPTH-1);
+ BEGIN
+ -- Copy the top of the linked list pointer to a working pointer
+ current_cell_v := next_cell;
+ -- Calculate the index within the page from the given address
+ index_v := addr MOD PAGEDEPTH;
+ -- Calculate the page address from the given address
+ page_address_v := addr - index_v;
+ -- Search through the memory to determine if the calculated
+ -- memory page exists. Stop searching when reach the end of
+ -- the linked list.
+ WHILE ( current_cell_v /= NULL
+ AND current_cell_v.page_address /= page_address_v) LOOP
+ current_cell_v := current_cell_v.next_cell;
+ END LOOP;
+
+ IF write_flag THEN
+ IF ( current_cell_v /= NULL AND -- Check if address exists in memory.
+ current_cell_v.page_address = page_address_v
+ ) THEN
+ -- Found the memory page the particular address belongs to
+ current_cell_v.mem_array(index_v) := TO_BITVECTOR(data);
+ -- set memory location valid flag
+ current_cell_v.data_valid_array(index_v) := '1';
+ ELSE
+ -- The memory page the address belongs to was not allocated in memory.
+ -- Allocate page here and assign data.
+ mem_array_v(index_v) := TO_BITVECTOR(data);
+ data_valid_array_v(index_v) := '1';
+ next_cell := NEW mem_page_typ'( mem_array => mem_array_v,
+ data_valid_array => data_valid_array_v,
+ page_address => page_address_v,
+ next_cell => next_cell
+ );
+ END IF;
+ ELSE -- Read memory
+ IF ( current_cell_v /= NULL AND -- Check if address exists in memory.
+ current_cell_v.page_address = page_address_v AND
+ current_cell_v.data_valid_array(index_v) = '1'
+ ) THEN
+ -- Found the memory page the particular address belongs to,
+ -- and the memory location has valid data.
+ data := TO_STDLOGICVECTOR(current_cell_v.mem_array(index_v));
+ ELSE
+ -- Trying to read from unwritten or unallocated
+ -- memory location, return 'U';
+ data := (OTHERS => 'U');
+ END IF;
+ END IF;
+ END PROCEDURE rw_mem;
+
+ PROCEDURE deallocate_mem (
+ VARIABLE next_cell : INOUT mem_page_ptr
+ ) IS
+ VARIABLE delete_cell_v : mem_page_ptr;
+ BEGIN
+ -- Deallocate the linked link memory from work station memory.
+ WHILE next_cell /= NULL LOOP -- while not reached the end of the LL
+ delete_cell_v := next_cell; -- Copy pointer to record for deleting
+ next_cell := next_cell.next_cell; -- set pointer to next cell in LL
+ deallocate(delete_cell_v); -- Deallocate current cell from memory.
+ END LOOP;
+ END PROCEDURE deallocate_mem;
+END PACKAGE BODY LINKED_LIST_MEM_PKG;
+
+-- $Log: not supported by cvs2svn $
+-- Revision 1.1 2003/01/14 17:47:32 Default
+-- Initial revision
+--
+-- Revision 1.1 2002/12/24 18:03:50 Default
+-- Initial revision
+--
+
+
+
Index: single_port/tags/REL/VHDL/pkg_image.vhd
===================================================================
--- single_port/tags/REL/VHDL/pkg_image.vhd (nonexistent)
+++ single_port/tags/REL/VHDL/pkg_image.vhd (revision 15)
@@ -0,0 +1,307 @@
+-- $Author: rpaley_yid $
+-- $Date: 2003-01-14 21:48:10 $
+-- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/pkg_image.vhd,v 1.1.1.1 2003-01-14 21:48:10 rpaley_yid Exp $
+-- $Locker
+-- $Revision: 1.1.1.1 $
+-- $State: Exp $
+
+-- Copyright (c) 1997 Ben Cohen. All rights reserved.
+-- This model can be used in conjunction with the Kluwer Academic books
+-- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0
+-- "VHDL Amswers to Frequently Asked Questions", Kluwer Academic
+-- by Ben Cohen. email: vhdlcohen@aol.com
+--
+-- This source file for the Image Package
+-- may be used and distributed without restriction provided
+-- that this copyright statement is not removed from the file
+-- and that any derivative work contains this copyright notice.
+--
+--
+-- Original Author: Ben Cohen
+-- Description:
+-- Convert VHDL types to string for printing. This is especially useful when
+-- compiling with VHDL-87
+
+---------------------------------------------------------------
+LIBRARY IEEE;
+ USE IEEE.STD_LOGIC_1164.ALL;
+ USE IEEE.STD_LOGIC_TEXTIO.ALL;
+ USE IEEE.NUMERIC_STD.ALL;
+
+LIBRARY STD;
+ USE STD.TEXTIO.ALL;
+
+package pkg_image is
+ function Image(In_Image : Time) return String;
+ function Image(In_Image : Bit) return String;
+ function Image(In_Image : Bit_Vector) return String;
+ function Image(In_Image : Integer) return String;
+ function Image(In_Image : Real) return String;
+ function Image(In_Image : Std_uLogic) return String;
+ function Image(In_Image : Std_uLogic_Vector) return String;
+ function Image(In_Image : Std_Logic_Vector) return String;
+ function Image(In_Image : Signed) return String;
+ function Image(In_Image : UnSigned) return String;
+
+ function HexImage(InStrg : String) return String;
+ function HexImage(In_Image : Bit_Vector) return String;
+ function HexImage(In_Image : Std_uLogic_Vector) return String;
+ function HexImage(In_Image : Std_Logic_Vector) return String;
+ function HexImage(In_Image : Signed) return String;
+ function HexImage(In_Image : UnSigned) return String;
+
+ function DecImage(In_Image : Bit_Vector) return String;
+ function DecImage(In_Image : Std_uLogic_Vector) return String;
+ function DecImage(In_Image : Std_Logic_Vector) return String;
+ function DecImage(In_Image : Signed) return String;
+ function DecImage(In_Image : UnSigned) return String;
+end pkg_image;
+
+package body pkg_image is
+ function Image(In_Image : Time) return String is
+ variable L : Line; -- access type
+ variable W : String(1 to 14) := (others => ' ');
+ -- Long enough to hold a time string
+ begin
+ -- the WRITE procedure creates an object with "NEW".
+ -- L is passed as an output of the procedure.
+ Std.TextIO.WRITE(L, in_image);
+ -- Copy L.all onto W
+ W(L.all'range) := L.all;
+ Deallocate(L);
+ return W;
+ end Image;
+
+ function Image(In_Image : Bit) return String is
+ variable L : Line; -- access type
+ variable W : String(1 to 3) := (others => ' ');
+ begin
+ Std.TextIO.WRITE(L, in_image);
+ W(L.all'range) := L.all;
+ Deallocate(L);
+ return W;
+ end Image;
+
+ function Image(In_Image : Bit_Vector) return String is
+ variable L : Line; -- access type
+ variable W : String(1 to In_Image'length) := (others => ' ');
+ begin
+ Std.TextIO.WRITE(L, in_image);
+ W(L.all'range) := L.all;
+ Deallocate(L);
+ return W;
+ end Image;
+
+ function Image(In_Image : Integer) return String is
+ variable L : Line; -- access type
+ variable W : String(1 to 32) := (others => ' ');
+ -- Long enough to hold a time string
+ begin
+ Std.TextIO.WRITE(L, in_image);
+ W(L.all'range) := L.all;
+ Deallocate(L);
+ return W;
+ end Image;
+
+ function Image(In_Image : Real) return String is
+ variable L : Line; -- access type
+ variable W : String(1 to 32) := (others => ' ');
+ -- Long enough to hold a time string
+ begin
+ Std.TextIO.WRITE(L, in_image);
+ W(L.all'range) := L.all;
+ Deallocate(L);
+ return W;
+ end Image;
+
+ function Image(In_Image : Std_uLogic) return String is
+ variable L : Line; -- access type
+ variable W : String(1 to 3) := (others => ' ');
+ begin
+ IEEE.Std_Logic_Textio.WRITE(L, in_image);
+ W(L.all'range) := L.all;
+ Deallocate(L);
+ return W;
+ end Image;
+
+ function Image(In_Image : Std_uLogic_Vector) return String is
+ variable L : Line; -- access type
+ variable W : String(1 to In_Image'length) := (others => ' ');
+ begin
+ IEEE.Std_Logic_Textio.WRITE(L, in_image);
+ W(L.all'range) := L.all;
+ Deallocate(L);
+ return W;
+ end Image;
+
+ function Image(In_Image : Std_Logic_Vector) return String is
+ variable L : Line; -- access type
+ variable W : String(1 to In_Image'length) := (others => ' ');
+ begin
+ IEEE.Std_Logic_TextIO.WRITE(L, In_Image);
+ W(L.all'range) := L.all;
+ Deallocate(L);
+ return W;
+ end Image;
+
+ function Image(In_Image : Signed) return String is
+ begin
+ return Image(Std_Logic_Vector(In_Image));
+ end Image;
+
+ function Image(In_Image : UnSigned) return String is
+ begin
+ return Image(Std_Logic_Vector(In_Image));
+ end Image;
+
+ function HexImage(InStrg : String) return String is
+ subtype Int03_Typ is Integer range 0 to 3;
+ variable Result : string(1 to ((InStrg'length - 1)/4)+1) :=
+ (others => '0');
+ variable StrTo4 : string(1 to Result'length * 4) :=
+ (others => '0');
+ variable MTspace : Int03_Typ; -- Empty space to fill in
+ variable Str4 : String(1 to 4);
+ variable Group_v : Natural := 0;
+ begin
+ MTspace := Result'length * 4 - InStrg'length;
+ StrTo4(MTspace + 1 to StrTo4'length) := InStrg; -- padded with '0'
+ Cnvrt_Lbl : for I in Result'range loop
+ Group_v := Group_v + 4; -- identifies end of bit # in a group of 4
+ Str4 := StrTo4(Group_v - 3 to Group_v); -- get next 4 characters
+ case Str4 is
+ when "0000" => Result(I) := '0';
+ when "0001" => Result(I) := '1';
+ when "0010" => Result(I) := '2';
+ when "0011" => Result(I) := '3';
+ when "0100" => Result(I) := '4';
+ when "0101" => Result(I) := '5';
+ when "0110" => Result(I) := '6';
+ when "0111" => Result(I) := '7';
+ when "1000" => Result(I) := '8';
+ when "1001" => Result(I) := '9';
+ when "1010" => Result(I) := 'A';
+ when "1011" => Result(I) := 'B';
+ when "1100" => Result(I) := 'C';
+ when "1101" => Result(I) := 'D';
+ when "1110" => Result(I) := 'E';
+ when "1111" => Result(I) := 'F';
+ when others => Result(I) := 'X';
+ end case; -- Str4
+ end loop Cnvrt_Lbl;
+
+ return Result;
+ end HexImage;
+
+
+ function HexImage(In_Image : Bit_Vector) return String is
+ begin
+ return HexImage(Image(In_Image));
+ end HexImage;
+
+ function HexImage(In_Image : Std_uLogic_Vector) return String is
+ begin
+ return HexImage(Image(In_Image));
+ end HexImage;
+
+ function HexImage(In_Image : Std_Logic_Vector) return String is
+ begin
+ return HexImage(Image(In_Image));
+ end HexImage;
+
+ function HexImage(In_Image : Signed) return String is
+ begin
+ return HexImage(Image(In_Image));
+ end HexImage;
+
+ function HexImage(In_Image : UnSigned) return String is
+ begin
+ return HexImage(Image(In_Image));
+ end HexImage;
+
+ function DecImage(In_Image : Bit_Vector) return String is
+ variable In_Image_v : Bit_Vector(In_Image'length downto 1) := In_Image;
+ begin
+ if In_Image'length > 31 then
+ assert False
+ report "Number too large for Integer, clipping to 31 bits"
+ severity Warning;
+ return Image(To_Integer
+ (Unsigned(To_StdLogicVector
+ (In_Image_v(31 downto 1)))));
+ else
+ return Image(To_Integer(Unsigned(To_StdLogicVector(In_Image))));
+ end if;
+ end DecImage;
+
+ function DecImage(In_Image : Std_uLogic_Vector) return String is
+ variable In_Image_v : Std_uLogic_Vector(In_Image'length downto 1)
+ := In_Image;
+ begin
+ if In_Image'length > 31 then
+ assert False
+ report "Number too large for Integer, clipping to 31 bits"
+ severity Warning;
+ return Image(To_Integer(Unsigned(In_Image_v(31 downto 1))));
+ else
+ return Image(To_Integer(Unsigned(In_Image)));
+ end if;
+ end DecImage;
+
+ function DecImage(In_Image : Std_Logic_Vector) return String is
+ variable In_Image_v : Std_Logic_Vector(In_Image'length downto 1)
+ := In_Image;
+ begin
+ if In_Image'length > 31 then
+ assert False
+ report "Number too large for Integer, clipping to 31 bits"
+ severity Warning;
+ return Image(To_Integer(Unsigned(In_Image_v(31 downto 1))));
+ else
+ return Image(To_Integer(Unsigned(In_Image)));
+ end if;
+ end DecImage;
+
+ function DecImage(In_Image : Signed) return String is
+ variable In_Image_v : Signed(In_Image'length downto 1) := In_Image;
+ begin
+ if In_Image'length > 31 then
+ assert False
+ report "Number too large for Integer, clipping to 31 bits"
+ severity Warning;
+ return Image(To_Integer(In_Image_v(31 downto 1)));
+ else
+ return Image(To_Integer(In_Image));
+ end if;
+ end DecImage;
+
+ function DecImage(In_Image : UnSigned) return String is
+ variable In_Image_v : UnSigned(In_Image'length downto 1) := In_Image;
+ begin
+ if In_Image'length > 31 then
+ assert False
+ report "Number too large for Integer, clipping to 31 bits"
+ severity Warning;
+ return Image(To_Integer(In_Image_v(31 downto 1)));
+ else
+ return Image(To_Integer(In_Image));
+ end if;
+ end DecImage;
+
+end pkg_image;
+
+-- $Log: not supported by cvs2svn $
+-- Revision 1.1 2003/01/14 17:48:44 Default
+-- Initial revision
+--
+-- Revision 1.1 2002/12/24 18:07:50 Default
+-- Initial revision
+--
+
+
+
+
+
+
+
+
Index: single_port/tags/REL/VHDL/single_port.vhd
===================================================================
--- single_port/tags/REL/VHDL/single_port.vhd (nonexistent)
+++ single_port/tags/REL/VHDL/single_port.vhd (revision 15)
@@ -0,0 +1,131 @@
+-- $Author: rpaley_yid $
+-- $Date: 2003-01-14 21:48:11 $
+-- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/single_port.vhd,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $
+-- $Locker
+-- $Revision: 1.1.1.1 $
+-- $State: Exp $
+
+-- --------------------------------------------------------------------------
+--
+-- Purpose: This is a single port asynchronous memory. This files
+-- describes three architectures. Two architectures are traditional
+-- array based memories. One describes the memory as an array of
+-- STD_LOGIC_VECTOR, and the other describes the ARRAY as BIT_VECTOR.
+-- The third architecture describes the memory arranged as a linked
+-- list in order to conserve computer memory usage. The memory
+-- is organized as a linked list of BIT_VECTOR arrays whose size
+-- is defined PAGEDEPTH in single_port_pkg.vhd.
+--
+--
+-- References:
+-- 1. The Designer's Guide to VHDL by Peter Ashenden
+-- ISBN: 1-55860-270-4 (pbk.)
+-- 2. Writing Testbenches - Functional Verification of HDL models by
+-- Janick Bergeron | ISBN: 0-7923-7766-4
+--
+-- Notes:
+--
+-- --------------------------------------------------------------------------
+LIBRARY IEEE;
+LIBRARY WORK;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE WORK.single_port_pkg.ALL;
+USE WORK.linked_list_mem_pkg.ALL;
+
+ENTITY single_port IS
+ GENERIC (
+ rnwtQ : TIME := 1 NS
+ );
+ PORT (
+ d : IN data_inter_typ;
+ q : OUT data_inter_typ;
+ a : IN addr_inter_typ;
+ rnw : IN STD_LOGIC;
+ dealloc_mem : IN BOOLEAN
+ );
+END ENTITY single_port;
+
+ARCHITECTURE ArrayMemNoFlag OF single_port IS
+BEGIN
+
+ mem_proc : PROCESS
+ TYPE mem_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1) OF data_inter_typ;
+ VARIABLE mem : mem_typ;
+ BEGIN
+ WAIT on rnw'transaction;
+ IF ( rnw = '0') THEN -- Write
+ mem(TO_INTEGER(unsigned(a))) := d;
+ ELSE -- Read
+ q <= mem(TO_INTEGER(unsigned(a))) AFTER rnwtQ;
+ END IF;
+ END PROCESS mem_proc;
+
+END ArrayMemNoFlag;
+
+ARCHITECTURE ArrayMem OF single_port IS
+BEGIN
+
+ mem_proc : PROCESS
+ TYPE mem_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1 ) OF data_typ;
+ TYPE flag_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1 ) OF BOOLEAN;
+ VARIABLE mem : mem_typ;
+ VARIABLE flag : flag_typ;
+ BEGIN
+ WAIT ON rnw'transaction;
+ IF ( rnw = '0') THEN -- Write
+ mem(TO_INTEGER(unsigned(a))) := TO_BITVECTOR(d);
+ flag(TO_INTEGER(unsigned(a))) := true; -- set valid memory location flag
+ ELSE -- read data, either valid or 'U'
+ IF ( flag(TO_INTEGER(unsigned(a))) = true ) THEN
+ q <= TO_STDLOGICVECTOR(mem(TO_INTEGER(unsigned(a)))) AFTER rnwtQ;
+ ELSE -- reading invalid memory location
+ q <= (OTHERS => 'U') after rnwtQ;
+ END IF;
+ END IF;
+ END PROCESS mem_proc;
+END ArrayMem;
+
+ARCHITECTURE LinkedList OF single_port IS
+ BEGIN
+
+ mem_proc : PROCESS
+ VARIABLE mem_page_v : mem_page_ptr;
+ VARIABLE d_v : data_inter_typ;
+ VARIABLE a_v : addr_typ;
+ VARIABLE WRITE_MEM_v : BOOLEAN := true;
+ VARIABLE READ_MEM_v : BOOLEAN := false;
+ BEGIN
+ WAIT ON dealloc_mem'transaction , rnw'TRANSACTION;
+ IF NOT dealloc_mem THEN
+ d_v := d;
+ a_v := TO_INTEGER(unsigned(a));
+ IF ( rnw = '0' ) THEN -- write to linked list memory
+ rw_mem( data => d_v,
+ addr => a_v,
+ write_flag => WRITE_MEM_v,
+ next_cell => mem_page_v
+ );
+ ELSE -- read from linked list memory
+ rw_mem( data => d_v,
+ addr => a_v,
+ write_flag => READ_MEM_v,
+ next_cell => mem_page_v
+ );
+ q <= d_v after rnwtQ;
+ END IF;
+ ELSE -- Deallocate memory from work station memory.
+ deallocate_mem(mem_page_v);
+ END IF;
+ END PROCESS mem_proc;
+
+END LinkedList;
+
+-- $Log: not supported by cvs2svn $
+-- Revision 1.1 2003/01/14 17:48:31 Default
+-- Initial revision
+--
+-- Revision 1.1 2002/12/24 18:09:05 Default
+-- Initial revision
+--
+
Index: single_port/tags/REL/VHDL/single_port_pkg.vhd
===================================================================
--- single_port/tags/REL/VHDL/single_port_pkg.vhd (nonexistent)
+++ single_port/tags/REL/VHDL/single_port_pkg.vhd (revision 15)
@@ -0,0 +1,70 @@
+-- $Author: rpaley_yid $
+-- $Date: 2003-01-14 21:48:11 $
+-- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/single_port_pkg.vhd,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $
+-- $Locker: $
+-- $Revision: 1.1.1.1 $
+-- $State: Exp $
+
+-- --------------------------------------------------------------------------
+--
+-- Purpose: Package file for single_port memory and testbench
+--
+-- References:
+-- 1. The Designer's Guide to VHDL by Peter Ashenden
+-- ISBN: 1-55860-270-4 (pbk.)
+-- 2. Writing Testbenches - Functional Verification of HDL models by
+-- Janick Bergeron | ISBN: 0-7923-7766-4
+--
+-- Notes:
+--
+-- --------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+PACKAGE single_port_pkg IS
+CONSTANT PAGEDEPTH : INTEGER := 256; -- memory page depth
+CONSTANT PAGENUM : INTEGER := 4096; -- number of pages in memory.
+CONSTANT DATA_WIDTH : INTEGER := 32; -- memory data bus width
+CONSTANT ADDRESS_WIDTH : INTEGER := 16; -- memory address bus width
+-- Data bus type for memory interface
+SUBTYPE data_inter_typ IS STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
+-- Data bus type for internal memory
+SUBTYPE data_typ IS BIT_VECTOR(DATA_WIDTH-1 DOWNTO 0);
+-- Address bus type for memory interface
+SUBTYPE addr_inter_typ IS STD_LOGIC_VECTOR(ADDRESS_WIDTH-1 DOWNTO 0);
+-- Address bus type for internal memory
+SUBTYPE addr_typ IS NATURAL;
+-- Operations testbench can do.
+TYPE do_typ IS ( init , read , write , dealloc , end_test );
+
+TYPE to_srv_typ IS RECORD -- Record passed from test case to test bench
+ do : do_typ;
+ addr : addr_inter_typ;
+ data : data_inter_typ;
+ event : BOOLEAN;
+END RECORD to_srv_typ;
+
+TYPE frm_srv_typ IS RECORD -- Record passed from test bench to test case
+ data : data_inter_typ;
+ event : BOOLEAN;
+END RECORD frm_srv_typ;
+
+
+END PACKAGE single_port_pkg;
+
+PACKAGE BODY single_port_pkg IS
+
+END PACKAGE BODY single_port_pkg;
+
+-- $Log: not supported by cvs2svn $
+-- Revision 1.1 2003/01/14 17:48:44 Default
+-- Initial revision
+--
+-- Revision 1.1 2002/12/24 17:58:49 Default
+-- Initial revision
+--
+
+
+
Index: single_port/tags/REL/VHDL/tb_single_port.vhd
===================================================================
--- single_port/tags/REL/VHDL/tb_single_port.vhd (nonexistent)
+++ single_port/tags/REL/VHDL/tb_single_port.vhd (revision 15)
@@ -0,0 +1,191 @@
+-- $Author: rpaley_yid $
+-- $Date: 2003-01-14 21:48:11 $
+-- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/tb_single_port.vhd,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $
+-- $Locker
+-- $Revision: 1.1.1.1 $
+-- $State: Exp $
+
+-- --------------------------------------------------------------------------
+--
+-- Purpose: This file specifies test bench harness for the single_port
+-- Memory. It also contains the configuration files for all the
+-- tests.
+--
+--
+-- References:
+-- 1. The Designer's Guide to VHDL by Peter Ashenden
+-- ISBN: 1-55860-270-4 (pbk.)
+-- 2. Writing Testbenches - Functional Verification of HDL models by
+-- Janick Bergeron | ISBN: 0-7923-7766-4
+--
+-- Notes:
+--
+-- --------------------------------------------------------------------------
+LIBRARY IEEE;
+LIBRARY WORK;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE WORK.linked_list_mem_pkg.ALL;
+USE WORK.single_port_pkg.all;
+USE STD.TEXTIO.ALL;
+
+ENTITY tb_single_port IS
+END ENTITY tb_single_port;
+
+ARCHITECTURE BHV of tb_single_port IS
+
+COMPONENT single_port IS
+ GENERIC (
+ rnwtQ : TIME := 1 NS
+ );
+ PORT (
+ d : IN data_inter_typ;
+ q : OUT data_inter_typ;
+ a : IN addr_inter_typ;
+ rnw : IN STD_LOGIC;
+ dealloc_mem : BOOLEAN
+);
+END COMPONENT single_port;
+
+COMPONENT tc_single_port IS
+ PORT (
+ to_srv : OUT to_srv_typ;
+ frm_srv : IN frm_srv_typ
+);
+END COMPONENT tc_single_port;
+
+SIGNAL d : data_inter_typ;
+SIGNAL q : data_inter_typ;
+SIGNAL a : addr_inter_typ;
+SIGNAL rnw : STD_LOGIC;
+SIGNAL dealloc_mem : BOOLEAN;
+SIGNAL to_srv : to_srv_typ;
+SIGNAL frm_srv : frm_srv_typ;
+SIGNAL tie_vdd : STD_LOGIC := '1';
+BEGIN
+ dut : single_port
+ PORT MAP (
+ d => d,
+ a => a,
+ q => q,
+ rnw => rnw,
+ dealloc_mem => dealloc_mem
+ );
+
+ tc : tc_single_port
+ PORT MAP (
+ to_srv => to_srv,
+ frm_srv => frm_srv
+ );
+
+ single_port_server : PROCESS
+ VARIABLE frm_srv_v : frm_srv_typ;
+ CONSTANT ACCESS_DELAY : TIME := 5 NS;
+ BEGIN
+ -- Wait until the test case is finished setting up the next memory access.
+ WAIT ON to_srv'TRANSACTION;
+ CASE to_srv.do IS
+ WHEN init =>
+ ASSERT FALSE
+ REPORT "initialized"
+ SEVERITY NOTE;
+ WHEN read => -- perform memory read
+ d <= to_srv.data;
+ a <= to_srv.addr;
+ rnw <= '1';
+ -- Wait for data to appear
+ WAIT FOR ACCESS_DELAY;
+ WHEN write => -- perform memory write
+ d <= to_srv.data;
+ a <= to_srv.addr;
+ rnw <= '0';
+ WAIT FOR ACCESS_DELAY;
+ WHEN dealloc => -- deallocate the linked list for the LL architecture
+ dealloc_mem <= true;
+ WHEN end_test => -- reached the end of the test case
+ WAIT;
+ END CASE;
+ frm_srv_v.data := q;
+ -- Send message to test case to continue the test.
+ frm_srv <= frm_srv_v ; WAIT FOR 0 NS;
+ END PROCESS single_port_server;
+END BHV;
+
+CONFIGURATION ll_main_cfg OF TB_SINGLE_PORT IS
+ FOR BHV
+ FOR dut : single_port
+ USE ENTITY work.single_port(LinkedList);
+ END FOR; -- dut
+ FOR tc : tc_single_port
+ USE ENTITY work.tc_single_port(TC0);
+ END FOR; -- tc;
+ END FOR; -- BHV
+END CONFIGURATION ll_main_cfg;
+
+CONFIGURATION ll_error_cfg OF TB_SINGLE_PORT IS
+ FOR BHV
+ FOR dut : single_port
+ USE ENTITY work.single_port(LinkedList);
+ END FOR; -- dut
+ FOR tc : tc_single_port
+ USE ENTITY work.tc_single_port(TC1);
+ END FOR; -- tc;
+ END FOR; -- BHV
+END CONFIGURATION ll_error_cfg ;
+
+CONFIGURATION mem_main_cfg of TB_SINGLE_PORT IS
+ FOR BHV
+ FOR dut : single_port
+ USE ENTITY work.single_port(ArrayMem);
+ END FOR; -- dut
+ FOR tc : tc_single_port
+ USE ENTITY work.tc_single_port(TC0);
+ END FOR; -- tc;
+ END FOR; -- BHV
+END CONFIGURATION mem_main_cfg;
+
+CONFIGURATION mem_error_cfg of TB_SINGLE_PORT IS
+ FOR BHV
+ FOR dut : single_port
+ USE ENTITY work.single_port(ArrayMem);
+ END FOR; -- dut
+ FOR tc : tc_single_port
+ USE ENTITY work.tc_single_port(TC1);
+ END FOR; -- tc;
+ END FOR; -- BHV
+END CONFIGURATION mem_error_cfg;
+
+CONFIGURATION memnoflag_main_cfg of TB_SINGLE_PORT IS
+ FOR BHV
+ FOR dut : single_port
+ USE ENTITY work.single_port(ArrayMemNoFlag);
+ END FOR; -- dut
+ FOR tc : tc_single_port
+ USE ENTITY work.tc_single_port(TC0);
+ END FOR; -- tc;
+ END FOR; -- BHV
+END CONFIGURATION memnoflag_main_cfg;
+
+CONFIGURATION memnoflag_error_cfg of TB_SINGLE_PORT IS
+ FOR BHV
+ FOR dut : single_port
+ USE ENTITY work.single_port(ArrayMemNoFlag);
+ END FOR; -- dut
+ FOR tc : tc_single_port
+ USE ENTITY work.tc_single_port(TC1);
+ END FOR; -- tc;
+ END FOR; -- BHV
+END CONFIGURATION memnoflag_error_cfg;
+
+-- $Log: not supported by cvs2svn $
+-- Revision 1.1 2003/01/14 17:49:04 Default
+-- Initial revision
+--
+-- Revision 1.2 2002/12/31 19:19:43 Default
+-- Updated 'transaction statements for fixed simulator.
+--
+-- Revision 1.1 2002/12/24 18:10:18 Default
+-- Initial revision
+--
+
+
Index: single_port/tags/REL/VHDL/tc_single_port.vhd
===================================================================
--- single_port/tags/REL/VHDL/tc_single_port.vhd (nonexistent)
+++ single_port/tags/REL/VHDL/tc_single_port.vhd (revision 15)
@@ -0,0 +1,194 @@
+-- $Author: rpaley_yid $
+-- $Date: 2003-01-14 21:48:11 $
+-- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/tc_single_port.vhd,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $
+-- $Locker
+-- $Revision: 1.1.1.1 $
+-- $State: Exp $
+
+-- --------------------------------------------------------------------------
+--
+-- Purpose: This file specifies test cases for the single_port
+-- Memory.
+--
+--
+-- References:
+-- 1. The Designer's Guide to VHDL by Peter Ashenden
+-- ISBN: 1-55860-270-4 (pbk.)
+-- 2. Writing Testbenches - Functional Verification of HDL models by
+-- Janick Bergeron | ISBN: 0-7923-7766-4
+--
+-- Notes:
+--
+-- --------------------------------------------------------------------------
+LIBRARY IEEE;
+LIBRARY WORK;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE WORK.SINGLE_PORT_PKG.ALL;
+USE WORK.PKG_IMAGE.ALL;
+
+ENTITY tc_single_port IS
+PORT (
+ to_srv : OUT to_srv_typ;
+ frm_srv : IN frm_srv_typ
+);
+END ENTITY tc_single_port;
+
+-- --------------------------------------------------
+-- Test Case TC0
+-- This test case is to check two pages of memory
+-- Starting at physical address 0x0 ,
+-- Write a '1' to bit position 0, leaving all other bits 0.
+-- Increment the address,
+-- Write a '1' to bit position 1, leaving all other bits 0.
+-- Increment the address.
+-- Write a '1' to bit position 2, leaving all other bits 0.
+-- Continue in this fasion, until write a 1 to the MSB.
+-- increment the address,
+-- Write a '1' to bit position 0, leaving all other bits 0.
+-- Continue until the entire page is written to.
+-- Read back all addresses in the page, ensuring the
+-- correct data is read back.
+-- --------------------------------------------------
+
+
+ARCHITECTURE TC0 OF tc_single_port IS
+BEGIN
+ MAIN : PROCESS
+ VARIABLE to_srv_v : to_srv_typ;
+ VARIABLE frm_srv_v : frm_srv_typ;
+ VARIABLE dv : data_inter_typ :=
+ STD_LOGIC_VECTOR(TO_UNSIGNED(1,data_inter_typ'length));
+ VARIABLE offset_v : INTEGER;
+ BEGIN
+ offset_v := 0;
+ -- Run this write/read test 10 times for benchmark
+ -- purposes.
+ for i in 0 to 9 loop
+ for index in 0 to 2*PAGEDEPTH-1 loop
+ -- Specify to testbench server to perform write operation;
+ to_srv_v.do := write;
+ to_srv_v.data := dv; -- specify data to write
+ dv := To_StdLogicVector(TO_BitVector(dv) rol 1); -- ROL 1 for next write
+ -- Specify physical address.
+ to_srv_v.addr := STD_LOGIC_VECTOR(TO_UNSIGNED(index+offset_v,
+ ADDRESS_WIDTH));
+ to_srv <= to_srv_v ; WAIT FOR 0 NS;
+ WAIT ON frm_srv'TRANSACTION;
+ end loop;
+ -- Reset data to 1.
+ dv := STD_LOGIC_VECTOR(TO_UNSIGNED(1,data_inter_typ'length));
+ for index in 0 to 2*PAGEDEPTH-1 loop
+ -- Perform read operation.
+ to_srv_v.do := read;
+ -- Specify physical address.
+ to_srv_v.addr := STD_LOGIC_VECTOR(TO_UNSIGNED(index+offset_v,
+ ADDRESS_WIDTH));
+ to_srv <= to_srv_v ; WAIT FOR 0 NS;
+ WAIT ON frm_srv'TRANSACTION;
+ -- Compare actual with expected read back data, if the
+ -- the expected and actual to not compare, print the
+ -- expected and actual values.
+ ASSERT frm_srv.data = dv
+ REPORT "Expected: " & HexImage(frm_srv.data) &
+ " did not equal Actual: " & HexImage(dv)
+ SEVERITY ERROR;
+ -- Set expected data for next read.
+ dv := TO_STDLOGICVECTOR(TO_BITVECTOR(dv) rol 1);
+ end loop;
+ end loop;
+ to_srv_v.do := dealloc; -- Deallocate memory
+ --
+ to_srv <= to_srv_v ; WAIT FOR 0 NS;
+ -- Tell test bench server process test completed.
+ to_srv_v.do := end_test;
+ to_srv <= to_srv_v;
+ ASSERT FALSE
+ REPORT "Completed Test TC0"
+ SEVERITY NOTE;
+ WAIT;
+ END PROCESS main;
+END TC0;
+
+-- --------------------------------------------------
+-- Test Case TC1
+-- This test case is to check if the test bench will
+-- return 'U' for invalid memory locations for
+-- single_port architectures ArrayMEm and LinkedList
+-- --------------------------------------------------
+ARCHITECTURE TC1 OF tc_single_port IS
+BEGIN
+ MAIN : PROCESS
+ VARIABLE to_srv_v : to_srv_typ;
+ VARIABLE frm_srv_v : frm_srv_typ;
+ VARIABLE dv : data_inter_typ := (OTHERS => 'U');
+ BEGIN
+ -- Perform read operation.
+ to_srv_v.do := read;
+ -- Specify physical address.
+ to_srv_v.addr := STD_LOGIC_VECTOR(TO_UNSIGNED(0,
+ ADDRESS_WIDTH));
+ to_srv <= to_srv_v; WAIT FOR 0 NS;
+ WAIT ON frm_srv'TRANSACTION;
+ -- Compare actual with expected read back data, if the
+ -- the expected and actual to not compare, print the
+ -- expected and actual values.
+ ASSERT frm_srv.data = dv
+ REPORT "Expected: " & HexImage(frm_srv.data) &
+ " did not equal Actual: " & HexImage(dv)
+ SEVERITY ERROR;
+
+ -- Write and read back from same address.
+
+ -- Specify to testbench server to perform write operation;
+ to_srv_v.do := write;
+ dv := X"a5a5a5a5";
+ to_srv_v.data := dv; -- specify data to write
+ -- Specify physical address.
+ to_srv_v.addr := STD_LOGIC_VECTOR(TO_UNSIGNED(0,
+ ADDRESS_WIDTH));
+ to_srv <= to_srv_v; WAIT FOR 0 NS;
+ -- Wait until the test bench server finished with the write.
+ -- WAIT UNTIL frm_srv.event = true;
+ WAIT ON frm_srv'transaction;
+
+ to_srv_v.do := read;
+ -- Specify physical address.
+ to_srv_v.addr := STD_LOGIC_VECTOR(TO_UNSIGNED(0,
+ ADDRESS_WIDTH));
+ to_srv <= to_srv_v; WAIT FOR 0 NS;
+ WAIT ON frm_srv'transaction;
+
+ -- Compare actual with expected read back data, if the
+ -- the expected and actual to not compare, print the
+ -- expected and actual values.
+ ASSERT frm_srv.data = dv
+ REPORT "Expected: " & HexImage(frm_srv.data) &
+ " did not equal Actual: " & HexImage(dv)
+ SEVERITY ERROR;
+
+ to_srv_v.do := dealloc; -- Deallocate memory
+ --
+ to_srv <= to_srv_v; WAIT FOR 0 NS;
+ -- Tell test bench server process test completed.
+ to_srv_v.do := end_test;
+ to_srv <= to_srv_v; WAIT FOR 0 NS;
+
+ ASSERT FALSE
+ REPORT "Completed Test TC1"
+ SEVERITY NOTE;
+ WAIT;
+ END PROCESS main;
+END TC1;
+
+-- $Log: not supported by cvs2svn $
+-- Revision 1.1 2003/01/14 17:49:04 Default
+-- Initial revision
+--
+-- Revision 1.2 2002/12/31 19:19:43 Default
+-- Updated 'transaction statements for fixed simulator.
+--
+-- Revision 1.1 2002/12/24 18:13:50 Default
+-- Initial revision
+--
+
Index: single_port/tags/REL/VHDL/Makefile
===================================================================
--- single_port/tags/REL/VHDL/Makefile (nonexistent)
+++ single_port/tags/REL/VHDL/Makefile (revision 15)
@@ -0,0 +1,161 @@
+#
+# Description: Top level make file for single_port test project.
+# make com to compile
+# make sim to simulate all tests
+# make ll_error to run this test only
+# make ll_main to run this test only
+# make mem_main to run this test only
+# make mem_error to run this test only
+# make memnoflag_main to run this test
+# make memnoflag_error to run this test
+# $Author: rpaley_yid $
+# $Date: 2003-01-14 21:48:11 $
+# $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/Makefile,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $
+# $Locker: $
+# $Revision: 1.1.1.1 $
+# $State: Exp $
+
+# VCOM , VSIM , and WORK variables are set for Sonata simulator,
+# Change appropriately for your simulator. Ex.for Modeltech,
+# VCOM = vcom
+# VSIM = vsim
+# WORK = work
+
+SHELL = /bin/sh
+VCOM = vhdlp
+VCOMOPT = -s
+VSIM = vhdle
+VSIMOPT =
+WORK = work.sym
+## Need to figure out how to put Bourne shell stuff in Makefile
+## will do so to generate log files in
+## LOGDIR = ../LOG/
+## For now, log files are in VHDL directory.
+
+
+# List of main compiled objects, does not include configurations,
+# which are included in the tb_single_port.vhd file.
+# These targets are for the Sonata simulator, adjust accordingly for
+# your simulator.
+
+SINGLE_PORT_PKG_OBJ = $(WORK)/single_port_pkg/prim.var
+LINKED_LIST_MEM_OBJ = $(WORK)/linked_list_mem_pkg/prim.var
+PKG_IMAGE_OBJ = $(WORK)/pkg_image/prim.var
+SINGLE_PORT_OBJ = $(WORK)/single_port/prim.var
+TC_SINGLE_PORT_OBJ = $(WORK)/tc_single_port/prim.var
+TB_SINGLE_PORT_OBJ = $(WORK)/tb_single_port/prim.var
+LL_ERROR_DEP = $(WORK)/ll_error_cfg/prim.var
+LL_MAIN_DEP = $(WORK)/ll_main_cfg/prim.var
+MEM_MAIN_DEP = $(WORK)/mem_main_cfg/prim.var
+MEM_ERROR_DEP = $(WORK)/mem_error_cfg/prim.var
+MEMNOFLAG_MAIN_DEP = $(WORK)/memnoflag_main_cfg/prim.var
+MEMNOFLAG_ERROR_DEP = $(WORK)/memnoflag_error_cfg/prim.var
+
+LL_ERROR = $(LOGDIR)ll_error.log
+LL_MAIN = ll_main.log
+MEM_MAIN = mem_main.log
+MEM_ERROR = mem_error.log
+MEMNOFLAG_MAIN = memnoflag_main.log
+MEMNOFLAG_ERROR = memnoflag_error.log
+
+OBJS = $(SINGLE_PORT_PKG_OBJ) \
+ $(LINKED_LIST_MEM_OBJ) \
+ $(PKG_IMAGE_OBJ) \
+ $(SINGLE_PORT_OBJ) \
+ $(TC_SINGLE_PORT_OBJ) \
+ $(TB_SINGLE_PORT_OBJ)
+
+SIMOBJS = $(LL_ERROR) \
+ $(LL_MAIN) \
+ $(MEM_MAIN) \
+ $(MEM_ERROR) \
+ $(MEMNOFLAG_MAIN) \
+ $(MEMNOFLAG_ERROR)
+
+# Compile the project
+com: $(OBJS)
+
+# Clean the library
+clean:: $(WORK)
+
+# Simulate all tests
+sim: $(SIMOBJS)
+
+## Run only ll_error test
+ll_error: $(LL_ERROR)
+
+# Run onle ll_main test
+ll_main: $(LL_MAIN)
+
+# Run only mem_main test
+mem_main: $(MEM_MAIN)
+
+# Run only mem_error test
+mem_error: $(MEM_ERROR)
+
+# Run only memnoflag_main test
+memnoflag_main: $(MEMNOFLAG_MAIN)
+
+# Run only memnoflag_error test
+memnoflag_error: $(MEMNOFLAG_ERROR)
+
+# Target dependency rules to run tests
+$(LL_ERROR) : $(LL_ERROR_DEP)
+ $(VSIM) $(VSIMOPT) ll_error_cfg | tee $@
+
+$(LL_MAIN) : $(LL_MAIN_DEP)
+ $(VSIM) $(VSIMOPT) ll_main_cfg | tee $@
+
+$(MEM_MAIN) : $(MEM_MAIN_DEP)
+ $(VSIM) $(VSIMOPT) mem_main_cfg | tee $@
+
+$(MEM_ERROR) : $(MEM_ERROR_DEP)
+ $(VSIM) $(VSIMOPT) mem_error_cfg | tee $@
+
+$(MEMNOFLAG_MAIN) : $(MEMNOFLAG_MAIN_DEP)
+ $(VSIM) $(VSIMOPT) memnoflag_main_cfg | tee $@
+
+$(MEMNOFLAG_ERROR) : $(MEMNOFLAG_ERROR_DEP)
+ $(VSIM) $(VSIMOPT) memnoflag_error_cfg | tee $@
+
+# Target dependency rules to compile tests
+
+$(SINGLE_PORT_PKG_OBJ) : single_port_pkg.vhd
+ $(VCOM) $(VCOMOPT) $<
+
+$(LINKED_LIST_MEM_OBJ) : linked_list_mem_pkg.vhd \
+ $(SINGLE_PORT_PKG_OBJ)
+ $(VCOM) $(VCOMOPT) $<
+
+$(PKG_IMAGE_OBJ) : pkg_image.vhd
+ $(VCOM) $(VCOMOPT) $<
+
+$(SINGLE_PORT_OBJ) : single_port.vhd \
+ $(SINGLE_PORT_PKG_OBJ) \
+ $(LINKED_LIST_MEM_OBJ)
+ $(VCOM) $(VCOMOPT) $<
+
+$(TC_SINGLE_PORT_OBJ) : tc_single_port.vhd \
+ $(SINGLE_PORT_PKG_OBJ) \
+ $(PKG_IMAGE_OBJ) \
+ $(SINGLE_PORT_OBJ)
+ $(VCOM) $(VCOMOPT) $<
+
+$(TB_SINGLE_PORT_OBJ) : tb_single_port.vhd \
+ $(SINGLE_PORT_PKG_OBJ) \
+ $(LINKED_LIST_MEM_OBJ) \
+ $(SINGLE_PORT_OBJ) \
+ $(TC_SINGLE_PORT_OBJ)
+ $(VCOM) $(VCOMOPT) $<
+
+$(WORK) ::
+ rm -rf $(WORK)/*
+
+
+####################################################################
+# $Log: not supported by cvs2svn $
+# Revision 1.1 2002/12/31 19:21:59 Default
+# Initial revision
+#
+#
+
Index: single_port/tags
===================================================================
--- single_port/tags (nonexistent)
+++ single_port/tags (revision 15)