URL
https://opencores.org/ocsvn/ao68000/ao68000/trunk
Subversion Repositories ao68000
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- from Rev 14 to Rev 15
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Rev 14 → Rev 15
/ao68000/trunk/rtl/ao68000.v
98,9 → 98,9
`define ADDRESS_FROM_TRAP 4'd9 // move trap {22'b0, trap[7:0], 2'b0} |
|
`define SIZE_IDLE 4'd0 |
`define SIZE_BYTE 4'd1 // load byte: 2'b00 |
`define SIZE_WORD 4'd2 // load word: 2'b01 |
`define SIZE_LONG 4'd3 // load long: 2'b10 |
`define SIZE_BYTE 4'd1 // load byte: 3'b001 |
`define SIZE_WORD 4'd2 // load word: 3'b010 |
`define SIZE_LONG 4'd3 // load long: 3'b100 |
`define SIZE_1 4'd4 // SIZE.1: word ( ir[7:6] == 2'b00 ), long ( ir[7:6] == 2'b01 ) |
`define SIZE_1_PLUS 4'd5 // SIZE.1+: word ( ir[7:6] == 2'b10 ), long ( ir[7:6] == 2'b11 ) |
`define SIZE_2 4'd6 // SIZE.2: word ( ir[6] == 1'b0 ), long ( ir[6] == 1'b1 ) |
1765,7 → 1765,7
if(reset_n == 1'b0) begin |
size <= 2'b00; |
end |
else begin |
else if(size_control != `SIZE_IDLE) begin |
// BYTE |
size[0] <= (size_control == `SIZE_BYTE) |
| ((size_control == `SIZE_3) && (ir[7:6] == 2'b00)) |
/ao68000/trunk/doc/doxygen/html/page_spec_registers.html
30,7 → 30,7
<div class="contents"> |
<p>The <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> IP Core is a WISHBONE Master and does not contain any registers available for reading or writing from outside of the core. </p> |
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/ao68000/trunk/doc/doxygen/html/functions_vars_0x62.html
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/ao68000/trunk/doc/doxygen/html/functions_vars_0x74.html
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/ao68000/trunk/doc/doxygen/html/functions_0x72.html
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/ao68000/trunk/doc/doxygen/html/globals_vars_0x64.html
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/ao68000/trunk/doc/doxygen/html/group__DAT__O.html
27,7 → 27,7
</table> |
<p>WISHBONE Master Data Output </p> |
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/ao68000/trunk/doc/doxygen/html/globals_0x65.html
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/ao68000/trunk/doc/doxygen/html/functions_vars_0x6e.html
70,7 → 70,7
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/ao68000/trunk/doc/doxygen/html/globals_defs_0x67.html
63,7 → 63,7
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/ao68000/trunk/doc/doxygen/html/functions_0x6c.html
75,7 → 75,7
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/ao68000/trunk/doc/doxygen/html/classcondition.html
178,7 → 178,7
<li><a class="el" href="ao68000_8v_source.html">ao68000.v</a></li> |
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/ao68000/trunk/doc/doxygen/html/annotated.html
41,7 → 41,7
<tr><td class="indexkey">Module </td><td class="memItemRight" valign="bottom"><a class="el" href="classregisters.html">registers</a></td><td class="indexvalue">Microcode controlled registers </td></tr> |
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/ao68000/trunk/doc/doxygen/html/functions_vars_0x67.html
68,7 → 68,7
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/ao68000/trunk/doc/doxygen/html/page_spec_references.html
51,7 → 51,7
  </li> |
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/ao68000/trunk/doc/doxygen/html/functions_0x65.html
92,7 → 92,7
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/ao68000/trunk/doc/doxygen/html/functions_0x77.html
71,7 → 71,7
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/ao68000/trunk/doc/doxygen/html/group__RMW__O.html
27,7 → 27,7
</table> |
<p>WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Read-Modify-Write Cycle. </p> |
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/ao68000/trunk/doc/doxygen/html/page_microcode_compilation.html
41,7 → 41,7
<p>The compiled microcode, in Altera MIF format, is located at <code>./rtl/ao68000_microcode.mif</code>.</p> |
<p>The tool <code>./sw/ao68000_tool/</code> (<a class="el" href="page_tool.html">ao68000_tool documentation</a>) is used to compile the microcode source and transform it into a MIF file. The makefile containing instructions for performing the compilation is located at <code>./Makefile</code>. </p> |
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/ao68000/trunk/doc/doxygen/html/globals_vars_0x73.html
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/ao68000/trunk/doc/doxygen/html/globals_0x62.html
102,7 → 102,7
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/ao68000/trunk/doc/doxygen/html/page_microcode_operations.html
749,7 → 749,7
} |
} |
</pre></div> </div> |
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/ao68000/trunk/doc/doxygen/html/group__WE__O.html
27,7 → 27,7
</table> |
<p>WISHBONE Master Write Enable Output </p> |
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/ao68000/trunk/doc/doxygen/html/classcondition-members.html
39,7 → 39,7
<tr class="memlist"><td><a class="el" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a></td><td><a class="el" href="classcondition.html">condition</a></td><td><code> [Signal]</code></td></tr> |
<tr class="memlist"><td><a class="el" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a></td><td><a class="el" href="classcondition.html">condition</a></td><td><code> [Signal]</code></td></tr> |
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/ao68000/trunk/doc/doxygen/html/group__CTI__O.html
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<p>WISHBONE Address Tag, TAG_TYPE: TGA_O, Cycle Type Identifier, Incrementing Bus Cycle or End-of-Burst Cycle. </p> |
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/ao68000/trunk/doc/doxygen/html/group__STB__O.html
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<p>WISHBONE Master Strobe Output </p> |
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/ao68000/trunk/doc/doxygen/html/page_spec_architecture.html
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<p>The <a class="el" href="classmicrocode__branch.html" title="Select the next microcode word to execute.">microcode_branch</a> module is responsible for selecting the next microcode word to execute. This decision is based on the value of the current microcode word, the value of the interrupt privilege level, the state of the current bus cycle and other internal signals.</p> |
<p>The <a class="el" href="classmicrocode__branch.html" title="Select the next microcode word to execute.">microcode_branch</a> module implements a simple stack for the microcode addresses. This makes it possible to call subroutines inside the microcode. </p> |
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/ao68000/trunk/doc/doxygen/html/group__DAT__I.html
27,7 → 27,7
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<p>WISHBONE Master Data Input </p> |
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/ao68000/trunk/doc/doxygen/html/ao68000_8v_source.html
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<a name="l00098"></a><a class="code" href="ao68000_8v.html#a976e0837935917b54a3f575786283804">00098</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a2a30a0ecfa48e96cc5be837e7db71cab">ADDRESS_FROM_TRAP</a> <span class="vhdllogic">4'd9</span> <span class="keyword">// move trap {22'b0, trap[7:0], 2'b0}</span> |
<a name="l00099"></a>00099 |
<a name="l00100"></a><a class="code" href="ao68000_8v.html#a6b7b916e46f4e826e397f24c7e6cd5f1">00100</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a85698146140d774ffe2b54e5be255726">SIZE_IDLE</a> <span class="vhdllogic">4'd0</span> |
<a name="l00101"></a><a class="code" href="ao68000_8v.html#a80529f3bcf69bd83cb12853628e45dde">00101</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a8a04b85bed76a4381d1187aec9694a7e">SIZE_BYTE</a> <span class="vhdllogic">4'd1</span> <span class="keyword">// load byte: 2'b00</span> |
<a name="l00102"></a><a class="code" href="ao68000_8v.html#aa31da57c5af273923c08b1c95ff91fa6">00102</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a9da3fa515a6d6e5949573714c5682999">SIZE_WORD</a> <span class="vhdllogic">4'd2</span> <span class="keyword">// load word: 2'b01</span> |
<a name="l00103"></a><a class="code" href="ao68000_8v.html#a9f8b67ce84f0ac105c8c92764b32ee2d">00103</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ae54bb350f5d3a019211af2a214f46273">SIZE_LONG</a> <span class="vhdllogic">4'd3</span> <span class="keyword">// load long: 2'b10</span> |
<a name="l00101"></a><a class="code" href="ao68000_8v.html#a80529f3bcf69bd83cb12853628e45dde">00101</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a8a04b85bed76a4381d1187aec9694a7e">SIZE_BYTE</a> <span class="vhdllogic">4'd1</span> <span class="keyword">// load byte: 3'b001</span> |
<a name="l00102"></a><a class="code" href="ao68000_8v.html#aa31da57c5af273923c08b1c95ff91fa6">00102</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a9da3fa515a6d6e5949573714c5682999">SIZE_WORD</a> <span class="vhdllogic">4'd2</span> <span class="keyword">// load word: 3'b010</span> |
<a name="l00103"></a><a class="code" href="ao68000_8v.html#a9f8b67ce84f0ac105c8c92764b32ee2d">00103</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ae54bb350f5d3a019211af2a214f46273">SIZE_LONG</a> <span class="vhdllogic">4'd3</span> <span class="keyword">// load long: 3'b100</span> |
<a name="l00104"></a><a class="code" href="ao68000_8v.html#ab2a1ed498771dd52791361f258607630">00104</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a1b8724879ab643802f27348fa58f7208">SIZE_1</a> <span class="vhdllogic">4'd4</span> <span class="keyword">// SIZE.1: word ( ir[7:6] == 2'b00 ), long ( ir[7:6] == 2'b01 )</span> |
<a name="l00105"></a><a class="code" href="ao68000_8v.html#a5118e28f30c7e8403bed7875aeb8f902">00105</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a83d20a891b85a7fabe3d8c74b66ad884">SIZE_1_PLUS</a> <span class="vhdllogic">4'd5</span> <span class="keyword">// SIZE.1+: word ( ir[7:6] == 2'b10 ), long ( ir[7:6] == 2'b11 )</span> |
<a name="l00106"></a><a class="code" href="ao68000_8v.html#ac10136ab62631671a5e7ba54240bad1b">00106</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a1eca0e7e9287916bcfa96b96b0c46154">SIZE_2</a> <span class="vhdllogic">4'd6</span> <span class="keyword">// SIZE.2: word ( ir[6] == 1'b0 ), long ( ir[6] == 1'b1 )</span> |
1758,7 → 1758,7
<a name="l01765"></a>01765 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span> |
<a name="l01766"></a>01766 <span class="vhdlchar">size</span> <= <span class="vhdllogic">2'b00</span>; |
<a name="l01767"></a>01767 <span class="vhdlkeyword">end</span> |
<a name="l01768"></a>01768 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span> |
<a name="l01768"></a>01768 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">size_control</span> != <a class="code" href="ao68000_8v.html#a85698146140d774ffe2b54e5be255726">`SIZE_IDLE</a><span class="vhdlchar"></span>) <span class="vhdlkeyword">begin</span> |
<a name="l01769"></a>01769 <span class="keyword">// BYTE</span> |
<a name="l01770"></a>01770 <span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>] <= (<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a8a04b85bed76a4381d1187aec9694a7e">`SIZE_BYTE</a><span class="vhdlchar"></span>) |
<a name="l01771"></a>01771 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#ad8d417f0548efb4299bed1ed75004cbe">`SIZE_3</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b00</span>)) |
3451,7 → 3451,7
<a name="l03496"></a>03496 <span class="vhdlkeyword">endmodule</span> |
</pre></div></div> |
</div> |
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address> |
</body> |
/ao68000/trunk/doc/doxygen/html/functions_0x74.html
68,7 → 68,7
</li> |
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<a href="http://www.doxygen.org/index.html"> |
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address> |
</body> |
/ao68000/trunk/doc/doxygen/html/globals_vars_0x70.html
122,7 → 122,7
</li> |
</ul> |
</div> |
<hr class="footer"/><address class="footer"><small>Generated on Sat Jan 15 2011 16:54:37 for ao68000 by  |
<hr class="footer"/><address class="footer"><small>Generated on Sat Jan 15 2011 17:55:18 for ao68000 by  |
<a href="http://www.doxygen.org/index.html"> |
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address> |
</body> |
/ao68000/trunk/doc/doxygen/html/classregisters.html
756,7 → 756,7
<a name="l01765"></a>01765 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span> |
<a name="l01766"></a>01766 <span class="vhdlchar">size</span> <= <span class="vhdllogic">2'b00</span>; |
<a name="l01767"></a>01767 <span class="vhdlkeyword">end</span> |
<a name="l01768"></a>01768 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span> |
<a name="l01768"></a>01768 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">size_control</span> != <a class="code" href="ao68000_8v.html#a85698146140d774ffe2b54e5be255726">`SIZE_IDLE</a><span class="vhdlchar"></span>) <span class="vhdlkeyword">begin</span> |
<a name="l01769"></a>01769 <span class="keyword">// BYTE</span> |
<a name="l01770"></a>01770 <span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>] <= (<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a8a04b85bed76a4381d1187aec9694a7e">`SIZE_BYTE</a><span class="vhdlchar"></span>) |
<a name="l01771"></a>01771 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#ad8d417f0548efb4299bed1ed75004cbe">`SIZE_3</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b00</span>)) |
1394,7 → 1394,7
<li><a class="el" href="ao68000_8v_source.html">ao68000.v</a></li> |
</ul> |
</div> |
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</body> |
/ao68000/trunk/doc/doxygen/html/group__RTY__I.html
31,7 → 31,7
<li>on interrupt acknowledge: use auto-vector. </li> |
</ul> |
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/ao68000/trunk/doc/doxygen/html/page_microcode.html
1551,7 → 1551,7
} |
} |
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/ao68000/trunk/doc/doxygen/html/functions_vars_0x7a.html
68,7 → 68,7
</li> |
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address> |
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/ao68000/trunk/doc/doxygen/html/globals_defs_0x73.html
99,7 → 99,7
</li> |
</ul> |
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address> |
</body> |
/ao68000/trunk/doc/doxygen/html/classmicrocode__branch.html
708,7 → 708,7
<li><a class="el" href="ao68000_8v_source.html">ao68000.v</a></li> |
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address> |
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/ao68000/trunk/doc/doxygen/html/globals_0x67.html
63,7 → 63,7
</li> |
</ul> |
</div> |
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<a href="http://www.doxygen.org/index.html"> |
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</body> |
/ao68000/trunk/doc/doxygen/html/page_tool.html
37,7 → 37,7
</ul> |
<p>The tool is located at: <code>./sw/ao68000_tool.jar</code>. </p> |
</div> |
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/ao68000/trunk/doc/doxygen/html/globals_defs_0x69.html
78,7 → 78,7
</li> |
</ul> |
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</body> |
/ao68000/trunk/doc/doxygen/html/ao68000_8v.html
5217,7 → 5217,7
</div> |
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/ao68000/trunk/doc/doxygen/html/functions_0x6e.html
70,7 → 70,7
</li> |
</ul> |
</div> |
<hr class="footer"/><address class="footer"><small>Generated on Sat Jan 15 2011 16:54:37 for ao68000 by  |
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</body> |
/ao68000/trunk/doc/doxygen/html/group__reset__o.html
27,7 → 27,7
</table> |
<p>External device reset. Output high when processing the RESET instruction. </p> |
</div> |
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</body> |
/ao68000/trunk/doc/doxygen/html/group__SEL__O.html
27,7 → 27,7
</table> |
<p>WISHBONE Master Byte Select </p> |
</div> |
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address> |
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/ao68000/trunk/doc/doxygen/html/globals_vars.html
194,7 → 194,7
</li> |
</ul> |
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/ao68000/trunk/doc/doxygen/html/page_verification.html
66,7 → 66,7
<li>Java runtime (<a href="http://java.sun.com">http://java.sun.com</a>) is required to run the <code>ao68000_tool</code> (<a class="el" href="page_tool.html">ao68000_tool documentation</a>). </li> |
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/ao68000/trunk/doc/doxygen/html/group__fc__o.html
34,7 → 34,7
<li>7 - cpu space: interrupt acknowledge. </li> |
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/ao68000/trunk/doc/doxygen/html/functions_vars_0x73.html
157,7 → 157,7
</li> |
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/ao68000/trunk/doc/doxygen/html/classregisters-members.html
84,7 → 84,7
<tr class="memlist"><td><a class="el" href="classregisters.html#ae6143c84411ad159cbe1662f3909e726">ALWAYS_8</a>clock, reset_n</td><td><a class="el" href="classregisters.html">registers</a></td><td><code> [Always Construct]</code></td></tr> |
<tr class="memlist"><td><a class="el" href="classregisters.html#ae04888e60d745f9f64ca5c52d0969adb">ALWAYS_9</a>clock, reset_n</td><td><a class="el" href="classregisters.html">registers</a></td><td><code> [Always Construct]</code></td></tr> |
</table></div> |
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/ao68000/trunk/doc/doxygen/html/globals_defs_0x6d.html
420,7 → 420,7
</li> |
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/ao68000/trunk/doc/doxygen/html/documentation_8v.html
41,7 → 41,7
|
<p>Definition in file <a class="el" href="documentation_8v_source.html">documentation.v</a>.</p> |
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/ao68000/trunk/doc/doxygen/html/page_spec_revisions.html
39,7 → 39,7
<td>1.2 </td><td>15.01.2011 </td><td>Aleksander Osman, Frederic Requin</td><td>Core area optimization: biggest gain in ALU multiplication and division reimplementation. </td></tr> |
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/ao68000/trunk/doc/doxygen/html/page_mc68000.html
1149,7 → 1149,7
// required by: ANDI,EORI,ORI,ANDI to CCR,EORI to CCR,ORI to CCR,ANDI to SR,EORI to SR,ORI to SR,ADDI,SUBI |
|
</pre></div> </div> |
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/ao68000/trunk/doc/doxygen/html/functions_vars_0x69.html
96,7 → 96,7
</li> |
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</body> |
/ao68000/trunk/doc/doxygen/html/group__CLK__I.html
27,7 → 27,7
</table> |
<p>WISHBONE Clock Input </p> |
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/ao68000/trunk/doc/doxygen/html/functions_0x67.html
68,7 → 68,7
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<tr class="memlist"><td><a class="el" href="classmicrocode__branch.html#a5c48a82153e9796a3913029cde0cc182">ALWAYS_32</a>clock, reset_n</td><td><a class="el" href="classmicrocode__branch.html">microcode_branch</a></td><td><code> [Always Construct]</code></td></tr> |
<tr class="memlist"><td><a class="el" href="classmicrocode__branch.html#a4e2c393980b78c66fbb22710e14a1cbb">ALWAYS_33</a>clock, reset_n</td><td><a class="el" href="classmicrocode__branch.html">microcode_branch</a></td><td><code> [Always Construct]</code></td></tr> |
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<tr><td class="indexkey"><a class="el" href="documentation_8v.html">documentation.v</a> <a href="documentation_8v_source.html">[code]</a></td><td class="indexvalue">Ao68000 Doxygen documentation </td></tr> |
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<p>Processor blocked indicator. The processor is blocked after a double bus error. </p> |
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<tr class="memlist"><td><a class="el" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">Sm</a></td><td><a class="el" href="classalu.html">alu</a></td><td><code> [Define]</code></td></tr> |
<tr class="memlist"><td><a class="el" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">Z</a></td><td><a class="el" href="classalu.html">alu</a></td><td><code> [Define]</code></td></tr> |
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<tr class="memlist"><td><a class="el" href="classmemory__registers.html#afc54073a43b749eb1f1376c4b31cd1e3">altsyncram</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Module Instance]</code></td></tr> |
<tr class="memlist"><td><a class="el" href="classmemory__registers.html#a09281e3224878c570c81844785844fe0">ALWAYS_29</a>clock, reset_n</td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Always Construct]</code></td></tr> |
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<p>WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Single Bus Cycle. </p> |
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<td>CLK_I</td><td>Input Port</td><td>64</td><td>-</td><td>-</td><td>-</td><td>System clock. </td></tr> |
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<p>WISHBONE Master Address Output </p> |
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- tmp .......................................................................... Temporary build/run directory |
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<tr class="memlist"><td><a class="el" href="classbus__control.html#ad06cdf24c29b1b82596011bac2c9169c">ALWAYS_0</a>CLK_I, reset_n</td><td><a class="el" href="classbus__control.html">bus_control</a></td><td><code> [Always Construct]</code></td></tr> |
<tr class="memlist"><td><a class="el" href="classbus__control.html#af34450e53e6fd2fd36db7dff17caf063">ALWAYS_1</a>CLK_I, reset_n</td><td><a class="el" href="classbus__control.html">bus_control</a></td><td><code> [Always Construct]</code></td></tr> |
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<p>Asynchronous Reset Input </p> |
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<li>on interrupt acknowledge cycle: spurious interrupt. </li> |
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<li>on interrupt acknowledge cycle: external vector provided on DAT_I[7:0]. </li> |
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<tr class="memlist"><td><a class="el" href="classdecoder.html#a269c8223e03f340fbe89513326d22891">ILLEGAL_1111_INSTRUCTION_TRAP</a></td><td><a class="el" href="classdecoder.html">decoder</a></td><td><code> [Parameter]</code></td></tr> |
<tr class="memlist"><td><a class="el" href="classdecoder.html#aa6cefc0d2e58f3efccca7b784c2c9551">UNUSED_MICROPC</a></td><td><a class="el" href="classdecoder.html">decoder</a></td><td><code> [Parameter]</code></td></tr> |
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<li><b>MC68000</b> - the original Motorola MC68000 processor. </li> |
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[000765ee] [00000752] [000765f6] [000765ee] [000765e4] |
[000765da] [000765cf] [000811f8] [00000b00] [00000dc2] |
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<p>WISHBONE Master Cycle Output </p> |
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<a name="l00581"></a>00581 |
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</td><td><a class="el" href="classmemory__registers.html">memory_registers</a>   </td><td><a class="el" href="classregisters.html">registers</a>   </td></tr><tr><td><a class="el" href="classao68000.html">ao68000</a>   </td><td><a name="letter_C"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah">  C  </div></td></tr></table> |
</td><td><a class="el" href="classdecoder.html">decoder</a>   </td><td><a class="el" href="classmicrocode__branch.html">microcode_branch</a>   </td></tr></table><div class="qindex"><a class="qindex" href="#letter_A">A</a> | <a class="qindex" href="#letter_B">B</a> | <a class="qindex" href="#letter_C">C</a> | <a class="qindex" href="#letter_D">D</a> | <a class="qindex" href="#letter_M">M</a> | <a class="qindex" href="#letter_R">R</a></div> |
</div> |
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</table> |
<p>WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Block Bus Cycle. </p> |
</div> |
<hr class="footer"/><address class="footer"><small>Generated on Sat Jan 15 2011 16:54:37 for ao68000 by  |
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<p>WISHBONE Address Tag, TAG_TYPE: TGA_O, Burst Type Extension, always Linear Burst. </p> |
</div> |
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<li>RTY_I: auto-vector. </li> |
</ul> |
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<hr class="footer"/><address class="footer"><small>Generated on Sat Jan 15 2011 16:54:37 for ao68000 by  |
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<li>blocked state after a double bus error. </li> |
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<hr class="footer"/><address class="footer"><small>Generated on Sat Jan 15 2011 16:54:37 for ao68000 by  |
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<p><b>About the documentation:</b> The <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> core documentation is generated by the Doxygen tool (www.doxygen.org) with the doxverilog patch (<a href="http://developer.berlios.de/projects/doxverilog/">http://developer.berlios.de/projects/doxverilog/</a>). </p> |
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/ao68000/trunk/doc/doxygen/html/classao68000-members.html
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<tr class="memlist"><td><a class="el" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">Sm</a></td><td><a class="el" href="classalu.html">alu</a></td><td><code> [Define]</code></td></tr> |
<tr class="memlist"><td><a class="el" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">Z</a></td><td><a class="el" href="classalu.html">alu</a></td><td><code> [Define]</code></td></tr> |
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<hr class="footer"/><address class="footer"><small>Generated on Sat Jan 15 2011 16:54:37 for ao68000 by  |
<hr class="footer"/><address class="footer"><small>Generated on Sat Jan 15 2011 17:55:18 for ao68000 by  |
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address> |
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/ao68000/trunk/doc/doxygen/html/functions_0x6f.html
77,7 → 77,7
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<hr class="footer"/><address class="footer"><small>Generated on Sat Jan 15 2011 16:54:37 for ao68000 by  |
<hr class="footer"/><address class="footer"><small>Generated on Sat Jan 15 2011 17:55:18 for ao68000 by  |
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address> |
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/ao68000/trunk/Makefile
85,8 → 85,8
cd ./tmp/compare_with_winuae/verilog && iverilog -y. -y./../../../rtl -y./../../../tests/compare_with_winuae/verilog -o tb_ao68000 ./../../../tests/compare_with_winuae/verilog/tb_ao68000.v |
cp ./rtl/ao68000_microcode.mif ./tmp/compare_with_winuae/verilog |
|
START_IR_DEC := 32960 |
END_IR_DEC := 36864 |
START_IR_DEC := 17920 |
END_IR_DEC := 18176 |
TERM_PROGRAM := xterm |
COUNT := 4 |
COUNT_LIST := $(wordlist 1,$(COUNT),0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19) |