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Rev 14 → Rev 15

/trunk/bench/verilog/can_testbench.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2003/01/09 21:54:39 mohor
// rx fifo added. Not 100 % verified, yet.
//
// Revision 1.8 2003/01/08 02:09:43 mohor
// Acceptance filter added.
//
184,26 → 187,41
 
if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
begin
send_frame(0, 1, {26'h00000a6, 3'h5}, 2, 15'h2a11); // mode, rtr, id, length, crc
// send_frame(0, 1, {26'h00000a6, 3'h5}, 2, 15'h2a11); // mode, rtr, id, length, crc
// send_frame(0, 1, 29'h12567635, 2, 15'h75b4); // mode, rtr, id, length, crc
send_frame(0, 1, {26'h00000a6, 3'h5}, 4'h2, 15'h2a11); // mode, rtr, id, length, crc
end
else
begin
send_frame(0, 1, {26'h00000a6, 3'h5}, 2, 15'h2a11); // mode, rtr, id, length, crc
send_frame(0, 1, {26'h00000a6, 3'h5}, 4'h2, 15'h2a11); // mode, rtr, id, length, crc
 
read_receive_buffer;
$display("\n\n");
 
send_frame(0, 1, {26'h00000a6, 3'h5}, 4'h2, 15'h2a11); // mode, rtr, id, length, crc
end
 
 
repeat (50000) @ (posedge clk);
 
read_register(8'h4);
read_register(8'h20);
read_register(8'h21);
read_register(8'h22);
read_register(8'h23);
read_register(8'h24);
read_register(8'h25);
read_receive_buffer;
 
release_rx_buffer;
$display("\n\n");
 
read_receive_buffer;
 
release_rx_buffer;
$display("\n\n");
 
read_receive_buffer;
 
send_frame(0, 1, {26'h00000a6, 3'h5}, 4'h2, 15'h2a11); // mode, rtr, id, length, crc
 
$display("\n\n");
 
read_receive_buffer;
 
$display("CAN Testbench finished.");
$stop;
end
251,6 → 269,30
endtask
 
 
task read_receive_buffer;
integer i;
begin
if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
begin
for (i=8'h16; i<=8'h28; i=i+1)
read_register(i);
end
else
begin
for (i=8'h20; i<=8'h29; i=i+1)
read_register(i);
end
end
endtask
 
 
task release_rx_buffer;
begin
write_register(8'h1, 8'h4);
end
endtask
 
 
task test_synchronization;
begin
// Hard synchronization
299,8 → 341,66
input [28:0] id;
input [3:0] length;
input [14:0] crc;
integer pointer;
integer cnt;
integer total_bits;
integer stuff_cnt;
reg [117:0] data;
begin
 
stuff_cnt = 0;
 
if(mode) // Extended format
data = {id[28:18], 1'b1, 1'b1, 1'b0, id[17:0], remote_trans_req, 2'h0, length};
else // Standard format
data = {id[10:0], remote_trans_req, 1'b0, 1'b0, length};
 
if(length) // Send data if length is > 0
begin
for (cnt=1; cnt<=(2*length); cnt=cnt+1) // data (we are sending nibbles)
data = {data[113:0], cnt[3:0]};
end
 
// Adding CRC
data = {data[104:0], crc[14:0]};
 
 
// Calculating pointer that points to the bit that will be send
if(mode) // Extended format
pointer = 53 + 8 * length;
else // Standard format
pointer = 32 + 8 * length;
 
// This is how many bits we need to shift
total_bits = pointer;
 
send_bit(0); // SOF
 
for (cnt=0; cnt<=total_bits; cnt =cnt+1)
begin
send_bit(data[pointer]); // Bit stuffing comes here !!!
pointer = pointer - 1;
end
 
// Nothing send after the data (just recessive bit)
repeat (13) send_bit(1); // CRC delimiter + ack + ack delimiter + EOF !!! Check what is the minimum value for which core works ok
 
 
 
end
endtask
 
 
task send_frame_old;
input mode;
input remote_trans_req;
input [28:0] id;
input [3:0] length;
input [14:0] crc;
integer cnt;
 
reg [28:0] data;
reg [3:0] len;
begin
344,6 → 444,7
data=data<<1;
end
send_bit(remote_trans_req);
send_bit(0); // IDE
send_bit(0); // r0 (reserved 0)
 
/trunk/rtl/verilog/can_btl.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2003/01/08 02:10:53 mohor
// Acceptance filter added.
//
// Revision 1.6 2002/12/28 04:13:23 mohor
// Backup version.
//
292,7 → 295,7
sampled_bit_q <= 1;
sample_point <= 0;
end
else if (clk_en)
else if (clk_en & (~hard_sync))
begin
if (seg1 & (quant_cnt == (time_segment1 + delay)))
begin
/trunk/rtl/verilog/can_top.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2003/01/09 21:54:45 mohor
// rx fifo added. Not 100 % verified, yet.
//
// Revision 1.5 2003/01/08 02:10:56 mohor
// Acceptance filter added.
//
100,6 → 103,9
wire acceptance_filter_mode;
wire sleep_mode;
 
/* Command register */
wire release_buffer;
 
/* Bus Timing 0 register */
wire [5:0] baud_r_presc;
wire [1:0] sync_jump_width;
155,6 → 161,13
.acceptance_filter_mode(acceptance_filter_mode),
.sleep_mode(sleep_mode),
 
/* Command register */
.clear_data_overrun(),
.release_buffer(release_buffer),
.abort_tx(),
.tx_request(),
.self_rx_request(),
 
/* Bus Timing 0 register */
.baud_r_presc(baud_r_presc),
.sync_jump_width(sync_jump_width),
269,6 → 282,9
.reset_mode(reset_mode),
.acceptance_filter_mode(acceptance_filter_mode),
/* Command register */
.release_buffer(release_buffer),
 
/* Clock Divider register */
.extended_mode(extended_mode),
 
/trunk/rtl/verilog/can_bsp.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2003/01/09 21:54:45 mohor
// rx fifo added. Not 100 % verified, yet.
//
// Revision 1.6 2003/01/09 14:46:58 mohor
// Temporary files (backup).
//
90,7 → 93,10
reset_mode,
acceptance_filter_mode,
 
// Clock Divider register
/* Command register */
release_buffer,
 
/* Clock Divider register */
extended_mode,
 
rx_idle,
134,6 → 140,8
input acceptance_filter_mode;
input extended_mode;
 
/* Command register */
input release_buffer;
 
output rx_idle;
 
576,6 → 584,8
begin
if (rst)
bit_stuff_cnt <= 1;
else if (bit_de_stuff_reset)
bit_stuff_cnt <=#Tp 1;
else if (sample_point & bit_stuff_cnt_en)
begin
if (bit_stuff_cnt == 5)
817,7 → 827,7
.data_out(data_out),
 
.reset_mode(reset_mode),
.release_buffer(1'b0), // FIX ME
.release_buffer(release_buffer),
.extended_mode(extended_mode)
 
/trunk/rtl/verilog/can_registers.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2003/01/09 14:46:58 mohor
// Temporary files (backup).
//
// Revision 1.4 2003/01/08 02:10:55 mohor
// Acceptance filter added.
//
81,6 → 84,14
acceptance_filter_mode,
sleep_mode,
 
 
/* Command register */
clear_data_overrun,
release_buffer,
abort_tx,
tx_request,
self_rx_request,
 
/* Bus Timing 0 register */
baud_r_presc,
sync_jump_width,
141,6 → 152,13
output acceptance_filter_mode;
output sleep_mode;
 
/* Command register */
output clear_data_overrun;
output release_buffer;
output abort_tx;
output tx_request;
output self_rx_request;
 
/* Bus Timing 0 register */
output [5:0] baud_r_presc;
output [1:0] sync_jump_width;
186,6 → 204,7
 
 
wire we_mode = cs & (~rw) & (addr == 8'h0);
wire we_command = cs & (~rw) & (addr == 8'h1);
wire we_bus_timing_0 = cs & (~rw) & (addr == 8'h6) & reset_mode;
wire we_bus_timing_1 = cs & (~rw) & (addr == 8'h7) & reset_mode;
wire we_clock_divider_hi = cs & (~rw) & (addr == 8'h31) & reset_mode;
230,6 → 249,28
/* End Mode register */
 
 
/* Command register */
wire [4:0] command;
wire [2:0] command_dummy;
can_register_syn #(8, 8'h0) COMMAND_REG
( .data_in(data_in),
.data_out({command_dummy, command}),
.we(we_command),
.clk(clk),
.rst_sync(|command)
);
 
assign self_rx_request = command[4];
assign clear_data_overrun = command[3];
assign release_buffer = command[2];
assign abort_tx = command[1];
assign tx_request = command[0];
/* End Command register */
 
 
 
 
 
/* Bus Timing 0 register */
wire [7:0] bus_timing_0;
can_register #(8) BUS_TIMING_0_REG
396,6 → 437,7
begin
case(addr)
8'h0 : data_out <= mode;
8'h1 : data_out <= 8'h0;
8'h6 : data_out <= bus_timing_0;
8'h7 : data_out <= bus_timing_1;
8'h16 : data_out <= reset_mode? acceptance_code_0 : fix_me; // + fix TX identifiers
416,6 → 458,7
begin
case(addr)
8'h0 : data_out <= mode;
8'h1 : data_out <= 8'hff;
8'h4 : data_out <= reset_mode? acceptance_code_0 : 8'hff;
8'h5 : data_out <= reset_mode? acceptance_mask_0 : 8'hff;
8'h6 : data_out <= reset_mode? bus_timing_0 : 8'hff;

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