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URL https://opencores.org/ocsvn/cpu6502_true_cycle/cpu6502_true_cycle/trunk

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Rev 14 → Rev 15

/trunk/rtl/verilog_TRIAL/reg_pc.v
3,14 → 3,14
`define true 1'b 1
`define TRUE 1'b 1
 
`timescale 1 ns / 1 ns
`timescale 1 ns / 1 ns // timescale for following modules
 
 
// Verilog Entity R6502_TC.Reg_PC.symbol
// VHDL Entity R6502_TC.Reg_PC.symbol
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 19:07:21 07.01.2009
// at - 19:25:31 10.02.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
42,7 → 42,7
 
// Jens-D. Gutschmidt Project: R6502_TC
// scantara2003@yahoo.de
// COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
// COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG
//
// This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or any later version.
58,13 → 58,13
// <<-- more -->>
// Title: Program Counter Logic
// Path: R6502_TC/Reg_PC/struct
// Edited: by eda on 07 Jan 2009
// Edited: by eda on 10 Feb 2009
//
// Verilog Architecture R6502_TC.Reg_PC.struct
// VHDL Architecture R6502_TC.Reg_PC.struct
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 19:07:21 07.01.2009
// at - 19:25:32 10.02.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
/trunk/rtl/verilog_TRIAL/reg_sp.v
3,14 → 3,14
`define true 1'b 1
`define TRUE 1'b 1
 
`timescale 1 ns / 1 ns
`timescale 1 ns / 1 ns // timescale for following modules
 
 
// Verilog Entity R6502_TC.Reg_SP.symbol
// VHDL Entity R6502_TC.Reg_SP.symbol
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 18:23:46 07.01.2009
// at - 19:25:32 10.02.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
38,7 → 38,7
 
// Jens-D. Gutschmidt Project: R6502_TC
// scantara2003@yahoo.de
// COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
// COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG
//
// This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or any later version.
54,13 → 54,13
// <<-- more -->>
// Title: Stack Pointer Logic
// Path: R6502_TC/Reg_SP/struct
// Edited: by eda on 01 Jan 2009
// Edited: by eda on 10 Feb 2009
//
// Verilog Architecture R6502_TC.Reg_SP.struct
// VHDL Architecture R6502_TC.Reg_SP.struct
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 18:23:46 07.01.2009
// at - 19:25:32 10.02.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
/trunk/rtl/verilog_TRIAL/r6502_tc.v
3,14 → 3,14
`define true 1'b 1
`define TRUE 1'b 1
 
`timescale 1 ns / 1 ns
`timescale 1 ns / 1 ns // timescale for following modules
 
 
// Verilog Entity R6502_TC.R6502_TC.symbol
// VHDL Entity R6502_TC.R6502_TC.symbol
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 19:21:55 07.01.2009
// by - eda.UNKNOWN (ENTWICKL4-XP-PR)
// at - 11:47:57 23.02.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
27,7 → 27,6
d_o,
rd_o,
sync_o,
wr_n_o,
wr_o);
 
42,13 → 41,12
output [7:0] d_o;
output rd_o;
output sync_o;
output wr_n_o;
output wr_o;
 
 
// Jens-D. Gutschmidt Project: R6502_TC
// scantara2003@yahoo.de
// COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
// COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG
//
// This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or any later version.
64,13 → 62,13
// <<-- more -->>
// Title: Top Level
// Path: R6502_TC/R6502_TC/struct
// Edited: by eda on 04 Jan 2009
// Edited: by eda on 10 Feb 2009
//
// Verilog Architecture R6502_TC.R6502_TC.struct
// VHDL Architecture R6502_TC.R6502_TC.struct
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 19:21:55 07.01.2009
// by - eda.UNKNOWN (ENTWICKL4-XP-PR)
// at - 11:47:58 23.02.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
78,11 → 76,14
wire [7:0] d_o;
wire rd_o;
wire sync_o;
wire wr_n_o;
wire wr_o;
 
// Declarations
 
// Optional embedded configurations
// pragma synthesis_off
 
// pragma synthesis_on
// Instance port mappings.
 
Core U_0 (.clk_clk_i(clk_clk_i),
96,7 → 97,6
.d_o(d_o),
.rd_o(rd_o),
.sync_o(sync_o),
.wr_n_o(wr_n_o),
.wr_o(wr_o));
 
// Architecture declarations
/trunk/rtl/verilog_TRIAL/fsm_execution_unit.v
3,14 → 3,14
`define true 1'b 1
`define TRUE 1'b 1
 
`timescale 1 ns / 1 ns
`timescale 1 ns / 1 ns // timescale for following modules
 
 
// Verilog Entity R6502_TC.FSM_Execution_Unit.symbol
// VHDL Entity R6502_TC.FSM_Execution_Unit.symbol
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 19:21:47 07.01.2009
// by - eda.UNKNOWN (ENTWICKL4-XP-PR)
// at - 11:47:40 23.02.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
55,7 → 55,6
sel_sp_as_o,
sel_sp_in_o,
sync_o,
wr_n_o,
wr_o);
 
98,13 → 97,12
output sel_sp_as_o;
output sel_sp_in_o;
output sync_o;
output wr_n_o;
output wr_o;
 
 
// Jens-D. Gutschmidt Project: R6502_TC
// scantara2003@yahoo.de
// COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
// COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG
//
// This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or any later version.
120,13 → 118,13
// <<-- more -->>
// Title: FSM Execution Unit for all op codes
// Path: R6502_TC/FSM_Execution_Unit/fsm
// Edited: by eda on 07 Jan 2009
// Edited: by eda on 23 Feb 2009
//
// Verilog Architecture R6502_TC.FSM_Execution_Unit.fsm
// VHDL Architecture R6502_TC.FSM_Execution_Unit.fsm
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 19:21:50 07.01.2009
// by - eda.UNKNOWN (ENTWICKL4-XP-PR)
// at - 11:47:41 23.02.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
151,7 → 149,6
reg sel_sp_as_o;
reg sel_sp_in_o;
wire sync_o;
wire wr_n_o;
wire wr_o;
 
// Declarations
165,8 → 162,6
reg reg_sel_sp_in;
reg [7:0] sig_D_OUT;
reg [15:0] sig_PC;
reg sig_RD;
reg sig_RWn;
reg sig_SYNC;
reg sig_WR;
reg [8:0] zw_ALU;
184,143 → 179,137
reg [7:0] zw_b4;
reg zw_so;
parameter FETCH = 8'b 00000000;
parameter s1 = 8'b 00000001;
parameter s2 = 8'b 00000011;
parameter s5 = 8'b 00000010;
parameter s3 = 8'b 00000110;
parameter s4 = 8'b 00000111;
parameter s12 = 8'b 00000101;
parameter s16 = 8'b 00000100;
parameter s17 = 8'b 00001100;
parameter s24 = 8'b 00001101;
parameter s25 = 8'b 00001111;
parameter s271 = 8'b 00001110;
parameter s273 = 8'b 00001010;
parameter s304 = 8'b 00001011;
parameter s307 = 8'b 00001001;
parameter s177 = 8'b 00001000;
parameter s180 = 8'b 00011000;
parameter s181 = 8'b 00011001;
parameter s182 = 8'b 00011011;
parameter s183 = 8'b 00011010;
parameter s184 = 8'b 00011110;
parameter s185 = 8'b 00011111;
parameter s186 = 8'b 00011101;
parameter s187 = 8'b 00011100;
parameter s188 = 8'b 00010100;
parameter s189 = 8'b 00010101;
parameter s190 = 8'b 00010111;
parameter s191 = 8'b 00010110;
parameter s192 = 8'b 00010010;
parameter s193 = 8'b 00010011;
parameter s377 = 8'b 00010001;
parameter s381 = 8'b 00010000;
parameter s378 = 8'b 00110000;
parameter s382 = 8'b 00110001;
parameter s379 = 8'b 00110011;
parameter s383 = 8'b 00110010;
parameter s384 = 8'b 00110110;
parameter s380 = 8'b 00110111;
parameter s385 = 8'b 00110101;
parameter s386 = 8'b 00110100;
parameter s387 = 8'b 00111100;
parameter s388 = 8'b 00111101;
parameter s389 = 8'b 00111111;
parameter s391 = 8'b 00111110;
parameter s392 = 8'b 00111010;
parameter s390 = 8'b 00111011;
parameter s393 = 8'b 00111001;
parameter s394 = 8'b 00111000;
parameter s395 = 8'b 00101000;
parameter s396 = 8'b 00101001;
parameter s397 = 8'b 00101011;
parameter s398 = 8'b 00101010;
parameter s399 = 8'b 00101110;
parameter s400 = 8'b 00101111;
parameter s401 = 8'b 00101101;
parameter s526 = 8'b 00101100;
parameter s527 = 8'b 00100100;
parameter s528 = 8'b 00100101;
parameter s529 = 8'b 00100111;
parameter s530 = 8'b 00100110;
parameter s531 = 8'b 00100010;
parameter s544 = 8'b 00100011;
parameter s545 = 8'b 00100001;
parameter s546 = 8'b 00100000;
parameter s547 = 8'b 01100000;
parameter s549 = 8'b 01100001;
parameter s550 = 8'b 01100011;
parameter s404 = 8'b 01100010;
parameter s556 = 8'b 01100110;
parameter s557 = 8'b 01100111;
parameter s579 = 8'b 01100101;
parameter s201 = 8'b 01100100;
parameter s202 = 8'b 01101100;
parameter s210 = 8'b 01101101;
parameter s211 = 8'b 01101111;
parameter s215 = 8'b 01101110;
parameter s217 = 8'b 01101010;
parameter s218 = 8'b 01101011;
parameter s222 = 8'b 01101001;
parameter s223 = 8'b 01101000;
parameter s224 = 8'b 01111000;
parameter s225 = 8'b 01111001;
parameter s226 = 8'b 01111011;
parameter s243 = 8'b 01111010;
parameter s244 = 8'b 01111110;
parameter s247 = 8'b 01111111;
parameter s344 = 8'b 01111101;
parameter s343 = 8'b 01111100;
parameter s250 = 8'b 01110100;
parameter s251 = 8'b 01110101;
parameter s351 = 8'b 01110111;
parameter s361 = 8'b 01110110;
parameter s360 = 8'b 01110010;
parameter s403 = 8'b 01110011;
parameter s406 = 8'b 01110001;
parameter s407 = 8'b 01110000;
parameter s409 = 8'b 01010000;
parameter s412 = 8'b 01010001;
parameter s413 = 8'b 01010011;
parameter s416 = 8'b 01010010;
parameter s418 = 8'b 01010110;
parameter s510 = 8'b 01010111;
parameter s553 = 8'b 01010101;
parameter s555 = 8'b 01010100;
parameter s558 = 8'b 01011100;
parameter s560 = 8'b 01011101;
parameter s561 = 8'b 01011111;
parameter s563 = 8'b 01011110;
parameter s564 = 8'b 01011010;
parameter s565 = 8'b 01011011;
parameter s566 = 8'b 01011001;
parameter s266 = 8'b 01011000;
parameter s301 = 8'b 01001000;
parameter s302 = 8'b 01001001;
parameter RES = 8'b 01001011;
parameter s511 = 8'b 01001010;
parameter s559 = 8'b 01001110;
parameter s562 = 8'b 01001111;
parameter s567 = 8'b 01001101;
parameter s568 = 8'b 01001100;
parameter s569 = 8'b 01000100;
parameter s570 = 8'b 01000101;
parameter s571 = 8'b 01000111;
parameter s572 = 8'b 01000110;
parameter s573 = 8'b 01000010;
parameter s574 = 8'b 01000011;
parameter s548 = 8'b 01000001;
parameter s551 = 8'b 01000000;
parameter s552 = 8'b 11000000;
parameter s575 = 8'b 11000001;
parameter s576 = 8'b 11000011;
parameter s577 = 8'b 11000010;
parameter s532 = 8'b 11000110;
parameter s533 = 8'b 11000111;
parameter s534 = 8'b 11000101;
parameter s535 = 8'b 11000100;
parameter s536 = 8'b 11001100;
parameter s537 = 8'b 11001101;
parameter G10_1 = 8'b 00000001;
parameter G10_2 = 8'b 00000010;
parameter G10_3 = 8'b 00000011;
parameter G10_4 = 8'b 00000100;
parameter G10_5 = 8'b 00000101;
parameter G10_6 = 8'b 00000110;
parameter G10_7 = 8'b 00000111;
parameter G10_e1 = 8'b 00001000;
parameter G10_e2 = 8'b 00001001;
parameter G10_e3 = 8'b 00001010;
parameter G11_1 = 8'b 00001011;
parameter G11_2 = 8'b 00001100;
parameter G11_3 = 8'b 00001101;
parameter G11_4 = 8'b 00001110;
parameter G11_5 = 8'b 00001111;
parameter G11_6 = 8'b 00010000;
parameter G11_7 = 8'b 00010001;
parameter G11_e = 8'b 00010010;
parameter G12_1 = 8'b 00010011;
parameter G12_e1 = 8'b 00010100;
parameter G12_e2 = 8'b 00010101;
parameter G13_1 = 8'b 00010110;
parameter G13_2 = 8'b 00010111;
parameter G13_e = 8'b 00011000;
parameter G14_1 = 8'b 00011001;
parameter G14_2 = 8'b 00011010;
parameter G14_3 = 8'b 00011011;
parameter G14_4 = 8'b 00011100;
parameter G14_5 = 8'b 00011101;
parameter G14_6 = 8'b 00011110;
parameter G14_7 = 8'b 00011111;
parameter G14_e = 8'b 00100000;
parameter G15_1 = 8'b 00100001;
parameter G15_2 = 8'b 00100010;
parameter G15_3 = 8'b 00100011;
parameter G15_4 = 8'b 00100100;
parameter G15_5 = 8'b 00100101;
parameter G15_6 = 8'b 00100110;
parameter G15_7 = 8'b 00100111;
parameter G15_e1 = 8'b 00101000;
parameter G15_e2 = 8'b 00101001;
parameter G15_e3 = 8'b 00101010;
parameter G16_1 = 8'b 00101011;
parameter G16_2 = 8'b 00101100;
parameter G16_3 = 8'b 00101101;
parameter G16_4 = 8'b 00101110;
parameter G16_5 = 8'b 00101111;
parameter G16_6 = 8'b 00110000;
parameter G16_7 = 8'b 00110001;
parameter G16_e1 = 8'b 00110010;
parameter G16_e2 = 8'b 00110011;
parameter G16_e3 = 8'b 00110100;
parameter G17_1 = 8'b 00110101;
parameter G17_10 = 8'b 00110110;
parameter G17_2 = 8'b 00110111;
parameter G17_3 = 8'b 00111000;
parameter G17_4 = 8'b 00111001;
parameter G17_5 = 8'b 00111010;
parameter G17_6 = 8'b 00111011;
parameter G17_7 = 8'b 00111100;
parameter G17_8 = 8'b 00111101;
parameter G17_9 = 8'b 00111110;
parameter G17_e = 8'b 00111111;
parameter G18_1 = 8'b 01000000;
parameter G18_2 = 8'b 01000001;
parameter G18_3 = 8'b 01000010;
parameter G18_4 = 8'b 01000011;
parameter G18_5 = 8'b 01000100;
parameter G18_e = 8'b 01000101;
parameter G19_1 = 8'b 01000110;
parameter G1_1 = 8'b 01000111;
parameter G20_1 = 8'b 01001000;
parameter G20_2 = 8'b 01001001;
parameter G20_3 = 8'b 01001010;
parameter G20_e = 8'b 01001011;
parameter G21_1 = 8'b 01001100;
parameter G21_2 = 8'b 01001101;
parameter G21_3 = 8'b 01001110;
parameter G21_4 = 8'b 01001111;
parameter G21_e = 8'b 01010000;
parameter G22_1 = 8'b 01010001;
parameter G22_e = 8'b 01010010;
parameter G23_1 = 8'b 01010011;
parameter G23_e = 8'b 01010100;
parameter G24_1 = 8'b 01010101;
parameter G24_2 = 8'b 01010110;
parameter G24_e = 8'b 01010111;
parameter G25_1 = 8'b 01011000;
parameter G25_2 = 8'b 01011001;
parameter G25_e = 8'b 01011010;
parameter G26_1 = 8'b 01011011;
parameter G26_2 = 8'b 01011100;
parameter G26_3 = 8'b 01011101;
parameter G26_4 = 8'b 01011110;
parameter G26_e = 8'b 01011111;
parameter G27_1 = 8'b 01100000;
parameter G27_2 = 8'b 01100001;
parameter G27_3 = 8'b 01100010;
parameter G27_4 = 8'b 01100011;
parameter G27_e = 8'b 01100100;
parameter G28_1 = 8'b 01100101;
parameter G28_2 = 8'b 01100110;
parameter G28_3 = 8'b 01100111;
parameter G28_4 = 8'b 01101000;
parameter G28_5 = 8'b 01101001;
parameter G28_e = 8'b 01101010;
parameter G29_1 = 8'b 01101011;
parameter G29_2 = 8'b 01101100;
parameter G29_3 = 8'b 01101101;
parameter G29_4 = 8'b 01101110;
parameter G29_5 = 8'b 01101111;
parameter G29_e = 8'b 01110000;
parameter G2_1 = 8'b 01110001;
parameter G30_1 = 8'b 01110010;
parameter G30_2 = 8'b 01110011;
parameter G30_3 = 8'b 01110100;
parameter G30_4 = 8'b 01110101;
parameter G30_5 = 8'b 01110110;
parameter G30_e = 8'b 01110111;
parameter G31_1 = 8'b 01111000;
parameter G32_1 = 8'b 01111001;
parameter G33_1 = 8'b 01111010;
parameter G34_1 = 8'b 01111011;
parameter G3_1 = 8'b 01111100;
parameter G4_1 = 8'b 01111101;
parameter G5_1 = 8'b 01111110;
parameter G6_1 = 8'b 01111111;
parameter G7_1 = 8'b 10000000;
parameter G8_1 = 8'b 10000001;
parameter G9_1 = 8'b 10000010;
parameter RES = 8'b 10000011;
 
// Declare current and next state signals
reg [7:0] current_state;
330,7 → 319,6
reg [7:0] d_o_cld;
reg rd_o_cld;
reg sync_o_cld;
reg wr_n_o_cld;
reg wr_o_cld;
 
// ---------------------------------------------------------------
346,7 → 334,6
d_o_cld <= 8'h 00;
rd_o_cld <= 1'b 0;
sync_o_cld <= 1'b 0;
wr_n_o_cld <= 1'b 1;
wr_o_cld <= 1'b 0;
reg_F <= 8'b 00000100;
reg_sel_pc_in <= 1'b 0;
387,9 → 374,8
zw_b4 <= zw_b4;
zw_so <= (zw_so | ~so_n_i) & ~reg_F[6];
d_o_cld <= sig_D_OUT;
rd_o_cld <= sig_RD;
rd_o_cld <= ~sig_WR;
sync_o_cld <= sig_SYNC;
wr_n_o_cld <= sig_RWn;
wr_o_cld <= sig_WR;
 
// Combined Actions
605,6 → 591,8
else if (d_i == 8'h 40 & rdy_i == 1'b 1 )
begin
sig_PC <= adr_nxt_pc_i;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 0;
end
else if (d_i == 8'h 60 & rdy_i == 1'b 1 )
begin
722,23 → 710,67
reg_sel_sp_as <= 1'b 0;
end
end
s1:
G10_1:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 65)
begin
sig_PC <= adr_pc_i;
sig_PC <= {8'h 00, d_i};
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 69 &
reg_F[3] == 1'b 0 )
begin
sig_PC <= adr_nxt_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU[8];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s2:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 75 )
begin
sig_PC <= adr_pc_i;
reg_F[0] <= 1'b 1;
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 6D )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 7D )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 79 )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 71 )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 61 )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 69 &
reg_F[3] == 1'b 1 )
begin
sig_PC <= adr_nxt_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU4[4];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
745,165 → 777,110
reg_sel_sp_as <= 1'b 1;
end
end
s5:
G10_2:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[3] <= 1'b 1;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
sig_PC <= {8'h 00, zw_b1};
end
end
s3:
G10_3:
begin
sig_PC <= adr_pc_i;
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[2] <= 1'b 1;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
sig_PC <= {d_i, zw_b1};
end
end
s4:
G10_4:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 9A)
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h BA )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s12:
G10_5:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[0] <= 1'b 0;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
sig_PC <= {8'h 00, zw_b1};
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
end
s16:
G10_6:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[3] <= 1'b 0;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
end
end
s17:
G10_7:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[2] <= 1'b 0;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
sig_PC <= {8'h 00, zw_b1};
end
end
s24:
G10_e1:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 0)
begin
sig_PC <= adr_pc_i;
reg_F[6] <= 1'b 0;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU[8];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s25:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 1 )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU4[4];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s271:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 4C)
else if (rdy_i == 1'b 1 )
begin
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 11;
zw_b1 <= d_i;
sig_PC <= {zw_b3, zw_b1};
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 6C )
begin
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 00;
zw_b1 <= d_i;
end
end
s273:
G10_e2:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & reg_F[3] == 1'b 0)
begin
sig_PC <= {d_i, zw_b1};
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU[8];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
zw_b2 <= d_i;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s304:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & reg_F[3] == 1'b 1 )
begin
sig_PC <= {zw_b2, adr_pc_i[7:0]};
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 11;
zw_b1 <= d_i;
end
end
s307:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU4[4];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
910,124 → 887,91
reg_sel_sp_as <= 1'b 1;
end
end
s177:
G10_e3:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 85 |
zw_REG_OP == 8'h 86 | zw_REG_OP == 8'h 84))
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, d_i};
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 95 |
zw_REG_OP == 8'h 94) )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 8D |
zw_REG_OP == 8'h 8E | zw_REG_OP == 8'h 8C) )
begin
sig_PC <= adr_nxt_pc_i;
sig_PC <= {8'h 00, d_alu_i};
zw_b1 <= d_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 9D )
end
G11_1:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 1E |
zw_REG_OP == 8'h 7E | zw_REG_OP == 8'h 3E |
zw_REG_OP == 8'h 5E))
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 99 )
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 06 |
zw_REG_OP == 8'h 66 | zw_REG_OP == 8'h 26 |
zw_REG_OP == 8'h 46) )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 91 )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 81 )
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 16 |
zw_REG_OP == 8'h 76 | zw_REG_OP == 8'h 36 |
zw_REG_OP == 8'h 56) )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 96 )
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 0E |
zw_REG_OP == 8'h 6E | zw_REG_OP == 8'h 2E |
zw_REG_OP == 8'h 4E) )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end
end
s180:
G11_2:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
end
end
s181:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, zw_b1};
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
end
s182:
G11_4:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 06 |
zw_REG_OP == 8'h 16 | zw_REG_OP == 8'h 0E |
zw_REG_OP == 8'h 1E))
begin
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
zw_b1 <= {d_i[6:0], 1'b 0};
zw_b2[0] <= d_i[7];
end
end
s183:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 46 |
zw_REG_OP == 8'h 56 | zw_REG_OP == 8'h 4E |
zw_REG_OP == 8'h 5E) )
begin
sig_PC <= {d_i, zw_b1};
zw_b1 <= {1'b 0, d_i[7:1]};
zw_b2[0] <= d_i[0];
end
end
s184:
begin
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
s185:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 26 |
zw_REG_OP == 8'h 36 | zw_REG_OP == 8'h 2E |
zw_REG_OP == 8'h 3E) )
begin
sig_PC <= {8'h 00, zw_b1};
zw_b1 <= {d_i[6:0], reg_F[0]};
zw_b2[0] <= d_i[7];
end
end
s186:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 66 |
zw_REG_OP == 8'h 76 | zw_REG_OP == 8'h 6E |
zw_REG_OP == 8'h 7E) )
begin
sig_PC <= {8'h 00, zw_b1};
zw_b1 <= {reg_F[0], d_i[7:1]};
zw_b2[0] <= d_i[0];
end
end
s187:
G11_5:
begin
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
s188:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, d_alu_i};
zw_b1 <= d_i;
sig_PC <= {d_i, zw_b1};
end
end
s189:
G11_6:
begin
if (rdy_i == 1'b 1)
begin
1035,39 → 979,18
zw_b3 <= d_alu_i;
end
end
s190:
G11_7:
begin
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
s191:
begin
sig_PC <= {zw_b3, zw_b1};
end
s192:
begin
sig_PC <= {d_i, zw_b1};
end
s193:
begin
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
s377:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
sig_PC <= {zw_b3, zw_b1};
end
end
s381:
G11_e:
begin
reg_F[0] <= zw_b2[0];
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
1074,97 → 997,52
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
s378:
G12_1:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & (reg_F[0] == 1'b 1 &
zw_REG_OP == 8'h 90 | reg_F[0] == 1'b 0 &
zw_REG_OP == 8'h B0 | reg_F[1] == 1'b 0 &
zw_REG_OP == 8'h F0 | reg_F[7] == 1'b 0 &
zw_REG_OP == 8'h 30 | reg_F[1] == 1'b 1 &
zw_REG_OP == 8'h D0 | reg_F[7] == 1'b 1 &
zw_REG_OP == 8'h 10 | reg_F[6] == 1'b 1 &
zw_REG_OP == 8'h 50 | reg_F[6] == 1'b 0 &
zw_REG_OP == 8'h 70))
begin
sig_PC <= adr_sp_i;
end
end
s382:
begin
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
s383:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
end
end
s384:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s385:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 )
begin
sig_PC <= adr_sp_i;
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 10;
zw_b2 <= d_i;
end
end
s386:
G12_e1:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & zw_b3 == adr_nxt_pc_i[15:8])
begin
sig_PC <= adr_pc_i;
reg_F <= d_i;
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s387:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 )
begin
sig_PC <= adr_sp_i;
sig_PC <= {zw_b3, adr_nxt_pc_i[7:0]};
end
end
s388:
G12_e2:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
end
end
s389:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
reg_F <= d_i;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 11;
end
end
s391:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
end
end
s392:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
1171,31 → 1049,19
reg_sel_sp_as <= 1'b 1;
end
end
s390:
G13_1:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 24)
begin
sig_PC <= adr_sp_i;
sig_PC <= {8'h 00, d_i};
end
end
s393:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 2C )
begin
sig_PC <= adr_sp_i;
end
end
s394:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 00;
end
end
s395:
G13_2:
begin
if (rdy_i == 1'b 1)
begin
1202,11 → 1068,14
sig_PC <= {d_i, zw_b1};
end
end
s396:
G13_e:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[7] <= d_i[7];
reg_F[6] <= d_i[6];
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
1213,176 → 1082,81
reg_sel_sp_as <= 1'b 1;
end
end
s397:
G14_1:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h C6 |
zw_REG_OP == 8'h E6))
begin
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
sig_PC <= {8'h 00, d_i};
end
end
s399:
begin
sig_PC <= adr_sp_i;
end
s400:
begin
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 11;
end
s401:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h D6 |
zw_REG_OP == 8'h F6) )
begin
sig_PC <= {d_i, zw_b1[7:0]};
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
end
s526:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h CE |
zw_REG_OP == 8'h EE) )
begin
sig_PC <= adr_sp_i;
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end
end
s527:
begin
sig_PC <= adr_sp_i;
end
s528:
begin
sig_PC <= adr_sp_i;
end
s529:
begin
sig_PC <= 16'h FFFE;
end
s530:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h DE |
zw_REG_OP == 8'h FE) )
begin
sig_PC <= {d_i, zw_b1};
reg_F[2] <= 1'b 1;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
end
s531:
G14_2:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= 16'h FFFF;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 11;
zw_b1 <= d_i;
sig_PC <= {8'h 00, zw_b1};
end
end
s544:
G14_3:
begin
sig_PC <= adr_sp_i;
end
s545:
begin
sig_PC <= adr_sp_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
end
s546:
begin
sig_PC <= adr_pc_i;
end
s547:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
zw_b1 <= d_i;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 11;
zw_b1 <= d_alu_i;
end
end
s549:
G14_5:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s550:
G14_6:
begin
sig_PC <= adr_sp_i;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 00;
end
s404:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[0] <= q_a_i[7];
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
end
end
s556:
G14_7:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[0] <= q_a_i[0];
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
sig_PC <= {zw_b3, zw_b1};
end
end
s557:
G14_e:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[0] <= q_a_i[7];
reg_F[0] <= q_a_i[7];
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
s579:
G15_1:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[0] <= q_a_i[0];
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s201:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A5 |
zw_REG_OP == 8'h A6 | zw_REG_OP == 8'h A4 |
zw_REG_OP == 8'h 45 | zw_REG_OP == 8'h 05 |
1537,22 → 1311,21
zw_b1 <= d_alu_i;
end
end
s202:
G15_2:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
sig_PC <= {8'h 00, zw_b1};
end
end
s210:
G15_3:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
end
end
s211:
G15_4:
begin
if (rdy_i == 1'b 1)
begin
1560,7 → 1333,7
zw_b3 <= d_alu_i;
end
end
s215:
G15_5:
begin
if (rdy_i == 1'b 1)
begin
1569,14 → 1342,15
zw_b2[0] <= reg_0flag_i;
end
end
s217:
G15_6:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, zw_b1};
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
end
end
s218:
G15_7:
begin
if (rdy_i == 1'b 1)
begin
1583,30 → 1357,14
sig_PC <= {8'h 00, zw_b1};
end
end
s222:
G15_e1:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 09 | zw_REG_OP == 8'h 05 |
zw_REG_OP == 8'h 15 | zw_REG_OP == 8'h 0D |
zw_REG_OP == 8'h 1D | zw_REG_OP == 8'h 19 |
zw_REG_OP == 8'h 01 | zw_REG_OP == 8'h 11))
begin
sig_PC <= {8'h 00, d_alu_i};
zw_b1 <= d_i;
end
end
s223:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
end
end
s224:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 09 |
zw_REG_OP == 8'h 05 | zw_REG_OP == 8'h 15 |
zw_REG_OP == 8'h 0D | zw_REG_OP == 8'h 1D |
zw_REG_OP == 8'h 19 | zw_REG_OP == 8'h 01 |
zw_REG_OP == 8'h 11))
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
1615,11 → 1373,11
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 49 |
zw_REG_OP == 8'h 45 | zw_REG_OP == 8'h 55 |
zw_REG_OP == 8'h 4D | zw_REG_OP == 8'h 5D |
zw_REG_OP == 8'h 59 | zw_REG_OP == 8'h 41 |
zw_REG_OP == 8'h 51) )
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 45 |
zw_REG_OP == 8'h 55 | zw_REG_OP == 8'h 4D |
zw_REG_OP == 8'h 5D | zw_REG_OP == 8'h 59 |
zw_REG_OP == 8'h 41 | zw_REG_OP == 8'h 51) )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
1629,11 → 1387,11
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 29 |
zw_REG_OP == 8'h 25 | zw_REG_OP == 8'h 35 |
zw_REG_OP == 8'h 2D | zw_REG_OP == 8'h 3D |
zw_REG_OP == 8'h 39 | zw_REG_OP == 8'h 21 |
zw_REG_OP == 8'h 31) )
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h 25 |
zw_REG_OP == 8'h 35 | zw_REG_OP == 8'h 2D |
zw_REG_OP == 8'h 3D | zw_REG_OP == 8'h 39 |
zw_REG_OP == 8'h 21 | zw_REG_OP == 8'h 31) )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
1643,14 → 1401,14
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h C9 |
zw_REG_OP == 8'h C5 | zw_REG_OP == 8'h D5 |
zw_REG_OP == 8'h CD | zw_REG_OP == 8'h DD |
zw_REG_OP == 8'h D9 | zw_REG_OP == 8'h C1 |
zw_REG_OP == 8'h D1 | zw_REG_OP == 8'h C0 |
zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C4 |
zw_REG_OP == 8'h E4 | zw_REG_OP == 8'h CC |
zw_REG_OP == 8'h EC) )
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h C9 | zw_REG_OP == 8'h C5 |
zw_REG_OP == 8'h D5 | zw_REG_OP == 8'h CD |
zw_REG_OP == 8'h DD | zw_REG_OP == 8'h D9 |
zw_REG_OP == 8'h C1 | zw_REG_OP == 8'h D1 |
zw_REG_OP == 8'h C0 | zw_REG_OP == 8'h E0 |
zw_REG_OP == 8'h C4 | zw_REG_OP == 8'h E4 |
zw_REG_OP == 8'h CC | zw_REG_OP == 8'h EC) )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
1662,7 → 1420,7
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 )
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
1672,14 → 1430,18
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 )
begin
sig_PC <= {zw_b3, zw_b1};
end
end
s225:
G15_e2:
begin
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 09 | zw_REG_OP == 8'h 05 |
zw_REG_OP == 8'h 15 | zw_REG_OP == 8'h 0D |
zw_REG_OP == 8'h 1D | zw_REG_OP == 8'h 19 |
zw_REG_OP == 8'h 01 | zw_REG_OP == 8'h 11))
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 09 |
zw_REG_OP == 8'h 05 | zw_REG_OP == 8'h 15 |
zw_REG_OP == 8'h 0D | zw_REG_OP == 8'h 1D |
zw_REG_OP == 8'h 19 | zw_REG_OP == 8'h 01 |
zw_REG_OP == 8'h 11))
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
1689,11 → 1451,11
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 45 |
zw_REG_OP == 8'h 55 | zw_REG_OP == 8'h 4D |
zw_REG_OP == 8'h 5D | zw_REG_OP == 8'h 59 |
zw_REG_OP == 8'h 41 | zw_REG_OP == 8'h 51) )
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 49 |
zw_REG_OP == 8'h 45 | zw_REG_OP == 8'h 55 |
zw_REG_OP == 8'h 4D | zw_REG_OP == 8'h 5D |
zw_REG_OP == 8'h 59 | zw_REG_OP == 8'h 41 |
zw_REG_OP == 8'h 51) )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
1703,11 → 1465,11
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h 25 |
zw_REG_OP == 8'h 35 | zw_REG_OP == 8'h 2D |
zw_REG_OP == 8'h 3D | zw_REG_OP == 8'h 39 |
zw_REG_OP == 8'h 21 | zw_REG_OP == 8'h 31) )
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 29 |
zw_REG_OP == 8'h 25 | zw_REG_OP == 8'h 35 |
zw_REG_OP == 8'h 2D | zw_REG_OP == 8'h 3D |
zw_REG_OP == 8'h 39 | zw_REG_OP == 8'h 21 |
zw_REG_OP == 8'h 31) )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
1717,14 → 1479,14
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h C9 | zw_REG_OP == 8'h C5 |
zw_REG_OP == 8'h D5 | zw_REG_OP == 8'h CD |
zw_REG_OP == 8'h DD | zw_REG_OP == 8'h D9 |
zw_REG_OP == 8'h C1 | zw_REG_OP == 8'h D1 |
zw_REG_OP == 8'h C0 | zw_REG_OP == 8'h E0 |
zw_REG_OP == 8'h C4 | zw_REG_OP == 8'h E4 |
zw_REG_OP == 8'h CC | zw_REG_OP == 8'h EC) )
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h C9 |
zw_REG_OP == 8'h C5 | zw_REG_OP == 8'h D5 |
zw_REG_OP == 8'h CD | zw_REG_OP == 8'h DD |
zw_REG_OP == 8'h D9 | zw_REG_OP == 8'h C1 |
zw_REG_OP == 8'h D1 | zw_REG_OP == 8'h C0 |
zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C4 |
zw_REG_OP == 8'h E4 | zw_REG_OP == 8'h CC |
zw_REG_OP == 8'h EC) )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
1736,7 → 1498,7
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 )
else if (rdy_i == 1'b 1 )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
1746,104 → 1508,76
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 )
end
G15_e3:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {zw_b3, zw_b1};
sig_PC <= {8'h 00, d_alu_i};
zw_b1 <= d_i;
end
end
s226:
G16_1:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h C6 |
zw_REG_OP == 8'h E6))
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E5)
begin
sig_PC <= {8'h 00, d_i};
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h D6 |
zw_REG_OP == 8'h F6) )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E9 &
reg_F[3] == 1'b 0 )
begin
sig_PC <= adr_nxt_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU[8];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F5 )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h CE |
zw_REG_OP == 8'h EE) )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h ED )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h DE |
zw_REG_OP == 8'h FE) )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h FD )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
end
s243:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F9 )
begin
sig_PC <= {d_i, zw_b1};
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
end
s244:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F1 )
begin
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
end
end
s247:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, zw_b1};
end
end
s344:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {zw_b3, zw_b1};
end
end
s343:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
end
s251:
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
s351:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 24)
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E1 )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 2C )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E9 &
reg_F[3] == 1'b 1 )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end
end
s361:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[7] <= d_i[7];
reg_F[6] <= d_i[6];
reg_F[1] <= reg_1flag_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU2[4];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
1850,52 → 1584,21
reg_sel_sp_as <= 1'b 1;
end
end
s360:
G16_2:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
sig_PC <= {8'h 00, zw_b1};
end
end
s403:
G16_3:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 1E |
zw_REG_OP == 8'h 7E | zw_REG_OP == 8'h 3E |
zw_REG_OP == 8'h 5E))
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 06 |
zw_REG_OP == 8'h 66 | zw_REG_OP == 8'h 26 |
zw_REG_OP == 8'h 46) )
begin
sig_PC <= {8'h 00, d_i};
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 16 |
zw_REG_OP == 8'h 76 | zw_REG_OP == 8'h 36 |
zw_REG_OP == 8'h 56) )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 0E |
zw_REG_OP == 8'h 6E | zw_REG_OP == 8'h 2E |
zw_REG_OP == 8'h 4E) )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end
end
s406:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
end
end
s407:
G16_4:
begin
if (rdy_i == 1'b 1)
begin
1903,137 → 1606,168
zw_b3 <= d_alu_i;
end
end
s409:
G16_5:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, zw_b1};
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
end
s412:
G16_6:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {zw_b3, zw_b1};
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
end
end
s416:
G16_7:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 06 |
zw_REG_OP == 8'h 16 | zw_REG_OP == 8'h 0E |
zw_REG_OP == 8'h 1E))
if (rdy_i == 1'b 1)
begin
zw_b1 <= {d_i[6:0], 1'b 0};
zw_b2[0] <= d_i[7];
sig_PC <= {8'h 00, zw_b1};
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 46 |
zw_REG_OP == 8'h 56 | zw_REG_OP == 8'h 4E |
zw_REG_OP == 8'h 5E) )
end
G16_e1:
begin
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 0)
begin
zw_b1 <= {1'b 0, d_i[7:1]};
zw_b2[0] <= d_i[0];
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU[8];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 26 |
zw_REG_OP == 8'h 36 | zw_REG_OP == 8'h 2E |
zw_REG_OP == 8'h 3E) )
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 1 )
begin
zw_b1 <= {d_i[6:0], reg_F[0]};
zw_b2[0] <= d_i[7];
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU2[4];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 66 |
zw_REG_OP == 8'h 76 | zw_REG_OP == 8'h 6E |
zw_REG_OP == 8'h 7E) )
else if (rdy_i == 1'b 1 )
begin
zw_b1 <= {reg_F[0], d_i[7:1]};
zw_b2[0] <= d_i[0];
sig_PC <= {zw_b3, zw_b1};
end
end
s418:
G16_e2:
begin
sig_PC <= adr_pc_i;
reg_F[0] <= zw_b2[0];
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
s510:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 65)
if (rdy_i == 1'b 1 & reg_F[3] == 1'b 0)
begin
sig_PC <= {8'h 00, d_i};
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU[8];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 69 &
reg_F[3] == 1'b 0 )
else if (rdy_i == 1'b 1 & reg_F[3] == 1'b 1 )
begin
sig_PC <= adr_nxt_pc_i;
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU[8];
reg_F[0] <= zw_ALU2[4];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 75 )
end
G16_e3:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, d_alu_i};
zw_b1 <= d_i;
end
end
G17_1:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 85 |
zw_REG_OP == 8'h 86 | zw_REG_OP == 8'h 84))
begin
sig_PC <= {8'h 00, d_i};
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 95 |
zw_REG_OP == 8'h 94) )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 6D )
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 8D |
zw_REG_OP == 8'h 8E | zw_REG_OP == 8'h 8C) )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 7D )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 9D )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 79 )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 99 )
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 71 )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 91 )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 61 )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 81 )
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 69 &
reg_F[3] == 1'b 1 )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 96 )
begin
sig_PC <= adr_nxt_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU4[4];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
end
end
s553:
G17_10:
begin
sig_PC <= {d_i, zw_b1};
end
G17_2:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, zw_b1};
end
end
G17_3:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
end
end
s555:
G17_4:
begin
if (rdy_i == 1'b 1)
begin
2041,8 → 1775,12
zw_b3 <= d_alu_i;
end
end
s558:
G17_5:
begin
sig_PC <= {zw_b3, zw_b1};
end
G17_6:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, zw_b1};
2050,14 → 1788,15
zw_b2[0] <= reg_0flag_i;
end
end
s560:
G17_7:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, zw_b1};
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
end
end
s561:
G17_8:
begin
if (rdy_i == 1'b 1)
begin
2064,7 → 1803,7
sig_PC <= {8'h 00, zw_b1};
end
end
s563:
G17_9:
begin
if (rdy_i == 1'b 1)
begin
2072,64 → 1811,73
zw_b1 <= d_i;
end
end
s564:
G17_e:
begin
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 0)
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
G18_1:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU[8];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
sig_PC <= adr_sp_i;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 1 )
end
G18_2:
begin
sig_PC <= adr_sp_i;
end
G18_3:
begin
sig_PC <= adr_sp_i;
end
G18_4:
begin
sig_PC <= 16'h FFFE;
end
G18_5:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU4[4];
sig_PC <= 16'h FFFF;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 11;
zw_b1 <= d_i;
end
end
G18_e:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
reg_F[2] <= 1'b 1;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 )
begin
sig_PC <= {zw_b3, zw_b1};
end
end
s565:
G19_1:
begin
if (rdy_i == 1'b 1 & reg_F[3] == 1'b 0)
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU[8];
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & reg_F[3] == 1'b 1 )
end
G1_1:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU4[4];
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
2136,60 → 1884,77
reg_sel_sp_as <= 1'b 1;
end
end
s566:
G20_1:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 4C)
begin
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 11;
zw_b1 <= d_i;
end
end
s266:
begin
if (rdy_i == 1'b 1 & (reg_F[0] == 1'b 1 &
zw_REG_OP == 8'h 90 | reg_F[0] == 1'b 0 &
zw_REG_OP == 8'h B0 | reg_F[1] == 1'b 0 &
zw_REG_OP == 8'h F0 | reg_F[7] == 1'b 0 &
zw_REG_OP == 8'h 30 | reg_F[1] == 1'b 1 &
zw_REG_OP == 8'h D0 | reg_F[7] == 1'b 1 &
zw_REG_OP == 8'h 10 | reg_F[6] == 1'b 1 &
zw_REG_OP == 8'h 50 | reg_F[6] == 1'b 0 &
zw_REG_OP == 8'h 70))
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 6C )
begin
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
zw_b1 <= d_i;
end
else if (rdy_i == 1'b 1 )
end
G20_2:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_nxt_pc_i;
sig_PC <= {d_i, zw_b1};
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 10;
reg_sel_pc_val <= 2'b 00;
zw_b2 <= d_i;
end
end
s301:
G20_3:
begin
if (rdy_i == 1'b 1 & zw_b3 == adr_nxt_pc_i[15:8])
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_nxt_pc_i;
sig_PC <= {zw_b2, adr_pc_i[7:0]};
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 11;
zw_b1 <= d_i;
end
end
G20_e:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 )
end
G21_1:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {zw_b3, adr_nxt_pc_i[7:0]};
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
end
end
s302:
G21_3:
begin
sig_PC <= adr_sp_i;
end
G21_4:
begin
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 11;
end
G21_e:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
sig_PC <= {d_i, zw_b1[7:0]};
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
2196,77 → 1961,112
reg_sel_sp_as <= 1'b 1;
end
end
RES:
G22_1:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
end
end
G22_e:
begin
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
sig_PC <= adr_nxt_pc_i;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
G23_1:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
end
end
G23_e:
begin
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
s511:
G24_2:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E5)
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, d_i};
sig_PC <= adr_sp_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E9 &
reg_F[3] == 1'b 0 )
end
G24_e:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_nxt_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU[8];
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F5 )
end
G25_2:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
sig_PC <= adr_sp_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h ED )
end
G25_e:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
sig_PC <= adr_pc_i;
reg_F <= d_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h FD )
end
G26_1:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
sig_PC <= adr_sp_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F9 )
end
G26_2:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
sig_PC <= adr_sp_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F1 )
end
G26_3:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
sig_PC <= adr_sp_i;
reg_F <= d_i;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 11;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E1 )
end
G26_4:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, d_i};
zw_b1 <= d_alu_i;
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E9 &
reg_F[3] == 1'b 1 )
end
G26_e:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_nxt_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU2[4];
sig_PC <= {d_i, zw_b1};
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
2273,126 → 2073,188
reg_sel_sp_as <= 1'b 1;
end
end
s559:
G27_1:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
sig_PC <= adr_sp_i;
end
end
s562:
G27_2:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
sig_PC <= adr_sp_i;
end
end
s567:
G27_3:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 00;
end
end
G27_4:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
end
end
s568:
G27_e:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, zw_b1};
zw_b1 <= d_alu_i;
zw_b2[0] <= reg_0flag_i;
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s569:
G28_1:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, zw_b1};
sig_PC <= adr_sp_i;
end
end
s570:
G28_2:
begin
sig_PC <= adr_sp_i;
end
G28_3:
begin
sig_PC <= adr_sp_i;
end
G28_4:
begin
sig_PC <= 16'h FFFE;
end
G28_5:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, zw_b1};
sig_PC <= 16'h FFFF;
zw_b1 <= d_i;
end
end
s571:
G28_e:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
zw_b3 <= d_alu_i;
reg_F[2] <= 1'b 1;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s572:
G29_1:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {8'h 00, d_alu_i};
sig_PC <= adr_sp_i;
end
end
G29_2:
begin
sig_PC <= adr_sp_i;
end
G29_3:
begin
sig_PC <= adr_sp_i;
end
G29_4:
begin
sig_PC <= 16'h FFFA;
end
G29_5:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= 16'h FFFB;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 11;
zw_b1 <= d_i;
end
end
s573:
G29_e:
begin
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 0)
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU[8];
sig_PC <= {d_i, zw_b1};
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 1 )
end
G2_1:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU2[4];
reg_F[0] <= 1'b 1;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 )
end
G30_1:
begin
sig_PC <= adr_sp_i;
end
G30_2:
begin
sig_PC <= adr_sp_i;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 00;
end
G30_3:
begin
sig_PC <= adr_sp_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
end
G30_4:
begin
sig_PC <= adr_pc_i;
end
G30_5:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= {zw_b3, zw_b1};
sig_PC <= adr_pc_i;
zw_b1 <= d_i;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 11;
end
end
s574:
G30_e:
begin
if (rdy_i == 1'b 1 & reg_F[3] == 1'b 0)
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU[8];
sig_PC <= {d_i, zw_b1};
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & reg_F[3] == 1'b 1 )
end
G31_1:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[7] <= zw_ALU[7];
reg_F[6] <= zw_b1[0] ^ zw_ALU[7];
reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] |
zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]);
reg_F[0] <= zw_ALU2[4];
reg_F[0] <= q_a_i[7];
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
2399,38 → 2261,67
reg_sel_sp_as <= 1'b 1;
end
end
s548:
G32_1:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
sig_PC <= adr_pc_i;
reg_F[0] <= q_a_i[0];
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s551:
G33_1:
begin
sig_PC <= adr_sp_i;
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[0] <= q_a_i[7];
reg_F[0] <= q_a_i[7];
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s552:
G34_1:
begin
sig_PC <= adr_sp_i;
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[0] <= q_a_i[0];
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s575:
G3_1:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= 16'h FFFF;
zw_b1 <= d_i;
sig_PC <= adr_pc_i;
reg_F[3] <= 1'b 1;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s576:
G4_1:
begin
sig_PC <= 16'h FFFE;
end
s577:
begin
sig_PC <= adr_pc_i;
if (rdy_i == 1'b 1)
begin
sig_PC <= {d_i, zw_b1};
sig_PC <= adr_pc_i;
reg_F[2] <= 1'b 1;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
2438,46 → 2329,95
reg_sel_sp_as <= 1'b 1;
end
end
s532:
G5_1:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_sp_i;
sig_PC <= adr_pc_i;
reg_F[0] <= 1'b 0;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s533:
G6_1:
begin
sig_PC <= adr_sp_i;
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[3] <= 1'b 0;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s534:
G7_1:
begin
sig_PC <= adr_sp_i;
if (rdy_i == 1'b 1)
begin
sig_PC <= adr_pc_i;
reg_F[2] <= 1'b 0;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s535:
G8_1:
begin
if (rdy_i == 1'b 1)
begin
sig_PC <= 16'h FFFB;
reg_sel_pc_in <= 1'b 1;
reg_sel_pc_val <= 2'b 11;
zw_b1 <= d_i;
sig_PC <= adr_pc_i;
reg_F[6] <= 1'b 0;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
s536:
G9_1:
begin
sig_PC <= 16'h FFFA;
end
s537:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 9A)
begin
sig_PC <= {d_i, zw_b1};
sig_PC <= adr_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h BA )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
else if (rdy_i == 1'b 1 )
begin
sig_PC <= adr_pc_i;
reg_F[7] <= reg_7flag_i;
reg_F[1] <= reg_1flag_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
end
RES:
begin
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= 1'b 0;
reg_sel_pc_val <= 2'b 00;
reg_sel_sp_in <= 1'b 0;
reg_sel_sp_as <= 1'b 1;
end
default:
;
endcase
2496,12 → 2436,12
begin
if (nmi_i == 1'b 1 & rdy_i == 1'b 1)
begin
next_state <= s532;
next_state <= G29_1;
end
else if (irq_n_i == 1'b 0 & reg_F[2] == 1'b 0 &
rdy_i == 1'b 1 )
begin
next_state <= s548;
next_state <= G28_1;
end
else if ((d_i == 8'h 69 | d_i == 8'h 65 |
d_i == 8'h 75 | d_i == 8'h 6D |
2509,13 → 2449,13
d_i == 8'h 61 | d_i == 8'h 71) &
rdy_i == 1'b 1 )
begin
next_state <= s510;
next_state <= G10_1;
end
else if ((d_i == 8'h 06 | d_i == 8'h 16 |
d_i == 8'h 0E | d_i == 8'h 1E) &
rdy_i == 1'b 1 )
begin
next_state <= s403;
next_state <= G11_1;
end
else if ((d_i == 8'h 90 | d_i == 8'h B0 |
d_i == 8'h F0 | d_i == 8'h 30 |
2523,56 → 2463,56
d_i == 8'h 50 | d_i == 8'h 70) &
rdy_i == 1'b 1 )
begin
next_state <= s266;
next_state <= G12_1;
end
else if ((d_i == 8'h 24 | d_i == 8'h 2C) &
rdy_i == 1'b 1 )
begin
next_state <= s351;
next_state <= G13_1;
end
else if (d_i == 8'h 00 & rdy_i == 1'b 1 )
begin
next_state <= s526;
next_state <= G18_1;
end
else if (d_i == 8'h 18 & rdy_i == 1'b 1 )
begin
next_state <= s12;
next_state <= G5_1;
end
else if (d_i == 8'h D8 & rdy_i == 1'b 1 )
begin
next_state <= s16;
next_state <= G6_1;
end
else if (d_i == 8'h 58 & rdy_i == 1'b 1 )
begin
next_state <= s17;
next_state <= G7_1;
end
else if (d_i == 8'h B8 & rdy_i == 1'b 1 )
begin
next_state <= s24;
next_state <= G8_1;
end
else if ((d_i == 8'h E0 | d_i == 8'h E4 |
d_i == 8'h EC) & rdy_i == 1'b 1 )
begin
next_state <= s201;
next_state <= G15_1;
end
else if ((d_i == 8'h C0 | d_i == 8'h C4 |
d_i == 8'h CC) & rdy_i == 1'b 1 )
begin
next_state <= s201;
next_state <= G15_1;
end
else if ((d_i == 8'h C6 | d_i == 8'h D6 |
d_i == 8'h CE | d_i == 8'h DE) &
rdy_i == 1'b 1 )
begin
next_state <= s226;
next_state <= G14_1;
end
else if (d_i == 8'h CA & rdy_i == 1'b 1 )
begin
next_state <= s25;
next_state <= G19_1;
end
else if (d_i == 8'h 88 & rdy_i == 1'b 1 )
begin
next_state <= s25;
next_state <= G19_1;
end
else if ((d_i == 8'h 49 | d_i == 8'h 45 |
d_i == 8'h 55 | d_i == 8'h 4D |
2592,30 → 2532,30
d_i == 8'h C1 | d_i == 8'h D1) &
rdy_i == 1'b 1 )
begin
next_state <= s201;
next_state <= G15_1;
end
else if ((d_i == 8'h E6 | d_i == 8'h F6 |
d_i == 8'h EE | d_i == 8'h FE) &
rdy_i == 1'b 1 )
begin
next_state <= s226;
next_state <= G14_1;
end
else if (d_i == 8'h E8 & rdy_i == 1'b 1 )
begin
next_state <= s25;
next_state <= G19_1;
end
else if (d_i == 8'h C8 & rdy_i == 1'b 1 )
begin
next_state <= s25;
next_state <= G19_1;
end
else if ((d_i == 8'h 4C | d_i == 8'h 6C) &
rdy_i == 1'b 1 )
begin
next_state <= s271;
next_state <= G20_1;
end
else if (d_i == 8'h 20 & rdy_i == 1'b 1 )
begin
next_state <= s397;
next_state <= G21_1;
end
else if ((d_i == 8'h A9 | d_i == 8'h A5 |
d_i == 8'h B5 | d_i == 8'h AD |
2623,65 → 2563,65
d_i == 8'h A1 | d_i == 8'h B1) &
rdy_i == 1'b 1 )
begin
next_state <= s201;
next_state <= G15_1;
end
else if ((d_i == 8'h A2 | d_i == 8'h A6 |
d_i == 8'h B6 | d_i == 8'h AE |
d_i == 8'h BE) & rdy_i == 1'b 1 )
begin
next_state <= s201;
next_state <= G15_1;
end
else if ((d_i == 8'h A0 | d_i == 8'h A4 |
d_i == 8'h B4 | d_i == 8'h AC |
d_i == 8'h BC) & rdy_i == 1'b 1 )
begin
next_state <= s201;
next_state <= G15_1;
end
else if ((d_i == 8'h 46 | d_i == 8'h 56 |
d_i == 8'h 4E | d_i == 8'h 5E) &
rdy_i == 1'b 1 )
begin
next_state <= s403;
next_state <= G11_1;
end
else if (d_i == 8'h EA & rdy_i == 1'b 1 )
begin
next_state <= s1;
next_state <= G1_1;
end
else if (d_i == 8'h 48 & rdy_i == 1'b 1 )
begin
next_state <= s377;
next_state <= G22_1;
end
else if (d_i == 8'h 08 & rdy_i == 1'b 1 )
begin
next_state <= s378;
next_state <= G23_1;
end
else if (d_i == 8'h 68 & rdy_i == 1'b 1 )
begin
next_state <= s379;
next_state <= G24_1;
end
else if (d_i == 8'h 28 & rdy_i == 1'b 1 )
begin
next_state <= s380;
next_state <= G25_1;
end
else if ((d_i == 8'h 26 | d_i == 8'h 36 |
d_i == 8'h 2E | d_i == 8'h 3E) &
rdy_i == 1'b 1 )
begin
next_state <= s403;
next_state <= G11_1;
end
else if ((d_i == 8'h 66 | d_i == 8'h 76 |
d_i == 8'h 6E | d_i == 8'h 7E) &
rdy_i == 1'b 1 )
begin
next_state <= s403;
next_state <= G11_1;
end
else if (d_i == 8'h 40 & rdy_i == 1'b 1 )
begin
next_state <= s387;
next_state <= G26_1;
end
else if (d_i == 8'h 60 & rdy_i == 1'b 1 )
begin
next_state <= s390;
next_state <= G27_1;
end
else if ((d_i == 8'h E9 | d_i == 8'h E5 |
d_i == 8'h F5 | d_i == 8'h ED |
2689,19 → 2629,19
d_i == 8'h E1 | d_i == 8'h F1) &
rdy_i == 1'b 1 )
begin
next_state <= s511;
next_state <= G16_1;
end
else if (d_i == 8'h 38 & rdy_i == 1'b 1 )
begin
next_state <= s2;
next_state <= G2_1;
end
else if (d_i == 8'h F8 & rdy_i == 1'b 1 )
begin
next_state <= s5;
next_state <= G3_1;
end
else if (d_i == 8'h 78 & rdy_i == 1'b 1 )
begin
next_state <= s3;
next_state <= G4_1;
end
else if ((d_i == 8'h 85 | d_i == 8'h 95 |
d_i == 8'h 8D | d_i == 8'h 9D |
2708,61 → 2648,61
d_i == 8'h 99 | d_i == 8'h 81 |
d_i == 8'h 91) & rdy_i == 1'b 1 )
begin
next_state <= s177;
next_state <= G17_1;
end
else if ((d_i == 8'h 86 | d_i == 8'h 96 |
d_i == 8'h 8E) & rdy_i == 1'b 1 )
begin
next_state <= s177;
next_state <= G17_1;
end
else if ((d_i == 8'h 84 | d_i == 8'h 94 |
d_i == 8'h 8C) & rdy_i == 1'b 1 )
begin
next_state <= s177;
next_state <= G17_1;
end
else if (d_i == 8'h AA & rdy_i == 1'b 1 )
begin
next_state <= s4;
next_state <= G9_1;
end
else if (d_i == 8'h 0A & rdy_i == 1'b 1 )
begin
next_state <= s404;
next_state <= G31_1;
end
else if (d_i == 8'h 4A & rdy_i == 1'b 1 )
begin
next_state <= s556;
next_state <= G32_1;
end
else if (d_i == 8'h 2A & rdy_i == 1'b 1 )
begin
next_state <= s557;
next_state <= G33_1;
end
else if (d_i == 8'h 6A & rdy_i == 1'b 1 )
begin
next_state <= s579;
next_state <= G34_1;
end
else if (d_i == 8'h A8 & rdy_i == 1'b 1 )
begin
next_state <= s4;
next_state <= G9_1;
end
else if (d_i == 8'h 98 & rdy_i == 1'b 1 )
begin
next_state <= s4;
next_state <= G9_1;
end
else if (d_i == 8'h BA & rdy_i == 1'b 1 )
begin
next_state <= s4;
next_state <= G9_1;
end
else if (d_i == 8'h 8A & rdy_i == 1'b 1 )
begin
next_state <= s4;
next_state <= G9_1;
end
else if (d_i == 8'h 9A & rdy_i == 1'b 1 )
begin
next_state <= s4;
next_state <= G9_1;
end
else if (rdy_i == 1'b 1 )
begin
next_state <= s1;
next_state <= G1_1;
end
else
begin
2769,702 → 2709,470
next_state <= FETCH;
end
end
s1:
G10_1:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 65)
begin
next_state <= FETCH;
next_state <= G10_e2;
end
else
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 69 &
reg_F[3] == 1'b 0 )
begin
next_state <= s1;
end
end
s2:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 75 )
begin
next_state <= s2;
next_state <= G10_2;
end
end
s5:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 6D )
begin
next_state <= FETCH;
next_state <= G10_3;
end
else
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 7D )
begin
next_state <= s5;
next_state <= G10_4;
end
end
s3:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 79 )
begin
next_state <= FETCH;
next_state <= G10_4;
end
else
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 71 )
begin
next_state <= s3;
next_state <= G10_5;
end
end
s4:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 9A)
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 61 )
begin
next_state <= FETCH;
next_state <= G10_7;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h BA )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 69 &
reg_F[3] == 1'b 1 )
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 )
begin
next_state <= FETCH;
end
else
begin
next_state <= s4;
next_state <= G10_1;
end
end
s12:
G10_2:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
next_state <= G10_e2;
end
else
begin
next_state <= s12;
next_state <= G10_2;
end
end
s16:
G10_3:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
next_state <= G10_e2;
end
else
begin
next_state <= s16;
next_state <= G10_3;
end
end
s17:
G10_4:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
next_state <= G10_e1;
end
else
begin
next_state <= s17;
next_state <= G10_4;
end
end
s24:
G10_5:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
next_state <= G10_6;
end
else
begin
next_state <= s24;
next_state <= G10_5;
end
end
s25:
G10_6:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
next_state <= G10_e1;
end
else
begin
next_state <= s25;
next_state <= G10_6;
end
end
s271:
G10_7:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 4C)
begin
next_state <= s307;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 6C )
begin
next_state <= s273;
end
else
begin
next_state <= s271;
end
end
s273:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s304;
next_state <= G10_e3;
end
else
begin
next_state <= s273;
next_state <= G10_7;
end
end
s304:
G10_e1:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 0)
begin
next_state <= s307;
next_state <= FETCH;
end
else
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 1 )
begin
next_state <= s304;
end
end
s307:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
else if (rdy_i == 1'b 1 )
begin
next_state <= s307;
next_state <= G10_e2;
end
end
s177:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 85 |
zw_REG_OP == 8'h 86 | zw_REG_OP == 8'h 84))
begin
next_state <= s184;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 95 |
zw_REG_OP == 8'h 94) )
begin
next_state <= s185;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 8D |
zw_REG_OP == 8'h 8E | zw_REG_OP == 8'h 8C) )
begin
next_state <= s183;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 9D )
begin
next_state <= s182;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 99 )
begin
next_state <= s180;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 91 )
begin
next_state <= s181;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 81 )
begin
next_state <= s186;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 96 )
begin
next_state <= s185;
end
else
begin
next_state <= s177;
next_state <= G10_e1;
end
end
s180:
G10_e2:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & reg_F[3] == 1'b 0)
begin
next_state <= s191;
next_state <= FETCH;
end
else
else if (rdy_i == 1'b 1 & reg_F[3] == 1'b 1 )
begin
next_state <= s180;
next_state <= FETCH;
end
end
s181:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s189;
end
else
begin
next_state <= s181;
next_state <= G10_e2;
end
end
s182:
G10_e3:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s191;
next_state <= G10_3;
end
else
begin
next_state <= s182;
next_state <= G10_e3;
end
end
s183:
G11_1:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 1E |
zw_REG_OP == 8'h 7E | zw_REG_OP == 8'h 3E |
zw_REG_OP == 8'h 5E))
begin
next_state <= s187;
next_state <= G11_6;
end
else
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 06 |
zw_REG_OP == 8'h 66 | zw_REG_OP == 8'h 26 |
zw_REG_OP == 8'h 46) )
begin
next_state <= s183;
next_state <= G11_3;
end
end
s184:
begin
next_state <= FETCH;
end
s185:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 16 |
zw_REG_OP == 8'h 76 | zw_REG_OP == 8'h 36 |
zw_REG_OP == 8'h 56) )
begin
next_state <= s190;
next_state <= G11_2;
end
else
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 0E |
zw_REG_OP == 8'h 6E | zw_REG_OP == 8'h 2E |
zw_REG_OP == 8'h 4E) )
begin
next_state <= s185;
next_state <= G11_5;
end
end
s186:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s188;
end
else
begin
next_state <= s186;
next_state <= G11_1;
end
end
s187:
G11_2:
begin
next_state <= FETCH;
end
s188:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s192;
next_state <= G11_3;
end
else
begin
next_state <= s188;
next_state <= G11_2;
end
end
s189:
G11_3:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s191;
next_state <= G11_4;
end
else
begin
next_state <= s189;
next_state <= G11_3;
end
end
s190:
G11_4:
begin
next_state <= FETCH;
end
s191:
begin
next_state <= s193;
end
s192:
begin
next_state <= s193;
end
s193:
begin
next_state <= FETCH;
end
s377:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 06 |
zw_REG_OP == 8'h 16 | zw_REG_OP == 8'h 0E |
zw_REG_OP == 8'h 1E))
begin
next_state <= s381;
next_state <= G11_e;
end
else
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 46 |
zw_REG_OP == 8'h 56 | zw_REG_OP == 8'h 4E |
zw_REG_OP == 8'h 5E) )
begin
next_state <= s377;
next_state <= G11_e;
end
end
s381:
begin
next_state <= FETCH;
end
s378:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 26 |
zw_REG_OP == 8'h 36 | zw_REG_OP == 8'h 2E |
zw_REG_OP == 8'h 3E) )
begin
next_state <= s382;
next_state <= G11_e;
end
else
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 66 |
zw_REG_OP == 8'h 76 | zw_REG_OP == 8'h 6E |
zw_REG_OP == 8'h 7E) )
begin
next_state <= s378;
next_state <= G11_e;
end
end
s382:
begin
next_state <= FETCH;
end
s379:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s383;
end
else
begin
next_state <= s379;
next_state <= G11_4;
end
end
s383:
G11_5:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s384;
next_state <= G11_3;
end
else
begin
next_state <= s383;
next_state <= G11_5;
end
end
s384:
G11_6:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
next_state <= G11_7;
end
else
begin
next_state <= s384;
next_state <= G11_6;
end
end
s380:
G11_7:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s385;
next_state <= G11_3;
end
else
begin
next_state <= s380;
next_state <= G11_7;
end
end
s385:
G11_e:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s386;
end
else
begin
next_state <= s385;
end
next_state <= FETCH;
end
s386:
G12_1:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & (reg_F[0] == 1'b 1 &
zw_REG_OP == 8'h 90 | reg_F[0] == 1'b 0 &
zw_REG_OP == 8'h B0 | reg_F[1] == 1'b 0 &
zw_REG_OP == 8'h F0 | reg_F[7] == 1'b 0 &
zw_REG_OP == 8'h 30 | reg_F[1] == 1'b 1 &
zw_REG_OP == 8'h D0 | reg_F[7] == 1'b 1 &
zw_REG_OP == 8'h 10 | reg_F[6] == 1'b 1 &
zw_REG_OP == 8'h 50 | reg_F[6] == 1'b 0 &
zw_REG_OP == 8'h 70))
begin
next_state <= FETCH;
end
else
else if (rdy_i == 1'b 1 )
begin
next_state <= s386;
next_state <= G12_e1;
end
end
s387:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s388;
end
else
begin
next_state <= s387;
next_state <= G12_1;
end
end
s388:
G12_e1:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & zw_b3 == adr_nxt_pc_i[15:8])
begin
next_state <= s389;
next_state <= FETCH;
end
else
else if (rdy_i == 1'b 1 )
begin
next_state <= s388;
next_state <= G12_e2;
end
end
s389:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s391;
end
else
begin
next_state <= s389;
next_state <= G12_e1;
end
end
s391:
G12_e2:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s392;
end
else
begin
next_state <= s391;
end
end
s392:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s392;
next_state <= G12_e2;
end
end
s390:
G13_1:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 24)
begin
next_state <= s393;
next_state <= G13_e;
end
else
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 2C )
begin
next_state <= s390;
next_state <= G13_2;
end
end
s393:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s394;
end
else
begin
next_state <= s393;
next_state <= G13_1;
end
end
s394:
G13_2:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s395;
next_state <= G13_e;
end
else
begin
next_state <= s394;
next_state <= G13_2;
end
end
s395:
G13_e:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s396;
end
else
begin
next_state <= s395;
end
end
s396:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s396;
next_state <= G13_e;
end
end
s397:
G14_1:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h C6 |
zw_REG_OP == 8'h E6))
begin
next_state <= s398;
next_state <= G14_3;
end
else
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h D6 |
zw_REG_OP == 8'h F6) )
begin
next_state <= s397;
next_state <= G14_2;
end
end
s398:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h CE |
zw_REG_OP == 8'h EE) )
begin
next_state <= s399;
next_state <= G14_5;
end
else
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h DE |
zw_REG_OP == 8'h FE) )
begin
next_state <= s398;
next_state <= G14_6;
end
end
s399:
begin
next_state <= s400;
end
s400:
begin
next_state <= s401;
end
s401:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s401;
next_state <= G14_1;
end
end
s526:
G14_2:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s527;
next_state <= G14_3;
end
else
begin
next_state <= s526;
next_state <= G14_2;
end
end
s527:
G14_3:
begin
next_state <= s528;
end
s528:
begin
next_state <= s529;
end
s529:
begin
next_state <= s531;
end
s530:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
next_state <= G14_4;
end
else
begin
next_state <= s530;
next_state <= G14_3;
end
end
s531:
G14_4:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s530;
next_state <= G14_e;
end
else
begin
next_state <= s531;
next_state <= G14_4;
end
end
s544:
G14_5:
begin
next_state <= s550;
end
s545:
begin
next_state <= s546;
end
s546:
begin
next_state <= s547;
end
s547:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s549;
next_state <= G14_3;
end
else
begin
next_state <= s547;
next_state <= G14_5;
end
end
s549:
G14_6:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
next_state <= G14_7;
end
else
begin
next_state <= s549;
next_state <= G14_6;
end
end
s550:
G14_7:
begin
next_state <= s545;
end
s404:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
next_state <= G14_3;
end
else
begin
next_state <= s404;
next_state <= G14_7;
end
end
s556:
G14_e:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s556;
end
next_state <= FETCH;
end
s557:
G15_1:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s557;
end
end
s579:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s579;
end
end
s201:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A5 |
zw_REG_OP == 8'h A6 | zw_REG_OP == 8'h A4 |
zw_REG_OP == 8'h 45 | zw_REG_OP == 8'h 05 |
3471,7 → 3179,7
zw_REG_OP == 8'h 25 | zw_REG_OP == 8'h C5 |
zw_REG_OP == 8'h E4 | zw_REG_OP == 8'h C4))
begin
next_state <= s224;
next_state <= G15_e2;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 |
zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 |
3537,7 → 3245,7
zw_REG_OP == 8'h 15 | zw_REG_OP == 8'h 35 |
zw_REG_OP == 8'h D5) )
begin
next_state <= s217;
next_state <= G15_2;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h AD |
zw_REG_OP == 8'h AE | zw_REG_OP == 8'h AC |
3545,7 → 3253,7
zw_REG_OP == 8'h 2D | zw_REG_OP == 8'h CD |
zw_REG_OP == 8'h EC | zw_REG_OP == 8'h CC) )
begin
next_state <= s202;
next_state <= G15_3;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h BD |
zw_REG_OP == 8'h BC | zw_REG_OP == 8'h 5D |
3552,7 → 3260,7
zw_REG_OP == 8'h 1D | zw_REG_OP == 8'h 3D |
zw_REG_OP == 8'h DD) )
begin
next_state <= s210;
next_state <= G15_4;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h B9 |
zw_REG_OP == 8'h BE | zw_REG_OP == 8'h 59 |
3559,118 → 3267,146
zw_REG_OP == 8'h 19 | zw_REG_OP == 8'h 39 |
zw_REG_OP == 8'h D9) )
begin
next_state <= s211;
next_state <= G15_4;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h B1 |
zw_REG_OP == 8'h 51 | zw_REG_OP == 8'h 11 |
zw_REG_OP == 8'h 31 | zw_REG_OP == 8'h D1) )
begin
next_state <= s215;
next_state <= G15_5;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A1 |
zw_REG_OP == 8'h 41 | zw_REG_OP == 8'h 01 |
zw_REG_OP == 8'h 21 | zw_REG_OP == 8'h C1) )
begin
next_state <= s218;
next_state <= G15_7;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h B6 )
begin
next_state <= s217;
next_state <= G15_2;
end
else
begin
next_state <= s201;
next_state <= G15_1;
end
end
s202:
G15_2:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s224;
next_state <= G15_e2;
end
else
begin
next_state <= s202;
next_state <= G15_2;
end
end
s210:
G15_3:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s225;
next_state <= G15_e2;
end
else
begin
next_state <= s210;
next_state <= G15_3;
end
end
s211:
G15_4:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s225;
next_state <= G15_e1;
end
else
begin
next_state <= s211;
next_state <= G15_4;
end
end
s215:
G15_5:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s223;
next_state <= G15_6;
end
else
begin
next_state <= s215;
next_state <= G15_5;
end
end
s217:
G15_6:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s224;
next_state <= G15_e1;
end
else
begin
next_state <= s217;
next_state <= G15_6;
end
end
s218:
G15_7:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s222;
next_state <= G15_e3;
end
else
begin
next_state <= s218;
next_state <= G15_7;
end
end
s222:
G15_e1:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 09 | zw_REG_OP == 8'h 05 |
zw_REG_OP == 8'h 15 | zw_REG_OP == 8'h 0D |
zw_REG_OP == 8'h 1D | zw_REG_OP == 8'h 19 |
zw_REG_OP == 8'h 01 | zw_REG_OP == 8'h 11))
begin
next_state <= s202;
next_state <= FETCH;
end
else
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 45 |
zw_REG_OP == 8'h 55 | zw_REG_OP == 8'h 4D |
zw_REG_OP == 8'h 5D | zw_REG_OP == 8'h 59 |
zw_REG_OP == 8'h 41 | zw_REG_OP == 8'h 51) )
begin
next_state <= s222;
next_state <= FETCH;
end
end
s223:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h 25 |
zw_REG_OP == 8'h 35 | zw_REG_OP == 8'h 2D |
zw_REG_OP == 8'h 3D | zw_REG_OP == 8'h 39 |
zw_REG_OP == 8'h 21 | zw_REG_OP == 8'h 31) )
begin
next_state <= s225;
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h C9 | zw_REG_OP == 8'h C5 |
zw_REG_OP == 8'h D5 | zw_REG_OP == 8'h CD |
zw_REG_OP == 8'h DD | zw_REG_OP == 8'h D9 |
zw_REG_OP == 8'h C1 | zw_REG_OP == 8'h D1 |
zw_REG_OP == 8'h C0 | zw_REG_OP == 8'h E0 |
zw_REG_OP == 8'h C4 | zw_REG_OP == 8'h E4 |
zw_REG_OP == 8'h CC | zw_REG_OP == 8'h EC) )
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 )
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 )
begin
next_state <= G15_e2;
end
else
begin
next_state <= s223;
next_state <= G15_e1;
end
end
s224:
G15_e2:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 09 |
zw_REG_OP == 8'h 05 | zw_REG_OP == 8'h 15 |
3713,511 → 3449,551
end
else
begin
next_state <= s224;
next_state <= G15_e2;
end
end
s225:
G15_e3:
begin
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 09 | zw_REG_OP == 8'h 05 |
zw_REG_OP == 8'h 15 | zw_REG_OP == 8'h 0D |
zw_REG_OP == 8'h 1D | zw_REG_OP == 8'h 19 |
zw_REG_OP == 8'h 01 | zw_REG_OP == 8'h 11))
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
next_state <= G15_3;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 45 |
zw_REG_OP == 8'h 55 | zw_REG_OP == 8'h 4D |
zw_REG_OP == 8'h 5D | zw_REG_OP == 8'h 59 |
zw_REG_OP == 8'h 41 | zw_REG_OP == 8'h 51) )
else
begin
next_state <= FETCH;
next_state <= G15_e3;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h 25 |
zw_REG_OP == 8'h 35 | zw_REG_OP == 8'h 2D |
zw_REG_OP == 8'h 3D | zw_REG_OP == 8'h 39 |
zw_REG_OP == 8'h 21 | zw_REG_OP == 8'h 31) )
end
G16_1:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E5)
begin
next_state <= FETCH;
next_state <= G16_e2;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h C9 | zw_REG_OP == 8'h C5 |
zw_REG_OP == 8'h D5 | zw_REG_OP == 8'h CD |
zw_REG_OP == 8'h DD | zw_REG_OP == 8'h D9 |
zw_REG_OP == 8'h C1 | zw_REG_OP == 8'h D1 |
zw_REG_OP == 8'h C0 | zw_REG_OP == 8'h E0 |
zw_REG_OP == 8'h C4 | zw_REG_OP == 8'h E4 |
zw_REG_OP == 8'h CC | zw_REG_OP == 8'h EC) )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E9 &
reg_F[3] == 1'b 0 )
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F5 )
begin
next_state <= FETCH;
next_state <= G16_2;
end
else if (rdy_i == 1'b 1 )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h ED )
begin
next_state <= s224;
next_state <= G16_3;
end
else
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h FD )
begin
next_state <= s225;
next_state <= G16_4;
end
end
s226:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h C6 |
zw_REG_OP == 8'h E6))
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F9 )
begin
next_state <= s343;
next_state <= G16_4;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h D6 |
zw_REG_OP == 8'h F6) )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F1 )
begin
next_state <= s247;
next_state <= G16_5;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h CE |
zw_REG_OP == 8'h EE) )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E1 )
begin
next_state <= s243;
next_state <= G16_7;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h DE |
zw_REG_OP == 8'h FE) )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E9 &
reg_F[3] == 1'b 1 )
begin
next_state <= s244;
next_state <= FETCH;
end
else
begin
next_state <= s226;
next_state <= G16_1;
end
end
s243:
G16_2:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s343;
next_state <= G16_e2;
end
else
begin
next_state <= s243;
next_state <= G16_2;
end
end
s244:
G16_3:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s344;
next_state <= G16_e2;
end
else
begin
next_state <= s244;
next_state <= G16_3;
end
end
s247:
G16_4:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s343;
next_state <= G16_e1;
end
else
begin
next_state <= s247;
next_state <= G16_4;
end
end
s344:
G16_5:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s343;
next_state <= G16_6;
end
else
begin
next_state <= s344;
next_state <= G16_5;
end
end
s343:
G16_6:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s250;
next_state <= G16_e1;
end
else
begin
next_state <= s343;
next_state <= G16_6;
end
end
s250:
G16_7:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s251;
next_state <= G16_e3;
end
else
begin
next_state <= s250;
next_state <= G16_7;
end
end
s251:
G16_e1:
begin
next_state <= FETCH;
end
s351:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 24)
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 0)
begin
next_state <= s361;
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 2C )
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 1 )
begin
next_state <= s360;
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 )
begin
next_state <= G16_e2;
end
else
begin
next_state <= s351;
next_state <= G16_e1;
end
end
s361:
G16_e2:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & reg_F[3] == 1'b 0)
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & reg_F[3] == 1'b 1 )
begin
next_state <= FETCH;
end
else
begin
next_state <= s361;
next_state <= G16_e2;
end
end
s360:
G16_e3:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s361;
next_state <= G16_3;
end
else
begin
next_state <= s360;
next_state <= G16_e3;
end
end
s403:
G17_1:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 1E |
zw_REG_OP == 8'h 7E | zw_REG_OP == 8'h 3E |
zw_REG_OP == 8'h 5E))
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 85 |
zw_REG_OP == 8'h 86 | zw_REG_OP == 8'h 84))
begin
next_state <= s407;
next_state <= G17_e;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 06 |
zw_REG_OP == 8'h 66 | zw_REG_OP == 8'h 26 |
zw_REG_OP == 8'h 46) )
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 95 |
zw_REG_OP == 8'h 94) )
begin
next_state <= s413;
next_state <= G17_2;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 16 |
zw_REG_OP == 8'h 76 | zw_REG_OP == 8'h 36 |
zw_REG_OP == 8'h 56) )
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 8D |
zw_REG_OP == 8'h 8E | zw_REG_OP == 8'h 8C) )
begin
next_state <= s409;
next_state <= G17_3;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 0E |
zw_REG_OP == 8'h 6E | zw_REG_OP == 8'h 2E |
zw_REG_OP == 8'h 4E) )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 9D )
begin
next_state <= s406;
next_state <= G17_4;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 99 )
begin
next_state <= G17_4;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 91 )
begin
next_state <= G17_6;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 81 )
begin
next_state <= G17_8;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 96 )
begin
next_state <= G17_2;
end
else
begin
next_state <= s403;
next_state <= G17_1;
end
end
s406:
G17_10:
begin
next_state <= G17_e;
end
G17_2:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s413;
next_state <= G17_e;
end
else
begin
next_state <= s406;
next_state <= G17_2;
end
end
s407:
G17_3:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s412;
next_state <= G17_e;
end
else
begin
next_state <= s407;
next_state <= G17_3;
end
end
s409:
G17_4:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s413;
next_state <= G17_5;
end
else
begin
next_state <= s409;
next_state <= G17_4;
end
end
s412:
G17_5:
begin
next_state <= G17_e;
end
G17_6:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s413;
next_state <= G17_7;
end
else
begin
next_state <= s412;
next_state <= G17_6;
end
end
s413:
G17_7:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s416;
next_state <= G17_5;
end
else
begin
next_state <= s413;
next_state <= G17_7;
end
end
s416:
G17_8:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 06 |
zw_REG_OP == 8'h 16 | zw_REG_OP == 8'h 0E |
zw_REG_OP == 8'h 1E))
if (rdy_i == 1'b 1)
begin
next_state <= s418;
next_state <= G17_9;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 46 |
zw_REG_OP == 8'h 56 | zw_REG_OP == 8'h 4E |
zw_REG_OP == 8'h 5E) )
else
begin
next_state <= s418;
next_state <= G17_8;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 26 |
zw_REG_OP == 8'h 36 | zw_REG_OP == 8'h 2E |
zw_REG_OP == 8'h 3E) )
end
G17_9:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s418;
next_state <= G17_10;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 66 |
zw_REG_OP == 8'h 76 | zw_REG_OP == 8'h 6E |
zw_REG_OP == 8'h 7E) )
begin
next_state <= s418;
end
else
begin
next_state <= s416;
next_state <= G17_9;
end
end
s418:
G17_e:
begin
next_state <= FETCH;
end
s510:
G18_1:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 65)
if (rdy_i == 1'b 1)
begin
next_state <= s565;
next_state <= G18_2;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 69 &
reg_F[3] == 1'b 0 )
else
begin
next_state <= FETCH;
next_state <= G18_1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 75 )
end
G18_2:
begin
next_state <= G18_3;
end
G18_3:
begin
next_state <= G18_4;
end
G18_4:
begin
next_state <= G18_5;
end
G18_5:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s560;
next_state <= G18_e;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 6D )
else
begin
next_state <= s553;
next_state <= G18_5;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 7D )
end
G18_e:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s555;
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 79 )
else
begin
next_state <= s555;
next_state <= G18_e;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 71 )
end
G19_1:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s558;
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 61 )
else
begin
next_state <= s561;
next_state <= G19_1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 69 &
reg_F[3] == 1'b 1 )
end
G1_1:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s510;
next_state <= G1_1;
end
end
s553:
G20_1:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 4C)
begin
next_state <= s565;
next_state <= G20_e;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 6C )
begin
next_state <= G20_2;
end
else
begin
next_state <= s553;
next_state <= G20_1;
end
end
s555:
G20_2:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s564;
next_state <= G20_3;
end
else
begin
next_state <= s555;
next_state <= G20_2;
end
end
s558:
G20_3:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s566;
next_state <= G20_e;
end
else
begin
next_state <= s558;
next_state <= G20_3;
end
end
s560:
G20_e:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s565;
next_state <= FETCH;
end
else
begin
next_state <= s560;
next_state <= G20_e;
end
end
s561:
G21_1:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s563;
next_state <= G21_2;
end
else
begin
next_state <= s561;
next_state <= G21_1;
end
end
s563:
G21_2:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s553;
next_state <= G21_3;
end
else
begin
next_state <= s563;
next_state <= G21_2;
end
end
s564:
G21_3:
begin
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 0)
next_state <= G21_4;
end
G21_4:
begin
next_state <= G21_e;
end
G21_e:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 1 )
else
begin
next_state <= FETCH;
next_state <= G21_e;
end
else if (rdy_i == 1'b 1 )
end
G22_1:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s565;
next_state <= G22_e;
end
else
begin
next_state <= s564;
next_state <= G22_1;
end
end
s565:
G22_e:
begin
if (rdy_i == 1'b 1 & reg_F[3] == 1'b 0)
next_state <= FETCH;
end
G23_1:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
next_state <= G23_e;
end
else if (rdy_i == 1'b 1 & reg_F[3] == 1'b 1 )
else
begin
next_state <= FETCH;
next_state <= G23_1;
end
end
G23_e:
begin
next_state <= FETCH;
end
G24_1:
begin
if (rdy_i == 1'b 1)
begin
next_state <= G24_2;
end
else
begin
next_state <= s565;
next_state <= G24_1;
end
end
s566:
G24_2:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s564;
next_state <= G24_e;
end
else
begin
next_state <= s566;
next_state <= G24_2;
end
end
s266:
G24_e:
begin
if (rdy_i == 1'b 1 & (reg_F[0] == 1'b 1 &
zw_REG_OP == 8'h 90 | reg_F[0] == 1'b 0 &
zw_REG_OP == 8'h B0 | reg_F[1] == 1'b 0 &
zw_REG_OP == 8'h F0 | reg_F[7] == 1'b 0 &
zw_REG_OP == 8'h 30 | reg_F[1] == 1'b 1 &
zw_REG_OP == 8'h D0 | reg_F[7] == 1'b 1 &
zw_REG_OP == 8'h 10 | reg_F[6] == 1'b 1 &
zw_REG_OP == 8'h 50 | reg_F[6] == 1'b 0 &
zw_REG_OP == 8'h 70))
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 )
else
begin
next_state <= s301;
next_state <= G24_e;
end
end
G25_1:
begin
if (rdy_i == 1'b 1)
begin
next_state <= G25_2;
end
else
begin
next_state <= s266;
next_state <= G25_1;
end
end
s301:
G25_2:
begin
if (rdy_i == 1'b 1 & zw_b3 == adr_nxt_pc_i[15:8])
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
next_state <= G25_e;
end
else if (rdy_i == 1'b 1 )
begin
next_state <= s302;
end
else
begin
next_state <= s301;
next_state <= G25_2;
end
end
s302:
G25_e:
begin
if (rdy_i == 1'b 1)
begin
4225,217 → 4001,292
end
else
begin
next_state <= s302;
next_state <= G25_e;
end
end
RES:
G26_1:
begin
next_state <= s544;
end
s511:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E5)
if (rdy_i == 1'b 1)
begin
next_state <= s574;
next_state <= G26_2;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E9 &
reg_F[3] == 1'b 0 )
else
begin
next_state <= FETCH;
next_state <= G26_1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F5 )
end
G26_2:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s569;
next_state <= G26_3;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h ED )
else
begin
next_state <= s559;
next_state <= G26_2;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h FD )
end
G26_3:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s562;
next_state <= G26_4;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F9 )
else
begin
next_state <= s567;
next_state <= G26_3;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F1 )
end
G26_4:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s568;
next_state <= G26_e;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E1 )
else
begin
next_state <= s570;
next_state <= G26_4;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E9 &
reg_F[3] == 1'b 1 )
end
G26_e:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s511;
next_state <= G26_e;
end
end
s559:
G27_1:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s574;
next_state <= G27_2;
end
else
begin
next_state <= s559;
next_state <= G27_1;
end
end
s562:
G27_2:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s573;
next_state <= G27_3;
end
else
begin
next_state <= s562;
next_state <= G27_2;
end
end
s567:
G27_3:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s573;
next_state <= G27_4;
end
else
begin
next_state <= s567;
next_state <= G27_3;
end
end
s568:
G27_4:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s571;
next_state <= G27_e;
end
else
begin
next_state <= s568;
next_state <= G27_4;
end
end
s569:
G27_e:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s574;
next_state <= FETCH;
end
else
begin
next_state <= s569;
next_state <= G27_e;
end
end
s570:
G28_1:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s572;
next_state <= G28_2;
end
else
begin
next_state <= s570;
next_state <= G28_1;
end
end
s571:
G28_2:
begin
next_state <= G28_3;
end
G28_3:
begin
next_state <= G28_4;
end
G28_4:
begin
next_state <= G28_5;
end
G28_5:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s573;
next_state <= G28_e;
end
else
begin
next_state <= s571;
next_state <= G28_5;
end
end
s572:
G28_e:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s559;
next_state <= FETCH;
end
else
begin
next_state <= s572;
next_state <= G28_e;
end
end
s573:
G29_1:
begin
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 0)
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
next_state <= G29_2;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 1 )
else
begin
next_state <= FETCH;
next_state <= G29_1;
end
else if (rdy_i == 1'b 1 )
end
G29_2:
begin
next_state <= G29_3;
end
G29_3:
begin
next_state <= G29_4;
end
G29_4:
begin
next_state <= G29_5;
end
G29_5:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s574;
next_state <= G29_e;
end
else
begin
next_state <= s573;
next_state <= G29_5;
end
end
s574:
G29_e:
begin
if (rdy_i == 1'b 1 & reg_F[3] == 1'b 0)
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & reg_F[3] == 1'b 1 )
else
begin
next_state <= G29_e;
end
end
G2_1:
begin
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= s574;
next_state <= G2_1;
end
end
s548:
G30_1:
begin
next_state <= G30_2;
end
G30_2:
begin
next_state <= G30_3;
end
G30_3:
begin
next_state <= G30_4;
end
G30_4:
begin
next_state <= G30_5;
end
G30_5:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s551;
next_state <= G30_e;
end
else
begin
next_state <= s548;
next_state <= G30_5;
end
end
s551:
G30_e:
begin
next_state <= s552;
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= G30_e;
end
end
s552:
G31_1:
begin
next_state <= s576;
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= G31_1;
end
end
s575:
G32_1:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s577;
next_state <= FETCH;
end
else
begin
next_state <= s575;
next_state <= G32_1;
end
end
s576:
G33_1:
begin
next_state <= s575;
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= G33_1;
end
end
s577:
G34_1:
begin
if (rdy_i == 1'b 1)
begin
4443,44 → 4294,65
end
else
begin
next_state <= s577;
next_state <= G34_1;
end
end
s532:
G3_1:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s533;
next_state <= FETCH;
end
else
begin
next_state <= s532;
next_state <= G3_1;
end
end
s533:
G4_1:
begin
next_state <= s534;
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= G4_1;
end
end
s534:
G5_1:
begin
next_state <= s536;
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= G5_1;
end
end
s535:
G6_1:
begin
if (rdy_i == 1'b 1)
begin
next_state <= s537;
next_state <= FETCH;
end
else
begin
next_state <= s535;
next_state <= G6_1;
end
end
s536:
G7_1:
begin
next_state <= s535;
if (rdy_i == 1'b 1)
begin
next_state <= FETCH;
end
else
begin
next_state <= G7_1;
end
end
s537:
G8_1:
begin
if (rdy_i == 1'b 1)
begin
4488,9 → 4360,32
end
else
begin
next_state <= s537;
next_state <= G8_1;
end
end
G9_1:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 9A)
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h BA )
begin
next_state <= FETCH;
end
else if (rdy_i == 1'b 1 )
begin
next_state <= FETCH;
end
else
begin
next_state <= G9_1;
end
end
RES:
begin
next_state <= G30_1;
end
default:
begin
next_state <= RES;
4531,8 → 4426,6
 
// Default Assignment To Internals
sig_D_OUT <= 8'h 00;
sig_RD <= 1'b 1;
sig_RWn <= 1'b 1;
sig_SYNC <= 1'b 0;
sig_WR <= 1'b 0;
zw_ALU <= {1'b 0, 8'h 00};
4547,8 → 4440,6
case (current_state)
FETCH:
begin
sig_RWn <= 1'b 1;
sig_RD <= 1'b 1;
sig_SYNC <= ~rdy_i;
if (nmi_i == 1'b 1 & rdy_i == 1'b 1)
begin
4874,155 → 4765,203
ld_pc_o <= 1'b 1;
end
end
s1:
G10_1:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 65)
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s2:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 69 &
reg_F[3] == 1'b 0 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU <= {1'b 0, q_a_i} + {1'b 0, d_i} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s5:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 75 )
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
end
s3:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 6D )
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s4:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 9A)
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 7D )
begin
adr_o <= {8'h 01, d_regs_out_i};
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
ld_pc_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h BA )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 79 )
begin
d_regs_in_o <= adr_sp_i[7:0];
ch_a_o <= adr_sp_i[7:0];
ch_b_o <= 8'h 00;
load_regs_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end
else if (rdy_i == 1'b 1 )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 71 )
begin
ch_a_o <= d_regs_out_i;
ch_b_o <= 8'h 00;
load_regs_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= 8'h 01;
end
end
s12:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 61 )
begin
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 69 &
reg_F[3] == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU[7:4] <= zw_ALU2[3:0] + zw_ALU6[2:0];
zw_ALU[3:0] <= zw_ALU1[3:0] + zw_ALU5[2:0];
zw_ALU6[2:0] <= {(zw_ALU2[4] | zw_ALU4[4]), (zw_ALU2[4] | zw_ALU4[4]),
1'b 0};
zw_ALU5[2:0] <= {(zw_ALU1[4] | zw_ALU3[4]), (zw_ALU1[4] | zw_ALU3[4]),
1'b 0};
zw_ALU4 <= {1'b 0, zw_ALU2[3:0]} + 6;
zw_ALU2 <= {1'b 0, q_a_i[7:4]} + {1'b 0, d_i[7:4]} +
(zw_ALU1[4] | zw_ALU3[4]);
zw_ALU3 <= {1'b 0, zw_ALU1[3:0]} + 6;
zw_ALU1 <= {1'b 0, q_a_i[3:0]} + {1'b 0, d_i[3:0]} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s16:
G10_2:
begin
if (rdy_i == 1'b 1)
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s17:
G10_3:
begin
if (rdy_i == 1'b 1)
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s24:
G10_4:
begin
if (rdy_i == 1'b 1)
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= 8'h 01;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s25:
G10_5:
begin
if (rdy_i == 1'b 1)
begin
d_regs_in_o <= d_alu_i;
ch_a_o <= d_regs_out_i;
ch_b_o <= zw_b4;
load_regs_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end
end
s273:
G10_6:
begin
if (rdy_i == 1'b 1)
begin
adr_o <= {d_i, zw_b1};
ch_a_o <= d_i;
ch_b_o <= 8'h 01;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s307:
G10_e1:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 0)
begin
adr_o <= {d_i, zw_b1};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU <= {1'b 0, q_a_i} + {1'b 0, d_i} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 1 )
begin
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU[7:4] <= zw_ALU2[3:0] + zw_ALU6[2:0];
zw_ALU[3:0] <= zw_ALU1[3:0] + zw_ALU5[2:0];
zw_ALU6[2:0] <= {(zw_ALU2[4] | zw_ALU4[4]), (zw_ALU2[4] | zw_ALU4[4]),
1'b 0};
zw_ALU5[2:0] <= {(zw_ALU1[4] | zw_ALU3[4]), (zw_ALU1[4] | zw_ALU3[4]),
1'b 0};
zw_ALU4 <= {1'b 0, zw_ALU2[3:0]} + 6;
zw_ALU2 <= {1'b 0, q_a_i[7:4]} + {1'b 0, d_i[7:4]} +
(zw_ALU1[4] | zw_ALU3[4]);
zw_ALU3 <= {1'b 0, zw_ALU1[3:0]} + 6;
zw_ALU1 <= {1'b 0, q_a_i[3:0]} + {1'b 0, d_i[3:0]} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s177:
G10_e2:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 85 |
zw_REG_OP == 8'h 86 | zw_REG_OP == 8'h 84))
if (rdy_i == 1'b 1 & reg_F[3] == 1'b 0)
begin
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= d_regs_out_i;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU <= {1'b 0, q_a_i} + {1'b 0, d_i} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 95 |
zw_REG_OP == 8'h 94) )
else if (rdy_i == 1'b 1 & reg_F[3] == 1'b 1 )
begin
ch_a_o <= d_i;
ch_b_o <= q_x_i;
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU[7:4] <= zw_ALU2[3:0] + zw_ALU6[2:0];
zw_ALU[3:0] <= zw_ALU1[3:0] + zw_ALU5[2:0];
zw_ALU6[2:0] <= {(zw_ALU2[4] | zw_ALU4[4]), (zw_ALU2[4] | zw_ALU4[4]),
1'b 0};
zw_ALU5[2:0] <= {(zw_ALU1[4] | zw_ALU3[4]), (zw_ALU1[4] | zw_ALU3[4]),
1'b 0};
zw_ALU4 <= {1'b 0, zw_ALU2[3:0]} + 6;
zw_ALU2 <= {1'b 0, q_a_i[7:4]} + {1'b 0, d_i[7:4]} +
(zw_ALU1[4] | zw_ALU3[4]);
zw_ALU3 <= {1'b 0, zw_ALU1[3:0]} + 6;
zw_ALU1 <= {1'b 0, q_a_i[3:0]} + {1'b 0, d_i[3:0]} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 8D |
zw_REG_OP == 8'h 8E | zw_REG_OP == 8'h 8C) )
end
G10_e3:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ch_a_o <= zw_b1;
ch_b_o <= 8'h 01;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 9D )
end
G11_1:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 1E |
zw_REG_OP == 8'h 7E | zw_REG_OP == 8'h 3E |
zw_REG_OP == 8'h 5E))
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
5029,102 → 4968,76
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 99 )
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 06 |
zw_REG_OP == 8'h 66 | zw_REG_OP == 8'h 26 |
zw_REG_OP == 8'h 46) )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 91 )
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 16 |
zw_REG_OP == 8'h 76 | zw_REG_OP == 8'h 36 |
zw_REG_OP == 8'h 56) )
begin
ch_a_o <= d_i;
ch_b_o <= 8'h 01;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 81 )
begin
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 96 )
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 0E |
zw_REG_OP == 8'h 6E | zw_REG_OP == 8'h 2E |
zw_REG_OP == 8'h 4E) )
begin
ch_a_o <= d_i;
ch_b_o <= q_y_i;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s180:
G11_2:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= {7'b 0000000, zw_b2[0]};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s181:
G11_4:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 06 |
zw_REG_OP == 8'h 16 | zw_REG_OP == 8'h 0E |
zw_REG_OP == 8'h 1E))
begin
ch_a_o <= d_i;
ch_b_o <= q_y_i;
sig_D_OUT <= {d_i[6:0], 1'b 0};
sig_WR <= 1'b 1;
end
end
s182:
begin
sig_RWn <= 1'b 1;
sig_RD <= 1'b 1;
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 46 |
zw_REG_OP == 8'h 56 | zw_REG_OP == 8'h 4E |
zw_REG_OP == 8'h 5E) )
begin
ch_a_o <= d_i;
ch_b_o <= {7'b 0000000, zw_b2[0]};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
sig_D_OUT <= {1'b 0, d_i[7:1]};
sig_WR <= 1'b 1;
end
end
s183:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 26 |
zw_REG_OP == 8'h 36 | zw_REG_OP == 8'h 2E |
zw_REG_OP == 8'h 3E) )
begin
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_D_OUT <= {d_i[6:0], reg_F[0]};
sig_WR <= 1'b 1;
sig_D_OUT <= d_regs_out_i;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s184:
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
s185:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 66 |
zw_REG_OP == 8'h 76 | zw_REG_OP == 8'h 6E |
zw_REG_OP == 8'h 7E) )
begin
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_D_OUT <= {reg_F[0], d_i[7:1]};
sig_WR <= 1'b 1;
sig_D_OUT <= d_regs_out_i;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s187:
G11_5:
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
s188:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= zw_b1;
ch_b_o <= 8'h 01;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s189:
G11_6:
begin
if (rdy_i == 1'b 1)
begin
5134,95 → 5047,58
ld_pc_o <= 1'b 1;
end
end
s190:
G11_e:
begin
ch_a_o <= zw_b1;
ch_b_o <= 8'h 00;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
s191:
G12_1:
begin
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= d_regs_out_i;
end
s192:
begin
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= d_regs_out_i;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
s193:
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
s377:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & (reg_F[0] == 1'b 1 &
zw_REG_OP == 8'h 90 | reg_F[0] == 1'b 0 &
zw_REG_OP == 8'h B0 | reg_F[1] == 1'b 0 &
zw_REG_OP == 8'h F0 | reg_F[7] == 1'b 0 &
zw_REG_OP == 8'h 30 | reg_F[1] == 1'b 1 &
zw_REG_OP == 8'h D0 | reg_F[7] == 1'b 1 &
zw_REG_OP == 8'h 10 | reg_F[6] == 1'b 1 &
zw_REG_OP == 8'h 50 | reg_F[6] == 1'b 0 &
zw_REG_OP == 8'h 70))
begin
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= q_a_i;
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
ld_pc_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s381:
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
s378:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 )
begin
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= reg_F;
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
ld_pc_o <= 1'b 1;
end
end
s382:
G12_e1:
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
s379:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & zw_b3 == adr_nxt_pc_i[15:8])
begin
offset_o <= {zw_b2[7], zw_b2[7], zw_b2[7], zw_b2[7],
zw_b2[7], zw_b2[7], zw_b2[7], zw_b2[7],
zw_b2[7], zw_b2[6:0]};
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
end
end
s384:
begin
if (rdy_i == 1'b 1)
begin
d_regs_in_o <= d_i;
load_regs_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= 8'h 00;
ld_pc_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s380:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 )
begin
offset_o <= {zw_b2[7], zw_b2[7], zw_b2[7], zw_b2[7],
zw_b2[7], zw_b2[7], zw_b2[7], zw_b2[7],
zw_b2[7], zw_b2[6:0]};
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
ld_pc_o <= 1'b 1;
end
end
s386:
G12_e2:
begin
if (rdy_i == 1'b 1)
begin
5230,237 → 5106,117
fetch_o <= 1'b 1;
end
end
s387:
G13_1:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 24)
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
ld_pc_o <= 1'b 1;
end
end
s388:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 2C )
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
ld_pc_o <= 1'b 1;
end
end
s389:
G13_2:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
ld_pc_o <= 1'b 1;
end
end
s392:
G13_e:
begin
if (rdy_i == 1'b 1)
begin
adr_o <= {d_i, zw_b1};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ch_a_o <= q_a_i & d_i;
ch_b_o <= 8'h 00;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s390:
G14_1:
begin
if (rdy_i == 1'b 1)
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h C6 |
zw_REG_OP == 8'h E6))
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
ld_pc_o <= 1'b 1;
end
end
s393:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h D6 |
zw_REG_OP == 8'h F6) )
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
end
s395:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h CE |
zw_REG_OP == 8'h EE) )
begin
adr_o <= {d_i, zw_b1};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s396:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h DE |
zw_REG_OP == 8'h FE) )
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
end
s397:
G14_2:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
ld_pc_o <= 1'b 1;
end
end
s398:
G14_3:
begin
if (rdy_i == 1'b 1)
begin
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= adr_pc_i[15:8];
ch_a_o <= d_i;
ch_b_o <= zw_b4;
end
end
s399:
G14_4:
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= adr_pc_i[7:0];
end
s401:
begin
if (rdy_i == 1'b 1)
begin
adr_o <= {d_i, zw_b1};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s526:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
ld_pc_o <= 1'b 1;
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= adr_pc_i[15:8];
sig_D_OUT <= zw_b1;
end
end
s527:
G14_5:
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= adr_pc_i[7:0];
end
s528:
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= reg_F | 8'h 10;
end
s530:
begin
if (rdy_i == 1'b 1)
begin
adr_o <= {d_i, zw_b1};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s544:
G14_6:
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
end
s545:
begin
adr_o <= 16'h FFFB;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
s546:
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
s549:
begin
if (rdy_i == 1'b 1)
begin
adr_o <= {d_i, zw_b1};
ch_a_o <= d_i;
ch_b_o <= {7'b 0000000, zw_b2[0]};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s550:
G14_e:
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
ch_a_o <= zw_b1;
ch_b_o <= 8'h 00;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
s404:
G15_1:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= {q_a_i[6:0], 1'b 0};
ch_b_o <= 8'h 00;
d_regs_in_o <= {q_a_i[6:0], 1'b 0};
load_regs_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s556:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= {1'b 0, q_a_i[7:1]};
ch_b_o <= 8'h 00;
d_regs_in_o <= {1'b 0, q_a_i[7:1]};
load_regs_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s557:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= {q_a_i[6:0], reg_F[0]};
ch_b_o <= 8'h 00;
d_regs_in_o <= {q_a_i[6:0], reg_F[0]};
load_regs_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s579:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= {reg_F[0], q_a_i[7:1]};
ch_b_o <= 8'h 00;
d_regs_in_o <= {reg_F[0], q_a_i[7:1]};
load_regs_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s201:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A5 |
zw_REG_OP == 8'h A6 | zw_REG_OP == 8'h A4 |
zw_REG_OP == 8'h 45 | zw_REG_OP == 8'h 05 |
5619,7 → 5375,7
ch_b_o <= q_y_i;
end
end
s202:
G15_2:
begin
if (rdy_i == 1'b 1)
begin
5627,17 → 5383,15
ld_pc_o <= 1'b 1;
end
end
s210:
G15_3:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= {7'b 0000000, zw_b2[0]};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s211:
G15_4:
begin
if (rdy_i == 1'b 1)
begin
5647,7 → 5401,7
ld_pc_o <= 1'b 1;
end
end
s215:
G15_5:
begin
if (rdy_i == 1'b 1)
begin
5655,26 → 5409,10
ch_b_o <= q_y_i;
end
end
s217:
G15_6:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s222:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= zw_b1;
ch_b_o <= 8'h 01;
end
end
s223:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= {7'b 0000000, zw_b2[0]};
ld_o <= 2'b 11;
5681,13 → 5419,13
ld_pc_o <= 1'b 1;
end
end
s224:
G15_e1:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 09 |
zw_REG_OP == 8'h 05 | zw_REG_OP == 8'h 15 |
zw_REG_OP == 8'h 0D | zw_REG_OP == 8'h 1D |
zw_REG_OP == 8'h 19 | zw_REG_OP == 8'h 01 |
zw_REG_OP == 8'h 11))
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 09 | zw_REG_OP == 8'h 05 |
zw_REG_OP == 8'h 15 | zw_REG_OP == 8'h 0D |
zw_REG_OP == 8'h 1D | zw_REG_OP == 8'h 19 |
zw_REG_OP == 8'h 01 | zw_REG_OP == 8'h 11))
begin
d_regs_in_o <= d_i | q_a_i;
load_regs_o <= 1'b 1;
5696,11 → 5434,11
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 49 |
zw_REG_OP == 8'h 45 | zw_REG_OP == 8'h 55 |
zw_REG_OP == 8'h 4D | zw_REG_OP == 8'h 5D |
zw_REG_OP == 8'h 59 | zw_REG_OP == 8'h 41 |
zw_REG_OP == 8'h 51) )
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 45 |
zw_REG_OP == 8'h 55 | zw_REG_OP == 8'h 4D |
zw_REG_OP == 8'h 5D | zw_REG_OP == 8'h 59 |
zw_REG_OP == 8'h 41 | zw_REG_OP == 8'h 51) )
begin
d_regs_in_o <= d_i ^ q_a_i;
load_regs_o <= 1'b 1;
5709,11 → 5447,11
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 29 |
zw_REG_OP == 8'h 25 | zw_REG_OP == 8'h 35 |
zw_REG_OP == 8'h 2D | zw_REG_OP == 8'h 3D |
zw_REG_OP == 8'h 39 | zw_REG_OP == 8'h 21 |
zw_REG_OP == 8'h 31) )
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h 25 |
zw_REG_OP == 8'h 35 | zw_REG_OP == 8'h 2D |
zw_REG_OP == 8'h 3D | zw_REG_OP == 8'h 39 |
zw_REG_OP == 8'h 21 | zw_REG_OP == 8'h 31) )
begin
d_regs_in_o <= d_i & q_a_i;
load_regs_o <= 1'b 1;
5722,14 → 5460,14
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h C9 |
zw_REG_OP == 8'h C5 | zw_REG_OP == 8'h D5 |
zw_REG_OP == 8'h CD | zw_REG_OP == 8'h DD |
zw_REG_OP == 8'h D9 | zw_REG_OP == 8'h C1 |
zw_REG_OP == 8'h D1 | zw_REG_OP == 8'h C0 |
zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C4 |
zw_REG_OP == 8'h E4 | zw_REG_OP == 8'h CC |
zw_REG_OP == 8'h EC) )
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h C9 | zw_REG_OP == 8'h C5 |
zw_REG_OP == 8'h D5 | zw_REG_OP == 8'h CD |
zw_REG_OP == 8'h DD | zw_REG_OP == 8'h D9 |
zw_REG_OP == 8'h C1 | zw_REG_OP == 8'h D1 |
zw_REG_OP == 8'h C0 | zw_REG_OP == 8'h E0 |
zw_REG_OP == 8'h C4 | zw_REG_OP == 8'h E4 |
zw_REG_OP == 8'h CC | zw_REG_OP == 8'h EC) )
begin
zw_ALU <= {1'b 0, d_regs_out_i} + {1'b 0, (~d_i)} +
1;
5736,7 → 5474,7
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 )
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 )
begin
d_regs_in_o <= d_i;
load_regs_o <= 1'b 1;
5746,13 → 5484,13
fetch_o <= 1'b 1;
end
end
s225:
G15_e2:
begin
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 09 | zw_REG_OP == 8'h 05 |
zw_REG_OP == 8'h 15 | zw_REG_OP == 8'h 0D |
zw_REG_OP == 8'h 1D | zw_REG_OP == 8'h 19 |
zw_REG_OP == 8'h 01 | zw_REG_OP == 8'h 11))
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 09 |
zw_REG_OP == 8'h 05 | zw_REG_OP == 8'h 15 |
zw_REG_OP == 8'h 0D | zw_REG_OP == 8'h 1D |
zw_REG_OP == 8'h 19 | zw_REG_OP == 8'h 01 |
zw_REG_OP == 8'h 11))
begin
d_regs_in_o <= d_i | q_a_i;
load_regs_o <= 1'b 1;
5761,11 → 5499,11
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 45 |
zw_REG_OP == 8'h 55 | zw_REG_OP == 8'h 4D |
zw_REG_OP == 8'h 5D | zw_REG_OP == 8'h 59 |
zw_REG_OP == 8'h 41 | zw_REG_OP == 8'h 51) )
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 49 |
zw_REG_OP == 8'h 45 | zw_REG_OP == 8'h 55 |
zw_REG_OP == 8'h 4D | zw_REG_OP == 8'h 5D |
zw_REG_OP == 8'h 59 | zw_REG_OP == 8'h 41 |
zw_REG_OP == 8'h 51) )
begin
d_regs_in_o <= d_i ^ q_a_i;
load_regs_o <= 1'b 1;
5774,11 → 5512,11
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h 25 |
zw_REG_OP == 8'h 35 | zw_REG_OP == 8'h 2D |
zw_REG_OP == 8'h 3D | zw_REG_OP == 8'h 39 |
zw_REG_OP == 8'h 21 | zw_REG_OP == 8'h 31) )
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 29 |
zw_REG_OP == 8'h 25 | zw_REG_OP == 8'h 35 |
zw_REG_OP == 8'h 2D | zw_REG_OP == 8'h 3D |
zw_REG_OP == 8'h 39 | zw_REG_OP == 8'h 21 |
zw_REG_OP == 8'h 31) )
begin
d_regs_in_o <= d_i & q_a_i;
load_regs_o <= 1'b 1;
5787,14 → 5525,14
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
(zw_REG_OP == 8'h C9 | zw_REG_OP == 8'h C5 |
zw_REG_OP == 8'h D5 | zw_REG_OP == 8'h CD |
zw_REG_OP == 8'h DD | zw_REG_OP == 8'h D9 |
zw_REG_OP == 8'h C1 | zw_REG_OP == 8'h D1 |
zw_REG_OP == 8'h C0 | zw_REG_OP == 8'h E0 |
zw_REG_OP == 8'h C4 | zw_REG_OP == 8'h E4 |
zw_REG_OP == 8'h CC | zw_REG_OP == 8'h EC) )
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h C9 |
zw_REG_OP == 8'h C5 | zw_REG_OP == 8'h D5 |
zw_REG_OP == 8'h CD | zw_REG_OP == 8'h DD |
zw_REG_OP == 8'h D9 | zw_REG_OP == 8'h C1 |
zw_REG_OP == 8'h D1 | zw_REG_OP == 8'h C0 |
zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C4 |
zw_REG_OP == 8'h E4 | zw_REG_OP == 8'h CC |
zw_REG_OP == 8'h EC) )
begin
zw_ALU <= {1'b 0, d_regs_out_i} + {1'b 0, (~d_i)} +
1;
5801,7 → 5539,7
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 )
else if (rdy_i == 1'b 1 )
begin
d_regs_in_o <= d_i;
load_regs_o <= 1'b 1;
5811,110 → 5549,91
fetch_o <= 1'b 1;
end
end
s226:
G15_e3:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h C6 |
zw_REG_OP == 8'h E6))
if (rdy_i == 1'b 1)
begin
ch_a_o <= zw_b1;
ch_b_o <= 8'h 01;
end
end
G16_1:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E5)
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h D6 |
zw_REG_OP == 8'h F6) )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E9 &
reg_F[3] == 1'b 0 )
begin
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h CE |
zw_REG_OP == 8'h EE) )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU <= {1'b 0, q_a_i} + {1'b 0, (~d_i)} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h DE |
zw_REG_OP == 8'h FE) )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F5 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
end
s243:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h ED )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s244:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h FD )
begin
ch_a_o <= d_i;
ch_b_o <= {7'b 0000000, zw_b2[0]};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
end
s247:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F9 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end
end
s343:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F1 )
begin
ch_a_o <= d_i;
ch_b_o <= zw_b4;
ch_b_o <= 8'h 01;
end
end
s250:
begin
if (rdy_i == 1'b 1)
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E1 )
begin
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= zw_b1;
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
end
s251:
begin
ch_a_o <= zw_b1;
ch_b_o <= 8'h 00;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
s351:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 24)
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E9 &
reg_F[3] == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 2C )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s361:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= q_a_i & d_i;
ch_b_o <= 8'h 00;
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU[7:4] <= zw_ALU2[3:0] + zw_ALU6;
zw_ALU[3:0] <= zw_ALU1[3:0] + zw_ALU5;
zw_ALU6 <= {(zw_ALU4[4] | ~zw_ALU2[4]), 1'b 0, (zw_ALU4[4] |
~zw_ALU2[4]), 1'b 0};
zw_ALU5 <= {(zw_ALU3[4] | ~zw_ALU1[4]), 1'b 0, (zw_ALU3[4] |
~zw_ALU1[4]), 1'b 0};
zw_ALU4 <= {1'b 0, zw_ALU2[3:0]} + 6;
zw_ALU2 <= {1'b 0, q_a_i[7:4]} + {1'b 0, (~d_i[7:4])} +
zw_ALU1[4];
zw_ALU3 <= {1'b 0, zw_ALU1[3:0]} + 6;
zw_ALU1 <= {1'b 0, q_a_i[3:0]} + {1'b 0, (~d_i[3:0])} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s360:
G16_2:
begin
if (rdy_i == 1'b 1)
begin
5922,141 → 5641,137
ld_pc_o <= 1'b 1;
end
end
s403:
G16_3:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 1E |
zw_REG_OP == 8'h 7E | zw_REG_OP == 8'h 3E |
zw_REG_OP == 8'h 5E))
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 06 |
zw_REG_OP == 8'h 66 | zw_REG_OP == 8'h 26 |
zw_REG_OP == 8'h 46) )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 16 |
zw_REG_OP == 8'h 76 | zw_REG_OP == 8'h 36 |
zw_REG_OP == 8'h 56) )
begin
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 0E |
zw_REG_OP == 8'h 6E | zw_REG_OP == 8'h 2E |
zw_REG_OP == 8'h 4E) )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s406:
G16_4:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= 8'h 01;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s407:
G16_5:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= {7'b 0000000, zw_b2[0]};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ch_b_o <= q_y_i;
end
end
s409:
G16_6:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= 8'h 01;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s416:
G16_e1:
begin
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 06 |
zw_REG_OP == 8'h 16 | zw_REG_OP == 8'h 0E |
zw_REG_OP == 8'h 1E))
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 0)
begin
sig_D_OUT <= {d_i[6:0], 1'b 0};
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU <= {1'b 0, q_a_i} + {1'b 0, (~d_i)} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 46 |
zw_REG_OP == 8'h 56 | zw_REG_OP == 8'h 4E |
zw_REG_OP == 8'h 5E) )
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 1 )
begin
sig_D_OUT <= {1'b 0, d_i[7:1]};
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU[7:4] <= zw_ALU2[3:0] + zw_ALU6;
zw_ALU[3:0] <= zw_ALU1[3:0] + zw_ALU5;
zw_ALU6 <= {(zw_ALU4[4] | ~zw_ALU2[4]), 1'b 0, (zw_ALU4[4] |
~zw_ALU2[4]), 1'b 0};
zw_ALU5 <= {(zw_ALU3[4] | ~zw_ALU1[4]), 1'b 0, (zw_ALU3[4] |
~zw_ALU1[4]), 1'b 0};
zw_ALU4 <= {1'b 0, zw_ALU2[3:0]} + 6;
zw_ALU2 <= {1'b 0, q_a_i[7:4]} + {1'b 0, (~d_i[7:4])} +
zw_ALU1[4];
zw_ALU3 <= {1'b 0, zw_ALU1[3:0]} + 6;
zw_ALU1 <= {1'b 0, q_a_i[3:0]} + {1'b 0, (~d_i[3:0])} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 26 |
zw_REG_OP == 8'h 36 | zw_REG_OP == 8'h 2E |
zw_REG_OP == 8'h 3E) )
end
G16_e2:
begin
if (rdy_i == 1'b 1 & reg_F[3] == 1'b 0)
begin
sig_D_OUT <= {d_i[6:0], reg_F[0]};
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU <= {1'b 0, q_a_i} + {1'b 0, (~d_i)} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 66 |
zw_REG_OP == 8'h 76 | zw_REG_OP == 8'h 6E |
zw_REG_OP == 8'h 7E) )
else if (rdy_i == 1'b 1 & reg_F[3] == 1'b 1 )
begin
sig_D_OUT <= {reg_F[0], d_i[7:1]};
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU[7:4] <= zw_ALU2[3:0] + zw_ALU6;
zw_ALU[3:0] <= zw_ALU1[3:0] + zw_ALU5;
zw_ALU6 <= {(zw_ALU4[4] | ~zw_ALU2[4]), 1'b 0, (zw_ALU4[4] |
~zw_ALU2[4]), 1'b 0};
zw_ALU5 <= {(zw_ALU3[4] | ~zw_ALU1[4]), 1'b 0, (zw_ALU3[4] |
~zw_ALU1[4]), 1'b 0};
zw_ALU4 <= {1'b 0, zw_ALU2[3:0]} + 6;
zw_ALU2 <= {1'b 0, q_a_i[7:4]} + {1'b 0, (~d_i[7:4])} +
zw_ALU1[4];
zw_ALU3 <= {1'b 0, zw_ALU1[3:0]} + 6;
zw_ALU1 <= {1'b 0, q_a_i[3:0]} + {1'b 0, (~d_i[3:0])} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s418:
G16_e3:
begin
ch_a_o <= zw_b1;
ch_b_o <= 8'h 00;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
if (rdy_i == 1'b 1)
begin
ch_a_o <= zw_b1;
ch_b_o <= 8'h 01;
end
end
s510:
G17_1:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 65)
if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 85 |
zw_REG_OP == 8'h 86 | zw_REG_OP == 8'h 84))
begin
sig_WR <= 1'b 1;
sig_D_OUT <= d_regs_out_i;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 69 &
reg_F[3] == 1'b 0 )
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 95 |
zw_REG_OP == 8'h 94) )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU <= {1'b 0, q_a_i} + {1'b 0, d_i} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 75 )
begin
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 6D )
else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 8D |
zw_REG_OP == 8'h 8E | zw_REG_OP == 8'h 8C) )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 7D )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 9D )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
6063,7 → 5778,7
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 79 )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 99 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
6070,59 → 5785,66
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 71 )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 91 )
begin
ch_a_o <= d_i;
ch_b_o <= 8'h 01;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 61 )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 81 )
begin
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 69 &
reg_F[3] == 1'b 1 )
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 96 )
begin
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end
end
G17_10:
begin
sig_WR <= 1'b 1;
sig_D_OUT <= d_regs_out_i;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
G17_2:
begin
if (rdy_i == 1'b 1)
begin
sig_WR <= 1'b 1;
sig_D_OUT <= d_regs_out_i;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU[7:4] <= zw_ALU2[3:0] + zw_ALU6[2:0];
zw_ALU[3:0] <= zw_ALU1[3:0] + zw_ALU5[2:0];
zw_ALU6[2:0] <= {(zw_ALU2[4] | zw_ALU4[4]), (zw_ALU2[4] | zw_ALU4[4]),
1'b 0};
zw_ALU5[2:0] <= {(zw_ALU1[4] | zw_ALU3[4]), (zw_ALU1[4] | zw_ALU3[4]),
1'b 0};
zw_ALU4 <= {1'b 0, zw_ALU2[3:0]} + 6;
zw_ALU2 <= {1'b 0, q_a_i[7:4]} + {1'b 0, d_i[7:4]} +
(zw_ALU1[4] | zw_ALU3[4]);
zw_ALU3 <= {1'b 0, zw_ALU1[3:0]} + 6;
zw_ALU1 <= {1'b 0, q_a_i[3:0]} + {1'b 0, d_i[3:0]} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s553:
G17_3:
begin
if (rdy_i == 1'b 1)
begin
sig_WR <= 1'b 1;
sig_D_OUT <= d_regs_out_i;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s555:
G17_4:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= 8'h 01;
ch_b_o <= {7'b 0000000, zw_b2[0]};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s558:
G17_5:
begin
sig_WR <= 1'b 1;
sig_D_OUT <= d_regs_out_i;
end
G17_6:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
6129,15 → 5851,17
ch_b_o <= q_y_i;
end
end
s560:
G17_7:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= {7'b 0000000, zw_b2[0]};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s563:
G17_9:
begin
if (rdy_i == 1'b 1)
begin
6145,345 → 5869,257
ch_b_o <= 8'h 01;
end
end
s564:
G17_e:
begin
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 0)
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
G18_1:
begin
if (rdy_i == 1'b 1)
begin
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU <= {1'b 0, q_a_i} + {1'b 0, d_i} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
ld_pc_o <= 1'b 1;
sig_WR <= 1'b 1;
sig_D_OUT <= adr_pc_i[15:8];
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 1 )
end
G18_2:
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
sig_WR <= 1'b 1;
sig_D_OUT <= adr_pc_i[7:0];
end
G18_3:
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
sig_WR <= 1'b 1;
sig_D_OUT <= reg_F | 8'h 10;
end
G18_e:
begin
if (rdy_i == 1'b 1)
begin
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU[7:4] <= zw_ALU2[3:0] + zw_ALU6[2:0];
zw_ALU[3:0] <= zw_ALU1[3:0] + zw_ALU5[2:0];
zw_ALU6[2:0] <= {(zw_ALU2[4] | zw_ALU4[4]), (zw_ALU2[4] | zw_ALU4[4]),
1'b 0};
zw_ALU5[2:0] <= {(zw_ALU1[4] | zw_ALU3[4]), (zw_ALU1[4] | zw_ALU3[4]),
1'b 0};
zw_ALU4 <= {1'b 0, zw_ALU2[3:0]} + 6;
zw_ALU2 <= {1'b 0, q_a_i[7:4]} + {1'b 0, d_i[7:4]} +
(zw_ALU1[4] | zw_ALU3[4]);
zw_ALU3 <= {1'b 0, zw_ALU1[3:0]} + 6;
zw_ALU1 <= {1'b 0, q_a_i[3:0]} + {1'b 0, d_i[3:0]} +
reg_F[0];
adr_o <= {d_i, zw_b1};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s565:
G19_1:
begin
if (rdy_i == 1'b 1 & reg_F[3] == 1'b 0)
if (rdy_i == 1'b 1)
begin
d_regs_in_o <= zw_ALU[7:0];
d_regs_in_o <= d_alu_i;
ch_a_o <= d_regs_out_i;
ch_b_o <= zw_b4;
load_regs_o <= 1'b 1;
zw_ALU <= {1'b 0, q_a_i} + {1'b 0, d_i} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & reg_F[3] == 1'b 1 )
end
G1_1:
begin
if (rdy_i == 1'b 1)
begin
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU[7:4] <= zw_ALU2[3:0] + zw_ALU6[2:0];
zw_ALU[3:0] <= zw_ALU1[3:0] + zw_ALU5[2:0];
zw_ALU6[2:0] <= {(zw_ALU2[4] | zw_ALU4[4]), (zw_ALU2[4] | zw_ALU4[4]),
1'b 0};
zw_ALU5[2:0] <= {(zw_ALU1[4] | zw_ALU3[4]), (zw_ALU1[4] | zw_ALU3[4]),
1'b 0};
zw_ALU4 <= {1'b 0, zw_ALU2[3:0]} + 6;
zw_ALU2 <= {1'b 0, q_a_i[7:4]} + {1'b 0, d_i[7:4]} +
(zw_ALU1[4] | zw_ALU3[4]);
zw_ALU3 <= {1'b 0, zw_ALU1[3:0]} + 6;
zw_ALU1 <= {1'b 0, q_a_i[3:0]} + {1'b 0, d_i[3:0]} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s566:
G20_2:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= 8'h 01;
adr_o <= {d_i, zw_b1};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s266:
G20_e:
begin
if (rdy_i == 1'b 1 & (reg_F[0] == 1'b 1 &
zw_REG_OP == 8'h 90 | reg_F[0] == 1'b 0 &
zw_REG_OP == 8'h B0 | reg_F[1] == 1'b 0 &
zw_REG_OP == 8'h F0 | reg_F[7] == 1'b 0 &
zw_REG_OP == 8'h 30 | reg_F[1] == 1'b 1 &
zw_REG_OP == 8'h D0 | reg_F[7] == 1'b 1 &
zw_REG_OP == 8'h 10 | reg_F[6] == 1'b 1 &
zw_REG_OP == 8'h 50 | reg_F[6] == 1'b 0 &
zw_REG_OP == 8'h 70))
if (rdy_i == 1'b 1)
begin
adr_o <= {d_i, zw_b1};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s301:
G21_1:
begin
if (rdy_i == 1'b 1 & zw_b3 == adr_nxt_pc_i[15:8])
if (rdy_i == 1'b 1)
begin
offset_o <= {zw_b2[7], zw_b2[7], zw_b2[7], zw_b2[7],
zw_b2[7], zw_b2[7], zw_b2[7], zw_b2[7],
zw_b2[7], zw_b2[6:0]};
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
ld_pc_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 )
begin
offset_o <= {zw_b2[7], zw_b2[7], zw_b2[7], zw_b2[7],
zw_b2[7], zw_b2[7], zw_b2[7], zw_b2[7],
zw_b2[7], zw_b2[6:0]};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s302:
G21_2:
begin
if (rdy_i == 1'b 1)
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
sig_WR <= 1'b 1;
sig_D_OUT <= adr_pc_i[15:8];
end
end
RES:
G21_3:
begin
sig_RWn <= 1'b 1;
sig_RD <= 1'b 1;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ld_sp_o <= 1'b 1;
sig_RWn <= 1'b 1;
sig_RD <= 1'b 1;
sig_WR <= 1'b 1;
sig_D_OUT <= adr_pc_i[7:0];
end
s511:
G21_e:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E5)
if (rdy_i == 1'b 1)
begin
adr_o <= {d_i, zw_b1};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E9 &
reg_F[3] == 1'b 0 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU <= {1'b 0, q_a_i} + {1'b 0, (~d_i)} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F5 )
end
G22_1:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h ED )
begin
sig_WR <= 1'b 1;
sig_D_OUT <= q_a_i;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ld_sp_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h FD )
end
G22_e:
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
G23_1:
begin
if (rdy_i == 1'b 1)
begin
sig_WR <= 1'b 1;
sig_D_OUT <= reg_F;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ld_sp_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F9 )
end
G23_e:
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
G24_1:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= q_y_i;
ld_sp_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F1 )
end
G24_e:
begin
if (rdy_i == 1'b 1)
begin
d_regs_in_o <= d_i;
load_regs_o <= 1'b 1;
ch_a_o <= d_i;
ch_b_o <= 8'h 01;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E1 )
begin
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E9 &
reg_F[3] == 1'b 1 )
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU[7:4] <= zw_ALU2[3:0] + zw_ALU6;
zw_ALU[3:0] <= zw_ALU1[3:0] + zw_ALU5;
zw_ALU6 <= {(zw_ALU4[4] | ~zw_ALU2[4]), 1'b 0, (zw_ALU4[4] |
~zw_ALU2[4]), 1'b 0};
zw_ALU5 <= {(zw_ALU3[4] | ~zw_ALU1[4]), 1'b 0, (zw_ALU3[4] |
~zw_ALU1[4]), 1'b 0};
zw_ALU4 <= {1'b 0, zw_ALU2[3:0]} + 6;
zw_ALU2 <= {1'b 0, q_a_i[7:4]} + {1'b 0, (~d_i[7:4])} +
zw_ALU1[4];
zw_ALU3 <= {1'b 0, zw_ALU1[3:0]} + 6;
zw_ALU1 <= {1'b 0, q_a_i[3:0]} + {1'b 0, (~d_i[3:0])} +
reg_F[0];
ch_b_o <= 8'h 00;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s559:
G25_1:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ld_sp_o <= 1'b 1;
end
end
s562:
G25_e:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= 8'h 01;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s567:
G26_1:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= 8'h 01;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ld_sp_o <= 1'b 1;
end
end
s568:
G26_2:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= q_y_i;
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
end
end
s569:
G26_3:
begin
if (rdy_i == 1'b 1)
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ld_sp_o <= 1'b 1;
end
end
s571:
G26_e:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= d_i;
ch_b_o <= 8'h 01;
adr_o <= {d_i, zw_b1};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s572:
G27_1:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= zw_b1;
ch_b_o <= 8'h 01;
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
end
end
s573:
G27_2:
begin
if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 0)
if (rdy_i == 1'b 1)
begin
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU <= {1'b 0, q_a_i} + {1'b 0, (~d_i)} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 &
reg_F[3] == 1'b 1 )
end
G27_4:
begin
if (rdy_i == 1'b 1)
begin
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU[7:4] <= zw_ALU2[3:0] + zw_ALU6;
zw_ALU[3:0] <= zw_ALU1[3:0] + zw_ALU5;
zw_ALU6 <= {(zw_ALU4[4] | ~zw_ALU2[4]), 1'b 0, (zw_ALU4[4] |
~zw_ALU2[4]), 1'b 0};
zw_ALU5 <= {(zw_ALU3[4] | ~zw_ALU1[4]), 1'b 0, (zw_ALU3[4] |
~zw_ALU1[4]), 1'b 0};
zw_ALU4 <= {1'b 0, zw_ALU2[3:0]} + 6;
zw_ALU2 <= {1'b 0, q_a_i[7:4]} + {1'b 0, (~d_i[7:4])} +
zw_ALU1[4];
zw_ALU3 <= {1'b 0, zw_ALU1[3:0]} + 6;
zw_ALU1 <= {1'b 0, q_a_i[3:0]} + {1'b 0, (~d_i[3:0])} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
adr_o <= {d_i, zw_b1};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
end
s574:
G27_e:
begin
if (rdy_i == 1'b 1 & reg_F[3] == 1'b 0)
if (rdy_i == 1'b 1)
begin
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU <= {1'b 0, q_a_i} + {1'b 0, (~d_i)} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & reg_F[3] == 1'b 1 )
begin
d_regs_in_o <= zw_ALU[7:0];
load_regs_o <= 1'b 1;
zw_ALU[7:4] <= zw_ALU2[3:0] + zw_ALU6;
zw_ALU[3:0] <= zw_ALU1[3:0] + zw_ALU5;
zw_ALU6 <= {(zw_ALU4[4] | ~zw_ALU2[4]), 1'b 0, (zw_ALU4[4] |
~zw_ALU2[4]), 1'b 0};
zw_ALU5 <= {(zw_ALU3[4] | ~zw_ALU1[4]), 1'b 0, (zw_ALU3[4] |
~zw_ALU1[4]), 1'b 0};
zw_ALU4 <= {1'b 0, zw_ALU2[3:0]} + 6;
zw_ALU2 <= {1'b 0, q_a_i[7:4]} + {1'b 0, (~d_i[7:4])} +
zw_ALU1[4];
zw_ALU3 <= {1'b 0, zw_ALU1[3:0]} + 6;
zw_ALU1 <= {1'b 0, q_a_i[3:0]} + {1'b 0, (~d_i[3:0])} +
reg_F[0];
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
s548:
G28_1:
begin
if (rdy_i == 1'b 1)
begin
6490,31 → 6126,25
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
ld_pc_o <= 1'b 1;
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= adr_pc_i[15:8];
end
end
s551:
G28_2:
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= adr_pc_i[7:0];
end
s552:
G28_3:
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= reg_F;
end
s577:
G28_e:
begin
if (rdy_i == 1'b 1)
begin
6522,7 → 6152,7
fetch_o <= 1'b 1;
end
end
s532:
G29_1:
begin
if (rdy_i == 1'b 1)
begin
6529,31 → 6159,25
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
ld_pc_o <= 1'b 1;
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= adr_pc_i[15:8];
end
end
s533:
G29_2:
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= adr_pc_i[7:0];
end
s534:
G29_3:
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
sig_RWn <= 1'b 0;
sig_RD <= 1'b 0;
sig_WR <= 1'b 1;
sig_D_OUT <= reg_F;
end
s537:
G29_e:
begin
if (rdy_i == 1'b 1)
begin
6564,6 → 6188,176
fetch_o <= 1'b 1;
end
end
G2_1:
begin
if (rdy_i == 1'b 1)
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
G30_1:
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
end
G30_2:
begin
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
end
G30_3:
begin
adr_o <= 16'h FFFB;
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
G30_4:
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
end
G30_e:
begin
if (rdy_i == 1'b 1)
begin
adr_o <= {d_i, zw_b1};
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
G31_1:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= {q_a_i[6:0], 1'b 0};
ch_b_o <= 8'h 00;
d_regs_in_o <= {q_a_i[6:0], 1'b 0};
load_regs_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
G32_1:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= {1'b 0, q_a_i[7:1]};
ch_b_o <= 8'h 00;
d_regs_in_o <= {1'b 0, q_a_i[7:1]};
load_regs_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
G33_1:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= {q_a_i[6:0], reg_F[0]};
ch_b_o <= 8'h 00;
d_regs_in_o <= {q_a_i[6:0], reg_F[0]};
load_regs_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
G34_1:
begin
if (rdy_i == 1'b 1)
begin
ch_a_o <= {reg_F[0], q_a_i[7:1]};
ch_b_o <= 8'h 00;
d_regs_in_o <= {reg_F[0], q_a_i[7:1]};
load_regs_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
G3_1:
begin
if (rdy_i == 1'b 1)
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
G4_1:
begin
if (rdy_i == 1'b 1)
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
G5_1:
begin
if (rdy_i == 1'b 1)
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
G6_1:
begin
if (rdy_i == 1'b 1)
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
G7_1:
begin
if (rdy_i == 1'b 1)
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
G8_1:
begin
if (rdy_i == 1'b 1)
begin
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
G9_1:
begin
if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 9A)
begin
adr_o <= {8'h 01, d_regs_out_i};
ld_o <= 2'b 11;
ld_sp_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h BA )
begin
d_regs_in_o <= adr_sp_i[7:0];
ch_a_o <= adr_sp_i[7:0];
ch_b_o <= 8'h 00;
load_regs_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
else if (rdy_i == 1'b 1 )
begin
ch_a_o <= d_regs_out_i;
ch_b_o <= 8'h 00;
load_regs_o <= 1'b 1;
sig_SYNC <= 1'b 1;
fetch_o <= 1'b 1;
end
end
RES:
begin
ld_o <= 2'b 11;
ld_pc_o <= 1'b 1;
ld_sp_o <= 1'b 1;
end
default:
;
endcase
6577,7 → 6371,6
assign d_o = d_o_cld;
assign rd_o = rd_o_cld;
assign sync_o = sync_o_cld;
assign wr_n_o = wr_n_o_cld;
assign wr_o = wr_o_cld;
 
// Architecture Declarations
/trunk/rtl/verilog_TRIAL/core.v
3,14 → 3,14
`define true 1'b 1
`define TRUE 1'b 1
 
`timescale 1 ns / 1 ns
`timescale 1 ns / 1 ns // timescale for following modules
 
 
// Verilog Entity R6502_TC.Core.symbol
// VHDL Entity R6502_TC.Core.symbol
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 19:21:54 07.01.2009
// by - eda.UNKNOWN (ENTWICKL4-XP-PR)
// at - 11:47:55 23.02.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
27,7 → 27,6
d_o,
rd_o,
sync_o,
wr_n_o,
wr_o);
 
42,13 → 41,12
output [7:0] d_o;
output rd_o;
output sync_o;
output wr_n_o;
output wr_o;
 
 
// Jens-D. Gutschmidt Project: R6502_TC
// scantara2003@yahoo.de
// COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
// COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG
//
// This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version
// 3 of the License, or any later version.
64,13 → 62,13
// <<-- more -->>
// Title: Core
// Path: R6502_TC/Core/struct
// Edited: by eda on 07 Jan 2009
// Edited: by eda on 10 Feb 2009
//
// Verilog Architecture R6502_TC.Core.struct
// VHDL Architecture R6502_TC.Core.struct
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 19:21:55 07.01.2009
// by - eda.UNKNOWN (ENTWICKL4-XP-PR)
// at - 11:47:57 23.02.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
78,7 → 76,6
wire [7:0] d_o;
wire rd_o;
wire sync_o;
wire wr_n_o;
wire wr_o;
 
// Declarations
89,7 → 86,7
wire [7:0] ch_a_o_i;
wire [7:0] ch_b_o_i;
wire d_alu_n_o_i;
reg [7:0] d_alu_o_i;
wire [7:0] d_alu_o_i;
wire d_alu_or_o_i;
wire [7:0] d_regs_in_o_i;
wire [7:0] d_regs_out_o_i;
103,7 → 100,7
wire [7:0] q_a_o_i;
wire [7:0] q_x_o_i;
wire [7:0] q_y_o_i;
reg reg_0flag_o_i;
wire reg_0flag_o_i;
wire reg_1flag_o_i;
wire reg_7flag_o_i;
wire sel_pc_in_o_i;
114,25 → 111,32
wire sel_sp_as_o_i;
wire sel_sp_in_o_i;
 
// ModuleWare signal declarations(v1.9) for instance 'U_11' of 'add'
wire [8:0] mw_U_11temp_din0;
wire [8:0] mw_U_11temp_din1;
reg [8:0] mw_U_11sum;
 
// Component Declarations
 
// Optional embedded configurations
// pragma synthesis_off
 
// pragma synthesis_on
// ModuleWare code(v1.9) for instance 'U_11' of 'add'
reg [8:0] u_11combo_proc_temp_din0;
reg [8:0] u_11combo_proc_temp_din1;
reg [8:0] u_11combo_proc_temp_sum;
reg u_11combo_proc_temp_carry;
 
assign mw_U_11temp_din0 = {1'b 0, ch_a_o_i};
assign mw_U_11temp_din1 = {1'b 0, ch_b_o_i};
 
always @(ch_a_o_i or ch_b_o_i)
always @(mw_U_11temp_din0 or mw_U_11temp_din1)
begin : u_11combo_proc
u_11combo_proc_temp_din0 = {1'b 0, ch_a_o_i};
u_11combo_proc_temp_din1 = {1'b 0, ch_b_o_i};
u_11combo_proc_temp_carry = 1'b 0;
u_11combo_proc_temp_sum = u_11combo_proc_temp_din0 + u_11combo_proc_temp_din1 + u_11combo_proc_temp_carry;
d_alu_o_i <= u_11combo_proc_temp_sum[7:0];
reg_0flag_o_i <= u_11combo_proc_temp_sum[8];
mw_U_11sum <= mw_U_11temp_din0 + mw_U_11temp_din1 + u_11combo_proc_temp_carry;
end
 
assign d_alu_o_i = mw_U_11sum[7:0];
assign reg_0flag_o_i = mw_U_11sum[8];
 
// ModuleWare code(v1.9) for instance 'U_8' of 'inv'
assign reg_1flag_o_i = ~d_alu_or_o_i;
 
186,7 → 190,6
.sel_sp_as_o(sel_sp_as_o_i),
.sel_sp_in_o(sel_sp_in_o_i),
.sync_o(sync_o),
.wr_n_o(wr_n_o),
.wr_o(wr_o));
FSM_NMI U_6 (.clk_clk_i(clk_clk_i),
.fetch_i(fetch_o_i),
/trunk/rtl/verilog_TRIAL/fsm_nmi.v
3,14 → 3,14
`define true 1'b 1
`define TRUE 1'b 1
 
`timescale 1 ns / 1 ns
`timescale 1 ns / 1 ns // timescale for following modules
 
 
// Verilog Entity R6502_TC.FSM_NMI.symbol
// VHDL Entity R6502_TC.FSM_NMI.symbol
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 18:46:08 07.01.2009
// at - 19:25:41 10.02.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
32,7 → 32,7
 
// Jens-D. Gutschmidt Project: R6502_TC
// scantara2003@yahoo.de
// COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
// COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG
//
// This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or any later version.
48,13 → 48,13
// <<-- more -->>
// Title: FSM for NMI
// Path: R6502_TC/FSM_NMI/fsm
// Edited: by eda on 07 Jan 2009
// Edited: by eda on 10 Feb 2009
//
// Verilog Architecture R6502_TC.FSM_NMI.fsm
// VHDL Architecture R6502_TC.FSM_NMI.fsm
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 18:46:08 07.01.2009
// at - 19:25:41 10.02.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
/trunk/rtl/verilog_TRIAL/regbank_axy.v
3,14 → 3,14
`define true 1'b 1
`define TRUE 1'b 1
 
`timescale 1 ns / 1 ns
`timescale 1 ns / 1 ns // timescale for following modules
 
 
// Verilog Entity R6502_TC.RegBank_AXY.symbol
// VHDL Entity R6502_TC.RegBank_AXY.symbol
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 18:23:46 07.01.2009
// at - 19:25:32 10.02.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
44,7 → 44,7
 
// Jens-D. Gutschmidt Project: R6502_TC
// scantara2003@yahoo.de
// COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
// COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG
//
// This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or any later version.
60,13 → 60,13
// <<-- more -->>
// Title: Register Bank for register A, X and Y
// Path: R6502_TC/RegBank_AXY/struct
// Edited: by eda on 02 Jan 2009
// Edited: by eda on 10 Feb 2009
//
// Verilog Architecture R6502_TC.RegBank_AXY.struct
// VHDL Architecture R6502_TC.RegBank_AXY.struct
//
// Created:
// by - eda.UNKNOWN (TEST)
// at - 18:23:46 07.01.2009
// at - 19:25:32 10.02.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
/trunk/rtl/vhdl/reg_pc.vhd
2,7 → 2,7
--
-- Created:
-- by - eda.UNKNOWN (TEST)
-- at - 19:07:21 07.01.2009
-- at - 19:25:31 10.02.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
30,7 → 30,7
 
-- Jens-D. Gutschmidt Project: R6502_TC
-- scantara2003@yahoo.de
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
-- COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any later version.
46,13 → 46,13
-- <<-- more -->>
-- Title: Program Counter Logic
-- Path: R6502_TC/Reg_PC/struct
-- Edited: by eda on 07 Jan 2009
-- Edited: by eda on 10 Feb 2009
--
-- VHDL Architecture R6502_TC.Reg_PC.struct
--
-- Created:
-- by - eda.UNKNOWN (TEST)
-- at - 19:07:21 07.01.2009
-- at - 19:25:32 10.02.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
/trunk/rtl/vhdl/reg_sp.vhd
2,7 → 2,7
--
-- Created:
-- by - eda.UNKNOWN (TEST)
-- at - 18:23:46 07.01.2009
-- at - 19:25:32 10.02.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
28,7 → 28,7
 
-- Jens-D. Gutschmidt Project: R6502_TC
-- scantara2003@yahoo.de
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
-- COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any later version.
44,13 → 44,13
-- <<-- more -->>
-- Title: Stack Pointer Logic
-- Path: R6502_TC/Reg_SP/struct
-- Edited: by eda on 01 Jan 2009
-- Edited: by eda on 10 Feb 2009
--
-- VHDL Architecture R6502_TC.Reg_SP.struct
--
-- Created:
-- by - eda.UNKNOWN (TEST)
-- at - 18:23:46 07.01.2009
-- at - 19:25:32 10.02.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
/trunk/rtl/vhdl/r6502_tc.vhd
1,8 → 1,8
-- VHDL Entity R6502_TC.R6502_TC.symbol
--
-- Created:
-- by - eda.UNKNOWN (TEST)
-- at - 19:21:55 07.01.2009
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 11:47:57 23.02.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
10,30 → 10,29
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ENTITY R6502_TC IS
PORT(
clk_clk_i : IN std_logic;
d_i : IN std_logic_vector (7 DOWNTO 0);
irq_n_i : IN std_logic;
nmi_n_i : IN std_logic;
rdy_i : IN std_logic;
rst_rst_n_i : IN std_logic;
so_n_i : IN std_logic;
a_o : OUT std_logic_vector (15 DOWNTO 0);
d_o : OUT std_logic_vector (7 DOWNTO 0);
rd_o : OUT std_logic;
sync_o : OUT std_logic;
wr_n_o : OUT std_logic;
wr_o : OUT std_logic
entity R6502_TC is
port(
clk_clk_i : in std_logic;
d_i : in std_logic_vector (7 downto 0);
irq_n_i : in std_logic;
nmi_n_i : in std_logic;
rdy_i : in std_logic;
rst_rst_n_i : in std_logic;
so_n_i : in std_logic;
a_o : out std_logic_vector (15 downto 0);
d_o : out std_logic_vector (7 downto 0);
rd_o : out std_logic;
sync_o : out std_logic;
wr_o : out std_logic
);
 
-- Declarations
 
END R6502_TC ;
end R6502_TC ;
 
-- Jens-D. Gutschmidt Project: R6502_TC
-- scantara2003@yahoo.de
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
-- COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any later version.
49,13 → 48,13
-- <<-- more -->>
-- Title: Top Level
-- Path: R6502_TC/R6502_TC/struct
-- Edited: by eda on 04 Jan 2009
-- Edited: by eda on 10 Feb 2009
--
-- VHDL Architecture R6502_TC.R6502_TC.struct
--
-- Created:
-- by - eda.UNKNOWN (TEST)
-- at - 19:21:55 07.01.2009
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 11:47:58 23.02.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
62,8 → 61,9
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
library R6502_TC;
 
ARCHITECTURE struct OF R6502_TC IS
architecture struct of R6502_TC is
 
-- Architecture declarations
 
71,30 → 71,34
 
 
-- Component Declarations
COMPONENT Core
PORT (
clk_clk_i : IN std_logic ;
d_i : IN std_logic_vector (7 DOWNTO 0);
irq_n_i : IN std_logic ;
nmi_n_i : IN std_logic ;
rdy_i : IN std_logic ;
rst_rst_n_i : IN std_logic ;
so_n_i : IN std_logic ;
a_o : OUT std_logic_vector (15 DOWNTO 0);
d_o : OUT std_logic_vector (7 DOWNTO 0);
rd_o : OUT std_logic ;
sync_o : OUT std_logic ;
wr_n_o : OUT std_logic ;
wr_o : OUT std_logic
component Core
port (
clk_clk_i : in std_logic ;
d_i : in std_logic_vector (7 downto 0);
irq_n_i : in std_logic ;
nmi_n_i : in std_logic ;
rdy_i : in std_logic ;
rst_rst_n_i : in std_logic ;
so_n_i : in std_logic ;
a_o : out std_logic_vector (15 downto 0);
d_o : out std_logic_vector (7 downto 0);
rd_o : out std_logic ;
sync_o : out std_logic ;
wr_o : out std_logic
);
END COMPONENT;
end component;
 
-- Optional embedded configurations
-- pragma synthesis_off
for all : Core use entity R6502_TC.Core;
-- pragma synthesis_on
 
BEGIN
 
begin
 
-- Instance port mappings.
U_0 : Core
PORT MAP (
port map (
clk_clk_i => clk_clk_i,
d_i => d_i,
irq_n_i => irq_n_i,
106,8 → 110,7
d_o => d_o,
rd_o => rd_o,
sync_o => sync_o,
wr_n_o => wr_n_o,
wr_o => wr_o
);
 
END struct;
end struct;
/trunk/rtl/vhdl/fsm_execution_unit.vhd
1,8 → 1,8
-- VHDL Entity R6502_TC.FSM_Execution_Unit.symbol
--
-- Created:
-- by - eda.UNKNOWN (TEST)
-- at - 19:21:47 07.01.2009
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 11:47:40 23.02.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
10,60 → 10,59
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ENTITY FSM_Execution_Unit IS
PORT(
adr_nxt_pc_i : IN std_logic_vector (15 DOWNTO 0);
adr_pc_i : IN std_logic_vector (15 DOWNTO 0);
adr_sp_i : IN std_logic_vector (15 DOWNTO 0);
clk_clk_i : IN std_logic;
d_alu_i : IN std_logic_vector ( 7 DOWNTO 0 );
d_i : IN std_logic_vector ( 7 DOWNTO 0 );
d_regs_out_i : IN std_logic_vector ( 7 DOWNTO 0 );
irq_n_i : IN std_logic;
nmi_i : IN std_logic;
q_a_i : IN std_logic_vector ( 7 DOWNTO 0 );
q_x_i : IN std_logic_vector ( 7 DOWNTO 0 );
q_y_i : IN std_logic_vector ( 7 DOWNTO 0 );
rdy_i : IN std_logic;
reg_0flag_i : IN std_logic;
reg_1flag_i : IN std_logic;
reg_7flag_i : IN std_logic;
rst_rst_n_i : IN std_logic;
so_n_i : IN std_logic;
a_o : OUT std_logic_vector (15 DOWNTO 0);
adr_o : OUT std_logic_vector (15 DOWNTO 0);
ch_a_o : OUT std_logic_vector ( 7 DOWNTO 0 );
ch_b_o : OUT std_logic_vector ( 7 DOWNTO 0 );
d_o : OUT std_logic_vector ( 7 DOWNTO 0 );
d_regs_in_o : OUT std_logic_vector ( 7 DOWNTO 0 );
fetch_o : OUT std_logic;
ld_o : OUT std_logic_vector ( 1 DOWNTO 0 );
ld_pc_o : OUT std_logic;
ld_sp_o : OUT std_logic;
load_regs_o : OUT std_logic;
offset_o : OUT std_logic_vector ( 15 DOWNTO 0 );
rd_o : OUT std_logic;
sel_pc_in_o : OUT std_logic;
sel_pc_val_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_rb_in_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_rb_out_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_reg_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_sp_as_o : OUT std_logic;
sel_sp_in_o : OUT std_logic;
sync_o : OUT std_logic;
wr_n_o : OUT std_logic;
wr_o : OUT std_logic
entity FSM_Execution_Unit is
port(
adr_nxt_pc_i : in std_logic_vector (15 downto 0);
adr_pc_i : in std_logic_vector (15 downto 0);
adr_sp_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic;
d_alu_i : in std_logic_vector ( 7 downto 0 );
d_i : in std_logic_vector ( 7 downto 0 );
d_regs_out_i : in std_logic_vector ( 7 downto 0 );
irq_n_i : in std_logic;
nmi_i : in std_logic;
q_a_i : in std_logic_vector ( 7 downto 0 );
q_x_i : in std_logic_vector ( 7 downto 0 );
q_y_i : in std_logic_vector ( 7 downto 0 );
rdy_i : in std_logic;
reg_0flag_i : in std_logic;
reg_1flag_i : in std_logic;
reg_7flag_i : in std_logic;
rst_rst_n_i : in std_logic;
so_n_i : in std_logic;
a_o : out std_logic_vector (15 downto 0);
adr_o : out std_logic_vector (15 downto 0);
ch_a_o : out std_logic_vector ( 7 downto 0 );
ch_b_o : out std_logic_vector ( 7 downto 0 );
d_o : out std_logic_vector ( 7 downto 0 );
d_regs_in_o : out std_logic_vector ( 7 downto 0 );
fetch_o : out std_logic;
ld_o : out std_logic_vector ( 1 downto 0 );
ld_pc_o : out std_logic;
ld_sp_o : out std_logic;
load_regs_o : out std_logic;
offset_o : out std_logic_vector ( 15 downto 0 );
rd_o : out std_logic;
sel_pc_in_o : out std_logic;
sel_pc_val_o : out std_logic_vector ( 1 downto 0 );
sel_rb_in_o : out std_logic_vector ( 1 downto 0 );
sel_rb_out_o : out std_logic_vector ( 1 downto 0 );
sel_reg_o : out std_logic_vector ( 1 downto 0 );
sel_sp_as_o : out std_logic;
sel_sp_in_o : out std_logic;
sync_o : out std_logic;
wr_o : out std_logic
);
 
-- Declarations
 
END FSM_Execution_Unit ;
end FSM_Execution_Unit ;
 
-- Jens-D. Gutschmidt Project: R6502_TC
 
-- scantara2003@yahoo.de
 
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
-- COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG
 
--
 
95,223 → 94,213
 
-- Path: R6502_TC/FSM_Execution_Unit/fsm
 
-- Edited: by eda on 07 Jan 2009
-- Edited: by eda on 23 Feb 2009
 
--
-- VHDL Architecture R6502_TC.FSM_Execution_Unit.fsm
--
-- Created:
-- by - eda.UNKNOWN (TEST)
-- at - 19:21:50 07.01.2009
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 11:47:41 23.02.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.ALL;
ARCHITECTURE fsm OF FSM_Execution_Unit IS
architecture fsm of FSM_Execution_Unit is
 
-- Architecture Declarations
SIGNAL reg_F : std_logic_vector( 7 DOWNTO 0 );
SIGNAL reg_sel_pc_in : std_logic;
SIGNAL reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 );
SIGNAL reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 );
SIGNAL reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 );
SIGNAL reg_sel_reg : std_logic_vector( 1 DOWNTO 0 );
SIGNAL reg_sel_sp_as : std_logic;
SIGNAL reg_sel_sp_in : std_logic;
SIGNAL sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );
SIGNAL sig_PC : std_logic_vector(15 DOWNTO 0);
SIGNAL sig_RD : std_logic;
SIGNAL sig_RWn : std_logic;
SIGNAL sig_SYNC : std_logic;
SIGNAL sig_WR : std_logic;
SIGNAL zw_ALU : std_logic_vector( 8 DOWNTO 0 );
SIGNAL zw_ALU1 : std_logic_vector( 4 DOWNTO 0 );
SIGNAL zw_ALU2 : std_logic_vector( 4 DOWNTO 0 );
SIGNAL zw_ALU3 : std_logic_vector( 4 DOWNTO 0 );
SIGNAL zw_ALU4 : std_logic_vector( 4 DOWNTO 0 );
SIGNAL zw_ALU5 : std_logic_vector( 3 DOWNTO 0 );
SIGNAL zw_ALU6 : std_logic_vector( 3 DOWNTO 0 );
SIGNAL zw_REG_NMI : std_logic;
SIGNAL zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );
SIGNAL zw_b1 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL zw_b2 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL zw_b3 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL zw_b4 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL zw_so : std_logic;
signal reg_F : std_logic_vector( 7 DOWNTO 0 );
signal reg_sel_pc_in : std_logic;
signal reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_reg : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_sp_as : std_logic;
signal reg_sel_sp_in : std_logic;
signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );
signal sig_PC : std_logic_vector(15 DOWNTO 0);
signal sig_SYNC : std_logic;
signal sig_WR : std_logic;
signal zw_ALU : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU1 : std_logic_vector( 4 DOWNTO 0 );
signal zw_ALU2 : std_logic_vector( 4 DOWNTO 0 );
signal zw_ALU3 : std_logic_vector( 4 DOWNTO 0 );
signal zw_ALU4 : std_logic_vector( 4 DOWNTO 0 );
signal zw_ALU5 : std_logic_vector( 3 DOWNTO 0 );
signal zw_ALU6 : std_logic_vector( 3 DOWNTO 0 );
signal zw_REG_NMI : std_logic;
signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );
signal zw_b1 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b2 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b3 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b4 : std_logic_vector( 7 DOWNTO 0 );
signal zw_so : std_logic;
 
SUBTYPE STATE_TYPE IS
std_logic_vector(7 DOWNTO 0);
subtype state_type is
std_logic_vector(7 downto 0);
-- Hard encoding
CONSTANT FETCH : STATE_TYPE := "00000000";
CONSTANT s1 : STATE_TYPE := "00000001";
CONSTANT s2 : STATE_TYPE := "00000011";
CONSTANT s5 : STATE_TYPE := "00000010";
CONSTANT s3 : STATE_TYPE := "00000110";
CONSTANT s4 : STATE_TYPE := "00000111";
CONSTANT s12 : STATE_TYPE := "00000101";
CONSTANT s16 : STATE_TYPE := "00000100";
CONSTANT s17 : STATE_TYPE := "00001100";
CONSTANT s24 : STATE_TYPE := "00001101";
CONSTANT s25 : STATE_TYPE := "00001111";
CONSTANT s271 : STATE_TYPE := "00001110";
CONSTANT s273 : STATE_TYPE := "00001010";
CONSTANT s304 : STATE_TYPE := "00001011";
CONSTANT s307 : STATE_TYPE := "00001001";
CONSTANT s177 : STATE_TYPE := "00001000";
CONSTANT s180 : STATE_TYPE := "00011000";
CONSTANT s181 : STATE_TYPE := "00011001";
CONSTANT s182 : STATE_TYPE := "00011011";
CONSTANT s183 : STATE_TYPE := "00011010";
CONSTANT s184 : STATE_TYPE := "00011110";
CONSTANT s185 : STATE_TYPE := "00011111";
CONSTANT s186 : STATE_TYPE := "00011101";
CONSTANT s187 : STATE_TYPE := "00011100";
CONSTANT s188 : STATE_TYPE := "00010100";
CONSTANT s189 : STATE_TYPE := "00010101";
CONSTANT s190 : STATE_TYPE := "00010111";
CONSTANT s191 : STATE_TYPE := "00010110";
CONSTANT s192 : STATE_TYPE := "00010010";
CONSTANT s193 : STATE_TYPE := "00010011";
CONSTANT s377 : STATE_TYPE := "00010001";
CONSTANT s381 : STATE_TYPE := "00010000";
CONSTANT s378 : STATE_TYPE := "00110000";
CONSTANT s382 : STATE_TYPE := "00110001";
CONSTANT s379 : STATE_TYPE := "00110011";
CONSTANT s383 : STATE_TYPE := "00110010";
CONSTANT s384 : STATE_TYPE := "00110110";
CONSTANT s380 : STATE_TYPE := "00110111";
CONSTANT s385 : STATE_TYPE := "00110101";
CONSTANT s386 : STATE_TYPE := "00110100";
CONSTANT s387 : STATE_TYPE := "00111100";
CONSTANT s388 : STATE_TYPE := "00111101";
CONSTANT s389 : STATE_TYPE := "00111111";
CONSTANT s391 : STATE_TYPE := "00111110";
CONSTANT s392 : STATE_TYPE := "00111010";
CONSTANT s390 : STATE_TYPE := "00111011";
CONSTANT s393 : STATE_TYPE := "00111001";
CONSTANT s394 : STATE_TYPE := "00111000";
CONSTANT s395 : STATE_TYPE := "00101000";
CONSTANT s396 : STATE_TYPE := "00101001";
CONSTANT s397 : STATE_TYPE := "00101011";
CONSTANT s398 : STATE_TYPE := "00101010";
CONSTANT s399 : STATE_TYPE := "00101110";
CONSTANT s400 : STATE_TYPE := "00101111";
CONSTANT s401 : STATE_TYPE := "00101101";
CONSTANT s526 : STATE_TYPE := "00101100";
CONSTANT s527 : STATE_TYPE := "00100100";
CONSTANT s528 : STATE_TYPE := "00100101";
CONSTANT s529 : STATE_TYPE := "00100111";
CONSTANT s530 : STATE_TYPE := "00100110";
CONSTANT s531 : STATE_TYPE := "00100010";
CONSTANT s544 : STATE_TYPE := "00100011";
CONSTANT s545 : STATE_TYPE := "00100001";
CONSTANT s546 : STATE_TYPE := "00100000";
CONSTANT s547 : STATE_TYPE := "01100000";
CONSTANT s549 : STATE_TYPE := "01100001";
CONSTANT s550 : STATE_TYPE := "01100011";
CONSTANT s404 : STATE_TYPE := "01100010";
CONSTANT s556 : STATE_TYPE := "01100110";
CONSTANT s557 : STATE_TYPE := "01100111";
CONSTANT s579 : STATE_TYPE := "01100101";
CONSTANT s201 : STATE_TYPE := "01100100";
CONSTANT s202 : STATE_TYPE := "01101100";
CONSTANT s210 : STATE_TYPE := "01101101";
CONSTANT s211 : STATE_TYPE := "01101111";
CONSTANT s215 : STATE_TYPE := "01101110";
CONSTANT s217 : STATE_TYPE := "01101010";
CONSTANT s218 : STATE_TYPE := "01101011";
CONSTANT s222 : STATE_TYPE := "01101001";
CONSTANT s223 : STATE_TYPE := "01101000";
CONSTANT s224 : STATE_TYPE := "01111000";
CONSTANT s225 : STATE_TYPE := "01111001";
CONSTANT s226 : STATE_TYPE := "01111011";
CONSTANT s243 : STATE_TYPE := "01111010";
CONSTANT s244 : STATE_TYPE := "01111110";
CONSTANT s247 : STATE_TYPE := "01111111";
CONSTANT s344 : STATE_TYPE := "01111101";
CONSTANT s343 : STATE_TYPE := "01111100";
CONSTANT s250 : STATE_TYPE := "01110100";
CONSTANT s251 : STATE_TYPE := "01110101";
CONSTANT s351 : STATE_TYPE := "01110111";
CONSTANT s361 : STATE_TYPE := "01110110";
CONSTANT s360 : STATE_TYPE := "01110010";
CONSTANT s403 : STATE_TYPE := "01110011";
CONSTANT s406 : STATE_TYPE := "01110001";
CONSTANT s407 : STATE_TYPE := "01110000";
CONSTANT s409 : STATE_TYPE := "01010000";
CONSTANT s412 : STATE_TYPE := "01010001";
CONSTANT s413 : STATE_TYPE := "01010011";
CONSTANT s416 : STATE_TYPE := "01010010";
CONSTANT s418 : STATE_TYPE := "01010110";
CONSTANT s510 : STATE_TYPE := "01010111";
CONSTANT s553 : STATE_TYPE := "01010101";
CONSTANT s555 : STATE_TYPE := "01010100";
CONSTANT s558 : STATE_TYPE := "01011100";
CONSTANT s560 : STATE_TYPE := "01011101";
CONSTANT s561 : STATE_TYPE := "01011111";
CONSTANT s563 : STATE_TYPE := "01011110";
CONSTANT s564 : STATE_TYPE := "01011010";
CONSTANT s565 : STATE_TYPE := "01011011";
CONSTANT s566 : STATE_TYPE := "01011001";
CONSTANT s266 : STATE_TYPE := "01011000";
CONSTANT s301 : STATE_TYPE := "01001000";
CONSTANT s302 : STATE_TYPE := "01001001";
CONSTANT RES : STATE_TYPE := "01001011";
CONSTANT s511 : STATE_TYPE := "01001010";
CONSTANT s559 : STATE_TYPE := "01001110";
CONSTANT s562 : STATE_TYPE := "01001111";
CONSTANT s567 : STATE_TYPE := "01001101";
CONSTANT s568 : STATE_TYPE := "01001100";
CONSTANT s569 : STATE_TYPE := "01000100";
CONSTANT s570 : STATE_TYPE := "01000101";
CONSTANT s571 : STATE_TYPE := "01000111";
CONSTANT s572 : STATE_TYPE := "01000110";
CONSTANT s573 : STATE_TYPE := "01000010";
CONSTANT s574 : STATE_TYPE := "01000011";
CONSTANT s548 : STATE_TYPE := "01000001";
CONSTANT s551 : STATE_TYPE := "01000000";
CONSTANT s552 : STATE_TYPE := "11000000";
CONSTANT s575 : STATE_TYPE := "11000001";
CONSTANT s576 : STATE_TYPE := "11000011";
CONSTANT s577 : STATE_TYPE := "11000010";
CONSTANT s532 : STATE_TYPE := "11000110";
CONSTANT s533 : STATE_TYPE := "11000111";
CONSTANT s534 : STATE_TYPE := "11000101";
CONSTANT s535 : STATE_TYPE := "11000100";
CONSTANT s536 : STATE_TYPE := "11001100";
CONSTANT s537 : STATE_TYPE := "11001101";
constant FETCH : state_type := "00000000";
constant G10_1 : state_type := "00000001";
constant G10_2 : state_type := "00000010";
constant G10_3 : state_type := "00000011";
constant G10_4 : state_type := "00000100";
constant G10_5 : state_type := "00000101";
constant G10_6 : state_type := "00000110";
constant G10_7 : state_type := "00000111";
constant G10_e1 : state_type := "00001000";
constant G10_e2 : state_type := "00001001";
constant G10_e3 : state_type := "00001010";
constant G11_1 : state_type := "00001011";
constant G11_2 : state_type := "00001100";
constant G11_3 : state_type := "00001101";
constant G11_4 : state_type := "00001110";
constant G11_5 : state_type := "00001111";
constant G11_6 : state_type := "00010000";
constant G11_7 : state_type := "00010001";
constant G11_e : state_type := "00010010";
constant G12_1 : state_type := "00010011";
constant G12_e1 : state_type := "00010100";
constant G12_e2 : state_type := "00010101";
constant G13_1 : state_type := "00010110";
constant G13_2 : state_type := "00010111";
constant G13_e : state_type := "00011000";
constant G14_1 : state_type := "00011001";
constant G14_2 : state_type := "00011010";
constant G14_3 : state_type := "00011011";
constant G14_4 : state_type := "00011100";
constant G14_5 : state_type := "00011101";
constant G14_6 : state_type := "00011110";
constant G14_7 : state_type := "00011111";
constant G14_e : state_type := "00100000";
constant G15_1 : state_type := "00100001";
constant G15_2 : state_type := "00100010";
constant G15_3 : state_type := "00100011";
constant G15_4 : state_type := "00100100";
constant G15_5 : state_type := "00100101";
constant G15_6 : state_type := "00100110";
constant G15_7 : state_type := "00100111";
constant G15_e1 : state_type := "00101000";
constant G15_e2 : state_type := "00101001";
constant G15_e3 : state_type := "00101010";
constant G16_1 : state_type := "00101011";
constant G16_2 : state_type := "00101100";
constant G16_3 : state_type := "00101101";
constant G16_4 : state_type := "00101110";
constant G16_5 : state_type := "00101111";
constant G16_6 : state_type := "00110000";
constant G16_7 : state_type := "00110001";
constant G16_e1 : state_type := "00110010";
constant G16_e2 : state_type := "00110011";
constant G16_e3 : state_type := "00110100";
constant G17_1 : state_type := "00110101";
constant G17_10 : state_type := "00110110";
constant G17_2 : state_type := "00110111";
constant G17_3 : state_type := "00111000";
constant G17_4 : state_type := "00111001";
constant G17_5 : state_type := "00111010";
constant G17_6 : state_type := "00111011";
constant G17_7 : state_type := "00111100";
constant G17_8 : state_type := "00111101";
constant G17_9 : state_type := "00111110";
constant G17_e : state_type := "00111111";
constant G18_1 : state_type := "01000000";
constant G18_2 : state_type := "01000001";
constant G18_3 : state_type := "01000010";
constant G18_4 : state_type := "01000011";
constant G18_5 : state_type := "01000100";
constant G18_e : state_type := "01000101";
constant G19_1 : state_type := "01000110";
constant G1_1 : state_type := "01000111";
constant G20_1 : state_type := "01001000";
constant G20_2 : state_type := "01001001";
constant G20_3 : state_type := "01001010";
constant G20_e : state_type := "01001011";
constant G21_1 : state_type := "01001100";
constant G21_2 : state_type := "01001101";
constant G21_3 : state_type := "01001110";
constant G21_4 : state_type := "01001111";
constant G21_e : state_type := "01010000";
constant G22_1 : state_type := "01010001";
constant G22_e : state_type := "01010010";
constant G23_1 : state_type := "01010011";
constant G23_e : state_type := "01010100";
constant G24_1 : state_type := "01010101";
constant G24_2 : state_type := "01010110";
constant G24_e : state_type := "01010111";
constant G25_1 : state_type := "01011000";
constant G25_2 : state_type := "01011001";
constant G25_e : state_type := "01011010";
constant G26_1 : state_type := "01011011";
constant G26_2 : state_type := "01011100";
constant G26_3 : state_type := "01011101";
constant G26_4 : state_type := "01011110";
constant G26_e : state_type := "01011111";
constant G27_1 : state_type := "01100000";
constant G27_2 : state_type := "01100001";
constant G27_3 : state_type := "01100010";
constant G27_4 : state_type := "01100011";
constant G27_e : state_type := "01100100";
constant G28_1 : state_type := "01100101";
constant G28_2 : state_type := "01100110";
constant G28_3 : state_type := "01100111";
constant G28_4 : state_type := "01101000";
constant G28_5 : state_type := "01101001";
constant G28_e : state_type := "01101010";
constant G29_1 : state_type := "01101011";
constant G29_2 : state_type := "01101100";
constant G29_3 : state_type := "01101101";
constant G29_4 : state_type := "01101110";
constant G29_5 : state_type := "01101111";
constant G29_e : state_type := "01110000";
constant G2_1 : state_type := "01110001";
constant G30_1 : state_type := "01110010";
constant G30_2 : state_type := "01110011";
constant G30_3 : state_type := "01110100";
constant G30_4 : state_type := "01110101";
constant G30_5 : state_type := "01110110";
constant G30_e : state_type := "01110111";
constant G31_1 : state_type := "01111000";
constant G32_1 : state_type := "01111001";
constant G33_1 : state_type := "01111010";
constant G34_1 : state_type := "01111011";
constant G3_1 : state_type := "01111100";
constant G4_1 : state_type := "01111101";
constant G5_1 : state_type := "01111110";
constant G6_1 : state_type := "01111111";
constant G7_1 : state_type := "10000000";
constant G8_1 : state_type := "10000001";
constant G9_1 : state_type := "10000010";
constant RES : state_type := "10000011";
 
-- Declare current and next state signals
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;
signal current_state : state_type;
signal next_state : state_type;
 
-- Declare any pre-registered internal signals
SIGNAL d_o_cld : std_logic_vector ( 7 DOWNTO 0 );
SIGNAL rd_o_cld : std_logic ;
SIGNAL sync_o_cld : std_logic ;
SIGNAL wr_n_o_cld : std_logic ;
SIGNAL wr_o_cld : std_logic ;
signal d_o_cld : std_logic_vector ( 7 downto 0 );
signal rd_o_cld : std_logic ;
signal sync_o_cld : std_logic ;
signal wr_o_cld : std_logic ;
 
BEGIN
begin
 
-----------------------------------------------------------------
clocked_proc : PROCESS (
clocked_proc : process (
clk_clk_i,
rst_rst_n_i
)
-----------------------------------------------------------------
BEGIN
IF (rst_rst_n_i = '0') THEN
begin
if (rst_rst_n_i = '0') then
current_state <= RES;
-- Default Reset Values
d_o_cld <= X"00";
rd_o_cld <= '0';
sync_o_cld <= '0';
wr_n_o_cld <= '1';
wr_o_cld <= '0';
reg_F <= "00000100";
reg_sel_pc_in <= '0';
329,7 → 318,7
zw_b3 <= X"00";
zw_b4 <= X"00";
zw_so <= '0';
ELSIF (clk_clk_i'EVENT AND clk_clk_i = '1') THEN
elsif (clk_clk_i'event and clk_clk_i = '1') then
current_state <= next_state;
-- Default Assignment To Internals
reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0);
349,22 → 338,21
zw_b4 <= zw_b4;
zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6)));
d_o_cld <= sig_D_OUT;
rd_o_cld <= sig_RD;
rd_o_cld <= NOT(sig_WR);
sync_o_cld <= sig_SYNC;
wr_n_o_cld <= sig_RWn;
wr_o_cld <= sig_WR;
 
-- Combined Actions
CASE current_state IS
WHEN FETCH =>
case current_state is
when FETCH =>
zw_REG_OP <= d_i;
IF ((nmi_i = '1') AND (rdy_i = '1')) THEN
if ((nmi_i = '1') and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
zw_REG_NMI <= '0';
ELSIF ((irq_n_i = '0' and
reg_F(2) = '0') AND (rdy_i = '1')) THEN
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"69" or
elsif ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
371,17 → 359,17
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") AND (rdy_i = '1')) THEN
d_i = X"71") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
zw_b1(0) <= reg_F(7);
ELSIF ((d_i = X"06" or
elsif ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") AND (rdy_i = '1')) THEN
d_i = X"1E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"90" or
elsif ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
388,45 → 376,45
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") AND (rdy_i = '1')) THEN
d_i = X"70") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
zw_b3 <= adr_nxt_pc_i (15 downto 8);
ELSIF ((d_i = X"24" or
d_i = X"2C") AND (rdy_i = '1')) THEN
elsif ((d_i = X"24" or
d_i = X"2C") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN
elsif ((d_i = X"00") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"E0" or
elsif ((d_i = X"18") and (rdy_i = '1')) then
elsif ((d_i = X"D8") and (rdy_i = '1')) then
elsif ((d_i = X"58") and (rdy_i = '1')) then
elsif ((d_i = X"B8") and (rdy_i = '1')) then
elsif ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") AND (rdy_i = '1')) THEN
d_i = X"EC") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"C0" or
elsif ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") AND (rdy_i = '1')) THEN
d_i = X"CC") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"C6" or
elsif ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") AND (rdy_i = '1')) THEN
d_i = X"DE") and (rdy_i = '1')) then
zw_b4 <= X"FF";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN
elsif ((d_i = X"CA") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
zw_b4 <= X"FF";
ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN
elsif ((d_i = X"88") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
zw_b4 <= X"FF";
ELSIF ((d_i = X"49" or
elsif ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
457,33 → 445,33
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") AND (rdy_i = '1')) THEN
d_i = X"D1") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"E6" or
elsif ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") AND (rdy_i = '1')) THEN
d_i = X"FE") and (rdy_i = '1')) then
zw_b4 <= X"01";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN
elsif ((d_i = X"E8") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
zw_b4 <= X"01";
ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN
elsif ((d_i = X"C8") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
zw_b4 <= X"01";
ELSIF ((d_i = X"4C" or
d_i = X"6C") AND (rdy_i = '1')) THEN
elsif ((d_i = X"4C" or
d_i = X"6C") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN
elsif ((d_i = X"20") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"A9" or
elsif ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
490,62 → 478,63
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") AND (rdy_i = '1')) THEN
d_i = X"B1") and (rdy_i = '1')) then
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"A2" or
elsif ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") AND (rdy_i = '1')) THEN
d_i = X"BE") and (rdy_i = '1')) then
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"A0" or
elsif ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") AND (rdy_i = '1')) THEN
d_i = X"BC") and (rdy_i = '1')) then
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"46" or
elsif ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") AND (rdy_i = '1')) THEN
d_i = X"5E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN
elsif ((d_i = X"EA") and (rdy_i = '1')) then
elsif ((d_i = X"48") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN
elsif ((d_i = X"08") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN
elsif ((d_i = X"68") and (rdy_i = '1')) then
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN
elsif ((d_i = X"28") and (rdy_i = '1')) then
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
ELSIF ((d_i = X"26" or
elsif ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") AND (rdy_i = '1')) THEN
d_i = X"3E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"66" or
elsif ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") AND (rdy_i = '1')) THEN
d_i = X"7E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN
elsif ((d_i = X"40") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
elsif ((d_i = X"60") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
ELSIF ((d_i = X"E9" or
elsif ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
552,654 → 541,500
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") AND (rdy_i = '1')) THEN
d_i = X"F1") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
zw_b1(0) <= reg_F(7);
ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"85" or
elsif ((d_i = X"38") and (rdy_i = '1')) then
elsif ((d_i = X"F8") and (rdy_i = '1')) then
elsif ((d_i = X"78") and (rdy_i = '1')) then
elsif ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91") AND (rdy_i = '1')) THEN
d_i = X"91") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"86" or
elsif ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") AND (rdy_i = '1')) THEN
d_i = X"8E") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"84" or
elsif ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") AND (rdy_i = '1')) THEN
d_i = X"8C") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN
elsif ((d_i = X"AA") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "01";
reg_sel_rb_in <= "00";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"0A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"4A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"2A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"6A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN
elsif ((d_i = X"A8") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "10";
reg_sel_rb_in <= "00";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN
elsif ((d_i = X"98") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
reg_sel_reg <= "00";
reg_sel_rb_in <= "01";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN
elsif ((d_i = X"BA") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"8A") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "00";
reg_sel_rb_in <= "10";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"9A") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "11";
reg_sel_rb_in <= "11";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
END IF;
WHEN s1 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
end if;
when G10_1 =>
if (rdy_i = '1' and
zw_REG_OP = X"65") then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s2 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= '1';
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s5 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(3) <= '1';
reg_sel_pc_in <= '0';
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s3 =>
sig_PC <= adr_pc_i;
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(2) <= '1';
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s4 =>
IF (rdy_i = '1' and
zw_REG_OP = X"9A") THEN
end if;
when G10_2 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when G10_3 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when G10_4 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when G10_5 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when G10_6 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when G10_7 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when G10_e1 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"BA") THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s12 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= '0';
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s16 =>
IF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when G10_e2 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(3) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s17 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(2) <= '0';
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s24 =>
IF (rdy_i = '1') THEN
elsif (rdy_i = '1' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(6) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s25 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s271 =>
IF (rdy_i = '1' and
zw_REG_OP = X"4C") THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
end if;
when G10_e3 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"6C") THEN
end if;
when G11_1 =>
if (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "00";
zw_b1 <= d_i;
END IF;
WHEN s273 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
zw_b2 <= d_i;
END IF;
WHEN s304 =>
IF (rdy_i = '1') THEN
sig_PC <= zw_b2 & adr_pc_i(7 downto 0);
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
END IF;
WHEN s307 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s177 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) THEN
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) then
sig_PC <= X"00" & d_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) THEN
elsif (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) THEN
elsif (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"9D") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"99") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"91") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"81") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"96") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
END IF;
WHEN s180 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s181 =>
IF (rdy_i = '1') THEN
end if;
when G11_2 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
END IF;
WHEN s182 =>
IF (rdy_i = '1') THEN
end if;
when G11_4 =>
if (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) then
zw_b1 <= d_i(6 downto 0) & '0';
zw_b2(0) <= d_i(7);
elsif (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) then
zw_b1 <= '0' & d_i(7 downto 1);
zw_b2(0) <= d_i(0);
elsif (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) then
zw_b1 <= d_i(6 downto 0) & reg_F(0);
zw_b2(0) <= d_i(7);
elsif (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) then
zw_b1 <= reg_F(0) & d_i(7 downto 1);
zw_b2(0) <= d_i(0);
end if;
when G11_5 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s183 =>
IF (rdy_i = '1') THEN
end if;
when G11_6 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
END IF;
WHEN s184 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s185 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s186 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s187 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s188 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
END IF;
WHEN s189 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s190 =>
end if;
when G11_7 =>
if (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when G11_e =>
reg_F(0) <= zw_b2(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s191 =>
sig_PC <= zw_b3 & zw_b1;
WHEN s192 =>
sig_PC <= d_i & zw_b1;
WHEN s193 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s377 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
END IF;
WHEN s381 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s378 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
END IF;
WHEN s382 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s383 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
END IF;
WHEN s384 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
when G12_1 =>
if (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
(reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s385 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
END IF;
WHEN s386 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F <= d_i;
elsif (rdy_i = '1') then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "10";
zw_b2 <= d_i;
end if;
when G12_e1 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s387 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
END IF;
WHEN s388 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
END IF;
WHEN s389 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
reg_F <= d_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
END IF;
WHEN s391 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
END IF;
WHEN s392 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0);
end if;
when G12_e2 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s390 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
END IF;
WHEN s393 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
END IF;
WHEN s394 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
end if;
when G13_1 =>
if (rdy_i = '1' and
zw_REG_OP = X"24") then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "00";
END IF;
WHEN s395 =>
IF (rdy_i = '1') THEN
end if;
when G13_2 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
END IF;
WHEN s396 =>
IF (rdy_i = '1') THEN
end if;
when G13_e =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= d_i(7);
reg_F(6) <= d_i(6);
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s397 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
end if;
when G14_1 =>
if (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
END IF;
WHEN s399 =>
sig_PC <= adr_sp_i;
WHEN s400 =>
elsif (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when G14_2 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when G14_3 =>
if (rdy_i = '1') then
zw_b1 <= d_alu_i;
end if;
when G14_5 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when G14_6 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when G14_7 =>
if (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when G14_e =>
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
WHEN s401 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1 (7 downto 0);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s526 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
END IF;
WHEN s527 =>
sig_PC <= adr_sp_i;
WHEN s528 =>
sig_PC <= adr_sp_i;
WHEN s529 =>
sig_PC <= X"FFFE";
WHEN s530 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
reg_F(2) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s531 =>
IF (rdy_i = '1') THEN
sig_PC <= X"FFFF";
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
END IF;
WHEN s544 =>
sig_PC <= adr_sp_i;
WHEN s545 =>
sig_PC <= adr_sp_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
WHEN s546 =>
sig_PC <= adr_pc_i;
WHEN s547 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
zw_b1 <= d_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
END IF;
WHEN s549 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s550 =>
sig_PC <= adr_sp_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "00";
WHEN s404 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(7);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s556 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s557 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(7);
reg_F(0) <= q_a_i(7);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s579 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s201 =>
IF (rdy_i = '1' and
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when G15_1 =>
if (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
sig_PC <= X"00" & d_i;
ELSIF ((rdy_i = '1' and
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1' and
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1' and
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1' and
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
1207,30 → 1042,28
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) THEN
zw_REG_OP = X"D5")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
1239,132 → 1072,123
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) THEN
zw_REG_OP = X"CC")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) THEN
zw_REG_OP = X"DD")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) THEN
zw_REG_OP = X"D9")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) THEN
zw_REG_OP = X"D1")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) THEN
zw_REG_OP = X"C1")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"B6") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
END IF;
WHEN s202 =>
IF (rdy_i = '1') THEN
end if;
when G15_2 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when G15_3 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
END IF;
WHEN s210 =>
IF (rdy_i = '1') THEN
end if;
when G15_4 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s211 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s215 =>
IF (rdy_i = '1') THEN
end if;
when G15_5 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
END IF;
WHEN s217 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s218 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s222 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
END IF;
WHEN s223 =>
IF (rdy_i = '1') THEN
end if;
when G15_6 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s224 =>
IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
end if;
when G15_7 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when G15_e1 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
1372,68 → 1196,62
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s225 =>
IF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when G15_e2 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
1441,196 → 1259,32
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0') THEN
elsif (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1') THEN
sig_PC <= zw_b3 & zw_b1;
END IF;
WHEN s226 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) THEN
sig_PC <= X"00" & d_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) THEN
sig_PC <= adr_nxt_pc_i;
end if;
when G15_e3 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
END IF;
WHEN s243 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
END IF;
WHEN s244 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s247 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s344 =>
IF (rdy_i = '1') THEN
sig_PC <= zw_b3 & zw_b1;
END IF;
WHEN s343 =>
IF (rdy_i = '1') THEN
zw_b1 <= d_alu_i;
END IF;
WHEN s251 =>
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s351 =>
IF (rdy_i = '1' and
zw_REG_OP = X"24") THEN
end if;
when G16_1 =>
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
sig_PC <= X"00" & d_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"2C") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
END IF;
WHEN s361 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= d_i(7);
reg_F(6) <= d_i(6);
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s360 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
END IF;
WHEN s403 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) THEN
sig_PC <= X"00" & d_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
END IF;
WHEN s406 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
END IF;
WHEN s407 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s409 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s412 =>
IF (rdy_i = '1') THEN
sig_PC <= zw_b3 & zw_b1;
END IF;
WHEN s416 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) THEN
zw_b1 <= d_i(6 downto 0) & '0';
zw_b2(0) <= d_i(7);
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) THEN
zw_b1 <= '0' & d_i(7 downto 1);
zw_b2(0) <= d_i(0);
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) THEN
zw_b1 <= d_i(6 downto 0) & reg_F(0);
zw_b2(0) <= d_i(7);
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) THEN
zw_b1 <= reg_F(0) & d_i(7 downto 1);
zw_b2(0) <= d_i(0);
END IF;
WHEN s418 =>
sig_PC <= adr_pc_i;
reg_F(0) <= zw_b2(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s510 =>
IF (rdy_i = '1' and
zw_REG_OP = X"65") THEN
sig_PC <= X"00" & d_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
1638,39 → 1292,38
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"75") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"6D") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"7D") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"79") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"71") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"61") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
1678,45 → 1331,44
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
reg_F(0) <= zw_ALU2(4);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s553 =>
IF (rdy_i = '1') THEN
end if;
when G16_2 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when G16_3 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
END IF;
WHEN s555 =>
IF (rdy_i = '1') THEN
end if;
when G16_4 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s558 =>
IF (rdy_i = '1') THEN
end if;
when G16_5 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
END IF;
WHEN s560 =>
IF (rdy_i = '1') THEN
end if;
when G16_6 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when G16_7 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s561 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s563 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
END IF;
WHEN s564 =>
IF (rdy_i = '1' AND
end if;
when G16_e1 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') THEN
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
1726,13 → 1378,12
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' AND
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') THEN
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
1740,18 → 1391,17
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
reg_F(0) <= zw_ALU2(4);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
END IF;
WHEN s565 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
end if;
when G16_e2 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
1761,12 → 1411,11
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
elsif (rdy_i = '1' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
1774,300 → 1423,528
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
reg_F(0) <= zw_ALU2(4);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s566 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s266 =>
IF (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
(reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1') THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "10";
zw_b2 <= d_i;
END IF;
WHEN s301 =>
IF (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1') THEN
sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0);
END IF;
WHEN s302 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN RES =>
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s511 =>
IF (rdy_i = '1' and
zw_REG_OP = X"E5") THEN
end if;
when G16_e3 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when G17_1 =>
if (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) then
sig_PC <= X"00" & d_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F5") THEN
elsif (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"ED") THEN
elsif (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"FD") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"9D") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F9") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F1") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E1") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU2(4);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s559 =>
IF (rdy_i = '1') THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
end if;
when G17_10 =>
sig_PC <= d_i & zw_b1;
when G17_2 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when G17_3 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
END IF;
WHEN s562 =>
IF (rdy_i = '1') THEN
end if;
when G17_4 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s567 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s568 =>
IF (rdy_i = '1') THEN
end if;
when G17_5 =>
sig_PC <= zw_b3 & zw_b1;
when G17_6 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
END IF;
WHEN s569 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s570 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s571 =>
IF (rdy_i = '1') THEN
end if;
when G17_7 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s572 =>
IF (rdy_i = '1') THEN
end if;
when G17_8 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when G17_9 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
END IF;
WHEN s573 =>
IF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') THEN
end if;
when G17_e =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when G18_1 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when G18_2 =>
sig_PC <= adr_sp_i;
when G18_3 =>
sig_PC <= adr_sp_i;
when G18_4 =>
sig_PC <= X"FFFE";
when G18_5 =>
if (rdy_i = '1') then
sig_PC <= X"FFFF";
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
end if;
when G18_e =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_F(2) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when G19_1 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') THEN
end if;
when G1_1 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU2(4);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1') THEN
sig_PC <= zw_b3 & zw_b1;
END IF;
WHEN s574 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
end if;
when G20_1 =>
if (rdy_i = '1' and
zw_REG_OP = X"4C") then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"6C") then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "00";
zw_b1 <= d_i;
end if;
when G20_2 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
zw_b2 <= d_i;
end if;
when G20_3 =>
if (rdy_i = '1') then
sig_PC <= zw_b2 & adr_pc_i(7 downto 0);
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
end if;
when G20_e =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when G21_1 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
end if;
when G21_3 =>
sig_PC <= adr_sp_i;
when G21_4 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
when G21_e =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1 (7 downto 0);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when G22_1 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when G22_e =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when G23_1 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when G23_e =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when G24_2 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when G24_e =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
end if;
when G25_2 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when G25_e =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU2(4);
reg_F <= d_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s548 =>
IF (rdy_i = '1') THEN
end if;
when G26_1 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
END IF;
WHEN s551 =>
end if;
when G26_2 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when G26_3 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
reg_F <= d_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
end if;
when G26_4 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
end if;
when G26_e =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when G27_1 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when G27_2 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when G27_3 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "00";
end if;
when G27_4 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when G27_e =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when G28_1 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when G28_2 =>
sig_PC <= adr_sp_i;
WHEN s552 =>
when G28_3 =>
sig_PC <= adr_sp_i;
WHEN s575 =>
IF (rdy_i = '1') THEN
when G28_4 =>
sig_PC <= X"FFFE";
when G28_5 =>
if (rdy_i = '1') then
sig_PC <= X"FFFF";
zw_b1 <= d_i;
END IF;
WHEN s576 =>
sig_PC <= X"FFFE";
WHEN s577 =>
IF (rdy_i = '1') THEN
end if;
when G28_e =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_F(2) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s532 =>
IF (rdy_i = '1') THEN
end if;
when G29_1 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
END IF;
WHEN s533 =>
end if;
when G29_2 =>
sig_PC <= adr_sp_i;
WHEN s534 =>
when G29_3 =>
sig_PC <= adr_sp_i;
WHEN s535 =>
IF (rdy_i = '1') THEN
when G29_4 =>
sig_PC <= X"FFFA";
when G29_5 =>
if (rdy_i = '1') then
sig_PC <= X"FFFB";
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
END IF;
WHEN s536 =>
sig_PC <= X"FFFA";
WHEN s537 =>
IF (rdy_i = '1') THEN
end if;
when G29_e =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END PROCESS clocked_proc;
end if;
when G2_1 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when G30_1 =>
sig_PC <= adr_sp_i;
when G30_2 =>
sig_PC <= adr_sp_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "00";
when G30_3 =>
sig_PC <= adr_sp_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
when G30_4 =>
sig_PC <= adr_pc_i;
when G30_5 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
zw_b1 <= d_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
end if;
when G30_e =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when G31_1 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(7);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when G32_1 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when G33_1 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(7);
reg_F(0) <= q_a_i(7);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when G34_1 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when G3_1 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(3) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when G4_1 =>
sig_PC <= adr_pc_i;
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(2) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when G5_1 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when G6_1 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(3) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when G7_1 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(2) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when G8_1 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(6) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when G9_1 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when RES =>
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when others =>
null;
end case;
end if;
end process clocked_proc;
-----------------------------------------------------------------
nextstate_proc : PROCESS (
nextstate_proc : process (
adr_nxt_pc_i,
current_state,
d_i,
2080,15 → 1957,15
zw_b3
)
-----------------------------------------------------------------
BEGIN
CASE current_state IS
WHEN FETCH =>
IF ((nmi_i = '1') AND (rdy_i = '1')) THEN
next_state <= s532;
ELSIF ((irq_n_i = '0' and
reg_F(2) = '0') AND (rdy_i = '1')) THEN
next_state <= s548;
ELSIF ((d_i = X"69" or
begin
case current_state is
when FETCH =>
if ((nmi_i = '1') and (rdy_i = '1')) then
next_state <= G29_1;
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
next_state <= G28_1;
elsif ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
2095,14 → 1972,14
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") AND (rdy_i = '1')) THEN
next_state <= s510;
ELSIF ((d_i = X"06" or
d_i = X"71") and (rdy_i = '1')) then
next_state <= G10_1;
elsif ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") AND (rdy_i = '1')) THEN
next_state <= s403;
ELSIF ((d_i = X"90" or
d_i = X"1E") and (rdy_i = '1')) then
next_state <= G11_1;
elsif ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
2109,39 → 1986,39
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") AND (rdy_i = '1')) THEN
next_state <= s266;
ELSIF ((d_i = X"24" or
d_i = X"2C") AND (rdy_i = '1')) THEN
next_state <= s351;
ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN
next_state <= s526;
ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN
next_state <= s12;
ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN
next_state <= s16;
ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN
next_state <= s17;
ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN
next_state <= s24;
ELSIF ((d_i = X"E0" or
d_i = X"70") and (rdy_i = '1')) then
next_state <= G12_1;
elsif ((d_i = X"24" or
d_i = X"2C") and (rdy_i = '1')) then
next_state <= G13_1;
elsif ((d_i = X"00") and (rdy_i = '1')) then
next_state <= G18_1;
elsif ((d_i = X"18") and (rdy_i = '1')) then
next_state <= G5_1;
elsif ((d_i = X"D8") and (rdy_i = '1')) then
next_state <= G6_1;
elsif ((d_i = X"58") and (rdy_i = '1')) then
next_state <= G7_1;
elsif ((d_i = X"B8") and (rdy_i = '1')) then
next_state <= G8_1;
elsif ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") AND (rdy_i = '1')) THEN
next_state <= s201;
ELSIF ((d_i = X"C0" or
d_i = X"EC") and (rdy_i = '1')) then
next_state <= G15_1;
elsif ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") AND (rdy_i = '1')) THEN
next_state <= s201;
ELSIF ((d_i = X"C6" or
d_i = X"CC") and (rdy_i = '1')) then
next_state <= G15_1;
elsif ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") AND (rdy_i = '1')) THEN
next_state <= s226;
ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN
next_state <= s25;
ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN
next_state <= s25;
ELSIF ((d_i = X"49" or
d_i = X"DE") and (rdy_i = '1')) then
next_state <= G14_1;
elsif ((d_i = X"CA") and (rdy_i = '1')) then
next_state <= G19_1;
elsif ((d_i = X"88") and (rdy_i = '1')) then
next_state <= G19_1;
elsif ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
2172,23 → 2049,23
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") AND (rdy_i = '1')) THEN
next_state <= s201;
ELSIF ((d_i = X"E6" or
d_i = X"D1") and (rdy_i = '1')) then
next_state <= G15_1;
elsif ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") AND (rdy_i = '1')) THEN
next_state <= s226;
ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN
next_state <= s25;
ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN
next_state <= s25;
ELSIF ((d_i = X"4C" or
d_i = X"6C") AND (rdy_i = '1')) THEN
next_state <= s271;
ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN
next_state <= s397;
ELSIF ((d_i = X"A9" or
d_i = X"FE") and (rdy_i = '1')) then
next_state <= G14_1;
elsif ((d_i = X"E8") and (rdy_i = '1')) then
next_state <= G19_1;
elsif ((d_i = X"C8") and (rdy_i = '1')) then
next_state <= G19_1;
elsif ((d_i = X"4C" or
d_i = X"6C") and (rdy_i = '1')) then
next_state <= G20_1;
elsif ((d_i = X"20") and (rdy_i = '1')) then
next_state <= G21_1;
elsif ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
2195,50 → 2072,50
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") AND (rdy_i = '1')) THEN
next_state <= s201;
ELSIF ((d_i = X"A2" or
d_i = X"B1") and (rdy_i = '1')) then
next_state <= G15_1;
elsif ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") AND (rdy_i = '1')) THEN
next_state <= s201;
ELSIF ((d_i = X"A0" or
d_i = X"BE") and (rdy_i = '1')) then
next_state <= G15_1;
elsif ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") AND (rdy_i = '1')) THEN
next_state <= s201;
ELSIF ((d_i = X"46" or
d_i = X"BC") and (rdy_i = '1')) then
next_state <= G15_1;
elsif ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") AND (rdy_i = '1')) THEN
next_state <= s403;
ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN
next_state <= s1;
ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN
next_state <= s377;
ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN
next_state <= s378;
ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN
next_state <= s379;
ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN
next_state <= s380;
ELSIF ((d_i = X"26" or
d_i = X"5E") and (rdy_i = '1')) then
next_state <= G11_1;
elsif ((d_i = X"EA") and (rdy_i = '1')) then
next_state <= G1_1;
elsif ((d_i = X"48") and (rdy_i = '1')) then
next_state <= G22_1;
elsif ((d_i = X"08") and (rdy_i = '1')) then
next_state <= G23_1;
elsif ((d_i = X"68") and (rdy_i = '1')) then
next_state <= G24_1;
elsif ((d_i = X"28") and (rdy_i = '1')) then
next_state <= G25_1;
elsif ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") AND (rdy_i = '1')) THEN
next_state <= s403;
ELSIF ((d_i = X"66" or
d_i = X"3E") and (rdy_i = '1')) then
next_state <= G11_1;
elsif ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") AND (rdy_i = '1')) THEN
next_state <= s403;
ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN
next_state <= s387;
ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN
next_state <= s390;
ELSIF ((d_i = X"E9" or
d_i = X"7E") and (rdy_i = '1')) then
next_state <= G11_1;
elsif ((d_i = X"40") and (rdy_i = '1')) then
next_state <= G26_1;
elsif ((d_i = X"60") and (rdy_i = '1')) then
next_state <= G27_1;
elsif ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
2245,494 → 2122,403
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") AND (rdy_i = '1')) THEN
next_state <= s511;
ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN
next_state <= s2;
ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN
next_state <= s5;
ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN
next_state <= s3;
ELSIF ((d_i = X"85" or
d_i = X"F1") and (rdy_i = '1')) then
next_state <= G16_1;
elsif ((d_i = X"38") and (rdy_i = '1')) then
next_state <= G2_1;
elsif ((d_i = X"F8") and (rdy_i = '1')) then
next_state <= G3_1;
elsif ((d_i = X"78") and (rdy_i = '1')) then
next_state <= G4_1;
elsif ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91") AND (rdy_i = '1')) THEN
next_state <= s177;
ELSIF ((d_i = X"86" or
d_i = X"91") and (rdy_i = '1')) then
next_state <= G17_1;
elsif ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") AND (rdy_i = '1')) THEN
next_state <= s177;
ELSIF ((d_i = X"84" or
d_i = X"8E") and (rdy_i = '1')) then
next_state <= G17_1;
elsif ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") AND (rdy_i = '1')) THEN
next_state <= s177;
ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN
next_state <= s4;
ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN
next_state <= s404;
ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN
next_state <= s556;
ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN
next_state <= s557;
ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN
next_state <= s579;
ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN
next_state <= s4;
ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN
next_state <= s4;
ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN
next_state <= s4;
ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN
next_state <= s4;
ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN
next_state <= s4;
ELSIF (rdy_i = '1') THEN
next_state <= s1;
ELSE
d_i = X"8C") and (rdy_i = '1')) then
next_state <= G17_1;
elsif ((d_i = X"AA") and (rdy_i = '1')) then
next_state <= G9_1;
elsif ((d_i = X"0A") and (rdy_i = '1')) then
next_state <= G31_1;
elsif ((d_i = X"4A") and (rdy_i = '1')) then
next_state <= G32_1;
elsif ((d_i = X"2A") and (rdy_i = '1')) then
next_state <= G33_1;
elsif ((d_i = X"6A") and (rdy_i = '1')) then
next_state <= G34_1;
elsif ((d_i = X"A8") and (rdy_i = '1')) then
next_state <= G9_1;
elsif ((d_i = X"98") and (rdy_i = '1')) then
next_state <= G9_1;
elsif ((d_i = X"BA") and (rdy_i = '1')) then
next_state <= G9_1;
elsif ((d_i = X"8A") and (rdy_i = '1')) then
next_state <= G9_1;
elsif ((d_i = X"9A") and (rdy_i = '1')) then
next_state <= G9_1;
elsif (rdy_i = '1') then
next_state <= G1_1;
else
next_state <= FETCH;
END IF;
WHEN s1 =>
IF (rdy_i = '1') THEN
end if;
when G10_1 =>
if (rdy_i = '1' and
zw_REG_OP = X"65") then
next_state <= G10_e2;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
next_state <= FETCH;
ELSE
next_state <= s1;
END IF;
WHEN s2 =>
IF (rdy_i = '1') THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
next_state <= G10_2;
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
next_state <= G10_3;
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
next_state <= G10_4;
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
next_state <= G10_4;
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
next_state <= G10_5;
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
next_state <= G10_7;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
next_state <= FETCH;
ELSE
next_state <= s2;
END IF;
WHEN s5 =>
IF (rdy_i = '1') THEN
else
next_state <= G10_1;
end if;
when G10_2 =>
if (rdy_i = '1') then
next_state <= G10_e2;
else
next_state <= G10_2;
end if;
when G10_3 =>
if (rdy_i = '1') then
next_state <= G10_e2;
else
next_state <= G10_3;
end if;
when G10_4 =>
if (rdy_i = '1') then
next_state <= G10_e1;
else
next_state <= G10_4;
end if;
when G10_5 =>
if (rdy_i = '1') then
next_state <= G10_6;
else
next_state <= G10_5;
end if;
when G10_6 =>
if (rdy_i = '1') then
next_state <= G10_e1;
else
next_state <= G10_6;
end if;
when G10_7 =>
if (rdy_i = '1') then
next_state <= G10_e3;
else
next_state <= G10_7;
end if;
when G10_e1 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
next_state <= FETCH;
ELSE
next_state <= s5;
END IF;
WHEN s3 =>
IF (rdy_i = '1') THEN
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
next_state <= FETCH;
ELSE
next_state <= s3;
END IF;
WHEN s4 =>
IF (rdy_i = '1' and
zw_REG_OP = X"9A") THEN
elsif (rdy_i = '1') then
next_state <= G10_e2;
else
next_state <= G10_e1;
end if;
when G10_e2 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
next_state <= FETCH;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"BA") THEN
elsif (rdy_i = '1' and
reg_F(3) = '1') then
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
else
next_state <= G10_e2;
end if;
when G10_e3 =>
if (rdy_i = '1') then
next_state <= G10_3;
else
next_state <= G10_e3;
end if;
when G11_1 =>
if (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
next_state <= G11_6;
elsif (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) then
next_state <= G11_3;
elsif (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
next_state <= G11_2;
elsif (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) then
next_state <= G11_5;
else
next_state <= G11_1;
end if;
when G11_2 =>
if (rdy_i = '1') then
next_state <= G11_3;
else
next_state <= G11_2;
end if;
when G11_3 =>
if (rdy_i = '1') then
next_state <= G11_4;
else
next_state <= G11_3;
end if;
when G11_4 =>
if (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) then
next_state <= G11_e;
elsif (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) then
next_state <= G11_e;
elsif (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) then
next_state <= G11_e;
elsif (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) then
next_state <= G11_e;
else
next_state <= G11_4;
end if;
when G11_5 =>
if (rdy_i = '1') then
next_state <= G11_3;
else
next_state <= G11_5;
end if;
when G11_6 =>
if (rdy_i = '1') then
next_state <= G11_7;
else
next_state <= G11_6;
end if;
when G11_7 =>
if (rdy_i = '1') then
next_state <= G11_3;
else
next_state <= G11_7;
end if;
when G11_e =>
next_state <= FETCH;
when G12_1 =>
if (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
(reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) then
next_state <= FETCH;
ELSE
next_state <= s4;
END IF;
WHEN s12 =>
IF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
next_state <= G12_e1;
else
next_state <= G12_1;
end if;
when G12_e1 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
next_state <= FETCH;
ELSE
next_state <= s12;
END IF;
WHEN s16 =>
IF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
next_state <= G12_e2;
else
next_state <= G12_e1;
end if;
when G12_e2 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
next_state <= s16;
END IF;
WHEN s17 =>
IF (rdy_i = '1') THEN
else
next_state <= G12_e2;
end if;
when G13_1 =>
if (rdy_i = '1' and
zw_REG_OP = X"24") then
next_state <= G13_e;
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
next_state <= G13_2;
else
next_state <= G13_1;
end if;
when G13_2 =>
if (rdy_i = '1') then
next_state <= G13_e;
else
next_state <= G13_2;
end if;
when G13_e =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
next_state <= s17;
END IF;
WHEN s24 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s24;
END IF;
WHEN s25 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s25;
END IF;
WHEN s271 =>
IF (rdy_i = '1' and
zw_REG_OP = X"4C") THEN
next_state <= s307;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"6C") THEN
next_state <= s273;
ELSE
next_state <= s271;
END IF;
WHEN s273 =>
IF (rdy_i = '1') THEN
next_state <= s304;
ELSE
next_state <= s273;
END IF;
WHEN s304 =>
IF (rdy_i = '1') THEN
next_state <= s307;
ELSE
next_state <= s304;
END IF;
WHEN s307 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s307;
END IF;
WHEN s177 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) THEN
next_state <= s184;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) THEN
next_state <= s185;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) THEN
next_state <= s183;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"9D") THEN
next_state <= s182;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"99") THEN
next_state <= s180;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"91") THEN
next_state <= s181;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"81") THEN
next_state <= s186;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"96") THEN
next_state <= s185;
ELSE
next_state <= s177;
END IF;
WHEN s180 =>
IF (rdy_i = '1') THEN
next_state <= s191;
ELSE
next_state <= s180;
END IF;
WHEN s181 =>
IF (rdy_i = '1') THEN
next_state <= s189;
ELSE
next_state <= s181;
END IF;
WHEN s182 =>
IF (rdy_i = '1') THEN
next_state <= s191;
ELSE
next_state <= s182;
END IF;
WHEN s183 =>
IF (rdy_i = '1') THEN
next_state <= s187;
ELSE
next_state <= s183;
END IF;
WHEN s184 =>
else
next_state <= G13_e;
end if;
when G14_1 =>
if (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
next_state <= G14_3;
elsif (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
next_state <= G14_2;
elsif (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
next_state <= G14_5;
elsif (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
next_state <= G14_6;
else
next_state <= G14_1;
end if;
when G14_2 =>
if (rdy_i = '1') then
next_state <= G14_3;
else
next_state <= G14_2;
end if;
when G14_3 =>
if (rdy_i = '1') then
next_state <= G14_4;
else
next_state <= G14_3;
end if;
when G14_4 =>
if (rdy_i = '1') then
next_state <= G14_e;
else
next_state <= G14_4;
end if;
when G14_5 =>
if (rdy_i = '1') then
next_state <= G14_3;
else
next_state <= G14_5;
end if;
when G14_6 =>
if (rdy_i = '1') then
next_state <= G14_7;
else
next_state <= G14_6;
end if;
when G14_7 =>
if (rdy_i = '1') then
next_state <= G14_3;
else
next_state <= G14_7;
end if;
when G14_e =>
next_state <= FETCH;
WHEN s185 =>
IF (rdy_i = '1') THEN
next_state <= s190;
ELSE
next_state <= s185;
END IF;
WHEN s186 =>
IF (rdy_i = '1') THEN
next_state <= s188;
ELSE
next_state <= s186;
END IF;
WHEN s187 =>
next_state <= FETCH;
WHEN s188 =>
IF (rdy_i = '1') THEN
next_state <= s192;
ELSE
next_state <= s188;
END IF;
WHEN s189 =>
IF (rdy_i = '1') THEN
next_state <= s191;
ELSE
next_state <= s189;
END IF;
WHEN s190 =>
next_state <= FETCH;
WHEN s191 =>
next_state <= s193;
WHEN s192 =>
next_state <= s193;
WHEN s193 =>
next_state <= FETCH;
WHEN s377 =>
IF (rdy_i = '1') THEN
next_state <= s381;
ELSE
next_state <= s377;
END IF;
WHEN s381 =>
next_state <= FETCH;
WHEN s378 =>
IF (rdy_i = '1') THEN
next_state <= s382;
ELSE
next_state <= s378;
END IF;
WHEN s382 =>
next_state <= FETCH;
WHEN s379 =>
IF (rdy_i = '1') THEN
next_state <= s383;
ELSE
next_state <= s379;
END IF;
WHEN s383 =>
IF (rdy_i = '1') THEN
next_state <= s384;
ELSE
next_state <= s383;
END IF;
WHEN s384 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s384;
END IF;
WHEN s380 =>
IF (rdy_i = '1') THEN
next_state <= s385;
ELSE
next_state <= s380;
END IF;
WHEN s385 =>
IF (rdy_i = '1') THEN
next_state <= s386;
ELSE
next_state <= s385;
END IF;
WHEN s386 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s386;
END IF;
WHEN s387 =>
IF (rdy_i = '1') THEN
next_state <= s388;
ELSE
next_state <= s387;
END IF;
WHEN s388 =>
IF (rdy_i = '1') THEN
next_state <= s389;
ELSE
next_state <= s388;
END IF;
WHEN s389 =>
IF (rdy_i = '1') THEN
next_state <= s391;
ELSE
next_state <= s389;
END IF;
WHEN s391 =>
IF (rdy_i = '1') THEN
next_state <= s392;
ELSE
next_state <= s391;
END IF;
WHEN s392 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s392;
END IF;
WHEN s390 =>
IF (rdy_i = '1') THEN
next_state <= s393;
ELSE
next_state <= s390;
END IF;
WHEN s393 =>
IF (rdy_i = '1') THEN
next_state <= s394;
ELSE
next_state <= s393;
END IF;
WHEN s394 =>
IF (rdy_i = '1') THEN
next_state <= s395;
ELSE
next_state <= s394;
END IF;
WHEN s395 =>
IF (rdy_i = '1') THEN
next_state <= s396;
ELSE
next_state <= s395;
END IF;
WHEN s396 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s396;
END IF;
WHEN s397 =>
IF (rdy_i = '1') THEN
next_state <= s398;
ELSE
next_state <= s397;
END IF;
WHEN s398 =>
IF (rdy_i = '1') THEN
next_state <= s399;
ELSE
next_state <= s398;
END IF;
WHEN s399 =>
next_state <= s400;
WHEN s400 =>
next_state <= s401;
WHEN s401 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s401;
END IF;
WHEN s526 =>
IF (rdy_i = '1') THEN
next_state <= s527;
ELSE
next_state <= s526;
END IF;
WHEN s527 =>
next_state <= s528;
WHEN s528 =>
next_state <= s529;
WHEN s529 =>
next_state <= s531;
WHEN s530 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s530;
END IF;
WHEN s531 =>
IF (rdy_i = '1') THEN
next_state <= s530;
ELSE
next_state <= s531;
END IF;
WHEN s544 =>
next_state <= s550;
WHEN s545 =>
next_state <= s546;
WHEN s546 =>
next_state <= s547;
WHEN s547 =>
IF (rdy_i = '1') THEN
next_state <= s549;
ELSE
next_state <= s547;
END IF;
WHEN s549 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s549;
END IF;
WHEN s550 =>
next_state <= s545;
WHEN s404 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s404;
END IF;
WHEN s556 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s556;
END IF;
WHEN s557 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s557;
END IF;
WHEN s579 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s579;
END IF;
WHEN s201 =>
IF (rdy_i = '1' and
when G15_1 =>
if (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN
next_state <= s224;
ELSIF ((rdy_i = '1' and
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
next_state <= G15_e2;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
next_state <= FETCH;
ELSIF ((rdy_i = '1' and
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
next_state <= FETCH;
ELSIF ((rdy_i = '1' and
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
next_state <= FETCH;
ELSIF ((rdy_i = '1' and
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
next_state <= FETCH;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
next_state <= FETCH;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) THEN
next_state <= s217;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"D5")) then
next_state <= G15_2;
elsif (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
2741,617 → 2527,684
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) THEN
next_state <= s202;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"CC")) then
next_state <= G15_3;
elsif (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) THEN
next_state <= s210;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"DD")) then
next_state <= G15_4;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) THEN
next_state <= s211;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"D9")) then
next_state <= G15_4;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) THEN
next_state <= s215;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"D1")) then
next_state <= G15_5;
elsif (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) THEN
next_state <= s218;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"B6") THEN
next_state <= s217;
ELSE
next_state <= s201;
END IF;
WHEN s202 =>
IF (rdy_i = '1') THEN
next_state <= s224;
ELSE
next_state <= s202;
END IF;
WHEN s210 =>
IF (rdy_i = '1') THEN
next_state <= s225;
ELSE
next_state <= s210;
END IF;
WHEN s211 =>
IF (rdy_i = '1') THEN
next_state <= s225;
ELSE
next_state <= s211;
END IF;
WHEN s215 =>
IF (rdy_i = '1') THEN
next_state <= s223;
ELSE
next_state <= s215;
END IF;
WHEN s217 =>
IF (rdy_i = '1') THEN
next_state <= s224;
ELSE
next_state <= s217;
END IF;
WHEN s218 =>
IF (rdy_i = '1') THEN
next_state <= s222;
ELSE
next_state <= s218;
END IF;
WHEN s222 =>
IF (rdy_i = '1') THEN
next_state <= s202;
ELSE
next_state <= s222;
END IF;
WHEN s223 =>
IF (rdy_i = '1') THEN
next_state <= s225;
ELSE
next_state <= s223;
END IF;
WHEN s224 =>
IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"C1")) then
next_state <= G15_7;
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
next_state <= G15_2;
else
next_state <= G15_1;
end if;
when G15_2 =>
if (rdy_i = '1') then
next_state <= G15_e2;
else
next_state <= G15_2;
end if;
when G15_3 =>
if (rdy_i = '1') then
next_state <= G15_e2;
else
next_state <= G15_3;
end if;
when G15_4 =>
if (rdy_i = '1') then
next_state <= G15_e1;
else
next_state <= G15_4;
end if;
when G15_5 =>
if (rdy_i = '1') then
next_state <= G15_6;
else
next_state <= G15_5;
end if;
when G15_6 =>
if (rdy_i = '1') then
next_state <= G15_e1;
else
next_state <= G15_6;
end if;
when G15_7 =>
if (rdy_i = '1') then
next_state <= G15_e3;
else
next_state <= G15_7;
end if;
when G15_e1 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
next_state <= FETCH;
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
next_state <= FETCH;
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
next_state <= FETCH;
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
next_state <= FETCH;
ELSE
next_state <= s224;
END IF;
WHEN s225 =>
IF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
elsif (rdy_i = '1') then
next_state <= G15_e2;
else
next_state <= G15_e1;
end if;
when G15_e2 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
next_state <= FETCH;
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
next_state <= FETCH;
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
next_state <= FETCH;
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
next_state <= FETCH;
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0') THEN
elsif (rdy_i = '1') then
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
next_state <= s224;
ELSE
next_state <= s225;
END IF;
WHEN s226 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) THEN
next_state <= s343;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) THEN
next_state <= s247;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) THEN
next_state <= s243;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) THEN
next_state <= s244;
ELSE
next_state <= s226;
END IF;
WHEN s243 =>
IF (rdy_i = '1') THEN
next_state <= s343;
ELSE
next_state <= s243;
END IF;
WHEN s244 =>
IF (rdy_i = '1') THEN
next_state <= s344;
ELSE
next_state <= s244;
END IF;
WHEN s247 =>
IF (rdy_i = '1') THEN
next_state <= s343;
ELSE
next_state <= s247;
END IF;
WHEN s344 =>
IF (rdy_i = '1') THEN
next_state <= s343;
ELSE
next_state <= s344;
END IF;
WHEN s343 =>
IF (rdy_i = '1') THEN
next_state <= s250;
ELSE
next_state <= s343;
END IF;
WHEN s250 =>
IF (rdy_i = '1') THEN
next_state <= s251;
ELSE
next_state <= s250;
END IF;
WHEN s251 =>
else
next_state <= G15_e2;
end if;
when G15_e3 =>
if (rdy_i = '1') then
next_state <= G15_3;
else
next_state <= G15_e3;
end if;
when G16_1 =>
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
next_state <= G16_e2;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
next_state <= G16_2;
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
next_state <= G16_3;
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
next_state <= G16_4;
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
next_state <= G16_4;
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
next_state <= G16_5;
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
next_state <= G16_7;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
next_state <= FETCH;
else
next_state <= G16_1;
end if;
when G16_2 =>
if (rdy_i = '1') then
next_state <= G16_e2;
else
next_state <= G16_2;
end if;
when G16_3 =>
if (rdy_i = '1') then
next_state <= G16_e2;
else
next_state <= G16_3;
end if;
when G16_4 =>
if (rdy_i = '1') then
next_state <= G16_e1;
else
next_state <= G16_4;
end if;
when G16_5 =>
if (rdy_i = '1') then
next_state <= G16_6;
else
next_state <= G16_5;
end if;
when G16_6 =>
if (rdy_i = '1') then
next_state <= G16_e1;
else
next_state <= G16_6;
end if;
when G16_7 =>
if (rdy_i = '1') then
next_state <= G16_e3;
else
next_state <= G16_7;
end if;
when G16_e1 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= G16_e2;
else
next_state <= G16_e1;
end if;
when G16_e2 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
reg_F(3) = '1') then
next_state <= FETCH;
else
next_state <= G16_e2;
end if;
when G16_e3 =>
if (rdy_i = '1') then
next_state <= G16_3;
else
next_state <= G16_e3;
end if;
when G17_1 =>
if (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) then
next_state <= G17_e;
elsif (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) then
next_state <= G17_2;
elsif (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) then
next_state <= G17_3;
elsif (rdy_i = '1' and
zw_REG_OP = X"9D") then
next_state <= G17_4;
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
next_state <= G17_4;
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
next_state <= G17_6;
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
next_state <= G17_8;
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
next_state <= G17_2;
else
next_state <= G17_1;
end if;
when G17_10 =>
next_state <= G17_e;
when G17_2 =>
if (rdy_i = '1') then
next_state <= G17_e;
else
next_state <= G17_2;
end if;
when G17_3 =>
if (rdy_i = '1') then
next_state <= G17_e;
else
next_state <= G17_3;
end if;
when G17_4 =>
if (rdy_i = '1') then
next_state <= G17_5;
else
next_state <= G17_4;
end if;
when G17_5 =>
next_state <= G17_e;
when G17_6 =>
if (rdy_i = '1') then
next_state <= G17_7;
else
next_state <= G17_6;
end if;
when G17_7 =>
if (rdy_i = '1') then
next_state <= G17_5;
else
next_state <= G17_7;
end if;
when G17_8 =>
if (rdy_i = '1') then
next_state <= G17_9;
else
next_state <= G17_8;
end if;
when G17_9 =>
if (rdy_i = '1') then
next_state <= G17_10;
else
next_state <= G17_9;
end if;
when G17_e =>
next_state <= FETCH;
WHEN s351 =>
IF (rdy_i = '1' and
zw_REG_OP = X"24") THEN
next_state <= s361;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"2C") THEN
next_state <= s360;
ELSE
next_state <= s351;
END IF;
WHEN s361 =>
IF (rdy_i = '1') THEN
when G18_1 =>
if (rdy_i = '1') then
next_state <= G18_2;
else
next_state <= G18_1;
end if;
when G18_2 =>
next_state <= G18_3;
when G18_3 =>
next_state <= G18_4;
when G18_4 =>
next_state <= G18_5;
when G18_5 =>
if (rdy_i = '1') then
next_state <= G18_e;
else
next_state <= G18_5;
end if;
when G18_e =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
next_state <= s361;
END IF;
WHEN s360 =>
IF (rdy_i = '1') THEN
next_state <= s361;
ELSE
next_state <= s360;
END IF;
WHEN s403 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) THEN
next_state <= s407;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) THEN
next_state <= s413;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) THEN
next_state <= s409;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) THEN
next_state <= s406;
ELSE
next_state <= s403;
END IF;
WHEN s406 =>
IF (rdy_i = '1') THEN
next_state <= s413;
ELSE
next_state <= s406;
END IF;
WHEN s407 =>
IF (rdy_i = '1') THEN
next_state <= s412;
ELSE
next_state <= s407;
END IF;
WHEN s409 =>
IF (rdy_i = '1') THEN
next_state <= s413;
ELSE
next_state <= s409;
END IF;
WHEN s412 =>
IF (rdy_i = '1') THEN
next_state <= s413;
ELSE
next_state <= s412;
END IF;
WHEN s413 =>
IF (rdy_i = '1') THEN
next_state <= s416;
ELSE
next_state <= s413;
END IF;
WHEN s416 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) THEN
next_state <= s418;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) THEN
next_state <= s418;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) THEN
next_state <= s418;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) THEN
next_state <= s418;
ELSE
next_state <= s416;
END IF;
WHEN s418 =>
else
next_state <= G18_e;
end if;
when G19_1 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= G19_1;
end if;
when G1_1 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= G1_1;
end if;
when G20_1 =>
if (rdy_i = '1' and
zw_REG_OP = X"4C") then
next_state <= G20_e;
elsif (rdy_i = '1' and
zw_REG_OP = X"6C") then
next_state <= G20_2;
else
next_state <= G20_1;
end if;
when G20_2 =>
if (rdy_i = '1') then
next_state <= G20_3;
else
next_state <= G20_2;
end if;
when G20_3 =>
if (rdy_i = '1') then
next_state <= G20_e;
else
next_state <= G20_3;
end if;
when G20_e =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= G20_e;
end if;
when G21_1 =>
if (rdy_i = '1') then
next_state <= G21_2;
else
next_state <= G21_1;
end if;
when G21_2 =>
if (rdy_i = '1') then
next_state <= G21_3;
else
next_state <= G21_2;
end if;
when G21_3 =>
next_state <= G21_4;
when G21_4 =>
next_state <= G21_e;
when G21_e =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= G21_e;
end if;
when G22_1 =>
if (rdy_i = '1') then
next_state <= G22_e;
else
next_state <= G22_1;
end if;
when G22_e =>
next_state <= FETCH;
WHEN s510 =>
IF (rdy_i = '1' and
zw_REG_OP = X"65") THEN
next_state <= s565;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') THEN
when G23_1 =>
if (rdy_i = '1') then
next_state <= G23_e;
else
next_state <= G23_1;
end if;
when G23_e =>
next_state <= FETCH;
when G24_1 =>
if (rdy_i = '1') then
next_state <= G24_2;
else
next_state <= G24_1;
end if;
when G24_2 =>
if (rdy_i = '1') then
next_state <= G24_e;
else
next_state <= G24_2;
end if;
when G24_e =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"75") THEN
next_state <= s560;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"6D") THEN
next_state <= s553;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"7D") THEN
next_state <= s555;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"79") THEN
next_state <= s555;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"71") THEN
next_state <= s558;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"61") THEN
next_state <= s561;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') THEN
else
next_state <= G24_e;
end if;
when G25_1 =>
if (rdy_i = '1') then
next_state <= G25_2;
else
next_state <= G25_1;
end if;
when G25_2 =>
if (rdy_i = '1') then
next_state <= G25_e;
else
next_state <= G25_2;
end if;
when G25_e =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
next_state <= s510;
END IF;
WHEN s553 =>
IF (rdy_i = '1') THEN
next_state <= s565;
ELSE
next_state <= s553;
END IF;
WHEN s555 =>
IF (rdy_i = '1') THEN
next_state <= s564;
ELSE
next_state <= s555;
END IF;
WHEN s558 =>
IF (rdy_i = '1') THEN
next_state <= s566;
ELSE
next_state <= s558;
END IF;
WHEN s560 =>
IF (rdy_i = '1') THEN
next_state <= s565;
ELSE
next_state <= s560;
END IF;
WHEN s561 =>
IF (rdy_i = '1') THEN
next_state <= s563;
ELSE
next_state <= s561;
END IF;
WHEN s563 =>
IF (rdy_i = '1') THEN
next_state <= s553;
ELSE
next_state <= s563;
END IF;
WHEN s564 =>
IF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') THEN
else
next_state <= G25_e;
end if;
when G26_1 =>
if (rdy_i = '1') then
next_state <= G26_2;
else
next_state <= G26_1;
end if;
when G26_2 =>
if (rdy_i = '1') then
next_state <= G26_3;
else
next_state <= G26_2;
end if;
when G26_3 =>
if (rdy_i = '1') then
next_state <= G26_4;
else
next_state <= G26_3;
end if;
when G26_4 =>
if (rdy_i = '1') then
next_state <= G26_e;
else
next_state <= G26_4;
end if;
when G26_e =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') THEN
else
next_state <= G26_e;
end if;
when G27_1 =>
if (rdy_i = '1') then
next_state <= G27_2;
else
next_state <= G27_1;
end if;
when G27_2 =>
if (rdy_i = '1') then
next_state <= G27_3;
else
next_state <= G27_2;
end if;
when G27_3 =>
if (rdy_i = '1') then
next_state <= G27_4;
else
next_state <= G27_3;
end if;
when G27_4 =>
if (rdy_i = '1') then
next_state <= G27_e;
else
next_state <= G27_4;
end if;
when G27_e =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
next_state <= s565;
ELSE
next_state <= s564;
END IF;
WHEN s565 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
else
next_state <= G27_e;
end if;
when G28_1 =>
if (rdy_i = '1') then
next_state <= G28_2;
else
next_state <= G28_1;
end if;
when G28_2 =>
next_state <= G28_3;
when G28_3 =>
next_state <= G28_4;
when G28_4 =>
next_state <= G28_5;
when G28_5 =>
if (rdy_i = '1') then
next_state <= G28_e;
else
next_state <= G28_5;
end if;
when G28_e =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
else
next_state <= G28_e;
end if;
when G29_1 =>
if (rdy_i = '1') then
next_state <= G29_2;
else
next_state <= G29_1;
end if;
when G29_2 =>
next_state <= G29_3;
when G29_3 =>
next_state <= G29_4;
when G29_4 =>
next_state <= G29_5;
when G29_5 =>
if (rdy_i = '1') then
next_state <= G29_e;
else
next_state <= G29_5;
end if;
when G29_e =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
next_state <= s565;
END IF;
WHEN s566 =>
IF (rdy_i = '1') THEN
next_state <= s564;
ELSE
next_state <= s566;
END IF;
WHEN s266 =>
IF (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
(reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN
else
next_state <= G29_e;
end if;
when G2_1 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
next_state <= s301;
ELSE
next_state <= s266;
END IF;
WHEN s301 =>
IF (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN
else
next_state <= G2_1;
end if;
when G30_1 =>
next_state <= G30_2;
when G30_2 =>
next_state <= G30_3;
when G30_3 =>
next_state <= G30_4;
when G30_4 =>
next_state <= G30_5;
when G30_5 =>
if (rdy_i = '1') then
next_state <= G30_e;
else
next_state <= G30_5;
end if;
when G30_e =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
next_state <= s302;
ELSE
next_state <= s301;
END IF;
WHEN s302 =>
IF (rdy_i = '1') THEN
else
next_state <= G30_e;
end if;
when G31_1 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
next_state <= s302;
END IF;
WHEN RES =>
next_state <= s544;
WHEN s511 =>
IF (rdy_i = '1' and
zw_REG_OP = X"E5") THEN
next_state <= s574;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') THEN
else
next_state <= G31_1;
end if;
when G32_1 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F5") THEN
next_state <= s569;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"ED") THEN
next_state <= s559;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"FD") THEN
next_state <= s562;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F9") THEN
next_state <= s567;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F1") THEN
next_state <= s568;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E1") THEN
next_state <= s570;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') THEN
else
next_state <= G32_1;
end if;
when G33_1 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
next_state <= s511;
END IF;
WHEN s559 =>
IF (rdy_i = '1') THEN
next_state <= s574;
ELSE
next_state <= s559;
END IF;
WHEN s562 =>
IF (rdy_i = '1') THEN
next_state <= s573;
ELSE
next_state <= s562;
END IF;
WHEN s567 =>
IF (rdy_i = '1') THEN
next_state <= s573;
ELSE
next_state <= s567;
END IF;
WHEN s568 =>
IF (rdy_i = '1') THEN
next_state <= s571;
ELSE
next_state <= s568;
END IF;
WHEN s569 =>
IF (rdy_i = '1') THEN
next_state <= s574;
ELSE
next_state <= s569;
END IF;
WHEN s570 =>
IF (rdy_i = '1') THEN
next_state <= s572;
ELSE
next_state <= s570;
END IF;
WHEN s571 =>
IF (rdy_i = '1') THEN
next_state <= s573;
ELSE
next_state <= s571;
END IF;
WHEN s572 =>
IF (rdy_i = '1') THEN
next_state <= s559;
ELSE
next_state <= s572;
END IF;
WHEN s573 =>
IF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') THEN
else
next_state <= G33_1;
end if;
when G34_1 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') THEN
else
next_state <= G34_1;
end if;
when G3_1 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
next_state <= s574;
ELSE
next_state <= s573;
END IF;
WHEN s574 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
else
next_state <= G3_1;
end if;
when G4_1 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
else
next_state <= G4_1;
end if;
when G5_1 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
next_state <= s574;
END IF;
WHEN s548 =>
IF (rdy_i = '1') THEN
next_state <= s551;
ELSE
next_state <= s548;
END IF;
WHEN s551 =>
next_state <= s552;
WHEN s552 =>
next_state <= s576;
WHEN s575 =>
IF (rdy_i = '1') THEN
next_state <= s577;
ELSE
next_state <= s575;
END IF;
WHEN s576 =>
next_state <= s575;
WHEN s577 =>
IF (rdy_i = '1') THEN
else
next_state <= G5_1;
end if;
when G6_1 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
next_state <= s577;
END IF;
WHEN s532 =>
IF (rdy_i = '1') THEN
next_state <= s533;
ELSE
next_state <= s532;
END IF;
WHEN s533 =>
next_state <= s534;
WHEN s534 =>
next_state <= s536;
WHEN s535 =>
IF (rdy_i = '1') THEN
next_state <= s537;
ELSE
next_state <= s535;
END IF;
WHEN s536 =>
next_state <= s535;
WHEN s537 =>
IF (rdy_i = '1') THEN
else
next_state <= G6_1;
end if;
when G7_1 =>
if (rdy_i = '1') then
next_state <= FETCH;
ELSE
next_state <= s537;
END IF;
WHEN OTHERS =>
else
next_state <= G7_1;
end if;
when G8_1 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= G8_1;
end if;
when G9_1 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= G9_1;
end if;
when RES =>
next_state <= G30_1;
when others =>
next_state <= RES;
END CASE;
END PROCESS nextstate_proc;
end case;
end process nextstate_proc;
-----------------------------------------------------------------
output_proc : PROCESS (
output_proc : process (
adr_nxt_pc_i,
adr_pc_i,
adr_sp_i,
3388,7 → 3241,7
zw_b4
)
-----------------------------------------------------------------
BEGIN
begin
-- Default Assignment
a_o <= sig_PC;
adr_o <= X"0000";
3410,8 → 3263,6
sel_sp_in_o <= reg_sel_sp_in;
-- Default Assignment To Internals
sig_D_OUT <= X"00";
sig_RD <= '1';
sig_RWn <= '1';
sig_SYNC <= '0';
sig_WR <= '0';
zw_ALU <= '0' & X"00";
3423,19 → 3274,17
zw_ALU6 <= X"0";
 
-- Combined Actions
CASE current_state IS
WHEN FETCH =>
sig_RWn <= '1';
sig_RD <= '1';
case current_state is
when FETCH =>
sig_SYNC <= NOT (rdy_i);
IF ((nmi_i = '1') AND (rdy_i = '1')) THEN
if ((nmi_i = '1') and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((irq_n_i = '0' and
reg_F(2) = '0') AND (rdy_i = '1')) THEN
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"69" or
elsif ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
3442,16 → 3291,16
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") AND (rdy_i = '1')) THEN
d_i = X"71") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"06" or
elsif ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") AND (rdy_i = '1')) THEN
d_i = X"1E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"90" or
elsif ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
3458,51 → 3307,51
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") AND (rdy_i = '1')) THEN
d_i = X"70") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"24" or
d_i = X"2C") AND (rdy_i = '1')) THEN
elsif ((d_i = X"24" or
d_i = X"2C") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN
elsif ((d_i = X"00") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN
elsif ((d_i = X"18") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN
elsif ((d_i = X"D8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN
elsif ((d_i = X"58") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN
elsif ((d_i = X"B8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"E0" or
elsif ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") AND (rdy_i = '1')) THEN
d_i = X"EC") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"C0" or
elsif ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") AND (rdy_i = '1')) THEN
d_i = X"CC") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"C6" or
elsif ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") AND (rdy_i = '1')) THEN
d_i = X"DE") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN
elsif ((d_i = X"CA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN
elsif ((d_i = X"88") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"49" or
elsif ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
3533,29 → 3382,29
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") AND (rdy_i = '1')) THEN
d_i = X"D1") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"E6" or
elsif ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") AND (rdy_i = '1')) THEN
d_i = X"FE") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN
elsif ((d_i = X"E8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN
elsif ((d_i = X"C8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"4C" or
d_i = X"6C") AND (rdy_i = '1')) THEN
elsif ((d_i = X"4C" or
d_i = X"6C") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN
elsif ((d_i = X"20") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"A9" or
elsif ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
3562,63 → 3411,63
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") AND (rdy_i = '1')) THEN
d_i = X"B1") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"A2" or
elsif ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") AND (rdy_i = '1')) THEN
d_i = X"BE") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"A0" or
elsif ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") AND (rdy_i = '1')) THEN
d_i = X"BC") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"46" or
elsif ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") AND (rdy_i = '1')) THEN
d_i = X"5E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN
elsif ((d_i = X"EA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN
elsif ((d_i = X"48") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN
elsif ((d_i = X"08") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN
elsif ((d_i = X"68") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN
elsif ((d_i = X"28") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"26" or
elsif ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") AND (rdy_i = '1')) THEN
d_i = X"3E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"66" or
elsif ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") AND (rdy_i = '1')) THEN
d_i = X"7E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN
elsif ((d_i = X"40") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN
elsif ((d_i = X"60") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"E9" or
elsif ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
3625,508 → 3474,437
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") AND (rdy_i = '1')) THEN
d_i = X"F1") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN
elsif ((d_i = X"38") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN
elsif ((d_i = X"F8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN
elsif ((d_i = X"78") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"85" or
elsif ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91") AND (rdy_i = '1')) THEN
d_i = X"91") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"86" or
elsif ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") AND (rdy_i = '1')) THEN
d_i = X"8E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"84" or
elsif ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") AND (rdy_i = '1')) THEN
d_i = X"8C") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN
elsif ((d_i = X"AA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"0A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"4A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"2A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"6A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN
elsif ((d_i = X"A8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN
elsif ((d_i = X"98") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN
elsif ((d_i = X"BA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"8A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN
elsif ((d_i = X"9A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s1 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s2 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s5 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s3 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s4 =>
IF (rdy_i = '1' and
zw_REG_OP = X"9A") THEN
adr_o <= X"01" & d_regs_out_i;
end if;
when G10_1 =>
if (rdy_i = '1' and
zw_REG_OP = X"65") then
ld_o <= "11";
ld_sp_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"BA") THEN
d_regs_in_o <= adr_sp_i (7 downto 0);
ch_a_o <= adr_sp_i (7 downto 0);
ch_b_o <= X"00";
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1') THEN
ch_a_o <= d_regs_out_i;
ch_b_o <= X"00";
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s12 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s16 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s17 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s24 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s25 =>
IF (rdy_i = '1') THEN
d_regs_in_o <= d_alu_i;
ch_a_o <= d_regs_out_i;
ch_b_o <= zw_b4;
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s273 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s307 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s177 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"9D") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"99") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"91") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
ch_a_o <= d_i;
ch_b_o <= X"01";
ELSIF (rdy_i = '1' and
zw_REG_OP = X"81") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"96") THEN
ch_a_o <= d_i;
ch_b_o <= q_y_i;
END IF;
WHEN s180 =>
IF (rdy_i = '1') THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
zw_ALU6(2 downto 0) <= (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
zw_ALU5(2 downto 0) <= (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when G10_2 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when G10_3 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when G10_4 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s181 =>
IF (rdy_i = '1') THEN
end if;
when G10_5 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
END IF;
WHEN s182 =>
sig_RWn <= '1';
sig_RD <= '1';
IF (rdy_i = '1') THEN
end if;
when G10_6 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s183 =>
IF (rdy_i = '1') THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
end if;
when G10_e1 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
zw_ALU6(2 downto 0) <= (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
zw_ALU5(2 downto 0) <= (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when G10_e2 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
zw_ALU6(2 downto 0) <= (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
zw_ALU5(2 downto 0) <= (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when G10_e3 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when G11_1 =>
if (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s184 =>
sig_SYNC <= '1';
fetch_o <= '1';
WHEN s185 =>
IF (rdy_i = '1') THEN
sig_RWn <= '0';
sig_RD <= '0';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when G11_2 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when G11_4 =>
if (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) then
sig_D_OUT <= d_i(6 downto 0) & '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) then
sig_D_OUT <= '0' & d_i(7 downto 1);
sig_WR <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) then
sig_D_OUT <= d_i(6 downto 0) & reg_F(0);
sig_WR <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) then
sig_D_OUT <= reg_F(0) & d_i(7 downto 1);
sig_WR <= '1';
end if;
when G11_5 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s187 =>
sig_SYNC <= '1';
fetch_o <= '1';
WHEN s188 =>
IF (rdy_i = '1') THEN
ch_a_o <= zw_b1;
ch_b_o <= X"01";
END IF;
WHEN s189 =>
IF (rdy_i = '1') THEN
end if;
when G11_6 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s190 =>
end if;
when G11_e =>
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
WHEN s191 =>
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
WHEN s192 =>
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
WHEN s193 =>
sig_SYNC <= '1';
fetch_o <= '1';
WHEN s377 =>
IF (rdy_i = '1') THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= q_a_i;
when G12_1 =>
if (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
(reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) then
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s381 =>
sig_SYNC <= '1';
fetch_o <= '1';
WHEN s378 =>
IF (rdy_i = '1') THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F;
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s382 =>
sig_SYNC <= '1';
fetch_o <= '1';
WHEN s379 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s384 =>
IF (rdy_i = '1') THEN
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s380 =>
IF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s386 =>
IF (rdy_i = '1') THEN
ld_pc_o <= '1';
end if;
when G12_e1 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s387 =>
IF (rdy_i = '1') THEN
elsif (rdy_i = '1') then
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s388 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s389 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s392 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when G12_e2 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s390 =>
IF (rdy_i = '1') THEN
end if;
when G13_1 =>
if (rdy_i = '1' and
zw_REG_OP = X"24") then
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s393 =>
IF (rdy_i = '1') THEN
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s395 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_pc_o <= '1';
end if;
when G13_2 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s396 =>
IF (rdy_i = '1') THEN
end if;
when G13_e =>
if (rdy_i = '1') then
ch_a_o <= q_a_i AND d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s397 =>
IF (rdy_i = '1') THEN
end if;
when G14_1 =>
if (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
END IF;
WHEN s398 =>
IF (rdy_i = '1') THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
END IF;
WHEN s399 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
WHEN s401 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
elsif (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s526 =>
IF (rdy_i = '1') THEN
elsif (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end if;
when G14_2 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when G14_3 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= zw_b4;
end if;
when G14_4 =>
if (rdy_i = '1') then
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
END IF;
WHEN s527 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
WHEN s528 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F OR X"10";
WHEN s530 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
sig_D_OUT <= zw_b1;
end if;
when G14_5 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s544 =>
ld_o <= "11";
ld_sp_o <= '1';
WHEN s545 =>
adr_o <= X"FFFB";
ld_o <= "11";
ld_pc_o <= '1';
WHEN s546 =>
ld_o <= "11";
ld_pc_o <= '1';
WHEN s549 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
end if;
when G14_6 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s550 =>
ld_o <= "11";
ld_sp_o <= '1';
WHEN s404 =>
IF (rdy_i = '1') THEN
ch_a_o <= q_a_i (6 downto 0) & '0';
ch_b_o <= X"00";
d_regs_in_o <= q_a_i (6 downto 0) & '0';
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s556 =>
IF (rdy_i = '1') THEN
ch_a_o <= '0' & q_a_i (7 downto 1);
ch_b_o <= X"00";
d_regs_in_o <= '0' & q_a_i (7 downto 1);
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s557 =>
IF (rdy_i = '1') THEN
ch_a_o <= q_a_i (6 downto 0) & reg_F(0);
ch_b_o <= X"00";
d_regs_in_o <= q_a_i (6 downto 0) & reg_F(0);
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s579 =>
IF (rdy_i = '1') THEN
ch_a_o <= reg_F(0) & q_a_i (7 downto 1);
ch_b_o <= X"00";
d_regs_in_o <= reg_F(0) & q_a_i (7 downto 1);
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s201 =>
IF (rdy_i = '1' and
end if;
when G14_e =>
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
when G15_1 =>
if (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((rdy_i = '1' and
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i OR q_a_i;
4135,12 → 3913,12
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF ((rdy_i = '1' and
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i XOR q_a_i;
4149,12 → 3927,12
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF ((rdy_i = '1' and
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i AND q_a_i;
4163,23 → 3941,23
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF ((rdy_i = '1' and
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
ld_o <= "11";
ld_pc_o <= '1';
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i;
4188,15 → 3966,15
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) THEN
zw_REG_OP = X"D5")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
4205,98 → 3983,87
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) THEN
zw_REG_OP = X"CC")) then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) THEN
zw_REG_OP = X"DD")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) THEN
zw_REG_OP = X"D9")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) THEN
zw_REG_OP = X"D1")) then
ch_a_o <= d_i;
ch_b_o <= X"01";
ELSIF (rdy_i = '1' and
elsif (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) THEN
zw_REG_OP = X"C1")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"B6") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
END IF;
WHEN s202 =>
IF (rdy_i = '1') THEN
end if;
when G15_2 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s210 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
end if;
when G15_3 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s211 =>
IF (rdy_i = '1') THEN
end if;
when G15_4 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s215 =>
IF (rdy_i = '1') THEN
end if;
when G15_5 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
END IF;
WHEN s217 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s222 =>
IF (rdy_i = '1') THEN
ch_a_o <= zw_b1;
ch_b_o <= X"01";
END IF;
WHEN s223 =>
IF (rdy_i = '1') THEN
end if;
when G15_6 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s224 =>
IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
end if;
when G15_e1 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
4303,10 → 4070,11
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
4313,10 → 4081,11
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
4323,17 → 4092,19
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
4340,13 → 4111,12
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s225 =>
IF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
end if;
when G15_e2 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
4353,11 → 4123,10
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
4364,11 → 4133,10
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
4375,19 → 4143,17
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0') THEN
elsif (rdy_i = '1') then
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
4394,602 → 4160,596
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s226 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) THEN
end if;
when G15_e3 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when G16_1 =>
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
END IF;
WHEN s243 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s244 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s247 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s343 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= zw_b4;
END IF;
WHEN s250 =>
IF (rdy_i = '1') THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= zw_b1;
END IF;
WHEN s251 =>
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
WHEN s351 =>
IF (rdy_i = '1' and
zw_REG_OP = X"24") THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"2C") THEN
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s361 =>
IF (rdy_i = '1') THEN
ch_a_o <= q_a_i AND d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s360 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s403 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) THEN
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s406 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s407 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s409 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s416 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) THEN
sig_D_OUT <= d_i(6 downto 0) & '0';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) THEN
sig_D_OUT <= '0' & d_i(7 downto 1);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) THEN
sig_D_OUT <= d_i(6 downto 0) & reg_F(0);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) THEN
sig_D_OUT <= reg_F(0) & d_i(7 downto 1);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
END IF;
WHEN s418 =>
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
WHEN s510 =>
IF (rdy_i = '1' and
zw_REG_OP = X"65") THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') THEN
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"75") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"6D") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"7D") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"79") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"71") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
ch_a_o <= d_i;
ch_b_o <= X"01";
ELSIF (rdy_i = '1' and
zw_REG_OP = X"61") THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5);
zw_ALU6(2 downto 0) <= (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
zw_ALU5(2 downto 0) <= (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
zw_ALU6 <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5 <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s553 =>
IF (rdy_i = '1') THEN
end if;
when G16_2 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s555 =>
IF (rdy_i = '1') THEN
end if;
when G16_3 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when G16_4 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s558 =>
IF (rdy_i = '1') THEN
end if;
when G16_5 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
END IF;
WHEN s560 =>
IF (rdy_i = '1') THEN
end if;
when G16_6 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s563 =>
IF (rdy_i = '1') THEN
ch_a_o <= zw_b1;
ch_b_o <= X"01";
END IF;
WHEN s564 =>
IF (rdy_i = '1' AND
end if;
when G16_e1 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') THEN
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1' AND
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') THEN
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5);
zw_ALU6(2 downto 0) <= (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
zw_ALU5(2 downto 0) <= (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
zw_ALU6 <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5 <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s565 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
end if;
when G16_e2 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
elsif (rdy_i = '1' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5);
zw_ALU6(2 downto 0) <= (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
zw_ALU5(2 downto 0) <= (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
zw_ALU6 <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5 <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s566 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
end if;
when G16_e3 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when G17_1 =>
if (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) then
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s266 =>
IF (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
(reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN
elsif (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) then
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1') THEN
elsif (rdy_i = '1' and
zw_REG_OP = X"9D") then
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s301 =>
IF (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1') THEN
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s302 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN RES =>
sig_RWn <= '1';
sig_RD <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when G17_10 =>
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
ld_sp_o <= '1';
sig_RWn <= '1';
sig_RD <= '1';
WHEN s511 =>
IF (rdy_i = '1' and
zw_REG_OP = X"E5") THEN
when G17_2 =>
if (rdy_i = '1') then
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') THEN
end if;
when G17_3 =>
if (rdy_i = '1') then
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F5") THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"ED") THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"FD") THEN
ld_o <= "11";
ld_pc_o <= '1';
end if;
when G17_4 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F9") THEN
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when G17_5 =>
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
when G17_6 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F1") THEN
end if;
when G17_7 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when G17_9 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E1") THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') THEN
end if;
when G17_e =>
sig_SYNC <= '1';
fetch_o <= '1';
when G18_1 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
end if;
when G18_2 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
when G18_3 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_WR <= '1';
sig_D_OUT <= reg_F OR X"10";
when G18_e =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when G19_1 =>
if (rdy_i = '1') then
d_regs_in_o <= d_alu_i;
ch_a_o <= d_regs_out_i;
ch_b_o <= zw_b4;
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5);
zw_ALU6 <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5 <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s559 =>
IF (rdy_i = '1') THEN
end if;
when G1_1 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when G20_2 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s562 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
end if;
when G20_e =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s567 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when G21_1 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
END IF;
WHEN s568 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= q_y_i;
END IF;
WHEN s569 =>
IF (rdy_i = '1') THEN
end if;
when G21_2 =>
if (rdy_i = '1') then
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
end if;
when G21_3 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
when G21_e =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s571 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when G22_1 =>
if (rdy_i = '1') then
sig_WR <= '1';
sig_D_OUT <= q_a_i;
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s572 =>
IF (rdy_i = '1') THEN
ch_a_o <= zw_b1;
ch_b_o <= X"01";
END IF;
WHEN s573 =>
IF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
ld_sp_o <= '1';
end if;
when G22_e =>
sig_SYNC <= '1';
fetch_o <= '1';
when G23_1 =>
if (rdy_i = '1') then
sig_WR <= '1';
sig_D_OUT <= reg_F;
ld_o <= "11";
ld_sp_o <= '1';
end if;
when G23_e =>
sig_SYNC <= '1';
fetch_o <= '1';
when G24_1 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when G24_e =>
if (rdy_i = '1') then
d_regs_in_o <= d_i;
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5);
zw_ALU6 <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5 <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
end if;
when G25_1 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when G25_e =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s574 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
end if;
when G26_1 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when G26_2 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when G26_3 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when G26_e =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5);
zw_ALU6 <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5 <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
end if;
when G27_1 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when G27_2 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when G27_4 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when G27_e =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s548 =>
IF (rdy_i = '1') THEN
end if;
when G28_1 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
END IF;
WHEN s551 =>
end if;
when G28_2 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
WHEN s552 =>
when G28_3 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F;
WHEN s577 =>
IF (rdy_i = '1') THEN
when G28_e =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN s532 =>
IF (rdy_i = '1') THEN
end if;
when G29_1 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
END IF;
WHEN s533 =>
end if;
when G29_2 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
WHEN s534 =>
when G29_3 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F;
WHEN s537 =>
IF (rdy_i = '1') THEN
when G29_e =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS output_proc;
end if;
when G2_1 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when G30_1 =>
ld_o <= "11";
ld_sp_o <= '1';
when G30_2 =>
ld_o <= "11";
ld_sp_o <= '1';
when G30_3 =>
adr_o <= X"FFFB";
ld_o <= "11";
ld_pc_o <= '1';
when G30_4 =>
ld_o <= "11";
ld_pc_o <= '1';
when G30_e =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when G31_1 =>
if (rdy_i = '1') then
ch_a_o <= q_a_i (6 downto 0) & '0';
ch_b_o <= X"00";
d_regs_in_o <= q_a_i (6 downto 0) & '0';
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when G32_1 =>
if (rdy_i = '1') then
ch_a_o <= '0' & q_a_i (7 downto 1);
ch_b_o <= X"00";
d_regs_in_o <= '0' & q_a_i (7 downto 1);
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when G33_1 =>
if (rdy_i = '1') then
ch_a_o <= q_a_i (6 downto 0) & reg_F(0);
ch_b_o <= X"00";
d_regs_in_o <= q_a_i (6 downto 0) & reg_F(0);
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when G34_1 =>
if (rdy_i = '1') then
ch_a_o <= reg_F(0) & q_a_i (7 downto 1);
ch_b_o <= X"00";
d_regs_in_o <= reg_F(0) & q_a_i (7 downto 1);
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when G3_1 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when G4_1 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when G5_1 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when G6_1 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when G7_1 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when G8_1 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when G9_1 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
adr_o <= X"01" & d_regs_out_i;
ld_o <= "11";
ld_sp_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
d_regs_in_o <= adr_sp_i (7 downto 0);
ch_a_o <= adr_sp_i (7 downto 0);
ch_b_o <= X"00";
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1') then
ch_a_o <= d_regs_out_i;
ch_b_o <= X"00";
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when RES =>
ld_o <= "11";
ld_pc_o <= '1';
ld_sp_o <= '1';
when others =>
null;
end case;
end process output_proc;
-- Concurrent Statements
-- Clocked output assignments
4996,6 → 4756,5
d_o <= d_o_cld;
rd_o <= rd_o_cld;
sync_o <= sync_o_cld;
wr_n_o <= wr_n_o_cld;
wr_o <= wr_o_cld;
END fsm;
end fsm;
/trunk/rtl/vhdl/core.vhd
1,8 → 1,8
-- VHDL Entity R6502_TC.Core.symbol
--
-- Created:
-- by - eda.UNKNOWN (TEST)
-- at - 19:21:54 07.01.2009
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 11:47:55 23.02.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
10,30 → 10,29
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ENTITY Core IS
PORT(
clk_clk_i : IN std_logic;
d_i : IN std_logic_vector (7 DOWNTO 0);
irq_n_i : IN std_logic;
nmi_n_i : IN std_logic;
rdy_i : IN std_logic;
rst_rst_n_i : IN std_logic;
so_n_i : IN std_logic;
a_o : OUT std_logic_vector (15 DOWNTO 0);
d_o : OUT std_logic_vector (7 DOWNTO 0);
rd_o : OUT std_logic;
sync_o : OUT std_logic;
wr_n_o : OUT std_logic;
wr_o : OUT std_logic
entity Core is
port(
clk_clk_i : in std_logic;
d_i : in std_logic_vector (7 downto 0);
irq_n_i : in std_logic;
nmi_n_i : in std_logic;
rdy_i : in std_logic;
rst_rst_n_i : in std_logic;
so_n_i : in std_logic;
a_o : out std_logic_vector (15 downto 0);
d_o : out std_logic_vector (7 downto 0);
rd_o : out std_logic;
sync_o : out std_logic;
wr_o : out std_logic
);
 
-- Declarations
 
END Core ;
end Core ;
 
-- Jens-D. Gutschmidt Project: R6502_TC
-- scantara2003@yahoo.de
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
-- COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version
-- 3 of the License, or any later version.
49,13 → 48,13
-- <<-- more -->>
-- Title: Core
-- Path: R6502_TC/Core/struct
-- Edited: by eda on 07 Jan 2009
-- Edited: by eda on 10 Feb 2009
--
-- VHDL Architecture R6502_TC.Core.struct
--
-- Created:
-- by - eda.UNKNOWN (TEST)
-- at - 19:21:55 07.01.2009
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 11:47:57 23.02.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
63,175 → 62,186
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
library R6502_TC;
 
ARCHITECTURE struct OF Core IS
architecture struct of Core is
 
-- Architecture declarations
 
-- Internal signal declarations
SIGNAL adr_nxt_pc_o_i : std_logic_vector(15 DOWNTO 0);
SIGNAL adr_o_i : std_logic_vector(15 DOWNTO 0);
SIGNAL adr_pc_o_i : std_logic_vector(15 DOWNTO 0);
SIGNAL adr_sp_o_i : std_logic_vector(15 DOWNTO 0);
SIGNAL ch_a_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL ch_b_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL d_alu_n_o_i : std_logic;
SIGNAL d_alu_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL d_alu_or_o_i : std_logic;
SIGNAL d_regs_in_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL d_regs_out_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL fetch_o_i : std_logic;
SIGNAL ld_o_i : std_logic_vector(1 DOWNTO 0);
SIGNAL ld_pc_o_i : std_logic;
SIGNAL ld_sp_o_i : std_logic;
SIGNAL load_regs_o_i : std_logic;
SIGNAL nmi_o_i : std_logic;
SIGNAL offset_o_i : std_logic_vector(15 DOWNTO 0);
SIGNAL q_a_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL q_x_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL q_y_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL reg_0flag_o_i : std_logic;
SIGNAL reg_1flag_o_i : std_logic;
SIGNAL reg_7flag_o_i : std_logic;
SIGNAL sel_pc_in_o_i : std_logic;
SIGNAL sel_pc_val_o_i : std_logic_vector(1 DOWNTO 0);
SIGNAL sel_rb_in_o_i : std_logic_vector(1 DOWNTO 0);
SIGNAL sel_rb_out_o_i : std_logic_vector(1 DOWNTO 0);
SIGNAL sel_reg_o_i : std_logic_vector(1 DOWNTO 0);
SIGNAL sel_sp_as_o_i : std_logic;
SIGNAL sel_sp_in_o_i : std_logic;
signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0);
signal adr_o_i : std_logic_vector(15 downto 0);
signal adr_pc_o_i : std_logic_vector(15 downto 0);
signal adr_sp_o_i : std_logic_vector(15 downto 0);
signal ch_a_o_i : std_logic_vector(7 downto 0);
signal ch_b_o_i : std_logic_vector(7 downto 0);
signal d_alu_n_o_i : std_logic;
signal d_alu_o_i : std_logic_vector(7 downto 0);
signal d_alu_or_o_i : std_logic;
signal d_regs_in_o_i : std_logic_vector(7 downto 0);
signal d_regs_out_o_i : std_logic_vector(7 downto 0);
signal fetch_o_i : std_logic;
signal ld_o_i : std_logic_vector(1 downto 0);
signal ld_pc_o_i : std_logic;
signal ld_sp_o_i : std_logic;
signal load_regs_o_i : std_logic;
signal nmi_o_i : std_logic;
signal offset_o_i : std_logic_vector(15 downto 0);
signal q_a_o_i : std_logic_vector(7 downto 0);
signal q_x_o_i : std_logic_vector(7 downto 0);
signal q_y_o_i : std_logic_vector(7 downto 0);
signal reg_0flag_o_i : std_logic;
signal reg_1flag_o_i : std_logic;
signal reg_7flag_o_i : std_logic;
signal sel_pc_in_o_i : std_logic;
signal sel_pc_val_o_i : std_logic_vector(1 downto 0);
signal sel_rb_in_o_i : std_logic_vector(1 downto 0);
signal sel_rb_out_o_i : std_logic_vector(1 downto 0);
signal sel_reg_o_i : std_logic_vector(1 downto 0);
signal sel_sp_as_o_i : std_logic;
signal sel_sp_in_o_i : std_logic;
 
 
-- ModuleWare signal declarations(v1.9) for instance 'U_11' of 'add'
signal mw_U_11temp_din0 : std_logic_vector(8 downto 0);
signal mw_U_11temp_din1 : std_logic_vector(8 downto 0);
signal mw_U_11sum : unsigned(8 downto 0);
 
-- Component Declarations
COMPONENT FSM_Execution_Unit
PORT (
adr_nxt_pc_i : IN std_logic_vector (15 DOWNTO 0);
adr_pc_i : IN std_logic_vector (15 DOWNTO 0);
adr_sp_i : IN std_logic_vector (15 DOWNTO 0);
clk_clk_i : IN std_logic ;
d_alu_i : IN std_logic_vector ( 7 DOWNTO 0 );
d_i : IN std_logic_vector ( 7 DOWNTO 0 );
d_regs_out_i : IN std_logic_vector ( 7 DOWNTO 0 );
irq_n_i : IN std_logic ;
nmi_i : IN std_logic ;
q_a_i : IN std_logic_vector ( 7 DOWNTO 0 );
q_x_i : IN std_logic_vector ( 7 DOWNTO 0 );
q_y_i : IN std_logic_vector ( 7 DOWNTO 0 );
rdy_i : IN std_logic ;
reg_0flag_i : IN std_logic ;
reg_1flag_i : IN std_logic ;
reg_7flag_i : IN std_logic ;
rst_rst_n_i : IN std_logic ;
so_n_i : IN std_logic ;
a_o : OUT std_logic_vector (15 DOWNTO 0);
adr_o : OUT std_logic_vector (15 DOWNTO 0);
ch_a_o : OUT std_logic_vector ( 7 DOWNTO 0 );
ch_b_o : OUT std_logic_vector ( 7 DOWNTO 0 );
d_o : OUT std_logic_vector ( 7 DOWNTO 0 );
d_regs_in_o : OUT std_logic_vector ( 7 DOWNTO 0 );
fetch_o : OUT std_logic ;
ld_o : OUT std_logic_vector ( 1 DOWNTO 0 );
ld_pc_o : OUT std_logic ;
ld_sp_o : OUT std_logic ;
load_regs_o : OUT std_logic ;
offset_o : OUT std_logic_vector ( 15 DOWNTO 0 );
rd_o : OUT std_logic ;
sel_pc_in_o : OUT std_logic ;
sel_pc_val_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_rb_in_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_rb_out_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_reg_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_sp_as_o : OUT std_logic ;
sel_sp_in_o : OUT std_logic ;
sync_o : OUT std_logic ;
wr_n_o : OUT std_logic ;
wr_o : OUT std_logic
component FSM_Execution_Unit
port (
adr_nxt_pc_i : in std_logic_vector (15 downto 0);
adr_pc_i : in std_logic_vector (15 downto 0);
adr_sp_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic ;
d_alu_i : in std_logic_vector ( 7 downto 0 );
d_i : in std_logic_vector ( 7 downto 0 );
d_regs_out_i : in std_logic_vector ( 7 downto 0 );
irq_n_i : in std_logic ;
nmi_i : in std_logic ;
q_a_i : in std_logic_vector ( 7 downto 0 );
q_x_i : in std_logic_vector ( 7 downto 0 );
q_y_i : in std_logic_vector ( 7 downto 0 );
rdy_i : in std_logic ;
reg_0flag_i : in std_logic ;
reg_1flag_i : in std_logic ;
reg_7flag_i : in std_logic ;
rst_rst_n_i : in std_logic ;
so_n_i : in std_logic ;
a_o : out std_logic_vector (15 downto 0);
adr_o : out std_logic_vector (15 downto 0);
ch_a_o : out std_logic_vector ( 7 downto 0 );
ch_b_o : out std_logic_vector ( 7 downto 0 );
d_o : out std_logic_vector ( 7 downto 0 );
d_regs_in_o : out std_logic_vector ( 7 downto 0 );
fetch_o : out std_logic ;
ld_o : out std_logic_vector ( 1 downto 0 );
ld_pc_o : out std_logic ;
ld_sp_o : out std_logic ;
load_regs_o : out std_logic ;
offset_o : out std_logic_vector ( 15 downto 0 );
rd_o : out std_logic ;
sel_pc_in_o : out std_logic ;
sel_pc_val_o : out std_logic_vector ( 1 downto 0 );
sel_rb_in_o : out std_logic_vector ( 1 downto 0 );
sel_rb_out_o : out std_logic_vector ( 1 downto 0 );
sel_reg_o : out std_logic_vector ( 1 downto 0 );
sel_sp_as_o : out std_logic ;
sel_sp_in_o : out std_logic ;
sync_o : out std_logic ;
wr_o : out std_logic
);
END COMPONENT;
COMPONENT FSM_NMI
PORT (
clk_clk_i : IN std_logic ;
fetch_i : IN std_logic ;
nmi_n_i : IN std_logic ;
rst_rst_n_i : IN std_logic ;
nmi_o : OUT std_logic
end component;
component FSM_NMI
port (
clk_clk_i : in std_logic ;
fetch_i : in std_logic ;
nmi_n_i : in std_logic ;
rst_rst_n_i : in std_logic ;
nmi_o : out std_logic
);
END COMPONENT;
COMPONENT RegBank_AXY
PORT (
clk_clk_i : IN std_logic ;
d_regs_in_i : IN std_logic_vector (7 DOWNTO 0);
load_regs_i : IN std_logic ;
rst_rst_n_i : IN std_logic ;
sel_rb_in_i : IN std_logic_vector (1 DOWNTO 0);
sel_rb_out_i : IN std_logic_vector (1 DOWNTO 0);
sel_reg_i : IN std_logic_vector (1 DOWNTO 0);
d_regs_out_o : OUT std_logic_vector (7 DOWNTO 0);
q_a_o : OUT std_logic_vector (7 DOWNTO 0);
q_x_o : OUT std_logic_vector (7 DOWNTO 0);
q_y_o : OUT std_logic_vector (7 DOWNTO 0)
end component;
component RegBank_AXY
port (
clk_clk_i : in std_logic ;
d_regs_in_i : in std_logic_vector (7 downto 0);
load_regs_i : in std_logic ;
rst_rst_n_i : in std_logic ;
sel_rb_in_i : in std_logic_vector (1 downto 0);
sel_rb_out_i : in std_logic_vector (1 downto 0);
sel_reg_i : in std_logic_vector (1 downto 0);
d_regs_out_o : out std_logic_vector (7 downto 0);
q_a_o : out std_logic_vector (7 downto 0);
q_x_o : out std_logic_vector (7 downto 0);
q_y_o : out std_logic_vector (7 downto 0)
);
END COMPONENT;
COMPONENT Reg_PC
PORT (
adr_i : IN std_logic_vector (15 DOWNTO 0);
clk_clk_i : IN std_logic ;
ld_i : IN std_logic_vector (1 DOWNTO 0);
ld_pc_i : IN std_logic ;
offset_i : IN std_logic_vector (15 DOWNTO 0);
rst_rst_n_i : IN std_logic ;
sel_pc_in_i : IN std_logic ;
sel_pc_val_i : IN std_logic_vector (1 DOWNTO 0);
adr_nxt_pc_o : OUT std_logic_vector (15 DOWNTO 0);
adr_pc_o : OUT std_logic_vector (15 DOWNTO 0)
end component;
component Reg_PC
port (
adr_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic ;
ld_i : in std_logic_vector (1 downto 0);
ld_pc_i : in std_logic ;
offset_i : in std_logic_vector (15 downto 0);
rst_rst_n_i : in std_logic ;
sel_pc_in_i : in std_logic ;
sel_pc_val_i : in std_logic_vector (1 downto 0);
adr_nxt_pc_o : out std_logic_vector (15 downto 0);
adr_pc_o : out std_logic_vector (15 downto 0)
);
END COMPONENT;
COMPONENT Reg_SP
PORT (
adr_low_i : IN std_logic_vector (7 DOWNTO 0);
clk_clk_i : IN std_logic ;
ld_low_i : IN std_logic ;
ld_sp_i : IN std_logic ;
rst_rst_n_i : IN std_logic ;
sel_sp_as_i : IN std_logic ;
sel_sp_in_i : IN std_logic ;
adr_sp_o : OUT std_logic_vector (15 DOWNTO 0)
end component;
component Reg_SP
port (
adr_low_i : in std_logic_vector (7 downto 0);
clk_clk_i : in std_logic ;
ld_low_i : in std_logic ;
ld_sp_i : in std_logic ;
rst_rst_n_i : in std_logic ;
sel_sp_as_i : in std_logic ;
sel_sp_in_i : in std_logic ;
adr_sp_o : out std_logic_vector (15 downto 0)
);
END COMPONENT;
end component;
 
-- Optional embedded configurations
-- pragma synthesis_off
for all : FSM_Execution_Unit use entity R6502_TC.FSM_Execution_Unit;
for all : FSM_NMI use entity R6502_TC.FSM_NMI;
for all : RegBank_AXY use entity R6502_TC.RegBank_AXY;
for all : Reg_PC use entity R6502_TC.Reg_PC;
for all : Reg_SP use entity R6502_TC.Reg_SP;
-- pragma synthesis_on
 
BEGIN
 
begin
 
-- ModuleWare code(v1.9) for instance 'U_11' of 'add'
u_11combo_proc: PROCESS (ch_a_o_i, ch_b_o_i)
VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0);
VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0);
VARIABLE temp_sum : unsigned(8 DOWNTO 0);
VARIABLE temp_carry : std_logic;
BEGIN
temp_din0 := '0' & ch_a_o_i;
temp_din1 := '0' & ch_b_o_i;
mw_U_11temp_din0 <= '0' & ch_a_o_i;
mw_U_11temp_din1 <= '0' & ch_b_o_i;
u_11combo_proc: process (mw_U_11temp_din0, mw_U_11temp_din1)
variable temp_carry : std_logic;
begin
temp_carry := '0';
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
d_alu_o_i <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8);
reg_0flag_o_i <= temp_sum(8) ;
END PROCESS u_11combo_proc;
mw_U_11sum <= unsigned(mw_U_11temp_din0) + unsigned(mw_U_11temp_din1) + temp_carry;
end process u_11combo_proc;
d_alu_o_i <= conv_std_logic_vector(mw_U_11sum(7 downto 0),8);
reg_0flag_o_i <= mw_U_11sum(8) ;
 
-- ModuleWare code(v1.9) for instance 'U_8' of 'inv'
reg_1flag_o_i <= NOT(d_alu_or_o_i);
reg_1flag_o_i <= not(d_alu_or_o_i);
 
-- ModuleWare code(v1.9) for instance 'U_9' of 'inv'
reg_7flag_o_i <= NOT(d_alu_n_o_i);
reg_7flag_o_i <= not(d_alu_n_o_i);
 
-- ModuleWare code(v1.9) for instance 'U_10' of 'inv'
d_alu_n_o_i <= NOT(d_alu_o_i(7));
d_alu_n_o_i <= not(d_alu_o_i(7));
 
-- ModuleWare code(v1.9) for instance 'U_7' of 'por'
d_alu_or_o_i <= d_alu_o_i(0) OR d_alu_o_i(1) OR d_alu_o_i(2) OR d_alu_o_i(3) OR d_alu_o_i(4) OR d_alu_o_i(5) OR d_alu_o_i(6) OR d_alu_o_i(7);
d_alu_or_o_i <= d_alu_o_i(0) or d_alu_o_i(1) or d_alu_o_i(2) or d_alu_o_i(3) or d_alu_o_i(4) or d_alu_o_i(5) or d_alu_o_i(6) or d_alu_o_i(7);
 
-- Instance port mappings.
U_4 : FSM_Execution_Unit
PORT MAP (
port map (
adr_nxt_pc_i => adr_nxt_pc_o_i,
adr_pc_i => adr_pc_o_i,
adr_sp_i => adr_sp_o_i,
271,11 → 281,10
sel_sp_as_o => sel_sp_as_o_i,
sel_sp_in_o => sel_sp_in_o_i,
sync_o => sync_o,
wr_n_o => wr_n_o,
wr_o => wr_o
);
U_6 : FSM_NMI
PORT MAP (
port map (
clk_clk_i => clk_clk_i,
fetch_i => fetch_o_i,
nmi_n_i => nmi_n_i,
283,7 → 292,7
nmi_o => nmi_o_i
);
U_2 : RegBank_AXY
PORT MAP (
port map (
clk_clk_i => clk_clk_i,
d_regs_in_i => d_regs_in_o_i,
load_regs_i => load_regs_o_i,
297,7 → 306,7
q_y_o => q_y_o_i
);
U_0 : Reg_PC
PORT MAP (
port map (
adr_i => adr_o_i,
clk_clk_i => clk_clk_i,
ld_i => ld_o_i,
310,7 → 319,7
adr_pc_o => adr_pc_o_i
);
U_1 : Reg_SP
PORT MAP (
port map (
adr_low_i => adr_o_i(7 DOWNTO 0),
clk_clk_i => clk_clk_i,
ld_low_i => ld_o_i(0),
321,4 → 330,4
adr_sp_o => adr_sp_o_i
);
 
END struct;
end struct;
/trunk/rtl/vhdl/fsm_nmi.vhd
2,7 → 2,7
--
-- Created:
-- by - eda.UNKNOWN (TEST)
-- at - 18:46:08 07.01.2009
-- at - 19:25:41 10.02.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
27,7 → 27,7
 
-- scantara2003@yahoo.de
 
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
-- COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG
 
--
 
59,7 → 59,7
 
-- Path: R6502_TC/FSM_NMI/fsm
 
-- Edited: by eda on 07 Jan 2009
-- Edited: by eda on 10 Feb 2009
 
--
-- VHDL Architecture R6502_TC.FSM_NMI.fsm
66,7 → 66,7
--
-- Created:
-- by - eda.UNKNOWN (TEST)
-- at - 18:46:08 07.01.2009
-- at - 19:25:41 10.02.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
/trunk/rtl/vhdl/regbank_axy.vhd
2,7 → 2,7
--
-- Created:
-- by - eda.UNKNOWN (TEST)
-- at - 18:23:46 07.01.2009
-- at - 19:25:32 10.02.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
31,7 → 31,7
 
-- Jens-D. Gutschmidt Project: R6502_TC
-- scantara2003@yahoo.de
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
-- COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any later version.
47,13 → 47,13
-- <<-- more -->>
-- Title: Register Bank for register A, X and Y
-- Path: R6502_TC/RegBank_AXY/struct
-- Edited: by eda on 02 Jan 2009
-- Edited: by eda on 10 Feb 2009
--
-- VHDL Architecture R6502_TC.RegBank_AXY.struct
--
-- Created:
-- by - eda.UNKNOWN (TEST)
-- at - 18:23:46 07.01.2009
-- at - 19:25:32 10.02.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
/trunk/doc/HTML.rar Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/doc/src/6502 IP Core Specification_V0_5.doc Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/doc/src/6502 IP Core Specification_V0_5.doc
trunk/doc/src/6502 IP Core Specification_V0_5.doc Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/TO_DO_list.txt =================================================================== --- trunk/TO_DO_list.txt (revision 14) +++ trunk/TO_DO_list.txt (revision 15) @@ -1,3 +1,8 @@ +(February 25th 2009) +- (DONE) CORRECTED "RTI" (wrong: use of stack pointer) +- (DONE) RENAME all states of "FSM Execution Unit" for better reading +- (90%) Finish working for Specification of cpu6502_tc + (January, 4th 2009) - (DONE) Remove unused nets, register and modules - (85%) Finish working for Specification of cpu65C02_tc @@ -12,5 +17,5 @@ - (WORKING) Create high level testbench in assembler and hardware for testing all Op Codes (include accurate cycle timing) - (WORKING) Create simulation files for Modelsim -- (WORKING) Create a simple .wlf file to demonstrate the cpu65C02_tc +- (WORKING) Create a simple .wlf file to demonstrate the cpu6502_tc - Update the HDL Designer files for better viewing and understanding \ No newline at end of file

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