URL
https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk
Subversion Repositories dbg_interface
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 14 to Rev 15
- ↔ Reverse comparison
Rev 14 → Rev 15
/trunk/bench/verilog/dbg_tb.v
45,6 → 45,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.7 2001/10/16 10:10:18 mohor |
// Signal names changed to lowercase. |
// |
// Revision 1.6 2001/10/15 09:52:50 mohor |
// Wishbone interface added, few fixes for better performance, |
// hooks for boundary scan testing added. |
122,7 → 125,7
dbg_top dbgTAP1(.tms_pad_i(P_TMS), .tck_pad_i(P_TCK), .trst_pad_i(P_TRST), .tdi_pad_i(P_TDI), |
.tdo_pad_o(P_TDO), |
.capture_dr_o(), .shift_dr_o(), .update_dr_o(), .extest_selected_o(), |
.bs_chain_i(1'b0), |
.bs_chain_i(1'b0), .bs_chain_o(), |
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.wb_rst_i(wb_rst_i), .risc_clk_i(Mclk), |
/trunk/rtl/verilog/dbg_top.v
45,7 → 45,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.7 2001/10/16 10:09:56 mohor |
// Signal names changed to lowercase. |
// |
// |
// Revision 1.6 2001/10/15 09:55:47 mohor |
// Wishbone interface added, few fixes for better performance, |
// hooks for boundary scan testing added. |
85,7 → 88,7
tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o, |
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// Boundary Scan signals |
capture_dr_o, shift_dr_o, update_dr_o, extest_selected_o, bs_chain_i, |
capture_dr_o, shift_dr_o, update_dr_o, extest_selected_o, bs_chain_i, bs_chain_o, |
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// RISC signals |
risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i, |
117,8 → 120,8
output update_dr_o; |
output extest_selected_o; |
input bs_chain_i; |
output bs_chain_o; |
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// RISC signals |
input risc_clk_i; // Master clock (RISC clock) |
input [31:0] risc_data_i; // RISC data inputs (data that is written to the RISC registers) |
237,7 → 240,9
assign update_dr_o = UpdateDR; |
assign extest_selected_o = EXTESTSelected; |
wire BS_CHAIN_I = bs_chain_i; |
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assign bs_chain_o = tdi_pad_i; |
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// This signals are used only when TRACE is used in the design |
`ifdef TRACE_ENABLED |
wire [39:0] TraceChain; // Chain that comes from trace module |