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URL https://opencores.org/ocsvn/ha1588/ha1588/trunk

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Rev 14 → Rev 15

/ha1588/trunk/rtl/top/top.v
0,0 → 1,6
`timescale 1ns/1ns
 
module top (
);
 
endmodule
/ha1588/trunk/rtl/rtc/rtc_timer.v File deleted
/ha1588/trunk/rtl/rtc/rtc.v
0,0 → 1,96
`timescale 1ns/1ns
 
module rtc (
input rst, clk,
// 1. direct time adjustment: ToD set up
input time_ld,
input [37:0] time_reg_ns_in, // 37:8 ns, 7:0 ns_fraction
input [47:0] time_reg_sec_in, // 47:0 sec
// 2. frequency adjustment: frequency set up for drift compensation
input period_ld,
input [39:0] period_in, // 39:32 ns, 31:0 ns_fraction
input [37:0] time_acc_modulo, // 37: 8 ns, 7:0 ns_fraction
// 3. precise time adjustment: small time difference adjustment with a time mark
input adj_ld,
input [31:0] adj_ld_data,
input [39:0] period_adj, // 39:32 ns, 31:0 ns_fraction
 
// time output
output [37:0] time_reg_ns, // 37:8 ns, 7:0 ns_fraction
output [47:0] time_reg_sec // 47:0 sec
);
 
reg [39:0] period_fix; // 39:32 ns, 31:0 ns_fraction
reg [31:0] adj_cnt;
reg [39:0] time_adj; // 39:32 ns, 31:0 ns_fraction
// frequency and small time difference adjustment registers
always @(posedge rst or posedge clk) begin
if (rst) begin
period_fix <= 40'd0;
adj_cnt <= 32'hffffffff;
time_adj <= 40'd0;
end
else begin
if (period_ld) // load period adjustment
period_fix <= period_in;
else
period_fix <= period_fix;
 
if (adj_ld) // load precise time adjustment time mark
adj_cnt <= adj_ld_data;
else if (adj_cnt==32'hffffffff)
adj_cnt <= adj_cnt; // no cycling
else
adj_cnt <= adj_cnt - 1; // counting down
 
if (adj_cnt==0) // change period temparorily
time_adj <= period_fix + period_adj;
else
time_adj <= period_fix + 0;
end
end
 
wire [39:0] time_adj_08n_32f; // 39:32 ns, 31:0 ns_fraction
wire [15:0] time_adj_08n_08f; // 15: 8 ns, 7:0 ns_fraction
reg [23:0] time_adj_00n_24f; // 23:0 ns_fraction
// delta-sigma circuit to keep the lower 24bit of time_adj
assign time_adj_08n_32f = time_adj[39: 0] + {16'd0, time_adj_00n_24f}; // sigma the delta part
always @(posedge rst or posedge clk) begin // keep the delta part
if (rst) begin
time_adj_00n_24f <= 24'd0;
end
else begin
time_adj_00n_24f <= time_adj_08n_32f[23: 0];
end
end
assign time_adj_08n_08f = time_adj_08n_32f[39:24]; // output w/o the delta part
 
reg [37:0] time_acc_30n_08f; // 37:8 ns , 7:0 ns_fraction
reg [47:0] time_acc_48s; // 47:0 sec
// time accumulator (48bit_s + 30bit_ns + 8bit_ns_fraction)
always @(posedge rst or posedge clk) begin
if (rst) begin
time_acc_30n_08f <= 38'd0;
time_acc_48s <= 48'd0;
end
else begin
if (time_ld) begin // direct write
time_acc_30n_08f <= time_reg_ns_in;
time_acc_48s <= time_reg_sec_in;
end
else if (time_acc_30n_08f + {22'd0, time_adj_08n_08f} >= time_acc_modulo) begin
time_acc_30n_08f <= time_acc_30n_08f + {22'd0, time_adj_08n_08f} - time_acc_modulo;
time_acc_48s <= time_acc_48s + 1;
end
else begin
time_acc_30n_08f <= time_acc_30n_08f + {22'd0, time_adj_08n_08f};
time_acc_48s <= time_acc_48s;
end
end
end
 
// time output (48bit_s + 30bit_ns + 8bit_ns_fraction)
assign time_reg_ns = time_acc_30n_08f;
assign time_reg_sec = time_acc_48s;
 
endmodule
/ha1588/trunk/rtl/tsu/tsu_queue.v File deleted
/ha1588/trunk/rtl/tsu/tsu.v
0,0 → 1,202
`timescale 1ns/1ns
 
module tsu (
input rst,
 
input gmii_clk,
input gmii_ctrl,
input [7:0] gmii_data,
input rtc_timer_clk,
input [31:0] rtc_timer_in,
 
input q_rst,
input q_rd_clk,
input q_rd_en,
output [ 7:0] q_rd_stat,
output [55:0] q_rd_data
);
 
// buffer gmii input
reg int_gmii_ctrl;
reg int_gmii_ctrl_d1, int_gmii_ctrl_d2, int_gmii_ctrl_d3, int_gmii_ctrl_d4, int_gmii_ctrl_d5;
reg [7:0] int_gmii_data;
reg [7:0] int_gmii_data_d1;
always @(posedge rst or posedge gmii_clk) begin
if (rst) begin
int_gmii_ctrl <= 1'b0;
int_gmii_ctrl_d1 <= 1'b0;
int_gmii_ctrl_d2 <= 1'b0;
int_gmii_ctrl_d3 <= 1'b0;
int_gmii_ctrl_d4 <= 1'b0;
int_gmii_ctrl_d5 <= 1'b0;
int_gmii_data <= 8'h00;
int_gmii_data_d1 <= 8'h00;
end
else begin
int_gmii_ctrl <= gmii_ctrl;
int_gmii_ctrl_d1 <= int_gmii_ctrl;
int_gmii_ctrl_d2 <= int_gmii_ctrl_d1;
int_gmii_ctrl_d3 <= int_gmii_ctrl_d2;
int_gmii_ctrl_d4 <= int_gmii_ctrl_d3;
int_gmii_ctrl_d5 <= int_gmii_ctrl_d4;
int_gmii_data <= gmii_data;
int_gmii_data_d1 <= int_gmii_data;
end
end
 
// ptp CDC time stamping
wire ts_req = int_gmii_ctrl;
reg ts_req_d1, ts_req_d2, ts_req_d3;
always @(posedge rst or posedge rtc_timer_clk) begin
if (rst) begin
ts_req_d1 <= 1'b0;
ts_req_d2 <= 1'b0;
ts_req_d3 <= 1'b0;
end
else begin
ts_req_d1 <= ts_req;
ts_req_d2 <= ts_req_d1;
ts_req_d3 <= ts_req_d2;
end
end
reg [31:0] rtc_time_stamp;
always @(posedge rst or posedge rtc_timer_clk) begin
if (rst)
rtc_time_stamp <= 32'd0;
else
if (ts_req_d2 & !ts_req_d3)
rtc_time_stamp <= rtc_timer_in;
end
reg ts_ack, ts_ack_clr;
always @(posedge ts_ack_clr or posedge rtc_timer_clk) begin
if (ts_ack_clr)
ts_ack <= 1'b0;
else
if (ts_req_d2 & !ts_req_d3)
ts_ack <= 1'b1;
end
 
reg ts_ack_d1, ts_ack_d2, ts_ack_d3;
always @(posedge rst or posedge gmii_clk) begin
if (rst) begin
ts_ack_d1 <= 1'b0;
ts_ack_d2 <= 1'b0;
ts_ack_d3 <= 1'b0;
end
else begin
ts_ack_d1 <= ts_ack;
ts_ack_d2 <= ts_ack_d1;
ts_ack_d3 <= ts_ack_d2;
end
end
reg [31:0] gmii_time_stamp;
always @(posedge rst or posedge gmii_clk) begin
if (rst) begin
gmii_time_stamp <= 32'd0;
ts_ack_clr <= 1'b0;
end
else begin
if (ts_ack_d2 & !ts_ack_d3) begin
gmii_time_stamp <= rtc_time_stamp;
ts_ack_clr <= 1'b1;
end
else begin
gmii_time_stamp <= gmii_time_stamp;
ts_ack_clr <= 1'b0;
end
end
end
 
// 8b-32b datapath gearbox
reg int_valid;
reg int_sop, int_eop;
reg [ 1:0] int_bcnt, int_mod;
reg [31:0] int_data;
always @(posedge rst or posedge gmii_clk) begin
if (rst)
int_bcnt <= 2'd0;
else
if (int_gmii_ctrl_d1 | (int_bcnt!=2'd0))
int_bcnt <= int_bcnt + 2'd1;
else
int_bcnt <= 2'd0;
end
always @(posedge rst or posedge gmii_clk) begin
if (rst) begin
int_data <= 32'd0;
int_valid <= 1'b0;
int_mod <= 2'd0;
end
else begin
if (int_gmii_ctrl_d1) begin
int_data[ 7: 0] <= (int_bcnt==2'd3)? int_gmii_data_d1:int_data[ 7: 0];
int_data[15: 8] <= (int_bcnt==2'd2)? int_gmii_data_d1:int_data[15: 8];
int_data[23:16] <= (int_bcnt==2'd1)? int_gmii_data_d1:int_data[23:16];
int_data[31:24] <= (int_bcnt==2'd0)? int_gmii_data_d1:int_data[31:24];
end
 
if (int_bcnt==2'd3)
int_valid <= 1'b1;
else
int_valid <= 1'b0;
 
if (int_gmii_ctrl_d1 & !int_gmii_ctrl_d2)
int_mod <= 2'd0;
else if (!int_gmii_ctrl_d1 & int_gmii_ctrl_d2)
int_mod <= int_bcnt;
 
if (int_gmii_ctrl & !int_gmii_ctrl_d5 & int_bcnt==2'd3)
int_sop <= 1'b1;
else
int_sop <= 1'b0;
 
if (!int_gmii_ctrl & int_bcnt==2'd3)
int_eop <= 1'b1;
else
int_eop <= 1'b0;
 
end
end
 
// ptp packet parser here
// works at 1/4 gmii_clk frequency, needs multicycle timing constraint
wire ptp_found;
wire [51:0] ptp_infor;
ptp_parser parser(
.clk(gmii_clk),
.rst(rst),
.int_data(int_data),
.int_valid(int_valid),
.int_sop(int_sop),
.int_eop(int_eop),
.int_mod(int_mod),
.sop_time(gmii_time_stamp),
.ptp_found(ptp_found),
.ptp_infor(ptp_infor)
);
 
// ptp time stamp dcfifo
wire q_wr_clk = gmii_clk;
wire q_wr_en = ptp_found;
wire [55:0] q_wr_data = {4'd0, ptp_infor};
wire [3:0] q_wrusedw;
wire [3:0] q_rdusedw;
 
ptp_queue queue(
.aclr(q_rst),
 
.wrclk(q_wr_clk),
.wrreq(q_wr_en && q_wrusedw<=15),
.data(q_wr_data),
.wrusedw(q_wrusedw),
 
.rdclk(q_rd_clk),
.rdreq(q_rd_en && q_rdusedw>=1),
.q(q_rd_data),
.rdusedw(q_rdusedw)
);
 
assign q_rd_stat = {4'd0, q_rdusedw};
 
endmodule
/ha1588/trunk/rtl/reg/reg.v
0,0 → 1,6
`timescale 1ns/1ns
 
module reg (
);
 
endmodule
/ha1588/trunk/sim/rtc/rtc_timer_tb.v
15,7 → 15,7
reg time_ld;
reg [37:0] time_reg_ns_in;
reg [47:0] time_reg_sec_in;
rtc_timer
rtc
DUT (
.rst (rst ) ,
.clk (clk ) ,
/ha1588/trunk/sim/rtc/sim.do
1,5 → 1,5
vlib work
vlog -work work ../../rtl/rtc/rtc_timer.v
vlog -work work ../../rtl/rtc/rtc.v
vlog -work work rtc_timer_tb.v
vsim -novopt work.rtc_timer_tb
 
/ha1588/trunk/sim/tsu/tsu_queue_tb.v
47,7 → 47,7
forever @(posedge rtc_timer_clk) rtc_timer_in = rtc_timer_in +1;
end
 
tsu_queue DUT_RX
tsu DUT_RX
(
.rst(rst),
 
73,7 → 73,7
);
 
 
tsu_queue DUT_TX
tsu DUT_TX
(
.rst(rst),
 
/ha1588/trunk/sim/tsu/sim.do
9,7 → 9,7
vlog -work altera altera_mf.v
 
vlib work
vlog -work work ../../rtl/tsu/tsu_queue.v
vlog -work work ../../rtl/tsu/tsu.v
vlog -work work ../../rtl/tsu/ptp_parser.v
vlog -work work ../../rtl/tsu/ptp_queue.v
vlog -work work gmii_rx_bfm.v

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