OpenCores

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/hpdmc/doc/HYB25D256.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

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-\lstset{breaklines=true,basicstyle=\ttfamily} -\usepackage{graphicx} -\usepackage{moreverb} -\usepackage{url} -\usepackage{float} - -\title{High Performance Dynamic Memory Controller} -\author{S\'ebastien Bourdeauducq} -\date{\today} -\begin{document} -\maketitle{} -\section{Specifications} -This controller is targeted at high bandwidth applications such as live video processing. - -It is designed to drive 32-bit DDR SDRAM memory (which can be physically made up of two 16-bit chips). - -The memory contents are accessed through a 64-bit FML (Fast Memory Link) bus with a burst length of 4. FML is a burst-oriented bus designed to ease the design of DRAM controllers. Its signaling resembles WISHBONE, but basically removes all corner cases with burst modes to save on logic resources and aspirin. - -HPDMC provides high flexibility and savings on hardware by implementing a bypass mode which gives the CPU low-level access to the SDRAM command interface (address pins, bank address pins, and CKE, CS, WE, CAS and RAS). The SDRAM initialization sequence is assigned to the CPU, which should use this mode to implement it. Timing parameters are also configurable at runtime. These control interfaces are accessed on a 32-bit CSR bus, separate from the data bus. The CSR bus is a proprietary bus designed for Milkymist that helps reduce the FPGA resource usage and avoid failed timing paths on the system bus. - -Due to the use of \verb!IDDR!, \verb!ODDR! and \verb!IDELAY! primitives, HPDMC currently only supports the Virtex-4 FPGAs. - -\section{Architecture} - -\begin{figure}[H] -\centering -\includegraphics[height=100mm]{blockdiagram.eps} -\caption{Block diagram of the HPDMC architecture.}\label{fig:blockdiagram} -\end{figure} - -\subsection{Control interface} -The control interface provides a register bank on a low-speed dedicated CSR bus, which is used to control the operating mode of the core, set timings, and initialize the SDRAM. - -The interface can access directly the SDRAM address and command bus in the so-called \textit{bypass mode}. In this mode, the memory controller is disabled and the CPU can control each pin of the SDRAM control bus through the bypass register. - -This mode should be used at system boot-up to perform the SDRAM initialization sequence. HPDMC does not provide a hardware state machine that does such initialization. - -The mapped registers are the following (addresses are in bytes to match the addresses seen by the CPU when the CSR bus is bridged to Wishbone) : - -\subsubsection{System register, offset 0x00} -\begin{tabular}{|p{1.5cm}|l|l|p{10cm}|} -\hline -\bf Bits & \bf Access & \bf Default & \bf Description \\ -\hline -0 & RW & 1 & Bypass mode enable. Setting this bit transfers control of the SDRAM command and address bus from HPDMC to the system CPU. This bit should be set during the SDRAM initialization sequence and cleared during normal memory access. \\ -\hline -1 & RW & 1 & Reset. This bit should be cleared during normal operation and set while reconfiguring the memory subsystem. \\ -\hline -2 & RW & 0 & CKE control. This bit directly drives the CKE pin of the SDRAM and should be always set except during the first stage of the initialization sequence. The core does not support SDRAM power-down modes, so clearing this bit during normal operation results in undefined behaviour. \\ -\hline -31 -- 3 & --- & 0 & Reserved. \\ -\hline -\end{tabular} - -\subsubsection{Bypass register, offset 0x04} -The bypass register gives the system CPU low-level access to the SDRAM. It must be used at system power-up to initialize the SDRAM, as the controller does not provide this initialization. Such software initialization of the SDRAM provides greater flexibility and saves valuable hardware resources. - -Writing once to this register issues \textbf{one} transaction to the SDRAM command bus, ie. the values written to the CS, WE, RAS and CAS bits are only taken into account for one clock cycle, and then the signals go back to their default inactive state. - -The values written to this register have an effect on the SDRAM only if the controller is put in bypass mode using the system register.\\ - -\begin{tabular}{|p{1.5cm}|l|l|p{10cm}|} -\hline -\bf Bits & \bf Access & \bf Default & \bf Description \\ -\hline -0 & W & 0 & CS control. Setting this bit activates the CS line of the SDRAM during the command transaction that results from writing to the bypass register. As the SDRAM control bus is active low, setting this bit actually puts a '0' logic level to the CS line. \\ -\hline -1 & W & 0 & WE control (same as above). \\ -\hline -2 & W & 0 & CAS control (same as above). \\ -\hline -3 & W & 0 & RAS control (same as above). \\ -\hline -16 -- 4 & RW & 0 & Address. Defines the current state of the address pins. \\ -\hline -18 -- 17 & RW & 0 & Bank address. Defines the current state of the bank address pins. \\ -\hline -31 -- 19 & --- & 0 & Reserved. \\ -\hline -\end{tabular}\\ - -\textit{NB. When this register is written, the address pins change synchronously at the same time as the command pins, so there is no need to pre-position the address bits before issuing a command. Commands like loading the mode register can therefore be performed with a single write to this register.} - -\subsubsection{Timing register, offset 0x08} -This register allows the CPU to tune the behaviour of HPDMC so that it meets SDRAM timing requirements while avoiding unnecessary wait cycles. - -The controller must be held in reset using the system register when the timing register is modified.\\ - -\begin{tabular}{|p{1.5cm}|l|l|p{10cm}|} -\hline -\bf Bits & \bf Access & \bf Default & \bf Description \\ -\hline -2 -- 0 & RW & 2 & Number of clock cycles the scheduler must wait following a Precharge command. Usually referred to as $t_{RP}$ in SDRAM datasheets. \\ -\hline -5 -- 3 & RW & 2 & Number of clock cycles the scheduler must wait following an Activate command. Usually referred to as $t_{RCD}$ in SDRAM datasheets. \\ -\hline -6 & RW & 0 & CAS latency : 0 = CL2, 1 = CL3. CL2.5 is not supported. \\ -\hline -17 -- 7 & RW & 740 & Autorefresh period, in clock cycles. This is the time between \textbf{each} Auto Refresh command that is issued to the SDRAM, not the delay between two consecutive refreshes of a particular row. Usually referred to as $t_{REFI}$ in SDRAM datasheets, which is often 7.8$\mu$s (64ms is an improbable value for this field). \\ -\hline -21 -- 18 & RW & 8 & Number of clock cycles the controller must wait following an Auto Refresh command. Usually referred to as $t_{RFC}$ in SDRAM datasheets. \\ -\hline -23 -- 22 & RW & 1 & Number of clock cycles the controller must wait following the last data sent to the SDRAM during a write. Usually referred to as $t_{WR}$ in SDRAM datasheets. \\ -\hline -31 -- 24 & --- & 0 & Reserved. \\ -\hline -\end{tabular}\\ - -\textit{NB. The default values are example only, and must be adapted to your particular setup.} - -\subsubsection{Delay register, offset 0x0C} -This register controls the amount of delay that is introduced on the data lines when reading from memory. It directly controls the \verb!IDELAY! elements that are inserted between the pins and the \verb!IDDR! registers. - -Writing once to the register toggles the \verb!IDELAY! control signals \textbf{once}, that is to say, the signals will be active for one clock cycle and then go back to their default zero state. - -This register also controls the amount of phase shift that is introduced between the system clock and DQS (typically 90 degrees). HPDMC provides three signals, \verb!dqs_psen!, \verb!dqs_psincdec! and \verb!dqs_psdone! that should be connected to the DCM used to generate the DQS clock which is controlled by this register. - -The enable and incrementation bits work the same as for \verb!IDELAY!. They should only be used when the ready bit (5) is set.\\ - -\begin{tabular}{|p{1.5cm}|l|l|p{10cm}|} -\hline -\bf Bits & \bf Access & \bf Default & \bf Description \\ -\hline -0 & W & 0 & Resets delay to 0. If this bit is set, the others are ignored. \\ -\hline -1 & W & 0 & Increments or decrements delay by one tap (typically 78ps). If the bit 2 is set at the same time this bit is written, the tap delay is incremented. Otherwise, it is decremented. \\ -\hline -2 & W & 0 & Selects between incrementation and decrementation of the input tap delay. \\ -\hline -3 & W & 0 & Increments or decrements the phase shift on DQS. If the bit 4 is set at the same time this bit is written, the phase shift is incremented. Otherwise, it is decremented. The phase shift is typically between -255 and 255 and is expressed in 1/256ths of the clock period. \\ -\hline -4 & W & 0 & Selects between incrementation and decrementation of the DQS phase shift. \\ -\hline -5 & W & 0 & When this bit is set, the DCM used to generate DQS is ready for phase shift. \\ -\hline -31 -- 3 & --- & 0 & Reserved. \\ -\hline -\end{tabular}\\ - -This register can be written to at any time. - - -\subsection{SDRAM management unit} -The SDRAM management unit is a state machine which controls sequentially the SDRAM address and command bus. Unless the core is in bypass mode, the management unit has full control over the SDRAM bus. - -This unit is responsible for precharging banks, activating rows, periodically refreshing the DRAM, and sending read and write commands to the SDRAM. - -It has inputs connected to the control interface registers to retreive the $t_{RP}$, $t_{RCD}$, $t_{REFI}$ and $t_{RFC}$ timing values, as well as the row idle time. - -It handles read and write requests through a port made up of four elements : -\begin{itemize} -\item a strobe input -\item a write enable input (which tells if the command to send to the SDRAM should be a read or a write) -\item an address input -\item an acknowledgement output -\end{itemize} - -The protocol used on these signals is close to the one employed in Wishbone. The strobe signal indicates when a new command should be completed, and remains asserted (with other signals kept constant) until the acknowledgement signal is asserted. At the next clock cycle, a new command should be presented, or the strobe signal should be de-asserted. - -In HPDMC, those signals are driven by the bus interface. - -The management unit also signals the data path when it has sent a read or a write command into the SDRAM. The signal is asserted exactly at the same time as the command is asserted. - -It receives \verb!read_safe!, \verb!write_safe! and \verb!precharge_safe! signals from the data path, whose meanings are explained below. - -\subsection{Data path controller} -The data path controller is responsible for : -\begin{itemize} -\item deciding the direction of the DQ and DQS pins -\item delaying read, write and precharge commands from the management unit that would create conflicts -\end{itemize} - -The delaying of the commands is acheived through the use of three signals : -\begin{itemize} -\item \verb!read_safe! : when this signal is asserted, it is safe to send a Read command to the SDRAM. This is used to prevent conflicts on the data bus : this signal is asserted when, taking into account the CAS latency and the burst length, the resulting burst would not overlap the currently running one. -\item \verb!write_safe! : same thing, for the Write command. -\item \verb!concerned_bank[3..0]! : when the management unit issues a Read or Write command, it must inform the data path controller about the bank which the transfer takes place in, using this one-hot encoded signal. -\item \verb!precharge_safe[3..0]! : when a bit in this signal is asserted, it is safe to precharge the corresponding bank. The management unit must use this signal so as not to precharge a bank interrupting a read burst or causing a write-to-precharge violation. -\end{itemize} - -The data path controller is also connected to the control interface, to retreive $t_{WR}$ and the CAS latency. - -\subsection{Data path} -Data is captured from or sent to the SDRAM using \verb!IDDR! and \verb!ODDR! primitives, in order to limit timing nightmares with ISE. - -When writing to the DDRAM, the \verb!ODDR! primitive puts out data synchronously to the rising and falling edges of the system clock. This was chosen to ease timing between the FML (which is clocked by the system clock) and the I/O elements without introducing additional latency cycles. The data should therefore be strobed by DQS after a short time following each system clock edge. A delay corresponding to a 90 degrees phase shift gives the best margins, and can be controlled using the delay register. - -When reading from the DDRAM, the \verb!IDDR! element is also clocked by the system clock for the same reason. The data must therefore be delayed by typically one quarter of the clock cycle so that it becomes center-aligned with the system clock edges. \verb!IDELAY! primitives are used for this purpose. DQS lines are not used for reading. - -\verb!ODDR!, \verb!IDDR! and \verb!IDELAY! are only supported on Virtex-4 FPGAs, but have equivalents in other families. - -\subsection{Bus interface} -The bus interface is responsible for sending commands to the SDRAM management unit according to the request coming from the FML, and acknowledging bus cycles at the appropriate time. - -\section{Using the core} -\subsection{Connecting} -The differential clock going to the SDRAM chips should be generated using a dedicated FPGA clocking resource, such as a DCM. It is bad practice to simply add an inverter on the negative clock line, as the inverter will also add a delay. - -This DCM can also introduce a 90 degree delay on the clock and the resulting signal be used to generate DQS by connecting it to the \verb!dqs_clk! input of the HPDMC top-level. - -HPDMC uses \verb!IDELAY! elements internally, but does not include the required \verb!IDELAYCTRL! primitive. You must instantiate an \verb!IDELAYCTRL! in your design, generate the 200MHz reference clock and connect it to the \verb!IDELAYCTRL! through a \verb!BUFG!. The other signals of \verb!IDELAYCTRL! can be left unused. - -\subsection{Programming} -When the system is powered up, HPDMC comes up in bypass mode and the SDRAM initialization sequence should be performed from then, by controlling the pins at a low level using the bypass register. - -The SDRAM must be programmed to use a fixed burst length of 8, and a CAS latency of 2 (preferred) or 3. CAS latency 2.5 is not supported. - -HPDMC's timing registers may also have to be reprogrammed to match the memory chip's parameters. If a DIMM is used, it is possible to read those parameters from the serial presence detect (SPD) EEPROM and program HPDMC accordingly. - -Once the SDRAM is initialized and the timing registers are programmed, the controller can be brought up by clearing the bypass and reset bits from the system register. - -You may also need to tune the data capture delay. Reset the tap count to 0 by writing bit 0 to the delay register, then increment the delay to the desired value by repeatedly writing bits 1 and 2 simultaneously. - -The DQS phase shift may also be adjusted. The procedure is the same, except that the delay cannot be reset and that the ready bit should be set when writing the enable and incrementation bits. - -The memory is now ready to be accessed over the FML interface. - -\end{document} Index: hpdmc/doc/blockdiagram.dia =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: hpdmc/doc/blockdiagram.dia =================================================================== --- hpdmc/doc/blockdiagram.dia (revision 14) +++ hpdmc/doc/blockdiagram.dia (nonexistent)

hpdmc/doc/blockdiagram.dia Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: hpdmc/doc/Makefile =================================================================== --- hpdmc/doc/Makefile (revision 14) +++ hpdmc/doc/Makefile (nonexistent) @@ -1,23 +0,0 @@ -TEX=hpdmc.tex - -DVI=$(TEX:.tex=.dvi) -PS=$(TEX:.tex=.ps) -PDF=$(TEX:.tex=.pdf) -AUX=$(TEX:.tex=.aux) -LOG=$(TEX:.tex=.log) - -all: $(PDF) - -%.dvi: %.tex - latex $< - -%.ps: %.dvi - dvips $< - -%.pdf: %.ps - ps2pdf $< - -clean: - rm -f $(DVI) $(PS) $(PDF) $(AUX) $(LOG) - -.PHONY: clean Index: hpdmc/test/oddr.v =================================================================== --- hpdmc/test/oddr.v (revision 14) +++ hpdmc/test/oddr.v (nonexistent) @@ -1,99 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 1995/2005 Xilinx, Inc. -// All Right Reserved. -/////////////////////////////////////////////////////////////////////////////// -// Modified for HPDMC simulation, based on Xilinx 05/29/07 revision -/////////////////////////////////////////////////////////////////////////////// - -module ODDR #( - parameter DDR_CLK_EDGE = "OPPOSITE_EDGE", - parameter INIT = 1'b0, - parameter SRTYPE = "SYNC" -) ( - output Q, - input C, - input CE, - input D1, - input D2, - input R, - input S -); - -reg q_out = INIT, qd2_posedge_int; - -wire c_in; -wire ce_in; -wire d1_in; -wire d2_in; -wire gsr_in; -wire r_in; -wire s_in; - -buf buf_c(c_in, C); -buf buf_ce(ce_in, CE); -buf buf_d1(d1_in, D1); -buf buf_d2(d2_in, D2); -buf buf_q(Q, q_out); -buf buf_r(r_in, R); -buf buf_s(s_in, S); - -initial begin - if((INIT != 0) && (INIT != 1)) begin - $display("Attribute Syntax Error : The attribute INIT on ODDR instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT); - $finish; - end - - if((DDR_CLK_EDGE != "OPPOSITE_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE")) begin - $display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on ODDR instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE or SAME_EDGE.", DDR_CLK_EDGE); - $finish; - end - - if((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin - $display("Attribute Syntax Error : The attribute SRTYPE on ODDR instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE); - $finish; - end -end - -always @(r_in, s_in) begin - if(r_in == 1'b1 && SRTYPE == "ASYNC") begin - assign q_out = 1'b0; - assign qd2_posedge_int = 1'b0; - end else if(r_in == 1'b0 && s_in == 1'b1 && SRTYPE == "ASYNC") begin - assign q_out = 1'b1; - assign qd2_posedge_int = 1'b1; - end else if((r_in == 1'b1 || s_in == 1'b1) && SRTYPE == "SYNC") begin - deassign q_out; - deassign qd2_posedge_int; - end else if(r_in == 1'b0 && s_in == 1'b0) begin - deassign q_out; - deassign qd2_posedge_int; - end -end - -always @(posedge c_in) begin - if(r_in == 1'b1) begin - q_out <= 1'b0; - qd2_posedge_int <= 1'b0; - end else if(r_in == 1'b0 && s_in == 1'b1) begin - q_out <= 1'b1; - qd2_posedge_int <= 1'b1; - end else if(ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin - q_out <= d1_in; - qd2_posedge_int <= d2_in; - end -end - -always @(negedge c_in) begin - if(r_in == 1'b1) - q_out <= 1'b0; - else if(r_in == 1'b0 && s_in == 1'b1) - q_out <= 1'b1; - else if(ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin - if(DDR_CLK_EDGE == "SAME_EDGE") - q_out <= qd2_posedge_int; - else if(DDR_CLK_EDGE == "OPPOSITE_EDGE") - q_out <= d2_in; - end -end - -endmodule Index: hpdmc/test/ddr.v =================================================================== --- hpdmc/test/ddr.v (revision 14) +++ hpdmc/test/ddr.v (nonexistent) @@ -1,1452 +0,0 @@ -/**************************************************************************************** -* -* File Name: ddr.v -* Version: 6.00 -* Model: BUS Functional -* -* Dependencies: ddr_parameters.v -* -* Description: Micron SDRAM DDR (Double Data Rate) -* -* Limitation: - Doesn't check for 8K-cycle refresh. -* - Doesn't check power-down entry/exit -* - Doesn't check self-refresh entry/exit. -* -* Note: - Set simulator resolution to "ps" accuracy -* - Set DEBUG = 0 to disable $display messages -* - Model assume Clk and Clk# crossing at both edge -* -* Disclaimer This software code and all associated documentation, comments or other -* of Warranty: information (collectively "Software") is provided "AS IS" without -* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY -* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES -* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT -* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE -* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. -* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR -* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, -* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE -* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, -* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, -* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, -* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, -* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE -* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH -* DAMAGES. Because some jurisdictions prohibit the exclusion or -* limitation of liability for consequential or incidental damages, the -* above limitation may not apply to you. -* -* Copyright 2003 Micron Technology, Inc. All rights reserved. -* -* Rev Author Date Changes -* --- ------ ---------- --------------------------------------- -* 2.1 SPH 03/19/2002 - Second Release -* - Fix tWR and several incompatability -* between different simulators -* 3.0 TFK 02/18/2003 - Added tDSS and tDSH timing checks. -* - Added tDQSH and tDQSL timing checks. -* 3.1 CAH 05/28/2003 - update all models to release version 3.1 -* (no changes to this model) -* 3.2 JMK 06/16/2003 - updated all DDR400 models to support CAS Latency 3 -* 3.3 JMK 09/11/2003 - Added initialization sequence checks. -* 4.0 JMK 12/01/2003 - Grouped parameters into "ddr_parameters.v" -* - Fixed tWTR check -* 4.1 JMK 01/14/2004 - Grouped specify parameters by speed grade -* - Fixed mem_sizes parameter -* 4.2 JMK 03/19/2004 - Fixed pulse width checking on Dqs -* 4.3 JMK 04/27/2004 - Changed BL wire size in tb module -* - Changed Dq_buf size to [15:0] -* 5.0 JMK 06/16/2004 - Added read to write checking. -* - Added read with precharge truncation to write checking. -* - Added associative memory array to reduce memory consumption. -* - Added checking for required DQS edges during write. -* 5.1 JMK 08/16/2004 - Fixed checking for required DQS edges during write. -* - Fixed wdqs_valid window. -* 5.2 JMK 09/24/2004 - Read or Write without activate will be ignored. -* 5.3 JMK 10/27/2004 - Added tMRD checking during Auto Refresh and Activate. -* - Added tRFC checking during Load Mode and Precharge. -* 5.4 JMK 12/13/2004 - The model will not respond to illegal command sequences. -* 5.5 SPH 01/13/2005 - The model will issue a halt on illegal command sequences. -* JMK 02/11/2005 - Changed the display format for numbers to hex. -* 5.6 JMK 04/22/2005 - Fixed Write with auto precharge calculation. -* 5.7 JMK 08/05/2005 - Changed conditions for read with precharge truncation error. -* - Renamed parameters file with .vh extension. -* 5.8 BAS 12/26/2006 - Added parameters for T46A part - 256Mb -* - Added x32 functionality -* 6.00 JMK 05/31/2007 - Added ddr_184_dimm module model -* 6.00 BAS 05/31/2007 - Updated 128Mb, 256Mb, 512Mb, and 1024Mb parameter sheets -****************************************************************************************/ - -// DO NOT CHANGE THE TIMESCALE -// MAKE SURE YOUR SIMULATOR USE "PS" RESOLUTION -`timescale 1ns / 1ps - -module ddr (Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Ba , Addr, Dm, Dq, Dqs); - `include "ddr_parameters.vh" - - // Port Declarations - input Clk; - input Clk_n; - input Cke; - input Cs_n; - input Ras_n; - input Cas_n; - input We_n; - input [1 : 0] Ba; - input [ADDR_BITS - 1 : 0] Addr; - input [DM_BITS - 1 : 0] Dm; - inout [DQ_BITS - 1 : 0] Dq; - inout [DQS_BITS - 1 : 0] Dqs; - - // Internal Wires (fixed width) - wire [31 : 0] Dq_in; - wire [3 : 0] Dqs_in; - wire [3 : 0] Dm_in; - - assign Dq_in [DQ_BITS - 1 : 0] = Dq; - assign Dqs_in [DQS_BITS - 1 : 0] = Dqs; - assign Dm_in [DM_BITS - 1 : 0] = Dm; - - // Data pair - reg [31 : 0] dq_rise; - reg [3 : 0] dm_rise; - reg [31 : 0] dq_fall; - reg [3 : 0] dm_fall; - reg [7 : 0] dm_pair; - reg [31 : 0] Dq_buf; - - // Mode Register - reg [ADDR_BITS - 1 : 0] Mode_reg; - - // Internal System Clock - reg CkeZ, Sys_clk; - - // Internal Dqs initialize - reg Dqs_int; - - // Dqs buffer - reg [DQS_BITS - 1 : 0] Dqs_out; - - // Dq buffer - reg [DQ_BITS - 1 : 0] Dq_out; - - // Read pipeline variables - reg Read_cmnd [0 : 6]; - reg [1 : 0] Read_bank [0 : 6]; - reg [COL_BITS - 1 : 0] Read_cols [0 : 6]; - - // Write pipeline variables - reg Write_cmnd [0 : 3]; - reg [1 : 0] Write_bank [0 : 3]; - reg [COL_BITS - 1 : 0] Write_cols [0 : 3]; - - // Auto precharge variables - reg Read_precharge [0 : 3]; - reg Write_precharge [0 : 3]; - integer Count_precharge [0 : 3]; - - // Manual precharge variables - reg A10_precharge [0 : 6]; - reg [1 : 0] Bank_precharge [0 : 6]; - reg Cmnd_precharge [0 : 6]; - - // Burst terminate variables - reg Cmnd_bst [0 : 6]; - - // Memory Banks -`ifdef FULL_MEM - reg [DQ_BITS - 1 : 0] mem_array [0 : (1<= 2) begin - if (DEBUG) $display ("%m: at time %t MEMORY: Power Up and Initialization Sequence is complete", $time); - power_up_done = 1; - end else begin - aref_count = 0; - @ (aref_count >= 2) begin - if (DEBUG) $display ("%m: at time %t MEMORY: Power Up and Initialization Sequence is complete", $time); - power_up_done = 1; - end - end - end - end - end - end - end - - // Write Memory - task write_mem; - input [full_mem_bits - 1 : 0] addr; - input [DQ_BITS - 1 : 0] data; - reg [part_mem_bits : 0] i; - begin -`ifdef FULL_MEM - mem_array[addr] = data; -`else - begin : loop - for (i = 0; i < mem_used; i = i + 1) begin - if (addr_array[i] === addr) begin - disable loop; - end - end - end - if (i === mem_used) begin - if (i === (1<= burst_length) begin - Data_in_enable = 1'b0; - Data_out_enable = 1'b0; - read_precharge_truncation = 4'h0; - end - - end - endtask - - // Manual Precharge Pipeline - task Manual_Precharge_Pipeline; - begin - // A10 Precharge Pipeline - A10_precharge[0] = A10_precharge[1]; - A10_precharge[1] = A10_precharge[2]; - A10_precharge[2] = A10_precharge[3]; - A10_precharge[3] = A10_precharge[4]; - A10_precharge[4] = A10_precharge[5]; - A10_precharge[5] = A10_precharge[6]; - A10_precharge[6] = 1'b0; - - // Bank Precharge Pipeline - Bank_precharge[0] = Bank_precharge[1]; - Bank_precharge[1] = Bank_precharge[2]; - Bank_precharge[2] = Bank_precharge[3]; - Bank_precharge[3] = Bank_precharge[4]; - Bank_precharge[4] = Bank_precharge[5]; - Bank_precharge[5] = Bank_precharge[6]; - Bank_precharge[6] = 2'b0; - - // Command Precharge Pipeline - Cmnd_precharge[0] = Cmnd_precharge[1]; - Cmnd_precharge[1] = Cmnd_precharge[2]; - Cmnd_precharge[2] = Cmnd_precharge[3]; - Cmnd_precharge[3] = Cmnd_precharge[4]; - Cmnd_precharge[4] = Cmnd_precharge[5]; - Cmnd_precharge[5] = Cmnd_precharge[6]; - Cmnd_precharge[6] = 1'b0; - - // Terminate a Read if same bank or all banks - if (Cmnd_precharge[0] === 1'b1) begin - if (Bank_precharge[0] === Bank_addr || A10_precharge[0] === 1'b1) begin - if (Data_out_enable === 1'b1) begin - Data_out_enable = 1'b0; - read_precharge_truncation = 4'hF; - end - end - end - end - endtask - - // Burst Terminate Pipeline - task Burst_Terminate_Pipeline; - begin - // Command Precharge Pipeline - Cmnd_bst[0] = Cmnd_bst[1]; - Cmnd_bst[1] = Cmnd_bst[2]; - Cmnd_bst[2] = Cmnd_bst[3]; - Cmnd_bst[3] = Cmnd_bst[4]; - Cmnd_bst[4] = Cmnd_bst[5]; - Cmnd_bst[5] = Cmnd_bst[6]; - Cmnd_bst[6] = 1'b0; - - // Terminate a Read regardless of banks - if (Cmnd_bst[0] === 1'b1 && Data_out_enable === 1'b1) begin - Data_out_enable = 1'b0; - end - end - endtask - - // Dq and Dqs Drivers - task Dq_Dqs_Drivers; - begin - // read command pipeline - Read_cmnd [0] = Read_cmnd [1]; - Read_cmnd [1] = Read_cmnd [2]; - Read_cmnd [2] = Read_cmnd [3]; - Read_cmnd [3] = Read_cmnd [4]; - Read_cmnd [4] = Read_cmnd [5]; - Read_cmnd [5] = Read_cmnd [6]; - Read_cmnd [6] = 1'b0; - - // read bank pipeline - Read_bank [0] = Read_bank [1]; - Read_bank [1] = Read_bank [2]; - Read_bank [2] = Read_bank [3]; - Read_bank [3] = Read_bank [4]; - Read_bank [4] = Read_bank [5]; - Read_bank [5] = Read_bank [6]; - Read_bank [6] = 2'b0; - - // read column pipeline - Read_cols [0] = Read_cols [1]; - Read_cols [1] = Read_cols [2]; - Read_cols [2] = Read_cols [3]; - Read_cols [3] = Read_cols [4]; - Read_cols [4] = Read_cols [5]; - Read_cols [5] = Read_cols [6]; - Read_cols [6] = 0; - - // Initialize Read command - if (Read_cmnd [0] === 1'b1) begin - Data_out_enable = 1'b1; - Bank_addr = Read_bank [0]; - Cols_addr = Read_cols [0]; - Cols_brst = Cols_addr [2 : 0]; - Burst_counter = 0; - - // Row Address Mux - case (Bank_addr) - 2'd0 : Rows_addr = B0_row_addr; - 2'd1 : Rows_addr = B1_row_addr; - 2'd2 : Rows_addr = B2_row_addr; - 2'd3 : Rows_addr = B3_row_addr; - default : $display ("%m: At time %t ERROR: Invalid Bank Address", $time); - endcase - end - - // Toggle Dqs during Read command - if (Data_out_enable === 1'b1) begin - Dqs_int = 1'b0; - if (Dqs_out === {DQS_BITS{1'b0}}) begin - Dqs_out = {DQS_BITS{1'b1}}; - end else if (Dqs_out === {DQS_BITS{1'b1}}) begin - Dqs_out = {DQS_BITS{1'b0}}; - end else begin - Dqs_out = {DQS_BITS{1'b0}}; - end - end else if (Data_out_enable === 1'b0 && Dqs_int === 1'b0) begin - Dqs_out = {DQS_BITS{1'bz}}; - end - - // Initialize dqs for Read command - if (Read_cmnd [2] === 1'b1) begin - if (Data_out_enable === 1'b0) begin - Dqs_int = 1'b1; - Dqs_out = {DQS_BITS{1'b0}}; - end - end - - // Read latch - if (Data_out_enable === 1'b1) begin - // output data - read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_out); - if (DEBUG) begin - $display ("%m: At time %t READ : Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_out); - end - end else begin - Dq_out = {DQ_BITS{1'bz}}; - end - end - endtask - - // Write FIFO and DM Mask Logic - task Write_FIFO_DM_Mask_Logic; - begin - // Write command pipeline - Write_cmnd [0] = Write_cmnd [1]; - Write_cmnd [1] = Write_cmnd [2]; - Write_cmnd [2] = Write_cmnd [3]; - Write_cmnd [3] = 1'b0; - - // Write command pipeline - Write_bank [0] = Write_bank [1]; - Write_bank [1] = Write_bank [2]; - Write_bank [2] = Write_bank [3]; - Write_bank [3] = 2'b0; - - // Write column pipeline - Write_cols [0] = Write_cols [1]; - Write_cols [1] = Write_cols [2]; - Write_cols [2] = Write_cols [3]; - Write_cols [3] = {COL_BITS{1'b0}}; - - // Initialize Write command - if (Write_cmnd [0] === 1'b1) begin - Data_in_enable = 1'b1; - Bank_addr = Write_bank [0]; - Cols_addr = Write_cols [0]; - Cols_brst = Cols_addr [2 : 0]; - Burst_counter = 0; - - // Row address mux - case (Bank_addr) - 2'd0 : Rows_addr = B0_row_addr; - 2'd1 : Rows_addr = B1_row_addr; - 2'd2 : Rows_addr = B2_row_addr; - 2'd3 : Rows_addr = B3_row_addr; - default : $display ("%m: At time %t ERROR: Invalid Row Address", $time); - endcase - end - - // Write data - if (Data_in_enable === 1'b1) begin - - // Data Buffer - read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf); - - // write negedge Dqs on posedge Sys_clk - if (Sys_clk) begin - if (!dm_fall[0]) begin - Dq_buf [ 7 : 0] = dq_fall [ 7 : 0]; - end - if (!dm_fall[1]) begin - Dq_buf [15 : 8] = dq_fall [15 : 8]; - end - if (!dm_fall[2]) begin - Dq_buf [23 : 16] = dq_fall [23 : 16]; - end - if (!dm_fall[3]) begin - Dq_buf [31 : 24] = dq_fall [31 : 24]; - end - if (~&dm_fall) begin - if (DEBUG) begin - $display ("%m: At time %t WRITE: Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]); - end - end - // write posedge Dqs on negedge Sys_clk - end else begin - if (!dm_rise[0]) begin - Dq_buf [ 7 : 0] = dq_rise [ 7 : 0]; - end - if (!dm_rise[1]) begin - Dq_buf [15 : 8] = dq_rise [15 : 8]; - end - if (!dm_rise[2]) begin - Dq_buf [23 : 16] = dq_rise [23 : 16]; - end - if (!dm_rise[3]) begin - Dq_buf [31 : 24] = dq_rise [31 : 24]; - end - if (~&dm_rise) begin - if (DEBUG) begin - $display ("%m: At time %t WRITE: Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]); - end - end - end - - // Write Data - write_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf); - - // tWR start and tWTR check - if (Sys_clk && &dm_pair === 1'b0) begin - case (Bank_addr) - 2'd0 : WR_chk0 = $time; - 2'd1 : WR_chk1 = $time; - 2'd2 : WR_chk2 = $time; - 2'd3 : WR_chk3 = $time; - default : $display ("%m: At time %t ERROR: Invalid Bank Address (tWR)", $time); - endcase - - // tWTR check - if (Read_enable === 1'b1) begin - $display ("%m: At time %t ERROR: tWTR violation during Read", $time); - end - end - end - end - endtask - - // Auto Precharge Calculation - task Auto_Precharge_Calculation; - begin - // Precharge counter - if (Read_precharge [0] === 1'b1 || Write_precharge [0] === 1'b1) begin - Count_precharge [0] = Count_precharge [0] + 1; - end - if (Read_precharge [1] === 1'b1 || Write_precharge [1] === 1'b1) begin - Count_precharge [1] = Count_precharge [1] + 1; - end - if (Read_precharge [2] === 1'b1 || Write_precharge [2] === 1'b1) begin - Count_precharge [2] = Count_precharge [2] + 1; - end - if (Read_precharge [3] === 1'b1 || Write_precharge [3] === 1'b1) begin - Count_precharge [3] = Count_precharge [3] + 1; - end - - // Read with AutoPrecharge Calculation - // The device start internal precharge when: - // 1. Meet tRAS requirement - // 2. BL/2 cycles after command - if ((Read_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin - if (Count_precharge[0] >= burst_length/2) begin - Pc_b0 = 1'b1; - Act_b0 = 1'b0; - RP_chk0 = $time; - Read_precharge[0] = 1'b0; - end - end - if ((Read_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin - if (Count_precharge[1] >= burst_length/2) begin - Pc_b1 = 1'b1; - Act_b1 = 1'b0; - RP_chk1 = $time; - Read_precharge[1] = 1'b0; - end - end - if ((Read_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin - if (Count_precharge[2] >= burst_length/2) begin - Pc_b2 = 1'b1; - Act_b2 = 1'b0; - RP_chk2 = $time; - Read_precharge[2] = 1'b0; - end - end - if ((Read_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin - if (Count_precharge[3] >= burst_length/2) begin - Pc_b3 = 1'b1; - Act_b3 = 1'b0; - RP_chk3 = $time; - Read_precharge[3] = 1'b0; - end - end - - // Write with AutoPrecharge Calculation - // The device start internal precharge when: - // 1. Meet tRAS requirement - // 2. Write Latency PLUS BL/2 cycles PLUS tWR after Write command - - if ((Write_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin - if ((Count_precharge[0] >= burst_length/2+1) && ($time - WR_chk0 >= tWR)) begin - Pc_b0 = 1'b1; - Act_b0 = 1'b0; - RP_chk0 = $time; - Write_precharge[0] = 1'b0; - end - end - if ((Write_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin - if ((Count_precharge[1] >= burst_length/2+1) && ($time - WR_chk1 >= tWR)) begin - Pc_b1 = 1'b1; - Act_b1 = 1'b0; - RP_chk1 = $time; - Write_precharge[1] = 1'b0; - end - end - if ((Write_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin - if ((Count_precharge[2] >= burst_length/2+1) && ($time - WR_chk2 >= tWR)) begin - Pc_b2 = 1'b1; - Act_b2 = 1'b0; - RP_chk2 = $time; - Write_precharge[2] = 1'b0; - end - end - if ((Write_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin - if ((Count_precharge[3] >= burst_length/2+1) && ($time - WR_chk3 >= tWR)) begin - Pc_b3 = 1'b1; - Act_b3 = 1'b0; - RP_chk3 = $time; - Write_precharge[3] = 1'b0; - end - end - end - endtask - - // DLL Counter - task DLL_Counter; - begin - if (DLL_reset === 1'b1 && DLL_done === 1'b0) begin - DLL_count = DLL_count + 1; - if (DLL_count >= 200) begin - DLL_done = 1'b1; - end - end - end - endtask - - // Control Logic - task Control_Logic; - begin - // Auto Refresh - if (Aref_enable === 1'b1) begin - // Display DEBUG Message - if (DEBUG) begin - $display ("%m: At time %t AREF : Auto Refresh", $time); - end - - // Precharge to Auto Refresh - if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) || - ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin - $display ("%m: At time %t ERROR: tRP violation during Auto Refresh", $time); - end - - // LMR/EMR to Auto Refresh - if ($time - MRD_chk < tMRD) begin - $display ("%m: At time %t ERROR: tMRD violation during Auto Refresh", $time); - end - - // Auto Refresh to Auto Refresh - if ($time - RFC_chk < tRFC) begin - $display ("%m: At time %t ERROR: tRFC violation during Auto Refresh", $time); - end - - // Precharge to Auto Refresh - if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin - $display ("%m: At time %t ERROR: All banks must be Precharged before Auto Refresh", $time); - if (!no_halt) $stop (0); - end else begin - aref_count = aref_count + 1; - RFC_chk = $time; - end - end - - // Extended Mode Register - if (Ext_mode_enable === 1'b1) begin - if (DEBUG) begin - $display ("%m: At time %t EMR : Extended Mode Register", $time); - end - - // Precharge to LMR/EMR - if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) || - ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin - $display ("%m: At time %t ERROR: tRP violation during Extended Mode Register", $time); - end - - // LMR/EMR to LMR/EMR - if ($time - MRD_chk < tMRD) begin - $display ("%m: At time %t ERROR: tMRD violation during Extended Mode Register", $time); - end - - // Auto Refresh to LMR/EMR - if ($time - RFC_chk < tRFC) begin - $display ("%m: At time %t ERROR: tRFC violation during Extended Mode Register", $time); - end - - // Precharge to LMR/EMR - if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin - $display ("%m: At time %t ERROR: all banks must be Precharged before Extended Mode Register", $time); - if (!no_halt) $stop (0); - end else begin - if (Addr[0] === 1'b0) begin - DLL_enable = 1'b1; - if (DEBUG) begin - $display ("%m: At time %t EMR : Enable DLL", $time); - end - end else begin - DLL_enable = 1'b0; - if (DEBUG) begin - $display ("%m: At time %t EMR : Disable DLL", $time); - end - end - MRD_chk = $time; - end - end - - // Load Mode Register - if (Mode_reg_enable === 1'b1) begin - if (DEBUG) begin - $display ("%m: At time %t LMR : Load Mode Register", $time); - end - - // Precharge to LMR/EMR - if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) || - ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin - $display ("%m: At time %t ERROR: tRP violation during Load Mode Register", $time); - end - - // LMR/EMR to LMR/EMR - if ($time - MRD_chk < tMRD) begin - $display ("%m: At time %t ERROR: tMRD violation during Load Mode Register", $time); - end - - // Auto Refresh to LMR/EMR - if ($time - RFC_chk < tRFC) begin - $display ("%m: At time %t ERROR: tRFC violation during Load Mode Register", $time); - end - - // Precharge to LMR/EMR - if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin - $display ("%m: At time %t ERROR: all banks must be Precharged before Load Mode Register", $time); - end else begin - // Register Mode - Mode_reg = Addr; - - // DLL Reset - if (DLL_enable === 1'b1 && Addr [8] === 1'b1) begin - DLL_reset = 1'b1; - DLL_done = 1'b0; - DLL_count = 0; - end else if (DLL_enable === 1'b1 && DLL_reset === 1'b0 && Addr [8] === 1'b0) begin - $display ("%m: At time %t ERROR: DLL is ENABLE: DLL RESET is required.", $time); - end else if (DLL_enable === 1'b0 && Addr [8] === 1'b1) begin - $display ("%m: At time %t ERROR: DLL is DISABLE: DLL RESET will be ignored.", $time); - end - - // Burst Length - case (Addr [2 : 0]) - 3'b001 : $display ("%m: At time %t LMR : Burst Length = 2", $time); - 3'b010 : $display ("%m: At time %t LMR : Burst Length = 4", $time); - 3'b011 : $display ("%m: At time %t LMR : Burst Length = 8", $time); - default : $display ("%m: At time %t ERROR: Burst Length not supported", $time); - endcase - - // CAS Latency - case (Addr [6 : 4]) - 3'b010 : $display ("%m: At time %t LMR : CAS Latency = 2", $time); - 3'b110 : $display ("%m: At time %t LMR : CAS Latency = 2.5", $time); - 3'b011 : $display ("%m: At time %t LMR : CAS Latency = 3", $time); - default : $display ("%m: At time %t ERROR: CAS Latency not supported", $time); - endcase - - // Record current tMRD time - MRD_chk = $time; - end - end - - // Activate Block - if (Active_enable === 1'b1) begin - if (!(power_up_done)) begin - $display ("%m: %m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Activate command", $time); - end - // Display DEBUG Message - if (DEBUG) begin - $display ("%m: At time %t ACT : Bank = %h, Row = %h", $time, Ba, Addr); - end - - // Activate to Activate (different bank) - if ((Prev_bank != Ba) && ($time - RRD_chk < tRRD)) begin - $display ("%m: At time %t ERROR: tRRD violation during Activate bank %h", $time, Ba); - end - - // LMR/EMR to Activate - if ($time - MRD_chk < tMRD) begin - $display ("%m: At time %t ERROR: tMRD violation during Activate bank %h", $time, Ba); - end - - // AutoRefresh to Activate - if ($time - RFC_chk < tRFC) begin - $display ("%m: At time %t ERROR: tRFC violation during Activate bank %h", $time, Ba); - end - - // Precharge to Activate - if ((Ba === 2'b00 && Pc_b0 === 1'b0) || (Ba === 2'b01 && Pc_b1 === 1'b0) || - (Ba === 2'b10 && Pc_b2 === 1'b0) || (Ba === 2'b11 && Pc_b3 === 1'b0)) begin - $display ("%m: At time %t ERROR: Bank = %h is already activated - Command Ignored", $time, Ba); - if (!no_halt) $stop (0); - end else begin - // Activate Bank 0 - if (Ba === 2'b00 && Pc_b0 === 1'b1) begin - // Activate to Activate (same bank) - if ($time - RC_chk0 < tRC) begin - $display ("%m: At time %t ERROR: tRC violation during Activate bank %h", $time, Ba); - end - - // Precharge to Activate - if ($time - RP_chk0 < tRP) begin - $display ("%m: At time %t ERROR: tRP violation during Activate bank %h", $time, Ba); - end - - // Record variables for checking violation - Act_b0 = 1'b1; - Pc_b0 = 1'b0; - B0_row_addr = Addr; - RC_chk0 = $time; - RCD_chk0 = $time; - RAS_chk0 = $time; - RAP_chk0 = $time; - end - - // Activate Bank 1 - if (Ba === 2'b01 && Pc_b1 === 1'b1) begin - // Activate to Activate (same bank) - if ($time - RC_chk1 < tRC) begin - $display ("%m: At time %t ERROR: tRC violation during Activate bank %h", $time, Ba); - end - - // Precharge to Activate - if ($time - RP_chk1 < tRP) begin - $display ("%m: At time %t ERROR: tRP violation during Activate bank %h", $time, Ba); - end - - // Record variables for checking violation - Act_b1 = 1'b1; - Pc_b1 = 1'b0; - B1_row_addr = Addr; - RC_chk1 = $time; - RCD_chk1 = $time; - RAS_chk1 = $time; - RAP_chk1 = $time; - end - - // Activate Bank 2 - if (Ba === 2'b10 && Pc_b2 === 1'b1) begin - // Activate to Activate (same bank) - if ($time - RC_chk2 < tRC) begin - $display ("%m: At time %t ERROR: tRC violation during Activate bank %h", $time, Ba); - end - - // Precharge to Activate - if ($time - RP_chk2 < tRP) begin - $display ("%m: At time %t ERROR: tRP violation during Activate bank %h", $time, Ba); - end - - // Record variables for checking violation - Act_b2 = 1'b1; - Pc_b2 = 1'b0; - B2_row_addr = Addr; - RC_chk2 = $time; - RCD_chk2 = $time; - RAS_chk2 = $time; - RAP_chk2 = $time; - end - - // Activate Bank 3 - if (Ba === 2'b11 && Pc_b3 === 1'b1) begin - // Activate to Activate (same bank) - if ($time - RC_chk3 < tRC) begin - $display ("%m: At time %t ERROR: tRC violation during Activate bank %h", $time, Ba); - end - - // Precharge to Activate - if ($time - RP_chk3 < tRP) begin - $display ("%m: At time %t ERROR: tRP violation during Activate bank %h", $time, Ba); - end - - // Record variables for checking violation - Act_b3 = 1'b1; - Pc_b3 = 1'b0; - B3_row_addr = Addr; - RC_chk3 = $time; - RCD_chk3 = $time; - RAS_chk3 = $time; - RAP_chk3 = $time; - end - // Record variable for checking violation - RRD_chk = $time; - Prev_bank = Ba; - read_precharge_truncation[Ba] = 1'b0; - end - end - - // Precharge Block - consider NOP if bank already precharged or in process of precharging - if (Prech_enable === 1'b1) begin - // Display DEBUG Message - if (DEBUG) begin - $display ("%m: At time %t PRE : Addr[10] = %b, Bank = %b", $time, Addr[10], Ba); - end - - // LMR/EMR to Precharge - if ($time - MRD_chk < tMRD) begin - $display ("%m: At time %t ERROR: tMRD violation during Precharge", $time); - if (!no_halt) $stop (0); - end - - // AutoRefresh to Precharge - if ($time - RFC_chk < tRFC) begin - $display ("%m: At time %t ERROR: tRFC violation during Precharge", $time); - if (!no_halt) $stop (0); - end - - // Precharge bank 0 - if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin - Act_b0 = 1'b0; - Pc_b0 = 1'b1; - RP_chk0 = $time; - - // Activate to Precharge Bank - if ($time - RAS_chk0 < tRAS) begin - $display ("%m: At time %t ERROR: tRAS violation during Precharge", $time); - if (!no_halt) $stop (0); - end - - // tWR violation check for Write - if ($time - WR_chk0 < tWR) begin - $display ("%m: At time %t ERROR: tWR violation during Precharge", $time); - if (!no_halt) $stop (0); - end - end - - // Precharge bank 1 - if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin - Act_b1 = 1'b0; - Pc_b1 = 1'b1; - RP_chk1 = $time; - - // Activate to Precharge Bank 1 - if ($time - RAS_chk1 < tRAS) begin - $display ("%m: At time %t ERROR: tRAS violation during Precharge", $time); - if (!no_halt) $stop (0); - end - - // tWR violation check for Write - if ($time - WR_chk1 < tWR) begin - $display ("%m: At time %t ERROR: tWR violation during Precharge", $time); - if (!no_halt) $stop (0); - end - end - - // Precharge bank 2 - if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin - Act_b2 = 1'b0; - Pc_b2 = 1'b1; - RP_chk2 = $time; - - // Activate to Precharge Bank 2 - if ($time - RAS_chk2 < tRAS) begin - $display ("%m: At time %t ERROR: tRAS violation during Precharge", $time); - if (!no_halt) $stop (0); - end - - // tWR violation check for Write - if ($time - WR_chk2 < tWR) begin - $display ("%m: At time %t ERROR: tWR violation during Precharge", $time); - if (!no_halt) $stop (0); - end - end - - // Precharge bank 3 - if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin - Act_b3 = 1'b0; - Pc_b3 = 1'b1; - RP_chk3 = $time; - - // Activate to Precharge Bank 3 - if ($time - RAS_chk3 < tRAS) begin - $display ("%m: At time %t ERROR: tRAS violation during Precharge", $time); - if (!no_halt) $stop (0); - end - - // tWR violation check for Write - if ($time - WR_chk3 < tWR) begin - $display ("%m: At time %t ERROR: tWR violation during Precharge", $time); - if (!no_halt) $stop (0); - end - end - - // Prech_count is to make sure we have met part of the initialization sequence - Prech_count = Prech_count + 1; - - // Pipeline for READ - A10_precharge [cas_latency_x2] = Addr[10]; - Bank_precharge[cas_latency_x2] = Ba; - Cmnd_precharge[cas_latency_x2] = 1'b1; - end - - // Burst terminate - if (Burst_term === 1'b1) begin - // Display DEBUG Message - if (DEBUG) begin - $display ("%m: At time %t BST : Burst Terminate",$time); - end - - if (Data_in_enable === 1'b1) begin - // Illegal to burst terminate a Write - $display ("%m: At time %t ERROR: It's illegal to burst terminate a Write", $time); - if (!no_halt) $stop (0); - end else if (Read_precharge[0] === 1'b1 || Read_precharge[1] === 1'b1 || - // Illegal to burst terminate a Read with Auto Precharge - Read_precharge[2] === 1'b1 || Read_precharge[3] === 1'b1) begin - $display ("%m: At time %t ERROR: It's illegal to burst terminate a Read with Auto Precharge", $time); - if (!no_halt) $stop (0); - end else begin - // Burst Terminate Command Pipeline for Read - Cmnd_bst[cas_latency_x2] = 1'b1; - end - - end - - // Read Command - if (Read_enable === 1'b1) begin - if (!(power_up_done)) begin - $display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Read Command", $time); - end - // Check for DLL reset before Read - if (DLL_reset === 1 && DLL_done === 0) begin - $display ("%m: at time %t ERROR: You need to wait 200 tCK after DLL Reset Enable to Read, Not %0d clocks.", $time, DLL_count); - end - // Display DEBUG Message - if (DEBUG) begin - $display ("%m: At time %t READ : Bank = %h, Col = %h", $time, Ba, {Addr [11], Addr [9 : 0]}); - end - - // Terminate a Write - if (Data_in_enable === 1'b1) begin - Data_in_enable = 1'b0; - end - - // Activate to Read without Auto Precharge - if ((Addr [10] === 1'b0 && Ba === 2'b00 && $time - RCD_chk0 < tRCD) || - (Addr [10] === 1'b0 && Ba === 2'b01 && $time - RCD_chk1 < tRCD) || - (Addr [10] === 1'b0 && Ba === 2'b10 && $time - RCD_chk2 < tRCD) || - (Addr [10] === 1'b0 && Ba === 2'b11 && $time - RCD_chk3 < tRCD)) begin - $display("%m: At time %t ERROR: tRCD violation during Read", $time); - end - - // Activate to Read with Auto Precharge - if ((Addr [10] === 1'b1 && Ba === 2'b00 && $time - RAP_chk0 < tRAP) || - (Addr [10] === 1'b1 && Ba === 2'b01 && $time - RAP_chk1 < tRAP) || - (Addr [10] === 1'b1 && Ba === 2'b10 && $time - RAP_chk2 < tRAP) || - (Addr [10] === 1'b1 && Ba === 2'b11 && $time - RAP_chk3 < tRAP)) begin - $display ("%m: At time %t ERROR: tRAP violation during Read", $time); - end - - // Interrupt a Read with Auto Precharge (same bank only) - if (Read_precharge [Ba] === 1'b1) begin - $display ("%m: At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge", $time); - if (!no_halt) $stop (0); - // Cancel Auto Precharge - if (Addr[10] === 1'b0) begin - Read_precharge [Ba]= 1'b0; - end - end - // Activate to Read - if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) || - (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin - $display("%m: At time %t ERROR: Bank is not Activated for Read", $time); - if (!no_halt) $stop (0); - end else begin - // CAS Latency pipeline - Read_cmnd[cas_latency_x2] = 1'b1; - Read_bank[cas_latency_x2] = Ba; - Read_cols[cas_latency_x2] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]}; - // Auto Precharge - if (Addr[10] === 1'b1) begin - Read_precharge [Ba]= 1'b1; - Count_precharge [Ba]= 0; - end - end - end - - // Write Command - if (Write_enable === 1'b1) begin - if (!(power_up_done)) begin - $display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Write Command", $time); - if (!no_halt) $stop (0); - end - // display DEBUG message - if (DEBUG) begin - $display ("At time %t WRITE: Bank = %h, Col = %h", $time, Ba, {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]}); - end - - // Activate to Write - if ((Ba === 2'b00 && $time - RCD_chk0 < tRCD) || - (Ba === 2'b01 && $time - RCD_chk1 < tRCD) || - (Ba === 2'b10 && $time - RCD_chk2 < tRCD) || - (Ba === 2'b11 && $time - RCD_chk3 < tRCD)) begin - $display("%m: At time %t ERROR: tRCD violation during Write to Bank %h", $time, Ba); - end - - // Read to Write - if (Read_cmnd[0] || Read_cmnd[1] || Read_cmnd[2] || Read_cmnd[3] || - Read_cmnd[4] || Read_cmnd[5] || Read_cmnd[6] || (Burst_counter < burst_length)) begin - if (Data_out_enable || read_precharge_truncation[Ba]) begin - $display("%m: At time %t ERROR: Read to Write violation", $time); - end - end - - // Interrupt a Write with Auto Precharge (same bank only) - if (Write_precharge [Ba] === 1'b1) begin - $display ("At time %t ERROR: it's illegal to interrupt a Write with Auto Precharge", $time); - if (!no_halt) $stop (0); - // Cancel Auto Precharge - if (Addr[10] === 1'b0) begin - Write_precharge [Ba]= 1'b0; - end - end - // Activate to Write - if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) || - (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin - $display("%m: At time %t ERROR: Bank is not Activated for Write", $time); - if (!no_halt) $stop (0); - end else begin - // Pipeline for Write - Write_cmnd [3] = 1'b1; - Write_bank [3] = Ba; - Write_cols [3] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]}; - // Auto Precharge - if (Addr[10] === 1'b1) begin - Write_precharge [Ba]= 1'b1; - Count_precharge [Ba]= 0; - end - end - end - end - endtask - - task check_neg_dqs; - begin - if (Write_cmnd[2] || Write_cmnd[1] || Data_in_enable) begin - for (i=0; i 32'h80000000) begin - writeburst(addr); - //writeburst(addr+32'h20); - //writeburst(addr+32'h40); - end else begin - readburst(addr); - //readburst(addr+32'h20); - //readburst(addr+32'h40); - end - end - - $display(""); - $display("======================================================="); - $display(" Tested: %.0f reads, %.0f writes ", reads, writes); - $display("======================================================="); - $display(" Average read latency: %f cycles", read_clocks/reads); - $display(" Average write latency: %f cycles", write_clocks/writes); - $display("======================================================="); - $display(" Average read bandwidth: %f MBit/s @ 100MHz", (4/(4+read_clocks/reads))*64*100); - $display(" Average write bandwidth: %f MBit/s @ 100MHz", (4/(4+write_clocks/writes))*64*100); - $display("======================================================="); - -`endif - - $finish; -end - -endmodule - Index: hpdmc/test/subtest.vh =================================================================== --- hpdmc/test/subtest.vh (revision 14) +++ hpdmc/test/subtest.vh (nonexistent) @@ -1,236 +0,0 @@ -initial begin : test - -cke <= 1'b0; -cs_n <= 1'b1; -ras_n <= 1'b1; -cas_n <= 1'b1; -we_n <= 1'b1; -ba <= {BA_BITS{1'bz}}; -a <= {ADDR_BITS{1'bz}}; -dq_en <= 1'b0; -dqs_en <= 1'b0; -cke <= 1'b1; -power_up; -$display("Powerup complete"); -precharge('h00000000, 1); -nop(trp); -load_mode('h1, 'h00002000); -nop(tmrd-1); -load_mode('h0, 'h0000013A); -nop(tmrd-1); -precharge('h00000000, 1); -nop(trp); -refresh; -nop(trfc); -refresh; -nop(trfc); -load_mode('h0, 'h0000003A); -nop(tmrd-1); -nop('h000000C8); -activate('h00000000, 'h00000000); -nop(trcd-1); -write('h00000000, 'h00000000, 1, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h30003000, 32'h20002000, 32'h10001000, 32'h0}); -nop(BL/2+twr); -activate('h00000001, 'h00000000); -nop(trcd-1); -write('h00000001, 'h00000000, 1, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h30013001, 32'h20012001, 32'h10011001, 32'h10001}); -nop(BL/2+twr); -activate('h00000002, 'h00000000); -nop(trcd-1); -write('h00000002, 'h00000000, 1, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h30023002, 32'h20022002, 32'h10021002, 32'h20002}); -nop(BL/2+twr); -activate('h00000003, 'h00000000); -nop(trcd-1); -write('h00000003, 'h00000000, 1, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h30033003, 32'h20032003, 32'h10031003, 32'h30003}); -nop(BL/2+twr); -activate('h00000000, 'h00000000); -nop(trrd-1); -activate('h00000001, 'h00000000); -nop(trrd-1); -activate('h00000002, 'h00000000); -nop(trrd-1); -activate('h00000003, 'h00000000); -read('h00000000, 'h00000000, 1); -nop(BL/2-1); -read('h00000001, 'h00000000, 1); -nop(BL/2-1); -read('h00000002, 'h00000000, 1); -nop(BL/2-1); -read('h00000003, 'h00000000, 1); -nop(BL/2+twr-2); -activate('h00000001, 'h00000000); -nop(trrd-1); -activate('h00000000, 'h00000000); -nop(trcd-1); -$display("%m At time %t: WRITE Burst", $time);write('h00000000, 'h00000004, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h30403040, 32'h20402040, 32'h10401040, 32'h400040}); -nop(BL/2+4); -$display("%m At time %t: Consecutive WRITE to WRITE", $time);write('h00000000, 'h00000008, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h30803080, 32'h20802080, 32'h10801080, 32'h800080}); -nop(BL/2-1); -write('h00000000, 'h0000000C, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h31203120, 32'h21202120, 32'h11201120, 32'h1200120}); -nop(BL/2-1); -$display("%m At time %t: Nonconsecutive WRITE to WRITE", $time);write('h00000000, 'h00000010, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h31603160, 32'h21602160, 32'h11601160, 32'h1600160}); -nop(BL/2+4); -write('h00000000, 'h00000014, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h32003200, 32'h22002200, 32'h12001200, 32'h2000200}); -nop(BL/2+twr+4); -$display("%m At time %t: Random WRITE Cycles", $time);write('h00000000, 'h00000018, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h32403240, 32'h22402240, 32'h12401240, 32'h2400240}); -nop(BL/2-1); -write('h00000000, 'h0000001C, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h32803280, 32'h22802280, 32'h12801280, 32'h2800280}); -nop(BL/2-1); -write('h00000000, 'h00000020, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h33203320, 32'h23202320, 32'h13201320, 32'h3200320}); -nop(BL/2-1); -write('h00000000, 'h00000024, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h33603360, 32'h23602360, 32'h13601360, 32'h3600360}); -nop(BL/2-1); -$display("%m At time %t: WRITE to READ - Uninterrupting", $time);write('h00000000, 'h00000028, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h34003400, 32'h24002400, 32'h14001400, 32'h4000400}); -nop(BL/2+1); -read('h00000000, 'h00000028, 0); -nop(CL+BL/2-1); -$display("%m At time %t: WRITE to READ - Interrupting", $time);write('h00000000, 'h0000002C, 0, { 4'h1, 4'h1, 4'h0, 4'h0}, { 32'h34403440, 32'h24402440, 32'h14401440, 32'h4400440}); -nop(BL/2+1); -read('h00000000, 'h0000002C, 0); -nop(CL+BL/2-1); -$display("%m At time %t: WRITE to READ - Odd Number of Data, Interrupting", $time);write('h00000000, 'h00000030, 0, { 4'h1, 4'h1, 4'h1, 4'h0}, { 32'h34803480, 32'h24802480, 32'h14801480, 32'h4800480}); -nop(BL/2+1); -read('h00000000, 'h00000030, 0); -nop(CL+BL/2-1); -$display("%m At time %t: WRITE to PRECHARGE - Uninterrupting", $time);write('h00000000, 'h00000034, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h35203520, 32'h25202520, 32'h15201520, 32'h5200520}); -nop(BL/2+twr); -precharge('h00000000, 0); -nop(trp-1); -$display("%m At time %t: WRITE with AUTO PRECHARGE", $time);activate('h00000000, 'h00000000); -nop(trcd-1); -write('h00000000, 'h00000040, 1, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h36603660, 32'h26602660, 32'h16601660, 32'h6600660}); -nop(BL/2+twr+trp); -activate('h00000000, 'h00000000); -nop(trcd-1); -$display("%m At time %t: READ Burst", $time);read('h00000000, 'h00000000, 0); -nop(BL/2-1); -$display("%m At time %t: Consecutive READ Bursts", $time);read('h00000000, 'h00000004, 0); -nop(BL/2-2); -read('h00000000, 'h00000008, 0); -nop(BL/2-1); -$display("%m At time %t: Nonconsecutive READ Bursts", $time);read('h00000000, 'h0000000C, 0); -nop(BL/2); -read('h00000000, 'h00000010, 0); -nop(BL/2); -$display("%m At time %t: Random READ Accesses", $time);read('h00000000, 'h00000014, 0); -read('h00000000, 'h00000018, 0); -read('h00000000, 'h0000001C, 0); -read('h00000000, 'h00000020, 0); -nop(BL/2); -$display("%m At time %t: Terminating a READ Burst", $time);read('h00000000, 'h00000024, 0); -burst_term; -nop(BL/2-2); -$display("%m At time %t: READ to WRITE", $time);read('h00000000, 'h00000028, 0); -burst_term; -nop(CL); -write('h00000000, 'h0000002C, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h34C034C0, 32'h24C024C0, 32'h14C014C0, 32'h4C004C0}); -nop(BL/2+1); -$display("%m At time %t: READ to PRECHARGE", $time);read('h00000000, 'h00000030, 0); -nop('h00000001); -precharge('h00000000, 0); -nop(trp-1); -$display("%m At time %t: READ with AUTO PRECHARGE", $time);activate('h00000000, 'h00000000); -nop(trcd-1); -read('h00000000, 'h00000034, 1); -nop(CL+BL/2+twr); -$display("%m At time %t: WRITE to READ - Mask byte 0 of Burst 0", $time);activate('h00000000, 'h00000000); -nop(trcd-1); -write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); -nop(BL/2); -write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h1}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); -nop(BL/2+1); -read('h00000000, 'h00000064, 0); -nop(CL+BL/2-1); -$display("%m At time %t: WRITE to READ - Mask byte 1 of Burst 0", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); -nop(BL/2); -write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h2}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); -nop(BL/2+1); -read('h00000000, 'h00000064, 0); -nop(CL+BL/2-1); -$display("%m At time %t: WRITE to READ - Mask byte 2 of Burst 0", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); -nop(BL/2); -write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h4}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); -nop(BL/2+1); -read('h00000000, 'h00000064, 0); -nop(CL+BL/2-1); -$display("%m At time %t: WRITE to READ - Mask byte 3 of Burst 0", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); -nop(BL/2); -write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h8}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); -nop(BL/2+1); -read('h00000000, 'h00000064, 0); -nop(CL+BL/2-1); -$display("%m At time %t: WRITE to READ - Mask byte 0 of Burst 1", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); -nop(BL/2); -write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h1, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); -nop(BL/2+1); -read('h00000000, 'h00000064, 0); -nop(CL+BL/2-1); -$display("%m At time %t: WRITE to READ - Mask byte 1 of Burst 1", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); -nop(BL/2); -write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h2, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); -nop(BL/2+1); -read('h00000000, 'h00000064, 0); -nop(CL+BL/2-1); -$display("%m At time %t: WRITE to READ - Mask byte 2 of Burst 1", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); -nop(BL/2); -write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h4, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); -nop(BL/2+1); -read('h00000000, 'h00000064, 0); -nop(CL+BL/2-1); -$display("%m At time %t: WRITE to READ - Mask byte 3 of Burst 1", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); -nop(BL/2); -write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h8, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); -nop(BL/2+1); -read('h00000000, 'h00000064, 0); -nop(CL+BL/2-1); -$display("%m At time %t: WRITE to READ - Mask byte 0 of Burst 2", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); -nop(BL/2); -write('h00000000, 'h00000064, 0, { 4'h0, 4'h1, 4'h0, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); -nop(BL/2+1); -read('h00000000, 'h00000064, 0); -nop(CL+BL/2-1); -$display("%m At time %t: WRITE to READ - Mask byte 1 of Burst 2", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); -nop(BL/2); -write('h00000000, 'h00000064, 0, { 4'h0, 4'h2, 4'h0, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); -nop(BL/2+1); -read('h00000000, 'h00000064, 0); -nop(CL+BL/2-1); -$display("%m At time %t: WRITE to READ - Mask byte 2 of Burst 2", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); -nop(BL/2); -write('h00000000, 'h00000064, 0, { 4'h0, 4'h4, 4'h0, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); -nop(BL/2+1); -read('h00000000, 'h00000064, 0); -nop(CL+BL/2-1); -$display("%m At time %t: WRITE to READ - Mask byte 3 of Burst 2", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); -nop(BL/2); -write('h00000000, 'h00000064, 0, { 4'h0, 4'h8, 4'h0, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); -nop(BL/2+1); -read('h00000000, 'h00000064, 0); -nop(CL+BL/2-1); -$display("%m At time %t: WRITE to READ - Mask byte 0 of Burst 3", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); -nop(BL/2); -write('h00000000, 'h00000064, 0, { 4'h1, 4'h0, 4'h0, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); -nop(BL/2+1); -read('h00000000, 'h00000064, 0); -nop(CL+BL/2-1); -$display("%m At time %t: WRITE to READ - Mask byte 1 of Burst 3", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); -nop(BL/2); -write('h00000000, 'h00000064, 0, { 4'h2, 4'h0, 4'h0, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); -nop(BL/2+1); -read('h00000000, 'h00000064, 0); -nop(CL+BL/2-1); -$display("%m At time %t: WRITE to READ - Mask byte 2 of Burst 3", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); -nop(BL/2); -write('h00000000, 'h00000064, 0, { 4'h4, 4'h0, 4'h0, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); -nop(BL/2+1); -read('h00000000, 'h00000064, 0); -nop(CL+BL/2-1); -$display("%m At time %t: WRITE to READ - Mask byte 3 of Burst 3", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); -nop(BL/2); -write('h00000000, 'h00000064, 0, { 4'h8, 4'h0, 4'h0, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); -nop(BL/2+1); -read('h00000000, 'h00000064, 1); -nop(CL+BL/2-1); -test_done = 1; -end - Index: hpdmc/test/iddr.v =================================================================== --- hpdmc/test/iddr.v (revision 14) +++ hpdmc/test/iddr.v (nonexistent) @@ -1,135 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 1995/2005 Xilinx, Inc. -// All Right Reserved. -/////////////////////////////////////////////////////////////////////////////// -// Modified for HPDMC simulation, based on Xilinx 05/29/07 revision -/////////////////////////////////////////////////////////////////////////////// - - -module IDDR #( - parameter DDR_CLK_EDGE = "OPPOSITE_EDGE", - parameter INIT_Q1 = 1'b0, - parameter INIT_Q2 = 1'b0, - parameter SRTYPE = "SYNC" -) ( - output Q1, - output Q2, - input C, - input CE, - input D, - input R, - input S -); - -reg q1_out = INIT_Q1, q2_out = INIT_Q2; -reg q1_out_int, q2_out_int; -reg q1_out_pipelined, q2_out_same_edge_int; - -wire c_in; -wire ce_in; -wire d_in; -wire gsr_in; -wire r_in; -wire s_in; - -buf buf_c(c_in, C); -buf buf_ce(ce_in, CE); -buf buf_d(d_in, D); -buf buf_q1(Q1, q1_out); -buf buf_q2(Q2, q2_out); -buf buf_r(r_in, R); -buf buf_s(s_in, S); - -initial begin - if((INIT_Q1 != 0) && (INIT_Q1 != 1)) begin - $display("Attribute Syntax Error : The attribute INIT_Q1 on IDDR instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q1); - $finish; - end - - if((INIT_Q2 != 0) && (INIT_Q2 != 1)) begin - $display("Attribute Syntax Error : The attribute INIT_Q1 on IDDR instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q2); - $finish; - end - - if((DDR_CLK_EDGE != "OPPOSITE_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE_PIPELINED")) begin - $display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on IDDR instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.", DDR_CLK_EDGE); - $finish; - end - - if((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin - $display("Attribute Syntax Error : The attribute SRTYPE on IDDR instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE); - $finish; - end -end - -always @(r_in, s_in) begin - if(r_in == 1'b1 && SRTYPE == "ASYNC") begin - assign q1_out_int = 1'b0; - assign q1_out_pipelined = 1'b0; - assign q2_out_same_edge_int = 1'b0; - assign q2_out_int = 1'b0; - end else if(r_in == 1'b0 && s_in == 1'b1 && SRTYPE == "ASYNC") begin - assign q1_out_int = 1'b1; - assign q1_out_pipelined = 1'b1; - assign q2_out_same_edge_int = 1'b1; - assign q2_out_int = 1'b1; - end else if((r_in == 1'b1 || s_in == 1'b1) && SRTYPE == "SYNC") begin - deassign q1_out_int; - deassign q1_out_pipelined; - deassign q2_out_same_edge_int; - deassign q2_out_int; - end else if(r_in == 1'b0 && s_in == 1'b0) begin - deassign q1_out_int; - deassign q1_out_pipelined; - deassign q2_out_same_edge_int; - deassign q2_out_int; - end -end - -always @(posedge c_in) begin - if(r_in == 1'b1) begin - q1_out_int <= 1'b0; - q1_out_pipelined <= 1'b0; - q2_out_same_edge_int <= 1'b0; - end else if(r_in == 1'b0 && s_in == 1'b1) begin - q1_out_int <= 1'b1; - q1_out_pipelined <= 1'b1; - q2_out_same_edge_int <= 1'b1; - end else if(ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin - q1_out_int <= d_in; - q1_out_pipelined <= q1_out_int; - q2_out_same_edge_int <= q2_out_int; - end -end - -always @(negedge c_in) begin - if(r_in == 1'b1) - q2_out_int <= 1'b0; - else if(r_in == 1'b0 && s_in == 1'b1) - q2_out_int <= 1'b1; - else if(ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) - q2_out_int <= d_in; -end - -always @(c_in, q1_out_int, q2_out_int, q2_out_same_edge_int, q1_out_pipelined) begin - case(DDR_CLK_EDGE) - "OPPOSITE_EDGE" : begin - q1_out <= q1_out_int; - q2_out <= q2_out_int; - end - "SAME_EDGE" : begin - q1_out <= q1_out_int; - q2_out <= q2_out_same_edge_int; - end - "SAME_EDGE_PIPELINED" : begin - q1_out <= q1_out_pipelined; - q2_out <= q2_out_same_edge_int; - end - default: begin - $display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on IDDR instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.", DDR_CLK_EDGE); - $finish; - end - endcase -end - -endmodule Index: hpdmc/test/ddr_parameters.vh =================================================================== --- hpdmc/test/ddr_parameters.vh (revision 14) +++ hpdmc/test/ddr_parameters.vh (nonexistent) @@ -1,143 +0,0 @@ -/**************************************************************************************** -* -* Disclaimer This software code and all associated documentation, comments or other -* of Warranty: information (collectively "Software") is provided "AS IS" without -* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY -* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES -* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT -* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE -* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. -* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR -* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, -* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE -* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, -* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, -* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, -* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, -* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE -* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH -* DAMAGES. Because some jurisdictions prohibit the exclusion or -* limitation of liability for consequential or incidental damages, the -* above limitation may not apply to you. -* -* Copyright 2003 Micron Technology, Inc. All rights reserved. -* -****************************************************************************************/ - -`define sg75E -`define x16 - - // Timing parameters based on Speed Grade 04/07 - // SYMBOL UNITS DESCRIPTION - // ------ ----- ----------- -`ifdef sg5B // Timing Parameters for -5B (CL = 3) - parameter tCK = 5.0; // tCK ns Nominal Clock Cycle Time - parameter tDQSQ = 0.4; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter tMRD = 10.0; // tMRD ns Load Mode Register command cycle time - parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command - parameter tRAS = 40.0; // tRAS ns Active to Precharge command time - parameter tRC = 55.0; // tRC ns Active to Active/Auto Refresh command time - parameter tRFC = 70.0; // tRFC ns Refresh to Refresh Command interval time - parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time - parameter tRP = 15.0; // tRP ns Precharge command period - parameter tRRD = 10.0; // tRRD ns Active bank a to Active bank b command time - parameter tWR = 15.0; // tWR ns Write recovery time -`endif -`ifdef sg6T // Timing Parameters for -6T (CL = 2.5) - parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time - parameter tDQSQ = 0.45; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter tMRD = 12.0; // tMRD ns Load Mode Register command cycle time - parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command - parameter tRAS = 42.0; // tRAS ns Active to Precharge command time - parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time - parameter tRFC = 72.0; // tRFC ns Refresh to Refresh Command interval time - parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time - parameter tRP = 15.0; // tRP ns Precharge command period - parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time - parameter tWR = 15.0; // tWR ns Write recovery time -`endif -`ifdef sg6 // Timing Parameters for -6 (CL = 2.5) - parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time - parameter tDQSQ = 0.4; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter tMRD = 12.0; // tMRD ns Load Mode Register command cycle time - parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command - parameter tRAS = 42.0; // tRAS ns Active to Precharge command time - parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time - parameter tRFC = 72.0; // tRFC ns Refresh to Refresh Command interval time - parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time - parameter tRP = 15.0; // tRP ns Precharge command period - parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time - parameter tWR = 15.0; // tWR ns Write recovery time -`endif -`ifdef sg75E // Timing Parameters for -75E (CL = 2) - parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time - parameter tDQSQ = 0.5; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter tMRD = 15.0; // tMRD ns Load Mode Register command cycle time - parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command - parameter tRAS = 40.0; // tRAS ns Active to Precharge command time - parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time - parameter tRFC = 75.0; // tRFC ns Refresh to Refresh Command interval time - parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time - parameter tRP = 15.0; // tRP ns Precharge command period - parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time - parameter tWR = 15.0; // tWR ns Write recovery time -`endif -`ifdef sg75Z // Timing Parameters for -75Z (CL = 2) - parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time - parameter tDQSQ = 0.5; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter tMRD = 15.0; // tMRD ns Load Mode Register command cycle time - parameter tRAP = 20.0; // tRAP ns ACTIVE to READ with Auto precharge command - parameter tRAS = 40.0; // tRAS ns Active to Precharge command time - parameter tRC = 65.0; // tRC ns Active to Active/Auto Refresh command time - parameter tRFC = 75.0; // tRFC ns Refresh to Refresh Command interval time - parameter tRCD = 20.0; // tRCD ns Active to Read/Write command time - parameter tRP = 20.0; // tRP ns Precharge command period - parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time - parameter tWR = 15.0; // tWR ns Write recovery time -`endif -`ifdef sg75 // Timing Parameters for -75 (CL = 2.5) - parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time - parameter tDQSQ = 0.5; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter tMRD = 15.0; // tMRD ns Load Mode Register command cycle time - parameter tRAP = 20.0; // tRAP ns ACTIVE to READ with Auto precharge command - parameter tRAS = 40.0; // tRAS ns Active to Precharge command time - parameter tRC = 65.0; // tRC ns Active to Active/Auto Refresh command time - parameter tRFC = 75.0; // tRFC ns Refresh to Refresh Command interval time - parameter tRCD = 20.0; // tRCD ns Active to Read/Write command time - parameter tRP = 20.0; // tRP ns Precharge command period - parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time - parameter tWR = 15.0; // tWR ns Write recovery time -`endif - - // Size Parameters based on Part Width - -`ifdef x4 - parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used - parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used - parameter DQS_BITS = 1; // Set this parameter to control how many DQS bits are used - parameter DM_BITS = 1; // Set this parameter to control how many DM bits are used - parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used -`endif -`ifdef x8 - parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used - parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used - parameter DQS_BITS = 1; // Set this parameter to control how many DQS bits are used - parameter DM_BITS = 1; // Set this parameter to control how many DM bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used -`endif -`ifdef x16 - parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used - parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used - parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used - parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used - parameter COL_BITS = 9; // Set this parameter to control how many Column bits are used -`endif - - parameter BA_BITS = 2; // Set this parmaeter to control how many Bank Address bits are used - parameter full_mem_bits = BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used - parameter part_mem_bits = 10; // Set this parameter to control how many unique addresses are used - - parameter no_halt = 0; // If set to 1, the model won't halt on command sequence/major errors - parameter DEBUG = 1; // Turn on DEBUG message -`define FULL_MEM Index: hpdmc/test/tb_model.v =================================================================== --- hpdmc/test/tb_model.v (revision 14) +++ hpdmc/test/tb_model.v (nonexistent) @@ -1,556 +0,0 @@ -/**************************************************************************************** -* -* File Name: tb.v -* Version: 5.7 -* Model: BUS Functional -* -* Dependencies: ddr.v, ddr_parameters.v -* -* Description: Micron SDRAM DDR (Double Data Rate) test bench -* -* Note: - Set simulator resolution to "ps" accuracy -* - Set Debug = 0 to disable $display messages -* -* Disclaimer This software code and all associated documentation, comments or other -* of Warranty: information (collectively "Software") is provided "AS IS" without -* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY -* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES -* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT -* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE -* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. -* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR -* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, -* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE -* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, -* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, -* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, -* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, -* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE -* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH -* DAMAGES. Because some jurisdictions prohibit the exclusion or -* limitation of liability for consequential or incidental damages, the -* above limitation may not apply to you. -* -* Copyright 2003 Micron Technology, Inc. All rights reserved. -* -* Rev Author Date Changes -* -------------------------------------------------------------------------------- -* 2.1 SPH 03/19/2002 - Second Release -* - Fix tWR and several incompatability -* between different simulators -* 3.0 TFK 02/18/2003 - Added tDSS and tDSH timing checks. -* - Added tDQSH and tDQSL timing checks. -* 3.1 CAH 05/28/2003 - update all models to release version 3.1 -* (no changes to this model) -* 3.2 JMK 06/16/2003 - updated all DDR400 models to support CAS Latency 3 -* 3.3 JMK 09/11/2003 - Added initialization sequence checks. -* 4.0 JMK 12/01/2003 - Grouped parameters into "ddr_parameters.v" -* - Fixed tWTR check -* 4.1 JMK 01/14/2001 - Grouped specify parameters by speed grade -* - Fixed mem_sizes parameter -* 4.2 JMK 03/19/2004 - Fixed pulse width checking on Dqs -* 4.3 JMK 04/27/2004 - Changed BL wire size in tb module -* - Changed Dq_buf size to [15:0] -* 5.0 JMK 06/16/2004 - Added read to write checking. -* - Added read with precharge truncation to write checking. -* - Added associative memory array to reduce memory consumption. -* - Added checking for required DQS edges during write. -* 5.1 JMK 08/16/2004 - Fixed checking for required DQS edges during write. -* - Fixed wdqs_valid window. -* 5.2 JMK 09/24/2004 - Read or Write without activate will be ignored. -* 5.3 JMK 10/27/2004 - Added tMRD checking during Auto Refresh and Activate. -* - Added tRFC checking during Load Mode and Precharge. -* 5.4 JMK 12/13/2004 - The model will not respond to illegal command sequences. -* 5.5 SPH 01/13/2005 - The model will issue a halt on illegal command sequences. -* JMK 02/11/2005 - Changed the display format for numbers to hex. -* 5.6 JMK 04/22/2005 - Fixed Write with auto precharge calculation. -* 5.7 JMK 08/05/2005 - Changed conditions for read with precharge truncation error. -* - Renamed parameters file with .vh extension. -* 5.8 BAS 12/26/2006 - Added parameters for T46A part - 256Mb -* - Added x32 functionality -* 6.0 BAS 05/31/2007 - Added read_verify command -****************************************************************************************/ - -`timescale 1ns / 1ps - -module tb; - -`include "ddr_parameters.vh" - - reg clk ; - reg clk_n ; - reg cke ; - reg cs_n ; - reg ras_n ; - reg cas_n ; - reg we_n ; - reg [BA_BITS - 1 : 0] ba ; - reg [ADDR_BITS - 1 : 0] a ; - reg dq_en ; - reg [DM_BITS - 1 : 0] dm_out ; - reg [DQ_BITS - 1 : 0] dq_out ; - reg [DM_BITS-1 : 0] dm_fifo [0 : 13]; - reg [DQ_BITS-1 : 0] dq_fifo [0 : 13]; - reg [DQ_BITS-1 : 0] dq_in_pos ; - reg [DQ_BITS-1 : 0] dq_in_neg ; - reg dqs_en ; - reg [DQS_BITS - 1 : 0] dqs_out ; - - reg [12 : 0] mode_reg ; //Mode Register - reg [12 : 0] ext_mode_reg; //Extended Mode Register - - wire BO = mode_reg[3]; //Burst Order - wire [7 : 0] BL = (1< $rtoi(number)) - ciel = $rtoi(number) + 1; - else - ciel = number; - endfunction - - task power_up; - begin - cke <= 1'b0; - repeat(10) @(negedge clk); - $display ("%m at time %t TB: A 200 us delay is required before CKE can be brought high.", $time); - @ (negedge clk) cke = 1'b1; - nop (400/tck+1); - end - endtask - - task load_mode; - input [BA_BITS - 1 : 0] bank; - input [ADDR_BITS - 1 : 0] addr; - begin - case (bank) - 0: mode_reg = addr; - 1: ext_mode_reg = addr; - endcase - cke = 1'b1; - cs_n = 1'b0; - ras_n = 1'b0; - cas_n = 1'b0; - we_n = 1'b0; - ba = bank; - a = addr; - @(negedge clk); - end - endtask - - task refresh; - begin - cke = 1'b1; - cs_n = 1'b0; - ras_n = 1'b0; - cas_n = 1'b0; - we_n = 1'b1; - @(negedge clk); - end - endtask - - task burst_term; - integer i; - begin - cke = 1'b1; - cs_n = 1'b0; - ras_n = 1'b1; - cas_n = 1'b1; - we_n = 1'b0; - @(negedge clk); - for (i=0; i>10)<<11; //ADDR[ N:11] = COL[ N:10] - a = atemp[0] | atemp[1] | (ap<<10); - - for (i=0; i<=BL; i=i+1) begin - dqs_en <= #(WL*tck + i*tck/2) 1'b1; - if (i%2 === 0) begin - dqs_out <= #(WL*tck + i*tck/2) {DQS_BITS{1'b0}}; - end else begin - dqs_out <= #(WL*tck + i*tck/2) {DQS_BITS{1'b1}}; - end - dq_en <= #(WL*tck + i*tck/2 + tck/4) 1'b1; - for (j=0; j>((i*DM_BITS + j)*DQ_BITS/DM_BITS); - dm_out[j] <= #(WL*tck + i*tck/2 + tck/4) &dm_temp; - end - dq_out <= #(WL*tck + i*tck/2 + tck/4) dq>>i*DQ_BITS; - case (i) - 15: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[16*DM_BITS-1 : 15*DM_BITS]; - 14: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[15*DM_BITS-1 : 14*DM_BITS]; - 13: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[14*DM_BITS-1 : 13*DM_BITS]; - 12: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[13*DM_BITS-1 : 12*DM_BITS]; - 11: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[12*DM_BITS-1 : 11*DM_BITS]; - 10: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[11*DM_BITS-1 : 10*DM_BITS]; - 9: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[10*DM_BITS-1 : 9*DM_BITS]; - 8: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 9*DM_BITS-1 : 8*DM_BITS]; - 7: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 8*DM_BITS-1 : 7*DM_BITS]; - 6: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 7*DM_BITS-1 : 6*DM_BITS]; - 5: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 6*DM_BITS-1 : 5*DM_BITS]; - 4: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 5*DM_BITS-1 : 4*DM_BITS]; - 3: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 4*DM_BITS-1 : 3*DM_BITS]; - 2: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 3*DM_BITS-1 : 2*DM_BITS]; - 1: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 2*DM_BITS-1 : 1*DM_BITS]; - 0: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 1*DM_BITS-1 : 0*DM_BITS]; - endcase - case (i) - 15: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[16*DQ_BITS-1 : 15*DQ_BITS]; - 14: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[15*DQ_BITS-1 : 14*DQ_BITS]; - 13: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[14*DQ_BITS-1 : 13*DQ_BITS]; - 12: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[13*DQ_BITS-1 : 12*DQ_BITS]; - 11: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[12*DQ_BITS-1 : 11*DQ_BITS]; - 10: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[11*DQ_BITS-1 : 10*DQ_BITS]; - 9: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[10*DQ_BITS-1 : 9*DQ_BITS]; - 8: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 9*DQ_BITS-1 : 8*DQ_BITS]; - 7: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 8*DQ_BITS-1 : 7*DQ_BITS]; - 6: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 7*DQ_BITS-1 : 6*DQ_BITS]; - 5: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 6*DQ_BITS-1 : 5*DQ_BITS]; - 4: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 5*DQ_BITS-1 : 4*DQ_BITS]; - 3: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 4*DQ_BITS-1 : 3*DQ_BITS]; - 2: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 3*DQ_BITS-1 : 2*DQ_BITS]; - 1: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 2*DQ_BITS-1 : 1*DQ_BITS]; - 0: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 1*DQ_BITS-1 : 0*DQ_BITS]; - endcase - dq_en <= #(WL*tck + i*tck/2 + tck/4) 1'b1; - end - dqs_en <= #(WL*tck + BL*tck/2 + tck/2) 1'b0; - dq_en <= #(WL*tck + BL*tck/2 + tck/4) 1'b0; - @(negedge clk); - end - endtask - - task read; - input [BA_BITS - 1 : 0]bank; - input [COL_BITS - 1 : 0] col; - input ap; //Auto Precharge - reg [ADDR_BITS - 1 : 0] atemp [1:0]; - begin - cke = 1'b1; - cs_n = 1'b0; - ras_n = 1'b1; - cas_n = 1'b0; - we_n = 1'b1; - ba = bank; - atemp[0] = col & 10'h3ff; //ADDR[ 9: 0] = COL[ 9: 0] - atemp[1] = (col>>10)<<11; //ADDR[ N:11] = COL[ N:10] - a = atemp[0] | atemp[1] | (ap<<10); - @(negedge clk); - end - endtask - - // read with data verification - task read_verify; - input [BA_BITS - 1 : 0] bank; - input [COL_BITS - 1 : 0] col; - input ap; //Auto Precharge - input [16*DM_BITS - 1 : 0] dm; //Expected Data Mask - input [16*DQ_BITS - 1 : 0] dq; //Expected Data - integer i; - reg [2:0] brst_col; - begin - read (bank, col, ap); - for (i=0; i> (i*DM_BITS); - dq_fifo[2*RL + i] = dq >> (i*DQ_BITS); - end - end - endtask - - task nop; - input count; - integer count; - begin - cke = 1'b1; - cs_n = 1'b0; - ras_n = 1'b1; - cas_n = 1'b1; - we_n = 1'b1; - repeat(count) @(negedge clk); - end - endtask - - task deselect; - input count; - integer count; - begin - cke = 1'b1; - cs_n = 1'b1; - ras_n = 1'b1; - cas_n = 1'b1; - we_n = 1'b1; - repeat(count) @(negedge clk); - end - endtask - - task power_down; - input count; - integer count; - begin - cke = 1'b0; - cs_n = 1'b1; - ras_n = 1'b1; - cas_n = 1'b1; - we_n = 1'b1; - repeat(count) @(negedge clk); - end - endtask - - function [16*DQ_BITS - 1 : 0] sort_data; - input [16*DQ_BITS - 1 : 0] dq; - input [2:0] col; - integer i; - reg [2:0] brst_col; - reg [DQ_BITS - 1 :0] burst; - begin - sort_data = 0; - for (i=0; i> (brst_col*DQ_BITS); - sort_data = sort_data | burst<<(i*DQ_BITS); - end - end - endfunction - - // receiver(s) for data_verify process - always @(dqs_in[0]) begin #(tDQSQ); dqs_receiver(0); end - always @(dqs_in[1]) begin #(tDQSQ); dqs_receiver(1); end - always @(dqs_in[2]) begin #(tDQSQ); dqs_receiver(2); end - always @(dqs_in[3]) begin #(tDQSQ); dqs_receiver(3); end - always @(dqs_in[4]) begin #(tDQSQ); dqs_receiver(4); end - always @(dqs_in[5]) begin #(tDQSQ); dqs_receiver(5); end - always @(dqs_in[6]) begin #(tDQSQ); dqs_receiver(6); end - always @(dqs_in[7]) begin #(tDQSQ); dqs_receiver(7); end - - task dqs_receiver; - input i; - integer i; - begin - if (dqs_in[i]) begin - case (i) - 0: dq_in_pos[ 7: 0] <= dq_in[ 7: 0]; - 1: dq_in_pos[15: 8] <= dq_in[15: 8]; -/* 2: dq_in_pos[23:16] <= dq_in[23:16]; - 3: dq_in_pos[31:24] <= dq_in[31:24]; - 4: dq_in_pos[39:32] <= dq_in[39:32]; - 5: dq_in_pos[47:40] <= dq_in[47:40]; - 6: dq_in_pos[55:48] <= dq_in[55:48]; - 7: dq_in_pos[63:56] <= dq_in[63:56];*/ - endcase - end else if (!dqs_in[i]) begin - case (i) - 0: dq_in_neg[ 7: 0] <= dq_in[ 7: 0]; - 1: dq_in_neg[15: 8] <= dq_in[15: 8]; -/* 2: dq_in_neg[23:16] <= dq_in[23:16]; - 3: dq_in_neg[31:24] <= dq_in[31:24]; - 4: dq_in_pos[39:32] <= dq_in[39:32]; - 5: dq_in_pos[47:40] <= dq_in[47:40]; - 6: dq_in_pos[55:48] <= dq_in[55:48]; - 7: dq_in_pos[63:56] <= dq_in[63:56];*/ - endcase - end - end - endtask - - - // perform data verification as a result of read_verify task call - always @(clk) begin : data_verify - integer i; - reg [DM_BITS-1 : 0] data_mask; - reg [8*DM_BITS-1 : 0] bit_mask; - - for (i=0; i<=14; i=i+1) begin - dm_fifo[i] = dm_fifo[i+1]; - dq_fifo[i] = dq_fifo[i+1]; - end - dm_fifo[13] = 'bz; - dq_fifo[13] = 'bz; -// dm_fifo[30] = 0; -// dq_fifo[30] = 0; - data_mask = dm_fifo[0]; - - data_mask = dm_fifo[0]; - for (i=0; i

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