OpenCores
URL https://opencores.org/ocsvn/mdct/mdct/trunk

Subversion Repositories mdct

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 14 to Rev 15
    ↔ Reverse comparison
  •

Rev 14 → Rev 15

/trunk/source/DCT1D.vhd
55,9 → 55,7
romodatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
reqwrfail : in STD_LOGIC;
 
ready : out STD_LOGIC; -- read from FIFO
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
81,8 → 79,7
ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
ramwe : out STD_LOGIC;
requestwr : out STD_LOGIC;
releasewr : out STD_LOGIC
wmemsel : out STD_LOGIC
);
end DCT1D;
 
90,44 → 87,23
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture RTL of DCT1D is
 
type STATE_T is
(
MEMREQ,
IDLE,
GET_ROM,
SUM,
WRITE_ODD
);
type ISTATE_T is
(
ACQUIRE_1ROW
);
type INPUT_DATA is array (N-1 downto 0) of SIGNED(IP_W downto 0);
signal ready_reg : STD_LOGIC;
signal databuf_reg : INPUT_DATA;
signal latchbuf_reg : INPUT_DATA;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal inpcnt_reg : UNSIGNED(2 downto 0);
signal state_reg : STATE_T;
signal istate_reg : ISTATE_T;
signal cnt_reg : UNSIGNED(3 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal inpcnt_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal ramdatai_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramwe_s : STD_LOGIC;
signal latch_done_reg : STD_LOGIC;
signal latch_done_prev_reg : STD_LOGIC;
signal requestwr_reg : STD_LOGIC;
signal releasewr_reg : STD_LOGIC;
signal col_tmp_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal wmemsel_reg : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal col_2_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
begin
ready_sg:
ready <= ready_reg;
ramwe_sg:
ramwe <= ramwe_s;
140,137 → 116,61
dcto_sg:
dcto <= ramdatai_s(RAMDATA_W-1) & ramdatai_s(RAMDATA_W-1) & ramdatai_s;
releasewr_sg:
releasewr <= releasewr_reg;
requestwr_sg:
requestwr <= requestwr_reg;
--------------------------------------
-- PROCESS
--------------------------------------
GET_PROC : process(rst,clk)
wmemsel_sg:
wmemsel <= wmemsel_reg;
process(clk,rst)
begin
if rst = '1' then
inpcnt_reg <= (others => '0');
ready_reg <= '0';
latchbuf_reg <= (others => (others => '0'));
latch_done_reg <= '0';
databuf_reg <= (others => (others => '0'));
--latch_done_prev_reg <= '0';
if rst = '1' then
inpcnt_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
stage2_reg <= '0';
stage2_cnt_reg <= (others => '1');
ramdatai_s <= (others => '0');
ramwe_s <= '0';
ramwaddro <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
wmemsel_reg <= '0';
col_2_reg <= (others => '0');
elsif clk = '1' and clk'event then
--latch_done_prev_reg <= latch_done_reg;
 
if latch_done_reg = '0' or
(state_reg=IDLE and reqwrfail='0' and latch_done_reg = '1') then
-- wait until DCT1D_PROC process 1D DCT computation
-- before latching new 8 input words
if (state_reg = IDLE and reqwrfail = '0' and latch_done_reg = '1') then
latch_done_reg <= '0';
stage2_reg <= '0';
ramwe_s <= '0';
--------------------------------
-- 1st stage
--------------------------------
if idv = '1' then
inpcnt_reg <= inpcnt_reg + 1;
 
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= SIGNED('0' & dcti) - LEVEL_SHIFT;
 
if inpcnt_reg = N-1 then
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
stage2_reg <= '1';
end if;
if idv = '1' then
-- read next data from input FIFO
ready_reg <= '1';
if ready_reg = '1' then
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= SIGNED('0' & dcti) - LEVEL_SHIFT;
inpcnt_reg <= inpcnt_reg + 1;
if inpcnt_reg = N-1 then
latch_done_reg <= '1';
ready_reg <= '0';
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
end if;
end if;
else
ready_reg <= '0';
end if;
end if;
end if;
end process;
--------------------------------------
-- PROCESS
--------------------------------------
DCT1D_PROC: process(rst, clk)
begin
if rst = '1' then
col_reg <= (others => '0');
row_reg <= (others => '0');
state_reg <= MEMREQ;
cnt_reg <= (others => '0');
end if;
--------------------------------
ramwaddro <= (others => '0');
ramdatai_s <= (others => '0');
ramwe_s <= '0';
releasewr_reg <= '0';
col_tmp_reg <= (others => '0');
requestwr_reg <= '0';
elsif rising_edge(clk) then
case state_reg is
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
when MEMREQ =>
ramwe_s <= '0';
-- release memory fully written
releasewr_reg <= '0';
-- request free memory for writing
requestwr_reg <= '1';
-- DBUFCTL 1T delay
if requestwr_reg = '1' then
requestwr_reg <= '0';
state_reg <= IDLE;
end if;
 
----------------------
-- wait for input data
----------------------
when IDLE =>
 
ramwe_s <= '0';
-- failure to allocate any memory buffer
if reqwrfail = '1' then
-- restart allocation procedure
state_reg <= MEMREQ;
-- wait until 8 input words are latched in latchbuf_reg
-- by GET_PROC
elsif latch_done_reg = '1' then
state_reg <= SUM;
end if;
 
----------------------
-- get MAC results from ROM even and ROM odd memories
----------------------
when GET_ROM =>
ramwe_s <='0';
state_reg <= SUM;
---------------------
-- do distributed arithmetic sum on even part,
-- write even part to RAM
---------------------
when SUM =>
if stage2_cnt_reg(0) = '0' then
ramdatai_s <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao0),DA_W) +
(RESIZE(SIGNED(romedatao1),DA_W-1) & '0') +
282,27 → 182,7
(RESIZE(SIGNED(romedatao7),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romedatao8),DA_W-8) & "00000000"),
DA_W)(DA_W-1 downto 12));
-- write even part
ramwe_s <= '1';
-- reverse col/row order for transposition purpose
ramwaddro <= STD_LOGIC_VECTOR(col_reg & row_reg);
col_reg <= col_reg + 1;
col_tmp_reg <= col_reg + 2;
state_reg <= WRITE_ODD;
---------------------
-- do distributed arithmetic sum on odd part,
-- write odd part to RAM
---------------------
when WRITE_ODD =>
-- write odd part
--ramwe_s <= '1';
else
ramdatai_s <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao0),DA_W) +
(RESIZE(SIGNED(romodatao1),DA_W-1) & '0') +
313,87 → 193,87
(RESIZE(SIGNED(romodatao6),DA_W-6) & "000000") +
(RESIZE(SIGNED(romodatao7),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romodatao8),DA_W-8) & "00000000"),
DA_W)(DA_W-1 downto 12));
-- write odd part
-- reverse col/row order for transposition purpose
ramwaddro <= STD_LOGIC_VECTOR(col_reg & row_reg);
-- move to next column
col_reg <= col_reg + 1;
col_tmp_reg <= col_reg + 1;
-- finished processing one input row
if col_reg = N - 1 then
row_reg <= row_reg + 1;
DA_W)(DA_W-1 downto 12));
end if;
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- write RAM
ramwe_s <= '1';
-- reverse col/row order for transposition purpose
ramwaddro <= STD_LOGIC_VECTOR(col_2_reg & row_reg);
-- increment column counter
col_reg <= col_reg + 1;
col_2_reg <= col_2_reg + 1;
-- finished processing one input row
if col_reg = 0 then
row_reg <= row_reg + 1;
-- switch to 2nd memory
if row_reg = N - 1 then
wmemsel_reg <= not wmemsel_reg;
col_reg <= (others => '0');
col_tmp_reg <= (others => '0');
if row_reg = N - 1 then
releasewr_reg <= '1';
state_reg <= MEMREQ;
else
state_reg <= IDLE;
end if;
else
state_reg <= SUM;
end if;
--------------------------------
-- OTHERS
--------------------------------
when others =>
state_reg <= IDLE;
end case;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
col_2_reg <= (others => '0');
end if;
----------------------------------
end if;
end process;
-- read precomputed MAC results from LUT
romeaddro0 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
romeaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(0) &
databuf_reg(1)(0) &
databuf_reg(2)(0) &
databuf_reg(3)(0);
romeaddro1 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
romeaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(1) &
databuf_reg(1)(1) &
databuf_reg(2)(1) &
databuf_reg(3)(1);
romeaddro2 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
romeaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(2) &
databuf_reg(1)(2) &
databuf_reg(2)(2) &
databuf_reg(3)(2);
romeaddro3 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
romeaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(3) &
databuf_reg(1)(3) &
databuf_reg(2)(3) &
databuf_reg(3)(3);
romeaddro4 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
romeaddro4 <= STD_LOGIC_VECTOR( col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(4) &
databuf_reg(1)(4) &
databuf_reg(2)(4) &
databuf_reg(3)(4);
romeaddro5 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
romeaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(5) &
databuf_reg(1)(5) &
databuf_reg(2)(5) &
databuf_reg(3)(5);
romeaddro6 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
romeaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(6) &
databuf_reg(1)(6) &
databuf_reg(2)(6) &
databuf_reg(3)(6);
romeaddro7 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
romeaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(7) &
databuf_reg(1)(7) &
databuf_reg(2)(7) &
databuf_reg(3)(7);
romeaddro8 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
romeaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(8) &
databuf_reg(1)(8) &
databuf_reg(2)(8) &
databuf_reg(3)(8);
databuf_reg(3)(8);
-- odd
romoaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(0) &
440,6 → 320,7
databuf_reg(5)(8) &
databuf_reg(6)(8) &
databuf_reg(7)(8);
end RTL;
--------------------------------------------------------------------------------
/trunk/source/testbench/COMPILE_TIMING.DO
40,6 → 40,7
vcom SOURCE/DCT2D.VHD
vcom SOURCE/DBUFCTL.VHD
vcom SYNTHESIS/MDCT_TEMP_2/MDCT_OUT.VHD
vcom SOURCE/TESTBENCH/random1.VHD
vcom SOURCE/TESTBENCH/CLKGEN.VHD
vcom SOURCE/TESTBENCH/MDCTTB_PKG.VHD
vcom SOURCE/TESTBENCH/INPIMAGE.VHD
/trunk/source/testbench/random1.vhd
0,0 → 1,1056
-- Random number generators (RNG)
-- Author: Gnanasekaran Swaminathan
 
-- Random number generator algorithm is due to D. E. Knuth as
-- given in W. H. Press et al., "Numerical Recipes in C: The Art
-- of Scientific Computing," New York: Cambridge Univ. Press, 1988.
-- Translated into VHDL by Gnanasekaran Swaminathan <gs4t@virginia.edu>
 
-- Other algorithms are from libg++ by Dirk Grunwald <grunwald@cs.uiuc.edu>
-- Translated into VHDL by Gnanasekaran Swaminathan <gs4t@virginia.edu>
 
-- math functions factorial, "**", exp, ln, and sqrt are from
-- math_functions package due to Tom Ashworth <ashworth@ERC.MsState.Edu>
 
-- USAGE:
-- Following 10 random variables are supported:
-- Uniform, Negative Exponential, Poisson, Normal, Log Normal,
-- Erlang, Geometric, Hyper Geometric, Binomial, Weibull.
--
-- Each random variable has its own copy of random number generator.
-- Hence, you can have as many random variables of any type as you
-- want only limited by the amount of memory your system has.
--
-- First a random variable must be initialized using the corresponding
-- Init function. Thenceforth, the new value of the random variable can
-- can be obtained by a call to GenRnd.
--
-- EXAMPLES:
-- Uniform random number in [-50, 100] with seed 7
-- process
-- variable unf: Uniform := InitUniform(7, -50.0, 100.0);
-- variable rnd: real := 0;
-- begin
-- GenRnd(unf);
-- rnd := unf.rnd; -- -50 <= rnd <= 100
-- end;
--
-- Negative exponential distribution with mean 25 and seed 13
-- variable nexp: NegExp := InitNegExp(13, 25.0);
-- GenRnd(nexp)
-- rnd := nexp.rnd; -- 0 <= rnd <= real'High
--
--
-- Please send bug reports and additions and subtractions
-- to me at gs4t@virginia.edu
--
-- Enjoy!
-- Gnanasekaran Swaminathan
 
package RNG is
subtype rn is Real range 0.0 to 1.0;
subtype PositiveReal is Real range 0.0 to Real'High;
type IntA0to98 is array (0 to 98) of Integer;
type distribution is ( UniformDist,
NegExpDist,
PoissonDist,
BinomialDist,
GeomDist,
HypGeomDist,
NormalDist,
LogNormalDist,
ErlangDist,
WeibullDist
);
type realParams is array (0 to 10) of Real;
subtype intParams is Integer;
subtype booleanParams is Boolean;
 
type RndNum is
record
rnd : rn;
init : Integer;
iy : Integer;
ir : IntA0to98;
status : Boolean;
end record;
 
type random is record
rnd: Real;
r: RndNum;
a: realParams;
b: intParams;
c: booleanParams;
dist: distribution;
end record;
 
type Uniform is
record
rnd : Real;
pHigh : Real;
pLow : Real;
delta : Real;
r : RndNum;
end record;
 
type NegExp is
record
rnd : Real;
pMean : PositiveReal;
r : RndNum;
end record;
 
type Poisson is
record
rnd : Real;
pMean : PositiveReal;
r : RndNum;
end record;
 
type Normal is
record
rnd : Real;
pMean : Real;
pStdDev : Real;
pVariance : Real;
CachedNormal : Real;
haveCachedNormal: Boolean;
r : RndNum;
end record;
 
type LogNormal is
record
rnd : Real;
pLogMean : Real;
pLogVariance : Real;
n : Normal;
end record;
 
type Erlang is
record
rnd : Real;
pMean : Real;
pVariance : Real;
a : Real;
k : Integer;
r : RndNum;
end record;
 
type Binomial is
record
rnd : Real;
pU : Real;
pN : Integer;
r : RndNum;
end record;
 
type Geom is
record
rnd : Real;
pMean : Real;
r : RndNum;
end record;
 
type HypGeom is
record
rnd : Real;
pMean : Real;
pVariance : Real;
pP : Real;
r : RndNum;
end record;
 
type Weibull is
record
rnd : Real;
pAlpha : Real;
pInvAlpha : Real;
pBeta : Real;
r : RndNum;
end record;
constant LN2: real := 0.693147181;
function factorial (n: integer) return real;
function "**"(z: Real; y: Real) return Real;
function ln (z: Real) return Real;
function ln1p(z: Real) return Real;
function exp (z: Real) return Real;
function sqrt(z: Real) return Real;
 
procedure GenRnd(r: inout RndNum; seed: in Integer := 13);
procedure GenRnd(r: inout Uniform);
procedure GenRnd(r: inout NegExp);
procedure GenRnd(r: inout Poisson);
procedure GenRnd(r: inout Normal);
procedure GenRnd(r: inout LogNormal);
procedure GenRnd(r: inout Erlang);
procedure GenRnd(r: inout Binomial);
procedure GenRnd(r: inout Geom);
procedure GenRnd(r: inout HypGeom);
procedure GenRnd(r: inout Weibull);
procedure GenRnd(r: inout random);
 
-- Initialization functions
function InitRndNum (seed: in Integer := 13) return RndNum;
function InitUniform (seed: Integer := 13;
low: Real := 0.0;
high: Real := 100.0) return Uniform;
function InitNegExp (seed: Integer := 13;
mean: PositiveReal := 50.0) return NegExp;
function InitPoisson (seed: Integer := 13;
mean: PositiveReal := 50.0) return Poisson;
function InitNormal (seed: Integer := 13;
mean: Real := 0.0;
var: Real := 100.0) return Normal;
function InitLogNormal (seed: Integer := 13;
mean: Real := 50.0;
var: Real := 100.0) return LogNormal;
function InitErlang (seed: Integer := 13;
mean: Real := 50.0;
var: Real := 100.0) return Erlang;
function InitBinomial (seed: Integer := 13;
n: Integer := 0;
u: Real := 0.0) return Binomial;
function InitGeom (seed: Integer := 13;
mean: Real := 0.0) return Geom;
function InitHypGeom (seed: Integer := 13;
mean: Real := 0.0;
var: Real := 0.0) return HypGeom;
function InitWeibull (seed: Integer := 13;
alpha: Real := 0.0;
beta: Real := 0.0) return Weibull;
function InitUniform (low: Real := 0.0;
high: Real := 100.0;
seed: Integer := 13) return random;
function InitNegExp (mean: PositiveReal := 50.0;
seed: Integer := 13) return random;
function InitPoisson (mean: PositiveReal := 50.0;
seed: Integer := 13) return random;
function InitNormal (mean: Real := 0.0;
var: Real := 100.0;
seed: Integer := 13) return random;
function InitLogNormal (mean: Real := 50.0;
var: Real := 100.0;
seed: Integer := 13) return random;
function InitErlang (mean: Real := 50.0;
var: Real := 100.0;
seed: Integer := 13) return random;
function InitBinomial (n: Integer := 0;
u: Real := 0.0;
seed: Integer := 13) return random;
function InitGeom (mean: Real := 0.0;
seed: Integer := 13) return random;
function InitHypGeom (mean: Real := 0.0;
var: Real := 0.0;
seed: Integer := 13) return random;
function InitWeibull (alpha: Real := 0.0;
beta: Real := 0.0;
seed: Integer := 13) return random;
-- conversion functions
function CvtRandom (uni: in Uniform) return random;
function CvtRandom (nex: in NegExp) return random;
function CvtRandom (poi: in Poisson) return random;
function CvtRandom (nom: in Normal) return random;
function CvtRandom (lnom: in LogNormal) return random;
function CvtRandom (erl: in Erlang) return random;
function CvtRandom (bin: in Binomial) return random;
function CvtRandom (geo: in Geom) return random;
function CvtRandom (hypg: in HypGeom) return random;
function CvtRandom (wei: in Weibull) return random;
 
function CvtUniform (r: in random) return Uniform;
function CvtNegExp (r: in random) return NegExp;
function CvtPoisson (r: in random) return Poisson;
function CvtNormal (r: in random) return Normal;
function CvtLogNormal (r: in random) return LogNormal;
function CvtErlang (r: in random) return Erlang;
function CvtBinomial (r: in random) return Binomial;
function CvtGeom (r: in random) return Geom;
function CvtHypGeom (r: in random) return HypGeom;
function CvtWeibull (r: in random) return Weibull;
end RNG;
 
package body RNG is
-------------------------------------------------------------------------------
function factorial(n : integer) return real is
variable result : Integer;
begin
result := 1;
if (n > 1) then
for i in 2 to n loop
result := result * i;
end loop;
end if;
return Real(result);
end factorial;
-------------------------------------------------------------------------------
function "**" (z: Real; y: Real) return Real is
begin
return exp(y * ln(z));
end;
-------------------------------------------------------------------------------
function ln (z : real) return real is
variable Result : real;
variable tmpx : real;
variable n : integer;
variable acc : integer;
begin
assert not (z <= 0.0)
report "ERROR : Can't take the ln of a negative number"
severity error;
tmpx := z;
n := 0;
--reduce z to a number less than one in order
--to use a more accurate model that converges
--much faster. This will render the log function
--to ln(z) = ln(tmpx) + n * ln(2) where ln(2) is
--defined as a constant.
while (tmpx >= 1.0) loop
tmpx := tmpx / 2.0;
n := n +1;
end loop;
--acc determines the number of iterations of the series
--these values are results from comparisons with the SUN
--log() C function at a accuracy of at least 0.00001.
if (tmpx < 0.5) then
acc := 100;
else
acc := 20;
end if;
tmpx := tmpx - 1.0;
result := real(n) * LN2;
n := 1;
while (n < acc) loop
result := result + (tmpx**n)/real(n) - (tmpx**(n+1))/real(n+1);
n := n +2;
end loop;
return Result;
end ln;
-------------------------------------------------------------------------------
function ln1p(z: Real) return Real is
begin
assert false
report "ln1p is not implemented"
severity error;
return ln(z);
end;
-------------------------------------------------------------------------------
function exp (z : real) return real is
variable result,tmp : real;
variable i : integer;
begin
if (z = 0.0) then
result := 1.0;
else
result := z + 1.0;
i := 2;
tmp := z*z/2.0;
result := result + tmp;
while (abs(tmp) > 0.000005) loop
i := i +1;
tmp := tmp * z / Real(i);
result := result + tmp;
end loop;
end if;
return result;
end exp;
-------------------------------------------------------------------------------
function sqrt(z: Real) return Real is
begin
assert z >= 0.0
report "sqrt (negative number) is undefined"
severity error;
return z ** 0.5;
end;
-------------------------------------------------------------------------------
procedure GenRnd(r: inout RndNum; seed: in Integer := 13) is
constant RN_M : Integer := 714025;
constant RN_IA: Integer := 1366;
constant RN_IC: Integer := 150889;
variable j : Integer := 0;
begin
if (not r.status) then
r.status := True;
r.init := seed;
r.init := abs ( (RN_IC - r.init) mod RN_M );
for i in 0 to 1 loop for j in 1 to 97 loop
r.init := (RN_IA * r.init + RN_IC) mod RN_M;
r.ir(j) := r.init;
end loop; end loop;
r.init := (RN_IA * r.init + RN_IC) mod RN_M;
r.iy := r.init;
r.rnd := REAL(r.iy) / REAL(RN_M);
return;
end if;
 
j := 1 + 97 * r.iy / RN_M;
assert (1 <= j and j <= 97)
report "this cannon happen in GenRnd(RndNum)"
severity error;
r.iy := r.ir(j);
r.init := (RN_IA * r.init + RN_IC) mod RN_M;
r.ir(j) := r.init;
r.rnd := REAL(r.iy) / REAL(RN_M);
end GenRnd; -- RndNum
-------------------------------------------------------------------------------
procedure GenRnd(r: inout Uniform) is
begin
assert r.r.status
report "Uniform variable is not initialized"
severity error;
GenRnd(r.r);
r.rnd := r.pLow + r.delta * r.r.rnd;
end GenRnd; -- Uniform
-------------------------------------------------------------------------------
procedure GenRnd(r: inout NegExp) is
begin
assert r.r.status
report "NegExp variable is not initialized"
severity error;
GenRnd(r.r);
r.rnd := - r.pMean * ln(1.0 - r.r.rnd);
-- ln1p will be better here
end GenRnd; -- NegExp
-------------------------------------------------------------------------------
procedure GenRnd(r: inout Poisson) is
variable product: Real := 1.0;
variable bound: Real := 0.0;
begin
assert r.r.status
report "Poisson variable is not initialized"
severity error;
bound := exp(-1.0 * r.pMean);
r.rnd := -1.0;
 
while (product >= bound) loop
r.rnd := r.rnd + 1.0;
GenRnd(r.r);
product := product * r.r.rnd;
end loop;
end GenRnd; -- Poisson
-------------------------------------------------------------------------------
procedure GenRnd(r: inout Normal) is
variable v1: Real := 0.0;
variable v2: Real := 0.0;
variable w : Real := 0.0;
variable x1: Real := 0.0;
variable x2: Real := 0.0;
begin
assert r.r.status
report "Normal variable is not initialized"
severity error;
if (r.haveCachedNormal) then
r.haveCachedNormal := False;
r.rnd := r.cachedNormal * r.pStdDev + r.pMean;
return;
end if;
 
while (True) loop
GenRnd(r.r); v1 := 2.0 * r.r.rnd - 1.0;
GenRnd(r.r); v2 := 2.0 * r.r.rnd - 1.0;
w := v1 * v1 + v2* v2;
 
if ( w <= 1.0 ) then
w := sqrt(-2.0 * ln (w) / w);
x1 := v1 * w;
x2 := v2 * w;
 
r.haveCachedNormal := True;
r.CachedNormal := x2;
r.rnd := x1 * r.pStdDev + r.pMean;
return;
end if;
end loop;
end GenRnd; -- Normal
 
-------------------------------------------------------------------------------
 
procedure GenRnd(r: inout LogNormal) is
begin
assert r.n.r.status
report "LogNormal variable is not initialized"
severity error;
GenRnd(r.n);
r.rnd := exp(r.n.rnd);
end GenRnd; -- LogNormal
-------------------------------------------------------------------------------
 
procedure GenRnd(r: inout Erlang) is
variable prod : Real := 1.0;
begin
assert r.r.status
report "Erlang variable is not initialized"
severity error;
 
for i in 1 to r.k loop
GenRnd(r.r);
prod := prod * r.r.rnd;
end loop;
r.rnd := - ln( prod ) / r.a;
end GenRnd; -- Erlang
-------------------------------------------------------------------------------
procedure GenRnd(r: inout Binomial) is
begin
assert r.r.status
report "Binomial variable is not initialized"
severity error;
r.rnd := 0.0;
for i in 1 to r.pN loop
GenRnd(r.r);
if (r.r.rnd < r.pU) then
r.rnd := r.rnd + 1.0;
end if;
end loop;
end GenRnd; -- Binomial
 
-------------------------------------------------------------------------------
 
procedure GenRnd(r: inout Geom) is
begin
assert r.r.status
report "Geom variable is not initialized"
severity error;
r.rnd := 1.0;
GenRnd(r.r);
while (r.r.rnd < r.pMean) loop
r.rnd := r.rnd + 1.0;
GenRnd(r.r);
end loop;
end GenRnd; -- Geom
 
-------------------------------------------------------------------------------
 
procedure GenRnd(r: inout HypGeom) is
variable z: Real := 0.0;
begin
assert r.r.status
report "HypGeom variable is not initialized"
severity error;
GenRnd(r.r);
if (r.r.rnd > r.pP) then
z := 1.0 - r.pP;
else
z := r.pP;
end if;
GenRnd(r.r);
r.rnd := -r.pMean * ln( r.r.rnd )/ (2.0*z);
end GenRnd; -- HypGeom
 
-------------------------------------------------------------------------------
 
procedure GenRnd(r: inout Weibull) is
begin
assert r.r.status
report "Weibull variable r is not initialized"
severity error;
GenRnd(r.r);
r.rnd := ( -r.pBeta * ln(1.0 - r.r.rnd) ) ** r.pInvAlpha;
end GenRnd; -- Weibull
 
-------------------------------------------------------------------------------
function InitRndNum (seed: in Integer := 13) return RndNum is
constant RN_M : Integer := 714025;
constant RN_IA: Integer := 1366;
constant RN_IC: Integer := 150889;
variable j : Integer := 0;
variable r : RndNum;
begin
r.status := True;
r.init := seed;
r.init := abs ( (RN_IC - r.init) mod RN_M );
for i in 0 to 1 loop for j in 1 to 97 loop
r.init := (RN_IA * r.init + RN_IC) mod RN_M;
r.ir(j) := r.init;
end loop; end loop;
r.init := (RN_IA * r.init + RN_IC) mod RN_M;
r.iy := r.init;
return r;
end InitRndNum;
-------------------------------------------------------------------------------
function InitUniform (seed: Integer := 13;
low: Real := 0.0;
high: Real := 100.0) return Uniform is
variable r : Uniform;
begin
r.r.status := False;
if (low < high) then
r.pLow := low;
r.pHigh := high;
else
r.pLow := high;
r.pHigh := low;
end if;
r.delta := high-low;
GenRnd(r.r, seed);
return r;
end InitUniform;
-------------------------------------------------------------------------------
function InitNegExp (seed: Integer := 13;
mean: PositiveReal := 50.0) return NegExp is
variable r : NegExp;
begin
r.r.status := False;
r.pMean := mean;
GenRnd(r.r, seed);
return r;
end InitNegExp;
-------------------------------------------------------------------------------
function InitPoisson (seed: Integer := 13;
mean: PositiveReal := 50.0) return Poisson is
variable r : Poisson;
begin
r.r.status := False;
r.pMean := mean;
GenRnd(r.r, seed);
return r;
end InitPoisson;
-------------------------------------------------------------------------------
function InitNormal (seed: Integer := 13;
mean: Real := 0.0;
var: Real := 100.0) return Normal is
variable r : Normal;
begin
r.r.status := False;
r.haveCachedNormal := False;
r.pMean := mean;
r.pVariance := var;
r.pStdDev := sqrt(r.pVariance);
GenRnd(r.r, seed);
return r;
end InitNormal;
-------------------------------------------------------------------------------
function InitLogNormal (seed: Integer := 13;
mean: Real := 50.0;
var: Real := 100.0) return LogNormal is
variable m2: Real := 0.0;
variable mn: Real := 0.0;
variable sd: Real := 0.0;
variable r : LogNormal;
begin
r.n.r.status := False;
r.pLogMean := mean;
r.pLogVariance := var;
m2 := r.pLogMean * r.pLogMean;
mn := ln( m2 / sqrt(r.pLogVariance + m2) );
sd := sqrt( ln( (r.pLogVariance + m2) / m2 ) );
r.n := InitNormal(seed, mn, sd);
return r;
end InitLogNormal;
-------------------------------------------------------------------------------
function InitErlang (seed: Integer := 13;
mean: Real := 50.0;
var: Real := 100.0) return Erlang is
variable r : Erlang;
begin
r.r.status := False;
r.pMean := mean;
r.pVariance := var;
r.k := Integer(r.pMean*r.pMean/r.pVariance+0.5);
if (r.k <= 0) then
r.k := 1;
end if;
r.a := Real(r.k) / r.pMean;
GenRnd(r.r, seed);
return r;
end InitErlang;
-------------------------------------------------------------------------------
function InitBinomial (seed: Integer := 13;
n: Integer := 0;
u: Real := 0.0) return Binomial is
variable r : Binomial;
begin
r.r.status := False;
r.pN := n;
r.pU := u;
GenRnd(r.r, seed);
return r;
end InitBinomial;
-------------------------------------------------------------------------------
function InitGeom (seed: Integer := 13;
mean: Real := 0.0) return Geom is
variable r : Geom;
begin
r.r.status := False;
r.pMean := mean;
GenRnd(r.r, seed);
return r;
end InitGeom;
-------------------------------------------------------------------------------
function InitHypGeom (seed: Integer := 13;
mean: Real := 0.0;
var: Real := 0.0) return HypGeom is
variable z: Real := 0.0;
variable r : HypGeom;
begin
r.r.status := False;
r.pMean := mean;
r.pVariance := var;
z := r.pVariance / (r.pMean * r.pMean);
z := sqrt( (z-1.0) / (z+1.0) );
r.pP := 0.5 * ( 1.0 - z );
GenRnd(r.r, seed);
return r;
end InitHypGeom;
-------------------------------------------------------------------------------
function InitWeibull (seed: Integer := 13;
alpha: Real := 0.0;
beta: Real := 0.0) return Weibull is
variable r : Weibull;
begin
r.r.status := False;
r.pAlpha := alpha;
r.pBeta := beta;
r.pInvAlpha := 1.0 / r.pAlpha;
GenRnd(r.r, seed);
return r;
end InitWeibull;
-------------------------------------------------------------------------------
function InitUniform (low: Real := 0.0;
high: Real := 100.0;
seed: Integer := 13) return random is
begin
return CvtRandom (InitUniform (seed, low, high));
end InitUniform;
-------------------------------------------------------------------------------
function InitNegExp (mean: PositiveReal := 50.0;
seed: Integer := 13) return random is
begin
return CvtRandom (InitNegExp (seed, mean));
end InitNegExp;
-------------------------------------------------------------------------------
function InitPoisson (mean: PositiveReal := 50.0;
seed: Integer := 13) return random is
begin
return CvtRandom (InitPoisson (seed, mean));
end InitPoisson;
-------------------------------------------------------------------------------
function InitNormal (mean: Real := 0.0;
var: Real := 100.0;
seed: Integer := 13) return random is
begin
return CvtRandom (InitNormal (seed, mean, var));
end InitNormal;
-------------------------------------------------------------------------------
function InitLogNormal (mean: Real := 50.0;
var: Real := 100.0;
seed: Integer := 13) return random is
begin
return CvtRandom (InitLogNormal (seed, mean, var));
end InitLogNormal;
-------------------------------------------------------------------------------
function InitErlang (mean: Real := 50.0;
var: Real := 100.0;
seed: Integer := 13) return random is
begin
return CvtRandom (InitErlang (seed, mean, var));
end InitErlang;
-------------------------------------------------------------------------------
function InitBinomial (n: Integer := 0;
u: Real := 0.0;
seed: Integer := 13) return random is
begin
return CvtRandom (InitBinomial (seed, n, u));
end InitBinomial;
-------------------------------------------------------------------------------
function InitGeom (mean: Real := 0.0;
seed: Integer := 13) return random is
begin
return CvtRandom (InitGeom (seed, mean));
end InitGeom;
-------------------------------------------------------------------------------
function InitHypGeom (mean: Real := 0.0;
var: Real := 0.0;
seed: Integer := 13) return random is
begin
return CvtRandom (InitHypGeom (seed, mean, var));
end InitHypGeom;
-------------------------------------------------------------------------------
function InitWeibull (alpha: Real := 0.0;
beta: Real := 0.0;
seed: Integer := 13) return random is
begin
return CvtRandom (InitWeibull (seed, alpha, beta));
end InitWeibull;
-------------------------------------------------------------------------------
procedure GenRnd (r: inout random) is
variable unf : Uniform;
variable nex : NegExp;
variable poi : Poisson;
variable nom : Normal;
variable lnom : LogNormal;
variable erl : Erlang;
variable geo : Geom;
variable hypg : HypGeom;
variable bin : Binomial;
variable wei : Weibull;
begin
case r.dist is
when UniformDist =>
unf := (r.rnd, r.a(2), r.a(1), r.a(3), r.r);
GenRnd(unf);
r.rnd := unf.rnd;
r.r := unf.r;
return;
when NegExpDist =>
nex := (r.rnd, PositiveReal'(r.a(1)), r.r);
GenRnd(nex);
r.rnd := nex.rnd;
r.r := nex.r;
return;
when PoissonDist =>
poi := (r.rnd, PositiveReal'(r.a(1)), r.r);
GenRnd(poi);
r.rnd := poi.rnd;
r.r := poi.r;
return;
when NormalDist =>
nom := (r.rnd, r.a(1), r.a(3), r.a(2),
r.a(4), r.c, r.r);
GenRnd(nom);
r.rnd := nom.rnd;
r.r := nom.r;
r.a(4):= nom.CachedNormal;
r.c := nom.haveCachedNormal;
return;
when LogNormalDist =>
nom := (r.rnd, r.a(1), r.a(3), r.a(2),
r.a(4), r.c, r.r);
lnom := (r.rnd, r.a(5), r.a(6), nom);
GenRnd(lnom);
r.rnd := lnom.rnd;
r.r := lnom.n.r;
r.a(4):= lnom.n.CachedNormal;
r.c := lnom.n.haveCachedNormal;
return;
when ErlangDist =>
erl := (r.rnd, r.a(1), r.a(2), r.a(3),
r.b, r.r);
GenRnd(erl);
r.rnd := erl.rnd;
r.r := erl.r;
return;
when BinomialDist =>
bin := (r.rnd, r.a(1), r.b, r.r);
GenRnd(bin);
r.rnd := bin.rnd;
r.r := bin.r;
return;
when GeomDist =>
geo := (r.rnd, r.a(1), r.r);
GenRnd(geo);
r.rnd := geo.rnd;
r.r := geo.r;
return;
when HypGeomDist =>
hypg := (r.rnd, r.a(1), r.a(2), r.a(3), r.r);
GenRnd(hypg);
r.rnd := hypg.rnd;
r.r := hypg.r;
return;
when WeibullDist =>
wei := (r.rnd, r.a(1), r.a(3), r.a(2), r.r);
GenRnd(wei);
r.rnd := wei.rnd;
r.r := wei.r;
return;
end case;
end GenRnd;
-------------------------------------------------------------------------------
function CvtRandom (uni: in Uniform) return random is
variable r : random;
begin
r.dist := UniformDist;
r.rnd := uni.rnd;
r.a(1) := uni.pLow;
r.a(2) := uni.pHigh;
r.a(3) := uni.delta;
r.r := uni.r;
return r;
end CvtRandom;
-------------------------------------------------------------------------------
function CvtRandom (nex: in NegExp) return random is
variable r : random;
begin
r.dist := NegExpDist;
r.rnd := nex.rnd;
r.a(1) := nex.pMean;
r.r := nex.r;
return r;
end CvtRandom;
-------------------------------------------------------------------------------
function CvtRandom (poi: in Poisson) return random is
variable r : random;
begin
r.dist := PoissonDist;
r.rnd := poi.rnd;
r.a(1) := poi.pMean;
r.r := poi.r;
return r;
end CvtRandom;
-------------------------------------------------------------------------------
function CvtRandom (nom: in Normal) return random is
variable r : random;
begin
r.dist := NormalDist;
r.rnd := nom.rnd;
r.a(1) := nom.pMean;
r.a(2) := nom.pVariance;
r.a(3) := nom.pStdDev;
r.a(4) := nom.CachedNormal;
r.c := nom.haveCachedNormal;
r.r := nom.r;
return r;
end CvtRandom;
-------------------------------------------------------------------------------
function CvtRandom (lnom: in LogNormal) return random is
variable r : random := CvtRandom(lnom.n);
begin
r.dist := LogNormalDist;
r.a(5) := lnom.pLogMean;
r.a(6) := lnom.pLogVariance;
return r;
end CvtRandom;
-------------------------------------------------------------------------------
function CvtRandom (erl: in Erlang) return random is
variable r : random;
begin
r.dist := ErlangDist;
r.rnd := erl.rnd;
r.a(1) := erl.pMean;
r.a(2) := erl.pVariance;
r.a(3) := erl.a;
r.b := erl.k;
r.r := erl.r;
return r;
end CvtRandom;
-------------------------------------------------------------------------------
function CvtRandom (bin: in Binomial) return random is
variable r : random;
begin
r.dist := BinomialDist;
r.rnd := bin.rnd;
r.a(1) := bin.pU;
r.b := bin.pN;
r.r := bin.r;
return r;
end CvtRandom;
-------------------------------------------------------------------------------
function CvtRandom (geo: in Geom) return random is
variable r : random;
begin
r.dist := GeomDist;
r.a(1) := geo.pMean;
r.r := geo.r;
return r;
end CvtRandom;
-------------------------------------------------------------------------------
function CvtRandom (hypg: in HypGeom) return random is
variable r : random;
begin
r.dist := HypGeomDist;
r.a(1) := hypg.pMean;
r.a(2) := hypg.pVariance;
r.a(3) := hypg.pP;
r.r := hypg.r;
return r;
end CvtRandom;
-------------------------------------------------------------------------------
function CvtRandom (wei: in Weibull) return random is
variable r : random;
begin
r.dist := WeibullDist;
r.a(1) := wei.pAlpha;
r.a(2) := wei.pBeta;
r.a(3) := wei.pInvAlpha;
r.r := wei.r;
return r;
end CvtRandom;
-------------------------------------------------------------------------------
function CvtUniform (r: in random) return Uniform is
variable uni : Uniform := (r.rnd, r.a(2), r.a(1), r.a(3), r.r);
begin
return uni;
end CvtUniform;
-------------------------------------------------------------------------------
function CvtNegExp (r: in random) return NegExp is
variable nex : NegExp := (r.rnd, PositiveReal'(r.a(1)), r.r);
begin
return nex;
end CvtNegExp;
-------------------------------------------------------------------------------
function CvtPoisson (r: in random) return Poisson is
variable poi : Poisson := (r.rnd, PositiveReal'(r.a(1)), r.r);
begin
return poi;
end CvtPoisson;
-------------------------------------------------------------------------------
function CvtNormal (r: in random) return Normal is
variable nom : Normal := (r.rnd, r.a(1), r.a(3),
r.a(2), r.a(4), r.c, r.r);
begin
return nom;
end CvtNormal;
-------------------------------------------------------------------------------
function CvtLogNormal (r: in random) return LogNormal is
variable nom : Normal := (r.rnd, r.a(1), r.a(3), r.a(2),
r.a(4), r.c, r.r);
variable lnom : LogNormal := (r.rnd, r.a(5), r.a(6), nom);
begin
return lnom;
end CvtLogNormal;
-------------------------------------------------------------------------------
function CvtErlang (r: in random) return Erlang is
variable erl : Erlang := (r.rnd, r.a(1), r.a(2),
r.a(3), r.b, r.r);
begin
return erl;
end CvtErlang;
-------------------------------------------------------------------------------
function CvtBinomial (r: in random) return Binomial is
variable bin : Binomial := (r.rnd, r.a(1), r.b, r.r);
begin
return bin;
end CvtBinomial;
-------------------------------------------------------------------------------
function CvtGeom (r: in random) return Geom is
variable geo : Geom := (r.rnd, r.a(1), r.r);
begin
return geo;
end CvtGeom;
-------------------------------------------------------------------------------
function CvtHypGeom (r: in random) return HypGeom is
variable hypg : HypGeom := (r.rnd, r.a(1), r.a(2),
r.a(3), r.r);
begin
return hypg;
end CvtHypGeom;
-------------------------------------------------------------------------------
function CvtWeibull (r: in random) return Weibull is
variable wei : Weibull := (r.rnd, r.a(1), r.a(3),
r.a(2), r.r);
begin
return wei;
end CvtWeibull;
-------------------------------------------------------------------------------
end RNG;
 
/trunk/source/testbench/wave.do
1,53 → 1,43
onerror {resume}
quietly WaveActivateNextPane {} 0
quietly virtual signal -install /tb_mdct/u_mdct/u_dct1d { /tb_mdct/u_mdct/u_dct1d/col_reg(2 downto 1)} coLreg2
add wave -noupdate -format Literal /tb_mdct/u_inpimage/outimage_proc/error_matrix
add wave -noupdate -format Literal /tb_mdct/u_inpimage/outimage_proc/dcto_matrix
add wave -noupdate -format Literal /tb_mdct/u_inpimage/test_stim
add wave -noupdate -format Literal /tb_mdct/u_inpimage/test_inp
add wave -noupdate -format Literal /tb_mdct/u_inpimage/ycon_s
add wave -noupdate -format Literal /tb_mdct/u_inpimage/xcon_s
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_inpimage/testend
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dct1d/rst
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/requestwr
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/requestrd
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/releasewr
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/releaserd
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/memswitchwr
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/memswitchrd
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/mem1_full_reg
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/mem2_full_reg
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/mem1_lock_reg
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/mem2_lock_reg
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dct1d/clk
add wave -noupdate -format Literal -radix unsigned /tb_mdct/u_mdct/u_dct1d/dcti
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dct1d/idv
add wave -noupdate -format Logic /tb_mdct/u_inpimage/ready
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u_dct1d/istate_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u_dct1d/state_reg
add wave -noupdate -format Logic /tb_mdct/u_mdct/u_dct1d/latch_done_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u1_rome0/datao
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dct1d/clk
add wave -noupdate -format Logic /tb_mdct/u_mdct/odv1
add wave -noupdate -format Literal -radix decimal /tb_mdct/u_mdct/dcto1
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dct1d/ramwe
add wave -noupdate -format Literal -radix unsigned /tb_mdct/u_mdct/u_dct1d/ramwaddro
add wave -noupdate -format Literal -radix decimal /tb_mdct/u_mdct/u_dct1d/ramdatai
add wave -noupdate -format Literal /tb_mdct/u_inpimage/error_dcto1_matrix_s
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dct1d/ready_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u_dct1d/inpcnt_reg
add wave -noupdate -format Literal -radix unsigned /tb_mdct/u_mdct/u_dct1d/coLreg2
add wave -noupdate -format Literal -radix unsigned /tb_mdct/u_mdct/u_dct1d/col_reg
add wave -noupdate -format Literal -radix unsigned /tb_mdct/u_mdct/u_dct1d/col_2_reg
add wave -noupdate -format Literal -radix unsigned /tb_mdct/u_mdct/u_dct1d/row_reg
add wave -noupdate -format Literal -radix unsigned /tb_mdct/u_mdct/u_dct1d/stage2_cnt_reg
add wave -noupdate -format Logic /tb_mdct/u_mdct/u_dct1d/stage2_reg
add wave -noupdate -format Literal -radix decimal /tb_mdct/u_mdct/u_dct1d/databuf_reg
add wave -noupdate -format Literal -radix unsigned /tb_mdct/u_mdct/u_dct1d/latchbuf_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u_dct1d/col_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u_dct1d/row_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u_dct1d/inpcnt_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u_dct1d/cnt_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u_dct1d/ramdatai_s
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dct1d/ramwe_s
add wave -noupdate -format Literal /tb_mdct/u_inpimage/inpimage_proc/i
add wave -noupdate -format Literal /tb_mdct/u_inpimage/inpimage_proc/j
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/memswitchwr
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/memswitchrd
add wave -noupdate -format Logic /tb_mdct/u_mdct/u_dct2d/clk
add wave -noupdate -format Logic /tb_mdct/u_mdct/u_dct2d/rst
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dct2d/odv
add wave -noupdate -format Literal -radix decimal /tb_mdct/u_mdct/u_dct2d/dcto
add wave -noupdate -format Logic /tb_mdct/u_mdct/u_dct2d/stage1_reg
add wave -noupdate -format Logic /tb_mdct/u_mdct/u_dct2d/stage2_reg
add wave -noupdate -format Literal -radix unsigned /tb_mdct/u_mdct/u_dct2d/stage2_cnt_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u_dct2d/colram_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u_dct2d/rowram_reg
add wave -noupdate -format Literal -radix unsigned /tb_mdct/u_mdct/u_dct2d/ramraddro
54,30 → 44,24
add wave -noupdate -format Literal -radix decimal /tb_mdct/u_mdct/u_dct2d/ramdatao
add wave -noupdate -format Literal -radix decimal /tb_mdct/u_mdct/u_dct2d/latchbuf_reg
add wave -noupdate -format Literal -radix decimal /tb_mdct/u_mdct/u_dct2d/databuf_reg
add wave -noupdate -format Logic /tb_mdct/u_mdct/u_dct1d/wmemsel
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u_dct2d/col_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u_dct2d/row_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u_dct2d/state_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u_dct2d/istate_reg
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/dataready
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u_dct2d/cnt_reg
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dct2d/latch_done_reg
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dct2d/completed_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u_dct1d/ramdatai_s
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dct1d/ramwe_s
add wave -noupdate -format Literal /tb_mdct/u_inpimage/inpimage_proc/i
add wave -noupdate -format Literal /tb_mdct/u_inpimage/inpimage_proc/j
add wave -noupdate -format Literal /tb_mdct/u_inpimage/final_outimage_proc/error_matrix
add wave -noupdate -format Literal /tb_mdct/u_inpimage/error_dct_matrix_s
add wave -noupdate -format Literal -radix decimal /tb_mdct/u_mdct/u1_ram/mem
add wave -noupdate -format Literal /tb_mdct/u_mdct/u2_ram/mem
add wave -noupdate -format Logic /tb_mdct/u_mdct/u_dbufctl/clk
add wave -noupdate -format Logic /tb_mdct/u_mdct/u_dbufctl/rst
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/requestwr
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/requestrd
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/releasewr
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/releaserd
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/memswitchwr
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/memswitchrd
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/reqwrfail
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/reqrdfail
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/memswitchwr_reg
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/memswitchrd_reg
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/mem1_full_reg
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/mem2_full_reg
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/mem1_lock_reg
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/mem2_lock_reg
add wave -noupdate -format Literal /tb_mdct/u_inpimage/final_outimage_proc/i
add wave -noupdate -format Literal /tb_mdct/u_inpimage/final_outimage_proc/j
add wave -noupdate -format Literal /tb_mdct/u_inpimage/final_outimage_proc/error_cnt
85,7 → 69,6
add wave -noupdate -format Literal /tb_mdct/u_inpimage/outimage_proc/j
add wave -noupdate -format Literal /tb_mdct/u_inpimage/outimage_proc/error_cnt
add wave -noupdate -format Literal /tb_mdct/u_inpimage/outimage_proc/raport_str
add wave -noupdate -format Literal /tb_mdct/u_inpimage/final_outimage_proc/error_matrix
add wave -noupdate -format Literal /tb_mdct/u_inpimage/final_outimage_proc/ref_matrix_1d
add wave -noupdate -format Literal /tb_mdct/u_inpimage/final_outimage_proc/ref_matrix_2d
add wave -noupdate -format Literal /tb_mdct/u_inpimage/final_outimage_proc/dcto_matrix
96,21 → 79,22
add wave -noupdate -format Literal /tb_mdct/u_inpimage/final_outimage_proc/psnr
add wave -noupdate -format Literal /tb_mdct/u_inpimage/inpimage_proc/i
add wave -noupdate -format Literal /tb_mdct/u_inpimage/inpimage_proc/j
add wave -noupdate -format Literal /tb_mdct/u_inpimage/error_dct_matrix_s
add wave -noupdate -format Literal /tb_mdct/u_inpimage/error_dcto1_matrix_s
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u1_rome0/addr
add wave -noupdate -format Literal /tb_mdct/u_mdct/u1_romo0/datao
add wave -noupdate -format Literal /tb_mdct/u_mdct/u1_rome0/addr
add wave -noupdate -format Logic /tb_mdct/u_mdct/u1_rome0/clk
add wave -noupdate -format Literal /tb_mdct/u_mdct/u1_rome0/datao
add wave -noupdate -format Literal /tb_mdct/u_mdct/u1_rome0/raddr
add wave -noupdate -format Literal /tb_mdct/u_mdct/u1_romo0/addr
add wave -noupdate -format Logic /tb_mdct/u_mdct/u1_romo0/clk
add wave -noupdate -format Literal /tb_mdct/u_mdct/u1_romo0/raddr
add wave -noupdate -format Logic /tb_mdct/u_mdct/u1_ram/clk
add wave -noupdate -format Literal /tb_mdct/u_mdct/u1_ram/d
add wave -noupdate -format Literal /tb_mdct/u_mdct/u1_ram/waddr
add wave -noupdate -format Literal /tb_mdct/u_mdct/u1_ram/raddr
add wave -noupdate -format Logic /tb_mdct/u_mdct/u1_ram/we
add wave -noupdate -format Logic /tb_mdct/u_mdct/u1_ram/clk
add wave -noupdate -format Literal /tb_mdct/u_mdct/u1_ram/q
add wave -noupdate -format Literal /tb_mdct/u_mdct/u1_ram/mem
add wave -noupdate -format Literal /tb_mdct/u_mdct/u1_ram/read_addr
add wave -noupdate -format Literal /tb_mdct/u_inpimage/final_outimage_proc/i
add wave -noupdate -format Literal /tb_mdct/u_inpimage/final_outimage_proc/j
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {2168745 ps} 0}
WaveRestoreCursors {{Cursor 1} {220350000 ps} 0}
configure wave -namecolwidth 155
configure wave -valuecolwidth 40
configure wave -valuecolwidth 103
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
122,4 → 106,4
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {0 ps} {3002 ns}
WaveRestoreZoom {218222050 ps} {222338850 ps}
/trunk/source/testbench/INPIMAGE.VHD
29,6 → 29,7
library WORK;
use WORK.MDCT_PKG.all;
use WORK.MDCTTB_PKG.all;
use WORK.RNG.all;
entity INPIMAGE is
port (
54,6 → 55,7
signal rst_s : STD_LOGIC;
signal test_inp : INTEGER;
signal test_stim : INTEGER;
signal test_out : INTEGER;
signal xcon_s : INTEGER;
signal ycon_s : INTEGER;
68,9 → 70,12
-- input image stimuli
--------------------------
INPIMAGE_PROC: process
variable i : INTEGER := 0;
variable j : INTEGER := 0;
variable i : INTEGER := 0;
variable j : INTEGER := 0;
variable INSERT_DELAYS : BOOLEAN := FALSE;
variable unf: Uniform := InitUniform(7, 0.0, 2.0);
variable rnd: real := 0.0;
variable xi : INTEGER := 0;
-------------------------------------
-- wait for defined number of clock cycles
159,9 → 164,6
xcon_s <= x_blk_cnt*N+j;
ycon_s <= y_blk_cnt*N+i;
waitposedge;
while(ready = '0') loop
waitposedge;
end loop;
if INSERT_DELAYS = TRUE then
dv <= '0';
waitposedge(40);
179,6 → 181,7
-- process begin
---------------------------
begin
test_stim <= 0;
dv <= '0';
imageo <= (others => '0');
rst_s <= '1';
188,14 → 191,12
-------------------------
-- test 1
-------------------------
test_stim <= 1;
for i in 0 to 7 loop
for j in 0 to 7 loop
dv <= '1';
imageo <= STD_LOGIC_VECTOR(TO_UNSIGNED(INTEGER(input_data0(i,j)),IP_W));
waitposedge;
while(ready = '0') loop
waitposedge;
end loop;
end loop;
end loop;
207,14 → 208,12
-------------------------
-- test 2
-------------------------
test_stim <= 2;
for i in 0 to 7 loop
for j in 0 to 7 loop
dv <= '1';
imageo <= STD_LOGIC_VECTOR(TO_UNSIGNED(INTEGER(input_data1(i,j)),IP_W));
waitposedge;
while(ready = '0') loop
waitposedge;
end loop;
end loop;
end loop;
226,14 → 225,12
-------------------------
-- test 3
-------------------------
test_stim <= 3;
for i in 0 to 7 loop
for j in 0 to 7 loop
dv <= '1';
imageo <= STD_LOGIC_VECTOR(TO_UNSIGNED(INTEGER(input_data2(i,j)),IP_W));
waitposedge;
while(ready = '0') loop
waitposedge;
end loop;
end loop;
end loop;
245,14 → 242,12
-------------------------
-- test 4
-------------------------
test_stim <= 4;
for i in 0 to 7 loop
for j in 0 to 7 loop
dv <= '1';
imageo <= STD_LOGIC_VECTOR(TO_UNSIGNED(INTEGER(input_data1(i,j)),IP_W));
imageo <= STD_LOGIC_VECTOR(TO_UNSIGNED(INTEGER(input_data0(i,j)),IP_W));
waitposedge;
while(ready = '0') loop
waitposedge;
end loop;
dv <= '0';
waitposedge;
end loop;
266,14 → 261,12
-------------------------
-- test 5
-------------------------
test_stim <= 5;
for i in 0 to 7 loop
for j in 0 to 7 loop
dv <= '1';
imageo <= STD_LOGIC_VECTOR(TO_UNSIGNED(INTEGER(input_data1(i,j)),IP_W));
waitposedge;
while(ready = '0') loop
waitposedge;
end loop;
dv <= '0';
waitposedge(25);
end loop;
285,9 → 278,74
------------------------
-------------------------
-- test 6-16
-------------------------
for x in 0 to 10 loop
test_stim <= test_stim+1;
for i in 0 to 7 loop
for j in 0 to 7 loop
dv <= '1';
if x rem 2 = 0 then
imageo <= STD_LOGIC_VECTOR(TO_UNSIGNED(INTEGER(input_data0(i,j)),IP_W));
else
imageo <= STD_LOGIC_VECTOR(TO_UNSIGNED(INTEGER(input_data3(i,j)),IP_W));
end if;
waitposedge;
end loop;
end loop;
end loop;
 
dv <= '0';
waitposedge;
------------------------
-------------------------
-- test 17-33
-------------------------
for x in 0 to 48 loop
test_stim <= test_stim+1;
if xi < 4 then
xi := xi + 1;
else
xi := 0;
end if;
for i in 0 to 7 loop
for j in 0 to 7 loop
dv <= '1';
case xi is
when 0 =>
imageo <= STD_LOGIC_VECTOR(TO_UNSIGNED(INTEGER(input_data1(i,j)),IP_W));
when 1 =>
imageo <= STD_LOGIC_VECTOR(TO_UNSIGNED(INTEGER(input_data0(i,j)),IP_W));
when 2 =>
imageo <= STD_LOGIC_VECTOR(TO_UNSIGNED(INTEGER(input_data3(i,j)),IP_W));
when 3 =>
imageo <= STD_LOGIC_VECTOR(TO_UNSIGNED(INTEGER(input_data4(i,j)),IP_W));
when others =>
imageo <= STD_LOGIC_VECTOR(TO_UNSIGNED(INTEGER(input_data0(i,j)),IP_W));
end case;
waitposedge;
dv <= '0';
GenRnd(unf);
rnd := unf.rnd;
waitposedge(INTEGER(rnd));
end loop;
end loop;
end loop;
 
dv <= '0';
waitposedge;
------------------------
-------------------------
-- test 6
-------------------------
read_image;
if RUN_FULL_IMAGE = TRUE then
read_image;
end if;
-------------------------
-- test 7
313,6 → 371,7
variable raport_str : STRING(1 to 255);
variable ref_matrix : I_MATRIX_TYPE;
variable dcto_matrix : I_MATRIX_TYPE;
variable xi : INTEGER := 0;
-------------------------------------
-- wait for defined number of clock cycles
-------------------------------------
448,8 → 507,6
end loop;
end loop;
waitposedge;
CMP_MATRIX(ref_matrix,dcto_matrix,MAX_ERROR_1D,error_matrix,error_cnt);
-------------------------
477,8 → 534,6
end loop;
end loop;
waitposedge;
CMP_MATRIX(ref_matrix,dcto_matrix,MAX_ERROR_1D,error_matrix,error_cnt);
-------------------------
506,8 → 561,6
end loop;
end loop;
waitposedge;
CMP_MATRIX(ref_matrix,dcto_matrix,MAX_ERROR_1D,error_matrix,error_cnt);
-------------------------
516,7 → 569,7
-------------------------
test_inp <= 4;
-- compute reference coefficients
ref_matrix := COMPUTE_REF_DCT1D(input_data1,TRUE);
ref_matrix := COMPUTE_REF_DCT1D(input_data0,TRUE);
for i in 0 to N-1 loop
j := 0;
535,8 → 588,6
end loop;
end loop;
waitposedge;
CMP_MATRIX(ref_matrix,dcto_matrix,MAX_ERROR_1D,error_matrix,error_cnt);
-------------------------
564,17 → 615,92
end loop;
end loop;
waitposedge;
CMP_MATRIX(ref_matrix,dcto_matrix,MAX_ERROR_1D,error_matrix,error_cnt);
-------------------------
-------------------------
-- test 6-16
-------------------------
for x in 0 to 10 loop
test_inp <= test_inp + 1;
-- compute reference coefficients
if x rem 2 = 0 then
ref_matrix := COMPUTE_REF_DCT1D(input_data0,TRUE);
else
ref_matrix := COMPUTE_REF_DCT1D(input_data3,TRUE);
end if;
for i in 0 to N-1 loop
j := 0;
while(true) loop
waitposedge;
if odv1 = '1' then
dcto_matrix(j,i) := TO_INTEGER(SIGNED( dcto1 ));
j := j + 1;
end if;
if j = N then
exit;
end if;
end loop;
end loop;
CMP_MATRIX(ref_matrix,dcto_matrix,MAX_ERROR_1D,error_matrix,error_cnt);
end loop;
-------------------------
-------------------------
-- test 17-33
-------------------------
for x in 0 to 48 loop
test_inp <= test_inp + 1;
-- compute reference coefficients
if xi < 4 then
xi := xi + 1;
else
xi := 0;
end if;
case xi is
when 0 =>
ref_matrix := COMPUTE_REF_DCT1D(input_data1,TRUE);
when 1 =>
ref_matrix := COMPUTE_REF_DCT1D(input_data0,TRUE);
when 2 =>
ref_matrix := COMPUTE_REF_DCT1D(input_data3,TRUE);
when 3 =>
ref_matrix := COMPUTE_REF_DCT1D(input_data4,TRUE);
when others =>
ref_matrix := COMPUTE_REF_DCT1D(input_data0,TRUE);
end case;
 
for i in 0 to N-1 loop
j := 0;
while(true) loop
waitposedge;
if odv1 = '1' then
dcto_matrix(j,i) := TO_INTEGER(SIGNED( dcto1 ));
j := j + 1;
end if;
if j = N then
exit;
end if;
end loop;
end loop;
CMP_MATRIX(ref_matrix,dcto_matrix,MAX_ERROR_1D,error_matrix,error_cnt);
end loop;
-------------------------
-------------------------
-- test 6
-------------------------
test_inp <= 6;
read_image_for1dct(error_cnt);
if RUN_FULL_IMAGE = TRUE then
read_image_for1dct(error_cnt);
end if;
-------------------------
-------------------------
618,6 → 744,7
variable dcto_matrix : I_MATRIX_TYPE;
variable tmp_matrix : I_MATRIX_TYPE;
variable psnr : REAL;
variable xi : INTEGER := 0;
-------------------------------------
-- wait for defined number of clock cycles
-------------------------------------
935,7 → 1062,7
-- test 4
-------------------------
test_out <= 4;
tmp_matrix := input_data1;
tmp_matrix := input_data0;
-- compute reference coefficients
ref_matrix_1d := COMPUTE_REF_DCT1D(tmp_matrix,TRUE);
ref_matrix_2d := COMPUTE_REF_DCT1D(ref_matrix_1d,FALSE);
995,15 → 1122,103
CMP_MATRIX(ref_matrix_2d,dcto_matrix,MAX_ERROR_2D,error_matrix,error_cnt);
idcto_matrix := COMPUTE_REF_IDCT(dcto_matrix);
--error_idct_matrix := CMP_MATRIX(tmp_matrix,idcto_matrix,MAX_ERROR_2D);
psnr := COMPUTE_PSNR(tmp_matrix,idcto_matrix);
-------------------------
-------------------------
-- test 6-16
-------------------------
for x in 0 to 10 loop
test_out <= test_out+1;
if x rem 2 = 0 then
tmp_matrix := input_data0;
else
tmp_matrix := input_data3;
end if;
-- compute reference coefficients
ref_matrix_1d := COMPUTE_REF_DCT1D(tmp_matrix,TRUE);
ref_matrix_2d := COMPUTE_REF_DCT1D(ref_matrix_1d,FALSE);
for i in 0 to N-1 loop
j := 0;
while(true) loop
waitposedge;
if odv = '1' then
dcto_matrix(j,i) := TO_INTEGER(SIGNED( dcto ));
j := j + 1;
end if;
if j = N then
exit;
end if;
end loop;
end loop;
CMP_MATRIX(ref_matrix_2d,dcto_matrix,MAX_ERROR_2D,error_matrix,error_cnt);
idcto_matrix := COMPUTE_REF_IDCT(dcto_matrix);
psnr := COMPUTE_PSNR(tmp_matrix,idcto_matrix);
end loop;
-------------------------
-------------------------
-- test 17-33
-------------------------
for x in 0 to 48 loop
test_out <= test_out+1;
if xi < 4 then
xi := xi + 1;
else
xi := 0;
end if;
case xi is
when 0 =>
tmp_matrix := input_data1;
when 1 =>
tmp_matrix := input_data0;
when 2 =>
tmp_matrix := input_data3;
when 3 =>
tmp_matrix := input_data4;
when others =>
tmp_matrix := input_data0;
end case;
-- compute reference coefficients
ref_matrix_1d := COMPUTE_REF_DCT1D(tmp_matrix,TRUE);
ref_matrix_2d := COMPUTE_REF_DCT1D(ref_matrix_1d,FALSE);
for i in 0 to N-1 loop
j := 0;
while(true) loop
waitposedge;
if odv = '1' then
dcto_matrix(j,i) := TO_INTEGER(SIGNED( dcto ));
j := j + 1;
end if;
 
if j = N then
exit;
end if;
end loop;
end loop;
CMP_MATRIX(ref_matrix_2d,dcto_matrix,MAX_ERROR_2D,error_matrix,error_cnt);
idcto_matrix := COMPUTE_REF_IDCT(dcto_matrix);
psnr := COMPUTE_PSNR(tmp_matrix,idcto_matrix);
end loop;
-------------------------
-------------------------
-- test 6
-------------------------
test_out <= 6;
read_image_for2dct(error_cnt);
if RUN_FULL_IMAGE = TRUE then
read_image_for2dct(error_cnt);
end if;
-------------------------
-------------------------
/trunk/source/testbench/MDCT_TB.VHD
45,7 → 45,7
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
 
ready : out STD_LOGIC; -- ready for input data
fiforead : out STD_LOGIC; -- ready for input data
odv : out STD_LOGIC;
dcto : out std_logic_vector(COE_W-1 downto 0);
-- debug
89,7 → 89,7
signal dcti_s : STD_LOGIC_VECTOR(IP_W-1 downto 0);
signal idv_s : STD_LOGIC;
 
signal ready_s : STD_LOGIC;
signal fiforead_s : STD_LOGIC;
signal odv_s : STD_LOGIC;
signal dcto_s : STD_LOGIC_VECTOR(COE_W-1 downto 0);
signal odv1_s : STD_LOGIC;
110,7 → 110,7
dcti => dcti_s,
idv => idv_s,
 
ready => ready_s,
fiforead => fiforead_s,
odv => odv_s,
dcto => dcto_s,
odv1 => odv1_s,
134,7 → 134,7
U_INPIMAGE : INPIMAGE
port map (
clk => clk_s,
ready => ready_s,
ready => fiforead_s,
odv1 => odv1_s,
dcto1 => dcto1_s,
odv => odv_s,
/trunk/source/testbench/MDCT_TB.DO
41,6 → 41,7
vcom SOURCE/DCT2D.VHD
vcom SOURCE/DBUFCTL.VHD
vcom SOURCE/MDCT.VHD
vcom SOURCE/TESTBENCH/random1.VHD
vcom SOURCE/TESTBENCH/CLKGEN.VHD
vcom SOURCE/TESTBENCH/MDCTTB_PKG.VHD
vcom SOURCE/TESTBENCH/INPIMAGE.VHD
/trunk/source/testbench/MDCTTB_PKG.vhd
75,15 → 75,16
----------------------------------------------
-- set below to true to enable quantization in testbench
constant ENABLE_QUANTIZATION_C : BOOLEAN := FALSE;
constant HEX_BASE : INTEGER := 16;
constant DEC_BASE : INTEGER := 10;
constant FILEIN_NAME_C : STRING := "SOURCE\TESTBENCH\lena512.txt";
constant HEX_BASE : INTEGER := 16;
constant DEC_BASE : INTEGER := 10;
constant RUN_FULL_IMAGE : BOOLEAN := FALSE;
constant FILEIN_NAME_C : STRING := "SOURCE\TESTBENCH\lena512.txt";
constant FILEERROR_NAME_C : STRING := "SOURCE\TESTBENCH\imagee.txt";
constant FILEIMAGEO_NAME_C : STRING := "SOURCE\TESTBENCH\imageo.txt";
constant MAX_ERROR_1D : INTEGER := 1;
constant MAX_ERROR_2D : INTEGER := 4;
constant MAX_PIX_VAL : INTEGER := 2**IP_W-1;
constant null_data_r : MATRIX_TYPE :=
constant MAX_ERROR_1D : INTEGER := 1;
constant MAX_ERROR_2D : INTEGER := 4;
constant MAX_PIX_VAL : INTEGER := 2**IP_W-1;
constant null_data_r : MATRIX_TYPE :=
(
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0),
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0),
129,7 → 130,30
(000,000,000,000,000,000,000,000),
(000,000,000,000,000,000,000,000),
(000,000,000,000,000,000,000,000)
);
constant input_data3 : I_MATRIX_TYPE :=
(
(55,89,0,2,35,34,100,255),
(144,151,153,151,159,156,156,156),
(150,155,165,163,158,126,156,156),
(254,000,255,255,000,245,254,255),
(159,199,161,162,162,133,155,165),
(231,000,255,235,000,255,254,253),
(162,162,161,163,162,157,157,157),
(11,12,167,165,166,167,101,108)
);
constant input_data4 : I_MATRIX_TYPE :=
(
(135,14,145,15,155,15,155,15),
(140,15,151,15,152,15,153,15),
(154,15,165,16,156,15,157,15),
(158,16,168,16,169,15,150,15),
(15,161,16,162,16,153,15,154),
(165,16,166,16,167,15,158,15),
(16,169,16,160,16,152,15,153),
(164,16,165,16,165,15,156,15)
);
-- from JPEG standard (but not in standard itself!)
constant Q_JPEG_STD : I_MATRIX_TYPE :=
337,7 → 361,7
for a in 0 to N - 1 loop
for b in 0 to N - 1 loop
error_matrix_v(a,b) := ref_matrix(a,b) - dcto_matrix(a,b);
if error_matrix_v(a,b) > max_error then
if abs(error_matrix_v(a,b)) > max_error then
error_cnt := error_cnt + 1;
assert false
report "E01: DCT max error violated!"
/trunk/source/DCT2D.VHD
55,7 → 55,6
romodatao9 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao10 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
ramdatao : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
reqrdfail : in STD_LOGIC;
dataready : in STD_LOGIC;
odv : out STD_LOGIC;
83,28 → 82,14
romoaddro9 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro10 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
ramraddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
requestrd : out STD_LOGIC;
releaserd : out STD_LOGIC
rmemsel : out STD_LOGIC;
datareadyack : out STD_LOGIC
);
end DCT2D;
 
architecture RTL of DCT2D is
 
type STATE2_T is
(
IDLE,
GET_ROM,
SUM,
WRITE_ODD
);
type ISTATE2_T is
(
IDLE_I,
ACQUIRE_1ROW
);
type input_data2 is array (N-1 downto 0) of SIGNED(RAMDATA_W downto 0);
signal databuf_reg : input_data2;
111,177 → 96,96
signal latchbuf_reg : input_data2;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal state_reg : STATE2_T;
signal istate_reg : ISTATE2_T;
signal cnt_reg : UNSIGNED(3 downto 0);
signal latch_done_reg : STD_LOGIC;
signal colram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colram_reg : UNSIGNED(RAMADRR_W/2 downto 0);
signal requestrd_reg : STD_LOGIC;
signal releaserd_reg : STD_LOGIC;
signal completed_reg : STD_LOGIC;
signal col_tmp_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rmemsel_reg : STD_LOGIC;
signal stage1_reg : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal dataready_2_reg : STD_LOGIC;
begin
 
ramraddro_sg:
ramraddro <= STD_LOGIC_VECTOR(rowram_reg & colram_reg(2 downto 0));
ramraddro <= STD_LOGIC_VECTOR(rowr_reg & colr_reg);
requestrd_sg:
requestrd <= requestrd_reg;
rmemsel_sg:
rmemsel <= rmemsel_reg;
releaserd_sg:
releaserd <= releaserd_reg;
process(rst,clk)
begin
if rst = '1' then
stage2_cnt_reg <= (others => '1');
rmemsel_reg <= '0';
stage1_reg <= '0';
stage2_reg <= '0';
colram_reg <= (others => '0');
rowram_reg <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
dcto <= (others => '0');
odv <= '0';
colr_reg <= (others => '0');
rowr_reg <= (others => '0');
dataready_2_reg <= '0';
elsif clk='1' and clk'event then
GET_PROC : process(rst,clk)
begin
if rst = '1' then
rowram_reg <= (others => '0');
colram_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
istate_reg <= IDLE_I;
latch_done_reg <= '0';
completed_reg <= '0';
requestrd_reg <= '0';
releaserd_reg <= '0';
databuf_reg <= (others => (others => '0'));
elsif clk = '1' and clk'event then
case istate_reg is
stage2_reg <= '0';
odv <= '0';
datareadyack <= '0';
 
dataready_2_reg <= dataready;
----------------------
-- IDLE
----------------------
when IDLE_I =>
-- one of ram buffers has new data, process it
if dataready = '1' then
requestrd_reg <= '1';
----------------------------------
-- read DCT 1D to barrel shifer
----------------------------------
if stage1_reg = '1' then
 
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
colram_reg <= colram_reg + 1;
colr_reg <= colr_reg + 1;
if colram_reg = N-2 then
rowr_reg <= rowr_reg + 1;
end if;
if colram_reg = N-1 then
rowram_reg <= rowram_reg + 1;
if rowram_reg = N-1 then
stage1_reg <= '0';
colr_reg <= (others => '0');
-- release memory
rmemsel_reg <= not rmemsel_reg;
end if;
-- give 1T delay needed by DBUFCTL
if requestrd_reg = '1' then
requestrd_reg <= '0';
istate_reg <= ACQUIRE_1ROW;
-- to account for 1T RAM delay, increment RAM address counter
colram_reg <= (0=>'1',others => '0');
end if;
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
-- 8 point input latched
stage2_reg <= '1';
end if;
end if;
----------------------
-- latch input data to barrel shifter
----------------------
when ACQUIRE_1ROW =>
if latch_done_reg = '0' then
-- not starting from zero b/c of RAM 1T delay
if colram_reg /= 0 then
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
end if;
colram_reg <= colram_reg + 1;
-- not N-1
if colram_reg = N then
-- finished reading 64 point 1D DCT from RAM
if rowram_reg = N-1 then
-- release memory
releaserd_reg <= '1';
completed_reg <= '1';
end if;
colram_reg <= ( others => '0');
rowram_reg <= rowram_reg + 1;
-- 8 point input latched
latch_done_reg <= '1';
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
end if;
-- failure to allocate memory buffer
-- should never happen?
if reqrdfail = '1' then
istate_reg <= IDLE_I;
end if;
else
releaserd_reg <= '0';
-- wait until DCT1D_PROC process 1D DCT computation
-- before latching new 8 input words
if state_reg = IDLE then
latch_done_reg <= '0';
if completed_reg = '1' then
completed_reg <= '0';
colram_reg <= (others => '0');
istate_reg <= IDLE_I;
else
istate_reg <= ACQUIRE_1ROW;
-- to account for 1T RAM delay, increment RAM address counter
colram_reg <= (0=>'1',others => '0');
end if;
end if;
end if;
when others =>
istate_reg <= IDLE_I;
end case;
end if;
end process;
 
DCT1D_PROC: process(rst, clk)
begin
if rst = '1' then
col_reg <= (others => '0');
row_reg <= (others => '0');
state_reg <= IDLE;
cnt_reg <= (others => '0');
odv <= '0';
dcto <= (others => '0');
col_tmp_reg <= (others => '0');
elsif rising_edge(clk) then
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
case state_reg is
----------------------
-- wait for input data
----------------------
when IDLE =>
odv <= '0';
-- wait until 8 input words are latched in latchbuf_reg
-- by GET_PROC
if latch_done_reg = '1' then
state_reg <= SUM;
end if;
 
----------------------
-- get MAC results from ROM even and ROM odd memories
----------------------
when GET_ROM =>
odv <= '0';
state_reg <= SUM;
---------------------
-- do distributed arithmetic sum on even part,
-- write even part to RAM
---------------------
when SUM =>
-- (a0 +
-- a1*2 +
-- (a2 + a3*2)*4 +
-- a4 * 2^4 +
-- a5*2 * 2^4 +
-- (a6 +
-- a7*2)*2^6 )/
-- 2^11
if stage2_cnt_reg(0) = '0' then
dcto <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao0),DA2_W) +
(RESIZE(SIGNED(romedatao1),DA2_W-1) & '0') +
295,21 → 199,7
(RESIZE(SIGNED(romedatao9),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romedatao10),DA2_W-10) & "0000000000"),
DA2_W)(DA2_W-1 downto 12));
-- write even part
odv <= '1';
col_reg <= col_reg + 1;
col_tmp_reg <= col_reg + 2;
state_reg <= WRITE_ODD;
---------------------
-- do distributed arithmetic sum on odd part,
-- write odd part to RAM
---------------------
when WRITE_ODD =>
else
dcto <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao0),DA2_W) +
(RESIZE(SIGNED(romodatao1),DA2_W-1) & '0') +
322,80 → 212,97
(RESIZE(SIGNED(romodatao8),DA2_W-8) & "00000000") +
(RESIZE(SIGNED(romodatao9),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romodatao10),DA2_W-10) & "0000000000"),
DA2_W)(DA2_W-1 downto 12));
col_reg <= col_reg + 1;
col_tmp_reg <= col_reg + 1;
-- finished processing one input row (1 x N)
if col_reg = N - 1 then
row_reg <= row_reg + 1;
col_reg <= (others => '0');
col_tmp_reg <= (others => '0');
state_reg <= IDLE;
else
state_reg <= SUM;
end if;
DA2_W)(DA2_W-1 downto 12));
end if;
-----------------
when others =>
state_reg <= IDLE;
end case;
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- write RAM
odv <= '1';
-- increment column counter
col_reg <= col_reg + 1;
-- finished processing one input row
if col_reg = N - 1 then
row_reg <= row_reg + 1;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
end if;
--------------------------------
----------------------------------
-- wait for new data
----------------------------------
-- one of ram buffers has new data, process it
if dataready = '1' and dataready_2_reg = '0' then
stage1_reg <= '1';
-- to account for 1T RAM delay, increment RAM address counter
colram_reg <= (others => '0');
colr_reg <= (0=>'1',others => '0');
datareadyack <= '1';
end if;
----------------------------------
end if;
end process;
end process;
 
-- read precomputed MAC results from LUT
romeaddro0 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
romeaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(0) &
databuf_reg(1)(0) &
databuf_reg(2)(0) &
databuf_reg(3)(0);
romeaddro1 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
romeaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(1) &
databuf_reg(1)(1) &
databuf_reg(2)(1) &
databuf_reg(3)(1);
romeaddro2 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
romeaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(2) &
databuf_reg(1)(2) &
databuf_reg(2)(2) &
databuf_reg(3)(2);
romeaddro3 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
romeaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(3) &
databuf_reg(1)(3) &
databuf_reg(2)(3) &
databuf_reg(3)(3);
romeaddro4 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
romeaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(4) &
databuf_reg(1)(4) &
databuf_reg(2)(4) &
databuf_reg(3)(4);
romeaddro5 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
romeaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(5) &
databuf_reg(1)(5) &
databuf_reg(2)(5) &
databuf_reg(3)(5);
romeaddro6 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
romeaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(6) &
databuf_reg(1)(6) &
databuf_reg(2)(6) &
databuf_reg(3)(6);
romeaddro7 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
romeaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(7) &
databuf_reg(1)(7) &
databuf_reg(2)(7) &
databuf_reg(3)(7);
romeaddro8 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
romeaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(8) &
databuf_reg(1)(8) &
databuf_reg(2)(8) &
databuf_reg(3)(8);
romeaddro9 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
romeaddro9 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(9) &
databuf_reg(1)(9) &
databuf_reg(2)(9) &
databuf_reg(3)(9);
romeaddro10 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
romeaddro10 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(10) &
databuf_reg(1)(10) &
databuf_reg(2)(10) &
/trunk/source/DBUFCTL.VHD
29,15 → 29,12
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
requestwr : in STD_LOGIC;
requestrd : in STD_LOGIC;
releasewr : in STD_LOGIC;
releaserd : in STD_LOGIC;
wmemsel : in STD_LOGIC;
rmemsel : in STD_LOGIC;
datareadyack : in STD_LOGIC;
memswitchwr : out STD_LOGIC;
memswitchrd : out STD_LOGIC;
reqwrfail : out STD_LOGIC;
reqrdfail : out STD_LOGIC;
dataready : out STD_LOGIC
);
end DBUFCTL;
46,91 → 43,31
signal memswitchwr_reg : STD_LOGIC;
signal memswitchrd_reg : STD_LOGIC;
signal mem1_full_reg : STD_LOGIC;
signal mem2_full_reg : STD_LOGIC;
signal mem1_lock_reg : STD_LOGIC;
signal mem2_lock_reg : STD_LOGIC;
begin
 
dataready <= '1' when
((mem1_lock_reg = '0' and mem1_full_reg = '1') or
(mem2_lock_reg = '0' and mem2_full_reg = '1')) else '0';
 
memswitchwr <= memswitchwr_reg;
memswitchrd <= memswitchrd_reg;
memswitchrd_reg <= rmemsel;
 
MEM_SWITCH : process(rst,clk)
begin
if rst = '1' then
memswitchwr_reg <= '0'; -- initially mem 1 is selected
memswitchrd_reg <= '0'; -- initially mem 1 is selected
mem1_full_reg <= '0';
mem2_full_reg <= '0';
mem1_lock_reg <= '0';
mem2_lock_reg <= '0';
reqrdfail <= '0';
reqwrfail <= '0';
dataready <= '0';
elsif clk = '1' and clk'event then
-- write request by DCT1D
if requestwr = '1' then
-- if mem1 is free
if mem1_lock_reg = '0' and mem1_full_reg = '0' then
memswitchwr_reg <= '0';
mem1_lock_reg <= '1';
reqwrfail <= '0';
-- if mem2 is free
elsif mem2_lock_reg = '0' and mem2_full_reg = '0' then
memswitchwr_reg <= '1';
mem2_lock_reg <= '1';
reqwrfail <= '0';
else
reqwrfail <= '1';
end if;
end if;
 
memswitchwr_reg <= wmemsel;
-- write request released by DCT1D
if releasewr = '1' then
-- if mem1 locked by DCT1D release it
if mem1_lock_reg = '1' and memswitchwr_reg = '0' then
mem1_lock_reg <= '0';
mem1_full_reg <= '1';
-- if mem2 locked by DCT1D release it
elsif mem2_lock_reg = '1' and memswitchwr_reg = '1' then
mem2_lock_reg <= '0';
mem2_full_reg <= '1';
end if;
if wmemsel /= memswitchwr_reg then
dataready <= '1';
end if;
-- read request by DCT2D
if requestrd = '1' then
if mem1_lock_reg = '0' and mem1_full_reg = '1' then
memswitchrd_reg <= '0';
mem1_lock_reg <= '1';
reqrdfail <= '0';
elsif mem2_lock_reg = '0' and mem2_full_reg = '1' then
memswitchrd_reg <= '1';
mem2_lock_reg <= '1';
reqrdfail <= '0';
else
reqrdfail <= '1';
end if;
end if;
-- read request released by DCT2D
if releaserd = '1' then
-- if mem1 locked by DCT2D release it
if mem1_lock_reg = '1' and memswitchrd_reg = '0' then
mem1_lock_reg <= '0';
mem1_full_reg <= '0';
-- if mem2 locked by DCT2D release it
elsif mem2_lock_reg = '1' and memswitchrd_reg = '1' then
mem2_lock_reg <= '0';
mem2_full_reg <= '0';
end if;
if datareadyack = '1' then
dataready <= '0';
end if;
end if;
end process;
/trunk/source/MDCT.VHD
36,7 → 36,7
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
 
ready : out STD_LOGIC; -- ready for input data
fiforead : out STD_LOGIC; -- ready for input data
odv : out STD_LOGIC;
dcto : out std_logic_vector(COE_W-1 downto 0);
-- debug
53,8 → 53,8
------------------------------
component DCT1D
port(
clk : in STD_LOGIC;
rst : in std_logic;
clk : in STD_LOGIC;
rst : in std_logic;
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
romedatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
75,9 → 75,7
romodatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
reqwrfail : in STD_LOGIC;
 
ready : out STD_LOGIC; -- read from FIFO
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
101,8 → 99,7
ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
ramwe : out STD_LOGIC;
requestwr : out STD_LOGIC;
releasewr : out STD_LOGIC
wmemsel : out STD_LOGIC
);
end component;
 
136,7 → 133,6
romodatao9 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao10 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
ramdatao : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
reqrdfail : in STD_LOGIC;
dataready : in STD_LOGIC;
odv : out STD_LOGIC;
164,8 → 160,8
romoaddro9 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro10 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
ramraddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
requestrd : out STD_LOGIC;
releaserd : out STD_LOGIC
rmemsel : out STD_LOGIC;
datareadyack : out STD_LOGIC
);
end component;
 
215,16 → 211,13
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
requestwr : in STD_LOGIC;
requestrd : in STD_LOGIC;
releasewr : in STD_LOGIC;
releaserd : in STD_LOGIC;
wmemsel : in STD_LOGIC;
rmemsel : in STD_LOGIC;
datareadyack : in STD_LOGIC;
memswitchwr : out STD_LOGIC;
memswitchrd : out STD_LOGIC;
reqwrfail : out STD_LOGIC;
reqrdfail : out STD_LOGIC;
dataready : out STD_LOGIC
dataready : out STD_LOGIC
);
end component;
 
324,13 → 317,10
signal ramwe2_s : STD_LOGIC;
signal memswitchrd_s : STD_LOGIC;
signal memswitchwr_s : STD_LOGIC;
signal reqwrfail_s : STD_LOGIC;
signal reqrdfail_s : STD_LOGIC;
signal wmemsel_s : STD_LOGIC;
signal rmemsel_s : STD_LOGIC;
signal dataready_s : STD_LOGIC;
signal requestwr_s : STD_LOGIC;
signal releasewr_s : STD_LOGIC;
signal requestrd_s : STD_LOGIC;
signal releaserd_s : STD_LOGIC;
signal datareadyack_s : STD_LOGIC;
 
begin
 
360,10 → 350,8
romodatao5 => romodatao5_s,
romodatao6 => romodatao6_s,
romodatao7 => romodatao7_s,
romodatao8 => romodatao8_s,
reqwrfail => reqwrfail_s,
 
ready => ready,
romodatao8 => romodatao8_s,
odv => odv1,
dcto => dcto1,
romeaddro0 => romeaddro0_s,
387,8 → 375,7
ramwaddro => ramwaddro_s,
ramdatai => ramdatai_s,
ramwe => ramwe_s,
requestwr => requestwr_s,
releasewr => releasewr_s
wmemsel => wmemsel_s
);
 
------------------------------
421,7 → 408,6
romodatao9 => romo2datao9_s,
romodatao10 => romo2datao10_s,
ramdatao => ramdatao_s,
reqrdfail => reqrdfail_s,
dataready => dataready_s,
odv => odv,
449,8 → 435,8
romoaddro9 => romo2addro9_s,
romoaddro10 => romo2addro10_s,
ramraddro => ramraddro_s,
requestrd => requestrd_s,
releaserd => releaserd_s
rmemsel => rmemsel_s,
datareadyack => datareadyack_s
);
 
------------------------------
493,15 → 479,12
port map(
clk => clk,
rst => rst,
requestwr => requestwr_s,
requestrd => requestrd_s,
releasewr => releasewr_s,
releaserd => releaserd_s,
wmemsel => wmemsel_s,
rmemsel => rmemsel_s,
datareadyack => datareadyack_s,
memswitchwr => memswitchwr_s,
memswitchrd => memswitchrd_s,
reqwrfail => reqwrfail_s,
reqrdfail => reqrdfail_s,
dataready => dataready_s
);
 
/trunk/source/xilinx/RAM.VHD
0,0 → 1,77
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : RAM --
-- Design : MDCT --
-- Author : Michal Krepa -- -- --
-- --
--------------------------------------------------------------------------------
--
-- File : RAM.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : RAM memory simulation model
--
--------------------------------------------------------------------------------
 
-- 5:3 row select
-- 2:0 col select
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library WORK;
use WORK.MDCT_PKG.all;
entity RAM is
port (
da : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
db : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
waddra : in STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
waddrb : in STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
raddr : in STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
wea : in STD_LOGIC;
web : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0)
);
end RAM;
 
architecture RTL of RAM is
 
component ram_xil
port (
addra: IN std_logic_VECTOR(5 downto 0);
addrb: IN std_logic_VECTOR(5 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(9 downto 0);
dinb: IN std_logic_VECTOR(9 downto 0);
douta: OUT std_logic_VECTOR(9 downto 0);
wea: IN std_logic;
web: IN std_logic);
end component;
 
begin
U1 : ram_xil
port map (
addra => waddra,
addrb => waddrb,
clka => clk,
clkb => clk,
dina => da,
dinb => db,
douta => q,
wea => wea,
web => web);
end RTL;
/trunk/source/xilinx/ram_xil.edn
0,0 → 1,627
(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2006 4 21 22 42 33)
(author "Xilinx, Inc.")
(program "Xilinx CORE Generator" (version "Xilinx CORE Generator 6.3i"))))
(comment "
This file is owned and controlled by Xilinx and must be used
solely for design, simulation, implementation and creation of
design files limited to Xilinx devices or technologies. Use
with non-Xilinx devices or technologies is expressly prohibited
and immediately terminates your license.
XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'
SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE.
Xilinx products are not intended for use in life support
appliances, devices, or systems. Use in such applications are
expressly prohibited.
(c) Copyright 1995-2004 Xilinx, Inc.
All rights reserved.
")
(comment "Core parameters: ")
(comment "c_reg_inputsb = 0 ")
(comment "c_reg_inputsa = 0 ")
(comment "c_has_ndb = 0 ")
(comment "c_has_nda = 0 ")
(comment "c_ytop_addr = 1024 ")
(comment "c_has_rfdb = 0 ")
(comment "c_has_rfda = 0 ")
(comment "c_ywea_is_high = 1 ")
(comment "c_yena_is_high = 1 ")
(comment "InstanceName = ram_xil ")
(comment "c_yclka_is_rising = 1 ")
(comment "c_yhierarchy = hierarchy1 ")
(comment "c_family = spartan3 ")
(comment "c_ysinita_is_high = 1 ")
(comment "c_ybottom_addr = 0 ")
(comment "c_width_b = 10 ")
(comment "c_width_a = 10 ")
(comment "c_sinita_value = 0 ")
(comment "c_sinitb_value = 0 ")
(comment "c_limit_data_pitch = 18 ")
(comment "c_write_modeb = 2 ")
(comment "c_write_modea = 2 ")
(comment "c_has_rdyb = 0 ")
(comment "c_yuse_single_primitive = 0 ")
(comment "c_has_rdya = 0 ")
(comment "c_addra_width = 6 ")
(comment "c_addrb_width = 6 ")
(comment "c_has_limit_data_pitch = 0 ")
(comment "c_default_data = 0 ")
(comment "c_pipe_stages_b = 0 ")
(comment "c_yweb_is_high = 1 ")
(comment "c_yenb_is_high = 1 ")
(comment "c_pipe_stages_a = 0 ")
(comment "c_yclkb_is_rising = 1 ")
(comment "c_yydisable_warnings = 1 ")
(comment "c_enable_rlocs = 0 ")
(comment "c_ysinitb_is_high = 1 ")
(comment "c_has_default_data = 1 ")
(comment "c_has_web = 1 ")
(comment "c_has_sinitb = 0 ")
(comment "c_has_wea = 1 ")
(comment "c_has_sinita = 0 ")
(comment "c_has_dinb = 1 ")
(comment "c_has_dina = 1 ")
(comment "c_ymake_bmm = 0 ")
(comment "c_has_enb = 0 ")
(comment "c_has_ena = 0 ")
(comment "c_depth_b = 64 ")
(comment "c_mem_init_file = mif_file_16_1 ")
(comment "c_depth_a = 64 ")
(comment "c_has_doutb = 0 ")
(comment "c_has_douta = 1 ")
(comment "c_yprimitive_type = 16kx1 ")
(external xilinxun (edifLevel 0)
(technology (numberDefinition))
(cell VCC (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port P (direction OUTPUT))
)
)
)
(cell GND (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port G (direction OUTPUT))
)
)
)
(cell RAMB16_S18_S18 (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port WEA (direction INPUT))
(port ENA (direction INPUT))
(port SSRA (direction INPUT))
(port CLKA (direction INPUT))
(port (rename DIA_0_ "DIA<0>") (direction INPUT))
(port (rename DIA_1_ "DIA<1>") (direction INPUT))
(port (rename DIA_2_ "DIA<2>") (direction INPUT))
(port (rename DIA_3_ "DIA<3>") (direction INPUT))
(port (rename DIA_4_ "DIA<4>") (direction INPUT))
(port (rename DIA_5_ "DIA<5>") (direction INPUT))
(port (rename DIA_6_ "DIA<6>") (direction INPUT))
(port (rename DIA_7_ "DIA<7>") (direction INPUT))
(port (rename DIA_8_ "DIA<8>") (direction INPUT))
(port (rename DIA_9_ "DIA<9>") (direction INPUT))
(port (rename DIA_10_ "DIA<10>") (direction INPUT))
(port (rename DIA_11_ "DIA<11>") (direction INPUT))
(port (rename DIA_12_ "DIA<12>") (direction INPUT))
(port (rename DIA_13_ "DIA<13>") (direction INPUT))
(port (rename DIA_14_ "DIA<14>") (direction INPUT))
(port (rename DIA_15_ "DIA<15>") (direction INPUT))
(port (rename DOA_0_ "DOA<0>") (direction OUTPUT))
(port (rename DOA_1_ "DOA<1>") (direction OUTPUT))
(port (rename DOA_2_ "DOA<2>") (direction OUTPUT))
(port (rename DOA_3_ "DOA<3>") (direction OUTPUT))
(port (rename DOA_4_ "DOA<4>") (direction OUTPUT))
(port (rename DOA_5_ "DOA<5>") (direction OUTPUT))
(port (rename DOA_6_ "DOA<6>") (direction OUTPUT))
(port (rename DOA_7_ "DOA<7>") (direction OUTPUT))
(port (rename DOA_8_ "DOA<8>") (direction OUTPUT))
(port (rename DOA_9_ "DOA<9>") (direction OUTPUT))
(port (rename DOA_10_ "DOA<10>") (direction OUTPUT))
(port (rename DOA_11_ "DOA<11>") (direction OUTPUT))
(port (rename DOA_12_ "DOA<12>") (direction OUTPUT))
(port (rename DOA_13_ "DOA<13>") (direction OUTPUT))
(port (rename DOA_14_ "DOA<14>") (direction OUTPUT))
(port (rename DOA_15_ "DOA<15>") (direction OUTPUT))
(port (rename ADDRA_0_ "ADDRA<0>") (direction INPUT))
(port (rename ADDRA_1_ "ADDRA<1>") (direction INPUT))
(port (rename ADDRA_2_ "ADDRA<2>") (direction INPUT))
(port (rename ADDRA_3_ "ADDRA<3>") (direction INPUT))
(port (rename ADDRA_4_ "ADDRA<4>") (direction INPUT))
(port (rename ADDRA_5_ "ADDRA<5>") (direction INPUT))
(port (rename ADDRA_6_ "ADDRA<6>") (direction INPUT))
(port (rename ADDRA_7_ "ADDRA<7>") (direction INPUT))
(port (rename ADDRA_8_ "ADDRA<8>") (direction INPUT))
(port (rename ADDRA_9_ "ADDRA<9>") (direction INPUT))
(port (rename DIPA_0_ "DIPA<0>") (direction INPUT))
(port (rename DIPA_1_ "DIPA<1>") (direction INPUT))
(port (rename DOPA_0_ "DOPA<0>") (direction OUTPUT))
(port (rename DOPA_1_ "DOPA<1>") (direction OUTPUT))
(port WEB (direction INPUT))
(port ENB (direction INPUT))
(port SSRB (direction INPUT))
(port CLKB (direction INPUT))
(port (rename DIB_0_ "DIB<0>") (direction INPUT))
(port (rename DIB_1_ "DIB<1>") (direction INPUT))
(port (rename DIB_2_ "DIB<2>") (direction INPUT))
(port (rename DIB_3_ "DIB<3>") (direction INPUT))
(port (rename DIB_4_ "DIB<4>") (direction INPUT))
(port (rename DIB_5_ "DIB<5>") (direction INPUT))
(port (rename DIB_6_ "DIB<6>") (direction INPUT))
(port (rename DIB_7_ "DIB<7>") (direction INPUT))
(port (rename DIB_8_ "DIB<8>") (direction INPUT))
(port (rename DIB_9_ "DIB<9>") (direction INPUT))
(port (rename DIB_10_ "DIB<10>") (direction INPUT))
(port (rename DIB_11_ "DIB<11>") (direction INPUT))
(port (rename DIB_12_ "DIB<12>") (direction INPUT))
(port (rename DIB_13_ "DIB<13>") (direction INPUT))
(port (rename DIB_14_ "DIB<14>") (direction INPUT))
(port (rename DIB_15_ "DIB<15>") (direction INPUT))
(port (rename DOB_0_ "DOB<0>") (direction OUTPUT))
(port (rename DOB_1_ "DOB<1>") (direction OUTPUT))
(port (rename DOB_2_ "DOB<2>") (direction OUTPUT))
(port (rename DOB_3_ "DOB<3>") (direction OUTPUT))
(port (rename DOB_4_ "DOB<4>") (direction OUTPUT))
(port (rename DOB_5_ "DOB<5>") (direction OUTPUT))
(port (rename DOB_6_ "DOB<6>") (direction OUTPUT))
(port (rename DOB_7_ "DOB<7>") (direction OUTPUT))
(port (rename DOB_8_ "DOB<8>") (direction OUTPUT))
(port (rename DOB_9_ "DOB<9>") (direction OUTPUT))
(port (rename DOB_10_ "DOB<10>") (direction OUTPUT))
(port (rename DOB_11_ "DOB<11>") (direction OUTPUT))
(port (rename DOB_12_ "DOB<12>") (direction OUTPUT))
(port (rename DOB_13_ "DOB<13>") (direction OUTPUT))
(port (rename DOB_14_ "DOB<14>") (direction OUTPUT))
(port (rename DOB_15_ "DOB<15>") (direction OUTPUT))
(port (rename ADDRB_0_ "ADDRB<0>") (direction INPUT))
(port (rename ADDRB_1_ "ADDRB<1>") (direction INPUT))
(port (rename ADDRB_2_ "ADDRB<2>") (direction INPUT))
(port (rename ADDRB_3_ "ADDRB<3>") (direction INPUT))
(port (rename ADDRB_4_ "ADDRB<4>") (direction INPUT))
(port (rename ADDRB_5_ "ADDRB<5>") (direction INPUT))
(port (rename ADDRB_6_ "ADDRB<6>") (direction INPUT))
(port (rename ADDRB_7_ "ADDRB<7>") (direction INPUT))
(port (rename ADDRB_8_ "ADDRB<8>") (direction INPUT))
(port (rename ADDRB_9_ "ADDRB<9>") (direction INPUT))
(port (rename DIPB_0_ "DIPB<0>") (direction INPUT))
(port (rename DIPB_1_ "DIPB<1>") (direction INPUT))
(port (rename DOPB_0_ "DOPB<0>") (direction OUTPUT))
(port (rename DOPB_1_ "DOPB<1>") (direction OUTPUT))
)
)
)
)
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell ram_xil
(cellType GENERIC) (view view_1 (viewType NETLIST)
(interface
(port ( array ( rename addra "addra<5:0>") 6 ) (direction INPUT))
(port ( array ( rename addrb "addrb<5:0>") 6 ) (direction INPUT))
(port ( rename clka "clka") (direction INPUT))
(port ( rename clkb "clkb") (direction INPUT))
(port ( array ( rename dina "dina<9:0>") 10 ) (direction INPUT))
(port ( array ( rename dinb "dinb<9:0>") 10 ) (direction INPUT))
(port ( rename wea "wea") (direction INPUT))
(port ( rename web "web") (direction INPUT))
(port ( array ( rename douta "douta<9:0>") 10 ) (direction OUTPUT))
)
(contents
(instance VCC (viewRef view_1 (cellRef VCC (libraryRef xilinxun))))
(instance GND (viewRef view_1 (cellRef GND (libraryRef xilinxun))))
(instance B6
(viewRef view_1 (cellRef RAMB16_S18_S18 (libraryRef xilinxun)))
(property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_01 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_02 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_03 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_04 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_05 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_06 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_07 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_08 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_09 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_0A (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_0B (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_0C (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_0D (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_0E (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_0F (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_10 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_11 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_12 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_13 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_14 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_15 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_16 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_17 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_18 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_19 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_1A (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_1B (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_1C (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_1D (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_1E (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_1F (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_20 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_21 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_22 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_23 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_24 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_25 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_26 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_27 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_28 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_29 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_2A (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_2B (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_2C (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_2D (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_2E (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_2F (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_30 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_31 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_32 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_33 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_34 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_35 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_36 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_37 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_38 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_39 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_3A (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_3B (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_3C (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_3D (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_3E (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INIT_3F (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INITP_00 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INITP_01 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INITP_02 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INITP_03 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INITP_04 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INITP_05 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INITP_06 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property INITP_07 (string "0000000000000000000000000000000000000000000000000000000000000000"))
(property WRITE_MODE_A (string "NO_CHANGE"))
(property INIT_A (string "00000"))
(property SRVAL_A (string "00000"))
(property WRITE_MODE_B (string "NO_CHANGE"))
(property INIT_B (string "00000"))
(property SRVAL_B (string "00000"))
)
(net N0
(joined
(portRef G (instanceRef GND))
(portRef SSRA (instanceRef B6))
(portRef SSRB (instanceRef B6))
(portRef ADDRA_6_ (instanceRef B6))
(portRef ADDRA_7_ (instanceRef B6))
(portRef ADDRA_8_ (instanceRef B6))
(portRef ADDRA_9_ (instanceRef B6))
(portRef DIA_10_ (instanceRef B6))
(portRef DIA_11_ (instanceRef B6))
(portRef DIA_12_ (instanceRef B6))
(portRef DIA_13_ (instanceRef B6))
(portRef DIA_14_ (instanceRef B6))
(portRef DIA_15_ (instanceRef B6))
(portRef DIPA_0_ (instanceRef B6))
(portRef DIPA_1_ (instanceRef B6))
(portRef ADDRB_6_ (instanceRef B6))
(portRef ADDRB_7_ (instanceRef B6))
(portRef ADDRB_8_ (instanceRef B6))
(portRef ADDRB_9_ (instanceRef B6))
(portRef DIB_10_ (instanceRef B6))
(portRef DIB_11_ (instanceRef B6))
(portRef DIB_12_ (instanceRef B6))
(portRef DIB_13_ (instanceRef B6))
(portRef DIB_14_ (instanceRef B6))
(portRef DIB_15_ (instanceRef B6))
(portRef DIPB_0_ (instanceRef B6))
(portRef DIPB_1_ (instanceRef B6))
)
)
(net N1
(joined
(portRef P (instanceRef VCC))
(portRef ENA (instanceRef B6))
(portRef ENB (instanceRef B6))
)
)
(net (rename N2 "addra<5>")
(joined
(portRef (member addra 0))
(portRef ADDRA_5_ (instanceRef B6))
)
)
(net (rename N3 "addra<4>")
(joined
(portRef (member addra 1))
(portRef ADDRA_4_ (instanceRef B6))
)
)
(net (rename N4 "addra<3>")
(joined
(portRef (member addra 2))
(portRef ADDRA_3_ (instanceRef B6))
)
)
(net (rename N5 "addra<2>")
(joined
(portRef (member addra 3))
(portRef ADDRA_2_ (instanceRef B6))
)
)
(net (rename N6 "addra<1>")
(joined
(portRef (member addra 4))
(portRef ADDRA_1_ (instanceRef B6))
)
)
(net (rename N7 "addra<0>")
(joined
(portRef (member addra 5))
(portRef ADDRA_0_ (instanceRef B6))
)
)
(net (rename N8 "addrb<5>")
(joined
(portRef (member addrb 0))
(portRef ADDRB_5_ (instanceRef B6))
)
)
(net (rename N9 "addrb<4>")
(joined
(portRef (member addrb 1))
(portRef ADDRB_4_ (instanceRef B6))
)
)
(net (rename N10 "addrb<3>")
(joined
(portRef (member addrb 2))
(portRef ADDRB_3_ (instanceRef B6))
)
)
(net (rename N11 "addrb<2>")
(joined
(portRef (member addrb 3))
(portRef ADDRB_2_ (instanceRef B6))
)
)
(net (rename N12 "addrb<1>")
(joined
(portRef (member addrb 4))
(portRef ADDRB_1_ (instanceRef B6))
)
)
(net (rename N13 "addrb<0>")
(joined
(portRef (member addrb 5))
(portRef ADDRB_0_ (instanceRef B6))
)
)
(net (rename N14 "clka")
(joined
(portRef clka)
(portRef CLKA (instanceRef B6))
)
)
(net (rename N15 "clkb")
(joined
(portRef clkb)
(portRef CLKB (instanceRef B6))
)
)
(net (rename N16 "dina<9>")
(joined
(portRef (member dina 0))
(portRef DIA_9_ (instanceRef B6))
)
)
(net (rename N17 "dina<8>")
(joined
(portRef (member dina 1))
(portRef DIA_8_ (instanceRef B6))
)
)
(net (rename N18 "dina<7>")
(joined
(portRef (member dina 2))
(portRef DIA_7_ (instanceRef B6))
)
)
(net (rename N19 "dina<6>")
(joined
(portRef (member dina 3))
(portRef DIA_6_ (instanceRef B6))
)
)
(net (rename N20 "dina<5>")
(joined
(portRef (member dina 4))
(portRef DIA_5_ (instanceRef B6))
)
)
(net (rename N21 "dina<4>")
(joined
(portRef (member dina 5))
(portRef DIA_4_ (instanceRef B6))
)
)
(net (rename N22 "dina<3>")
(joined
(portRef (member dina 6))
(portRef DIA_3_ (instanceRef B6))
)
)
(net (rename N23 "dina<2>")
(joined
(portRef (member dina 7))
(portRef DIA_2_ (instanceRef B6))
)
)
(net (rename N24 "dina<1>")
(joined
(portRef (member dina 8))
(portRef DIA_1_ (instanceRef B6))
)
)
(net (rename N25 "dina<0>")
(joined
(portRef (member dina 9))
(portRef DIA_0_ (instanceRef B6))
)
)
(net (rename N26 "dinb<9>")
(joined
(portRef (member dinb 0))
(portRef DIB_9_ (instanceRef B6))
)
)
(net (rename N27 "dinb<8>")
(joined
(portRef (member dinb 1))
(portRef DIB_8_ (instanceRef B6))
)
)
(net (rename N28 "dinb<7>")
(joined
(portRef (member dinb 2))
(portRef DIB_7_ (instanceRef B6))
)
)
(net (rename N29 "dinb<6>")
(joined
(portRef (member dinb 3))
(portRef DIB_6_ (instanceRef B6))
)
)
(net (rename N30 "dinb<5>")
(joined
(portRef (member dinb 4))
(portRef DIB_5_ (instanceRef B6))
)
)
(net (rename N31 "dinb<4>")
(joined
(portRef (member dinb 5))
(portRef DIB_4_ (instanceRef B6))
)
)
(net (rename N32 "dinb<3>")
(joined
(portRef (member dinb 6))
(portRef DIB_3_ (instanceRef B6))
)
)
(net (rename N33 "dinb<2>")
(joined
(portRef (member dinb 7))
(portRef DIB_2_ (instanceRef B6))
)
)
(net (rename N34 "dinb<1>")
(joined
(portRef (member dinb 8))
(portRef DIB_1_ (instanceRef B6))
)
)
(net (rename N35 "dinb<0>")
(joined
(portRef (member dinb 9))
(portRef DIB_0_ (instanceRef B6))
)
)
(net (rename N36 "douta<9>")
(joined
(portRef (member douta 0))
(portRef DOA_9_ (instanceRef B6))
)
)
(net (rename N37 "douta<8>")
(joined
(portRef (member douta 1))
(portRef DOA_8_ (instanceRef B6))
)
)
(net (rename N38 "douta<7>")
(joined
(portRef (member douta 2))
(portRef DOA_7_ (instanceRef B6))
)
)
(net (rename N39 "douta<6>")
(joined
(portRef (member douta 3))
(portRef DOA_6_ (instanceRef B6))
)
)
(net (rename N40 "douta<5>")
(joined
(portRef (member douta 4))
(portRef DOA_5_ (instanceRef B6))
)
)
(net (rename N41 "douta<4>")
(joined
(portRef (member douta 5))
(portRef DOA_4_ (instanceRef B6))
)
)
(net (rename N42 "douta<3>")
(joined
(portRef (member douta 6))
(portRef DOA_3_ (instanceRef B6))
)
)
(net (rename N43 "douta<2>")
(joined
(portRef (member douta 7))
(portRef DOA_2_ (instanceRef B6))
)
)
(net (rename N44 "douta<1>")
(joined
(portRef (member douta 8))
(portRef DOA_1_ (instanceRef B6))
)
)
(net (rename N45 "douta<0>")
(joined
(portRef (member douta 9))
(portRef DOA_0_ (instanceRef B6))
)
)
(net (rename N66 "wea")
(joined
(portRef wea)
(portRef WEA (instanceRef B6))
)
)
(net (rename N67 "web")
(joined
(portRef web)
(portRef WEB (instanceRef B6))
)
)
))))
(design ram_xil (cellRef ram_xil (libraryRef test_lib))
(property X_CORE_INFO (string "blkmemdp_v6_1, Coregen 6.3i"))
(property PART (string "XC3S5000-4-fg900") (owner "Xilinx")))
)
/trunk/source/xilinx/ram_xil.vhd
0,0 → 1,141
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2004 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file ram_xil.vhd when simulating
-- the core, ram_xil. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".
 
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
Library XilinxCoreLib;
ENTITY ram_xil IS
port (
addra: IN std_logic_VECTOR(5 downto 0);
addrb: IN std_logic_VECTOR(5 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(9 downto 0);
dinb: IN std_logic_VECTOR(9 downto 0);
douta: OUT std_logic_VECTOR(9 downto 0);
wea: IN std_logic;
web: IN std_logic);
END ram_xil;
 
ARCHITECTURE ram_xil_a OF ram_xil IS
 
component wrapped_ram_xil
port (
addra: IN std_logic_VECTOR(5 downto 0);
addrb: IN std_logic_VECTOR(5 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(9 downto 0);
dinb: IN std_logic_VECTOR(9 downto 0);
douta: OUT std_logic_VECTOR(9 downto 0);
wea: IN std_logic;
web: IN std_logic);
end component;
 
-- Configuration specification
for all : wrapped_ram_xil use entity XilinxCoreLib.blkmemdp_v6_1(behavioral)
generic map(
c_reg_inputsb => 0,
c_reg_inputsa => 0,
c_has_ndb => 0,
c_has_nda => 0,
c_ytop_addr => "1024",
c_has_rfdb => 0,
c_has_rfda => 0,
c_yena_is_high => 1,
c_ywea_is_high => 1,
c_yclka_is_rising => 1,
c_yhierarchy => "hierarchy1",
c_ysinita_is_high => 1,
c_ybottom_addr => "0",
c_width_b => 10,
c_width_a => 10,
c_sinita_value => "0",
c_sinitb_value => "0",
c_limit_data_pitch => 18,
c_write_modeb => 2,
c_write_modea => 2,
c_has_rdyb => 0,
c_has_rdya => 0,
c_yuse_single_primitive => 0,
c_addra_width => 6,
c_addrb_width => 6,
c_has_limit_data_pitch => 0,
c_default_data => "0",
c_pipe_stages_b => 0,
c_yweb_is_high => 1,
c_yenb_is_high => 1,
c_pipe_stages_a => 0,
c_yclkb_is_rising => 1,
c_yydisable_warnings => 1,
c_enable_rlocs => 0,
c_ysinitb_is_high => 1,
c_has_default_data => 1,
c_has_web => 1,
c_has_sinitb => 0,
c_has_wea => 1,
c_has_sinita => 0,
c_has_dinb => 1,
c_has_dina => 1,
c_ymake_bmm => 0,
c_has_enb => 0,
c_has_ena => 0,
c_depth_b => 64,
c_mem_init_file => "mif_file_16_1",
c_depth_a => 64,
c_has_doutb => 0,
c_has_douta => 1,
c_yprimitive_type => "16kx1");
BEGIN
 
U0 : wrapped_ram_xil
port map (
addra => addra,
addrb => addrb,
clka => clka,
clkb => clkb,
dina => dina,
dinb => dinb,
douta => douta,
wea => wea,
web => web);
END ram_xil_a;
 
-- synopsys translate_on
 
/trunk/mdct.mpf
225,7 → 225,7
UserTimeUnit = default
 
; Default run length
RunLength = 0 ps
RunLength = 1 ps
 
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
531,53 → 531,55
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 23
Project_Files_Count = 24
Project_File_0 = C:/elektronika/dct/MDCT/source/xilinx/RAM.VHD
Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 17 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 17 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_1 = C:/elektronika/dct/mdct/source/ROME.VHD
Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1144870599 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 8 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1144870599 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 93
Project_File_2 = C:/elektronika/dct/MDCT/source/DBUFCTL.VHD
Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SOURCE last_compile 1143785621 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 11 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SOURCE last_compile 1143785621 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_3 = C:/elektronika/dct/mdct/source/testbench/MDCT_TB.DO
Project_File_P_3 = vhdl_novitalcheck 0 file_type tcl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder MODELSIM last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order -1 cover_nosub 0 dont_compile 1 vhdl_use93 2002
Project_File_P_3 = vhdl_novitalcheck 0 file_type tcl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder MODELSIM last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order -1 dont_compile 1 cover_nosub 0 vhdl_use93 2002
Project_File_4 = C:/elektronika/dct/MDCT/source/xilinx/ROME.VHD
Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 13 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 13 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_5 = C:/elektronika/dct/mdct/source/testbench/RUNSIM.DO
Project_File_P_5 = vhdl_novitalcheck 0 file_type tcl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder MODELSIM last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order -1 cover_nosub 0 dont_compile 1 vhdl_use93 2002
Project_File_P_5 = vhdl_novitalcheck 0 file_type tcl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder MODELSIM last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order -1 dont_compile 1 cover_nosub 0 vhdl_use93 2002
Project_File_6 = C:/elektronika/dct/MDCT/source/testbench/COMPILE_TIMING.DO
Project_File_P_6 = vhdl_novitalcheck 0 file_type tcl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder MODELSIM last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order -1 cover_nosub 0 dont_compile 1 vhdl_use93 2002
Project_File_P_6 = vhdl_novitalcheck 0 file_type tcl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder MODELSIM last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order -1 dont_compile 1 cover_nosub 0 vhdl_use93 2002
Project_File_7 = C:/elektronika/dct/mdct/source/RAM.VHD
Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1143489389 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 3 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1143489389 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 93
Project_File_8 = C:/elektronika/dct/MDCT/source/DCT2D.VHD
Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SOURCE last_compile 1143972066 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 87
Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SOURCE last_compile 1143972066 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 87
Project_File_9 = C:/elektronika/dct/mdct/source/testbench/CLKGEN.VHD
Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143489388 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 4 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143489388 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 93
Project_File_10 = C:/elektronika/dct/MDCT/source/xilinx/romo_xil.vhd
Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 16 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 16 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_11 = C:/elektronika/dct/mdct/source/testbench/MDCT_TB.VHD
Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1144881653 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 6 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1144881653 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 93
Project_File_12 = C:/elektronika/dct/mdct/source/ROMO.VHD
Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1145568090 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 93
Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1145568090 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 9 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_13 = C:/elektronika/dct/MDCT/source/testbench/RUNSIM_TIMING.DO
Project_File_P_13 = vhdl_novitalcheck 0 file_type tcl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder MODELSIM last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order -1 cover_nosub 0 dont_compile 1 vhdl_use93 2002
Project_File_P_13 = vhdl_novitalcheck 0 file_type tcl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder MODELSIM last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order -1 dont_compile 1 cover_nosub 0 vhdl_use93 2002
Project_File_14 = C:/elektronika/dct/MDCT/synthesis/mdct_temp_2/MDCT_out.vhd
Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder PAR last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 12 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder PAR last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_15 = C:/elektronika/dct/mdct/source/testbench/MDCTTB_PKG.vhd
Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143976585 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143976585 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 93
Project_File_16 = C:/elektronika/dct/MDCT/source/xilinx/ram_xil.vhd
Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 18 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 18 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_17 = C:/elektronika/dct/mdct/source/DCT1D.vhd
Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1145135163 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1145135163 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 93
Project_File_18 = C:/elektronika/dct/mdct/source/MDCT.VHD
Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1143931873 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 0 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1143931873 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 93
Project_File_19 = C:/elektronika/dct/MDCT/source/xilinx/ROMO.VHD
Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 15 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_20 = C:/elektronika/dct/mdct/source/MDCT_PKG.vhd
Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1144447956 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_21 = C:/elektronika/dct/mdct/source/testbench/INPIMAGE.VHD
Project_File_P_21 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143979283 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_22 = C:/elektronika/dct/MDCT/source/xilinx/rome_xil.vhd
Project_File_P_22 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 14 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_20 = C:/elektronika/dct/MDCT/source/testbench/random1.vhd
Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder TESTBENCH last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 19 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_21 = C:/elektronika/dct/mdct/source/MDCT_PKG.vhd
Project_File_P_21 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1144447956 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 93
Project_File_22 = C:/elektronika/dct/mdct/source/testbench/INPIMAGE.VHD
Project_File_P_22 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143979283 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 93
Project_File_23 = C:/elektronika/dct/MDCT/source/xilinx/rome_xil.vhd
Project_File_P_23 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_Sim_Count = 0
Project_Folder_Count = 5
Project_Folder_0 = XILINX
617,6 → 619,6
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
EditorState = {tabbed horizontal 1} {C:/elektronika/dct/MDCT/source/MDCT.VHD 0 0} {C:/elektronika/dct/MDCT/source/DCT1D.vhd 0 0} {C:/elektronika/dct/MDCT/source/testbench/INPIMAGE.VHD 0 0} {C:/elektronika/dct/MDCT/source/DCT2D.VHD 0 1} {C:/elektronika/dct/MDCT/source/DBUFCTL.VHD 0 0}
EditorState = {tabbed horizontal 1} {C:/elektronika/dct/MDCT/source/testbench/INPIMAGE.VHD 0 0} {C:/elektronika/dct/MDCT/source/testbench/MDCTTB_PKG.vhd 0 1}
Project_Major_Version = 6
Project_Minor_Version = 1

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.