URL
https://opencores.org/ocsvn/memory_cores/memory_cores/trunk
Subversion Repositories memory_cores
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- This comparison shows the changes necessary to convert path
/
- from Rev 14 to Rev 15
- ↔ Reverse comparison
Rev 14 → Rev 15
/trunk/Mempkg.vhd
25,51 → 25,96
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------------------------------------------------------------------------------- |
-- Revisions : |
-- Revision Number : 1 |
-- Version : 0.1 |
-- Date : 29th Feb 2000 |
-- Modifier : Jamil Khatib (khatib@ieee.org) |
-- Desccription : Created |
-- Revision Number : 1 |
-- Version : 0.1 |
-- Date : 29th Feb 2000 |
-- Modifier : Jamil Khatib (khatib@ieee.org) |
-- Desccription : Created |
-- |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Revision Number : 2 |
-- Version : 0.2 |
-- Date : 29th Mar 2000 |
-- Modifier : Jamil Khatib (khatib@ieee.org) |
-- Desccription : Memory components are added. |
-- |
------------------------------------------------------------------------------- |
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library ieee; |
use ieee.std_logic_1164.all; |
library ieee; |
use ieee.std_logic_1164.all; |
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package mempkg is |
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constant ADD_WIDTH : integer := 8; -- Address width |
constant WIDTH : integer := 4; -- Data width |
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function slv_2_int ( |
SLV :std_logic_vector ) |
return integer; |
SLV : std_logic_vector ) |
return integer; |
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end mempkg; |
component dpmem2clk |
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generic ( |
ADD_WIDTH : integer := ADD_WIDTH; -- Address width |
WIDTH : integer := WIDTH; -- Word Width |
coretype : integer := 0); -- memory bulding block type |
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port ( |
Wclk : in std_logic; -- write clock |
Wen : in std_logic; -- Write Enable |
Wadd : in std_logic_vector(ADD_WIDTH -1 downto 0); -- Write Address |
Datain : in std_logic_vector(WIDTH -1 downto 0); -- Input Data |
Rclk : in std_logic; -- Read clock |
Ren : in std_logic; -- Read Enable |
Radd : in std_logic_vector(ADD_WIDTH -1 downto 0); -- Read Address |
Dataout : out std_logic_vector(WIDTH -1 downto 0)); -- Output data |
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end component; |
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component dpmem |
generic (ADD_WIDTH : integer := 4; |
WIDTH : integer := 8 ); |
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port (clk : in std_logic; |
reset : in std_logic; |
w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 ); |
r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 ); |
data_in : in std_logic_vector(WIDTH - 1 downto 0); |
data_out : out std_logic_vector(WIDTH - 1 downto 0 ); |
WR : in std_logic; |
RE : in std_logic); |
end component; |
end mempkg; |
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------------------------------------------------------------------------------- |
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package body mempkg is |
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------------------------------------------------------------------------------- |
function slv_2_int ( |
SLV : std_logic_vector) -- std_logic_vector to convert |
return integer IS |
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variable Result : integer := 0; -- conversion result |
SLV : std_logic_vector) -- std_logic_vector to convert |
return integer is |
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variable Result : integer := 0; -- conversion result |
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begin |
for i in SLV'RANGE loop |
Result := Result * 2; -- shift the variable to left |
for i in SLV'range loop |
Result := Result * 2; -- shift the variable to left |
case SLV(i) is |
when '1' | 'H' => Result := Result + 1 ; |
when '0' | 'L' => Result := Result + 0; |
when others => null; |
end case; |
end loop; |
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return Result; |
end; |
when '1' | 'H' => Result := Result + 1; |
when '0' | 'L' => Result := Result + 0; |
when others => null; |
end case; |
end loop; |
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return Result; |
end; |
------------------------------------------------------------------------------- |
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end mempkg; |
end mempkg; |
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------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |