URL
https://opencores.org/ocsvn/mini_aes/mini_aes/trunk
Subversion Repositories mini_aes
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 14 to Rev 15
- ↔ Reverse comparison
Rev 14 → Rev 15
/mini_aes/trunk/source/mini_aes.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Mini AES 128 top component |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/mini_aes/trunk/source/key_scheduler.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Key Scheduler calculation component |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/mini_aes/trunk/source/xtime.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Xtime manipulation used in AES operations. |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/mini_aes/trunk/source/io_interface.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : IO Interface used to implement 8bit communications. |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/mini_aes/trunk/source/mix_column.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/mini_aes/trunk/source/bram_block_a.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : First block RAM used in AES implementation. |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/mini_aes/trunk/source/bram_block_b.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Second block RAM used in AES implementation. |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/mini_aes/trunk/source/counter2bit.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Counter 2 bit (e.g. from 0 to 3) |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/mini_aes/trunk/source/folded_register.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Folded register manipulations for manipulating data. |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |