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URL https://opencores.org/ocsvn/pltbutils/pltbutils/trunk

Subversion Repositories pltbutils

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    from Rev 14 to Rev 15
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Rev 14 → Rev 15

/pltbutils/trunk/example/vhdl/tb_example.vhd
128,7 → 128,8
tc0 : entity work.tc_example
generic map (
G_WIDTH => G_WIDTH
G_WIDTH => G_WIDTH,
G_DISABLE_BUGS => G_DISABLE_BUGS
)
port map(
clk => clk,
/pltbutils/trunk/example/vhdl/tc_example.vhd
51,7 → 51,8
 
entity tc_example is
generic (
G_WIDTH : integer := 8
G_WIDTH : integer := 8;
G_DISABLE_BUGS : integer range 0 to 1 := 0
);
port (
clk : in std_logic;
/pltbutils/trunk/example/vhdl/tc1.vhd
83,7 → 83,7
check("Carry out", carry_out, '0', pltbutils_sc);
testname(3, "Simple carry in test", pltbutils_sc);
print(pltbutils_sc, "Bug here somewhere");
print(G_DISABLE_BUGS=0, pltbutils_sc, "Bug here somewhere");
carry_in <= '1';
x <= std_logic_vector(to_unsigned(1, x'length));
y <= std_logic_vector(to_unsigned(2, x'length));

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