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URL https://opencores.org/ocsvn/spi/spi/trunk

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 14 to Rev 15
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Rev 14 → Rev 15

/trunk/rtl/verilog/spi_top.v
117,36 → 117,20
`SPI_RX_0: wb_dat = rx[31:0];
`SPI_RX_1: wb_dat = rx[63:32];
`SPI_RX_2: wb_dat = rx[95:64];
`SPI_RX_3: wb_dat = rx[127:96];
`SPI_RX_3: wb_dat = {{128-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:96]};
`else
`ifdef SPI_MAX_CHAR_64
`SPI_RX_0: wb_dat = rx[31:0];
`SPI_RX_1: wb_dat = rx[63:32];
`SPI_RX_1: wb_dat = {{64-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:32]};
`SPI_RX_2: wb_dat = 32'b0;
`SPI_RX_3: wb_dat = 32'b0;
`else
`ifdef SPI_MAX_CHAR_32
`SPI_RX_0: wb_dat = rx;
`SPI_RX_0: wb_dat = {{32-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:0]};
`SPI_RX_1: wb_dat = 32'b0;
`SPI_RX_2: wb_dat = 32'b0;
`SPI_RX_3: wb_dat = 32'b0;
`else
`ifdef SPI_MAX_CHAR_16
`SPI_RX_0: wb_dat = {16'b0, rx};
`SPI_RX_1: wb_dat = 32'b0;
`SPI_RX_2: wb_dat = 32'b0;
`SPI_RX_3: wb_dat = 32'b0;
`else
`ifdef SPI_MAX_CHAR_8
`SPI_RX_0: wb_dat = {24'b0, rx};
`SPI_RX_1: wb_dat = 32'b0;
`SPI_RX_2: wb_dat = 32'b0;
`SPI_RX_3: wb_dat = 32'b0;
`endif
`endif
`endif
`endif
`endif
`SPI_CTRL: wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl};
`SPI_DEVIDE: wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider};
`SPI_SS: wb_dat = {{32-`SPI_SS_NB{1'b0}}, ss};
195,13 → 179,21
begin
`ifdef SPI_DIVIDER_LEN_8
if (wb_sel_i[3])
divider <= #Tp wb_dat_i[7:0];
divider <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:0];
`endif
`ifdef SPI_DIVIDER_LEN_16
if (wb_sel_i[3])
divider[7:0] <= #Tp wb_dat_i[7:0];
if (wb_sel_i[2])
divider[`SPI_DIVIDER_LEN-1:8] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:8];
`endif
`ifdef SPI_DIVIDER_LEN_24
if (wb_sel_i[3])
divider[7:0] <= #Tp wb_dat_i[7:0];
if (wb_sel_i[2])
divider[15:8] <= #Tp wb_dat_i[15:8];
if (wb_sel_i[1])
divider[`SPI_DIVIDER_LEN-1:16] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:16];
`endif
`ifdef SPI_DIVIDER_LEN_32
if (wb_sel_i[3])
211,7 → 203,7
if (wb_sel_i[1])
divider[23:16] <= #Tp wb_dat_i[23:16];
if (wb_sel_i[0])
divider[31:24] <= #Tp wb_dat_i[31:24];
divider[`SPI_DIVIDER_LEN-1:24] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:24];
`endif
end
end
249,13 → 241,21
begin
`ifdef SPI_SS_NB_8
if (wb_sel_i[3])
ss <= #Tp wb_dat_i[7:0];
ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0];
`endif
`ifdef SPI_SS_NB_16
if (wb_sel_i[3])
ss[7:0] <= #Tp wb_dat_i[7:0];
if (wb_sel_i[2])
ss[`SPI_SS_NB-1:8] <= #Tp wb_dat_i[`SPI_SS_NB-1:8];
`endif
`ifdef SPI_SS_NB_24
if (wb_sel_i[3])
ss[7:0] <= #Tp wb_dat_i[7:0];
if (wb_sel_i[2])
ss[15:8] <= #Tp wb_dat_i[15:8];
if (wb_sel_i[1])
ss[`SPI_SS_NB-1:16] <= #Tp wb_dat_i[`SPI_SS_NB-1:16];
`endif
`ifdef SPI_SS_NB_32
if (wb_sel_i[3])
265,7 → 265,7
if (wb_sel_i[1])
ss[23:16] <= #Tp wb_dat_i[23:16];
if (wb_sel_i[0])
ss[31:24] <= #Tp wb_dat_i[31:24];
ss[`SPI_SS_NB-1:24] <= #Tp wb_dat_i[`SPI_SS_NB-1:24];
`endif
end
end
285,20 → 285,3
.s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o));
endmodule
/trunk/rtl/verilog/spi_defines.v
41,28 → 41,84
//
// Number of bits used for devider register. If used in system with
// low frequency of system clock this can be reduced.
// Default is 16.
// Use SPI_DIVIDER_LEN for fine tuning theexact number.
//
//`define SPI_DIVIDER_LEN_8
`define SPI_DIVIDER_LEN_16
//`define SPI_DIVIDER_LEN_24
//`define SPI_DIVIDER_LEN_32
 
`ifdef SPI_DIVIDER_LEN_8
`define SPI_DIVIDER_LEN 8 // Can be set from 1 to 8
`endif
`ifdef SPI_DIVIDER_LEN_16
`define SPI_DIVIDER_LEN 16 // Can be set from 9 to 16
`endif
`ifdef SPI_DIVIDER_LEN_24
`define SPI_DIVIDER_LEN 24 // Can be set from 17 to 24
`endif
`ifdef SPI_DIVIDER_LEN_32
`define SPI_DIVIDER_LEN 32 // Can be set from 25 to 32
`endif
 
//
// Maximum nuber of bits that can be send/received at once.
// Use SPI_MAX_CHAR for fine tuning theexact number.
//
`define SPI_MAX_CHAR_128
//`define SPI_MAX_CHAR_64
//`define SPI_MAX_CHAR_32
//`define SPI_MAX_CHAR_24
//`define SPI_MAX_CHAR_16
//`define SPI_MAX_CHAR_8
 
`ifdef SPI_MAX_CHAR_128
`define SPI_MAX_CHAR 128 // Can be set from 97 to 128
`define SPI_CHAR_LEN_BITS 7
`endif
`ifdef SPI_MAX_CHAR_64
`define SPI_MAX_CHAR 64 // Can be set from 33 to 64
`define SPI_CHAR_LEN_BITS 6
`endif
`ifdef SPI_MAX_CHAR_32
`define SPI_MAX_CHAR 32 // Can be set from 25 to 32
`define SPI_CHAR_LEN_BITS 5
`endif
`ifdef SPI_MAX_CHAR_24
`define SPI_MAX_CHAR 24 // Can be set from 17 to 24
`define SPI_CHAR_LEN_BITS 5
`endif
`ifdef SPI_MAX_CHAR_16
`define SPI_MAX_CHAR 16 // Can be set from 9 to 16
`define SPI_CHAR_LEN_BITS 4
`endif
`ifdef SPI_MAX_CHAR_8
`define SPI_MAX_CHAR 8 // Can be set from 1 to 8
`define SPI_CHAR_LEN_BITS 3
`endif
 
//
// Number of device select signals.
// Number of device select signals. Use SPI_SS_NB for fine tuning the
// exact number.
//
`define SPI_SS_NB_8
//`define SPI_SS_NB_16
//`define SPI_SS_NB_24
//`define SPI_SS_NB_32
 
`ifdef SPI_SS_NB_8
`define SPI_SS_NB 8 // Can be set from 1 to 8
`endif
`ifdef SPI_SS_NB_16
`define SPI_SS_NB 16 // Can be set from 9 to 16
`endif
`ifdef SPI_SS_NB_24
`define SPI_SS_NB 24 // Can be set from 17 to 24
`endif
`ifdef SPI_SS_NB_32
`define SPI_SS_NB 32 // Can be set from 25 to 32
`endif
 
//
// Bits of WISHBONE address used for partial decoding of SPI registers.
//
99,46 → 155,3
`define SPI_CTRL_RX_NEGEDGE 1
`define SPI_CTRL_GO 0
 
 
`ifdef SPI_DIVIDER_LEN_8
`define SPI_DIVIDER_LEN 8
`endif
`ifdef SPI_DIVIDER_LEN_16
`define SPI_DIVIDER_LEN 16
`endif
`ifdef SPI_DIVIDER_LEN_32
`define SPI_DIVIDER_LEN 32
`endif
 
`ifdef SPI_MAX_CHAR_128
`define SPI_MAX_CHAR 128
`define SPI_CHAR_LEN_BITS 7
`endif
`ifdef SPI_MAX_CHAR_64
`define SPI_MAX_CHAR 64
`define SPI_CHAR_LEN_BITS 6
`endif
`ifdef SPI_MAX_CHAR_32
`define SPI_MAX_CHAR 32
`define SPI_CHAR_LEN_BITS 5
`endif
`ifdef SPI_MAX_CHAR_16
`define SPI_MAX_CHAR 16
`define SPI_CHAR_LEN_BITS 4
`endif
`ifdef SPI_MAX_CHAR_8
`define SPI_MAX_CHAR 8
`define SPI_CHAR_LEN_BITS 3
`endif
 
`ifdef SPI_SS_NB_8
`define SPI_SS_NB 8
`endif
`ifdef SPI_SS_NB_16
`define SPI_SS_NB 16
`endif
`ifdef SPI_SS_NB_32
`define SPI_SS_NB 32
`endif
 
 
/trunk/rtl/verilog/spi_shift.v
208,7 → 208,15
if (byte_sel[3])
data[7:0] <= #Tp p_in[7:0];
if (byte_sel[2])
data[`SPI_MAX_CHAR-1:8] <= #Tp p_in[`SPI_MAX_CHAR-1:8];
`endif
`ifdef `SPI_MAX_CHAR_24
if (byte_sel[3])
data[7:0] <= #Tp p_in[7:0];
if (byte_sel[2])
data[15:8] <= #Tp p_in[15:8];
if (byte_sel[1])
data[`SPI_MAX_CHAR-1:16] <= #Tp p_in[`SPI_MAX_CHAR-1:16];
`endif
`ifdef `SPI_MAX_CHAR_32
if (byte_sel[3])
218,9 → 226,9
if (byte_sel[1])
data[23:16] <= #Tp p_in[23:16];
if (byte_sel[0])
data[31:24] <= #Tp p_in[31:24];
data[`SPI_MAX_CHAR-1:24] <= #Tp p_in[`SPI_MAX_CHAR-1:24];
`endif
end
`endif
`endif
`endif
else

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