URL
https://opencores.org/ocsvn/uart16750/uart16750/trunk
Subversion Repositories uart16750
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 14 to Rev 15
- ↔ Reverse comparison
Rev 14 → Rev 15
/trunk/bench/vhdl/uart_transactor.vhd
22,8 → 22,6
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LIBRARY IEEE; |
USE IEEE.std_logic_1164.all; |
USE IEEE.std_logic_arith.all; |
USE IEEE.std_logic_unsigned.all; |
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use std.textio.all; |
use work.uart_package.all; |
/trunk/rtl/vhdl/uart_16750.vhd
3,12 → 3,13
-- |
-- Author: Sebastian Witt |
-- Date: 29.01.2008 |
-- Version: 1.3 |
-- Version: 1.4 |
-- |
-- History: 1.0 - Initial version |
-- 1.1 - THR empty interrupt register connected to RST |
-- 1.2 - Registered outputs |
-- 1.3 - Automatic flow control |
-- 1.4 - De-assert IIR FIFO64 when FIFO is disabled |
-- |
-- |
-- This code is free software; you can redistribute it and/or |
403,10 → 404,10
UART_IS_RI: slib_input_sync port map (CLK, RST, RIN, iRINs); |
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-- Input filter for UART control signals |
UART_IF_CTS: slib_input_filter generic map (SIZE => 4) port map (CLK, RST, iBaudtick2x, iCTSNs, iCTSn); |
UART_IF_DSR: slib_input_filter generic map (SIZE => 4) port map (CLK, RST, iBaudtick2x, iDSRNs, iDSRn); |
UART_IF_DCD: slib_input_filter generic map (SIZE => 4) port map (CLK, RST, iBaudtick2x, iDCDNs, iDCDn); |
UART_IF_RI: slib_input_filter generic map (SIZE => 4) port map (CLK, RST, iBaudtick2x, iRINs, iRIn); |
UART_IF_CTS: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iCTSNs, iCTSn); |
UART_IF_DSR: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iDSRNs, iDSRn); |
UART_IF_DCD: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iDCDNs, iDCDn); |
UART_IF_RI: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iRINs, iRIn); |
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-- Sync. input synchronization |
UART_SIS: process (CLK, RST) |
491,7 → 492,7
iIIR_ID2 <= iIIR(3); |
iIIR_FIFO64 <= iIIR(5); |
iIIR(4) <= '0'; |
iIIR(5) <= iFCR_FIFO64E; |
iIIR(5) <= iFCR_FIFO64E when iFCR_FIFOEnable = '1' else '0'; |
iIIR(6) <= iFCR_FIFOEnable; |
iIIR(7) <= iFCR_FIFOEnable; |
|
719,7 → 720,7
iMSR_dDSR <= '0'; |
end if; |
-- Trailing edge RI |
if (iRInRE = '1') then |
if (iRInFE = '1') then |
iMSR_TERI <= '1'; |
elsif (iMSRRead = '1') then |
iMSR_TERI <= '0'; |
/trunk/doc/README
1,5 → 1,5
========================================== |
UART16750 1.0 (C) 2008-2009 Sebastian Witt |
UART16750 (C) 2008-2009 Sebastian Witt |
========================================== |
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Description: |
18,12 → 18,13
- 16/64 byte FIFO mode |
- Receiver FIFO trigger levels 1/4/8/14/16/32/56 |
- Control lines RTS/CTS/DTR/DSR/DCD/RI/OUT1/OUT2 |
- Automatic flow control with RTS/CTS |
- All interrupts sources/modes |
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Todo: |
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- Automatic flow control |
- Variable character time-out counter |
- DMA control |
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Tests: |
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53,3 → 54,22
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The top-word is always available at the output (no read-request/delay). |
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Resource usage: |
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* Altera Cyclone II |
o 440 LE |
o 1216 memory bits |
o Frequency: 130 MHz |
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* Xilinx Spartan 3E |
o 378 Slices |
o 1 RAMB |
o Frequency: 100 MHz |
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Simulation: |
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It's possible to simulate and test the design with GHDL [1]. |
A Makefile is available for starting the simulation. The testbench |
creates a log file (uart_log.txt). |
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[1] http://ghdl.free.fr |