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Rev 14 → Rev 15

/xilinx_virtex_fp_library/trunk/SinglePathFPAdderMappedConversions/d_ff.v
0,0 → 1,37
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:39:58 02/04/2013
// Design Name:
// Module Name: d_ff
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 / File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
 
module d_ff (clk, rst, d, q);
parameter SIZE = 24;
input clk;
input rst;
input [SIZE-1 : 0] d;
output reg [SIZE-1 : 0] q;
always
@(posedge clk, posedge rst)
begin
if (rst)
q <= {SIZE{1'b0}};
else
q <= d;
end
endmodule
/xilinx_virtex_fp_library/trunk/SinglePathFPAdderMappedConversions/effective_op.v
0,0 → 1,40
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:41:11 11/04/2013
// Design Name:
// Module Name: effective_op
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module effective_op( input a_sign,
input b_sign,
input sub,
output reg eff_op);
always
@(*)
begin
case ({sub,a_sign, b_sign})
3'b000: eff_op = 0;
3'b001: eff_op = 1;
3'b010: eff_op = 1;
3'b011: eff_op = 0;
3'b100: eff_op = 1;
3'b101: eff_op = 0;
3'b110: eff_op = 0;
3'b111: eff_op = 1;
endcase
end
endmodule
/xilinx_virtex_fp_library/trunk/SinglePathFPAdderMappedConversions/special_cases.v
0,0 → 1,57
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:56:11 10/07/2013
// Design Name:
// Module Name: special_cases_mul_acc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module special_cases #( parameter size_exception_field = 2'd2,
parameter [size_exception_field - 1 : 0] zero = 0, //00
parameter [size_exception_field - 1 : 0] normal_number= 1, //01
parameter [size_exception_field - 1 : 0] infinity = 2, //10
parameter [size_exception_field - 1 : 0] NaN = 3) //11
( input [size_exception_field - 1 : 0] sp_case_a_number,
input [size_exception_field - 1 : 0] sp_case_b_number,
output reg [size_exception_field - 1 : 0] sp_case_result_o);
always
@(*)
begin
case ({sp_case_a_number, sp_case_b_number})
{zero, zero}: sp_case_result_o = zero;
{zero, normal_number}: sp_case_result_o = normal_number;
{zero, infinity}: sp_case_result_o = infinity;
{zero, NaN}: sp_case_result_o = NaN;
{normal_number,zero}: sp_case_result_o = normal_number;
{normal_number,normal_number}: sp_case_result_o = normal_number;
{normal_number,infinity}: sp_case_result_o = infinity;
{normal_number,NaN}: sp_case_result_o = NaN;
{infinity, zero}: sp_case_result_o = infinity;
{infinity, normal_number}: sp_case_result_o = infinity;
{infinity, infinity}: sp_case_result_o = infinity;
{infinity, NaN}: sp_case_result_o = NaN;
{NaN, zero}: sp_case_result_o = NaN;
{NaN, normal_number}: sp_case_result_o = NaN;
{NaN, infinity}: sp_case_result_o = NaN;
{NaN, NaN}: sp_case_result_o = NaN;
default: sp_case_result_o = zero;
endcase
end
endmodule
/xilinx_virtex_fp_library/trunk/SinglePathFPAdderMappedConversions/SinglePathAdderConversion.v
0,0 → 1,224
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:09:49 11/04/2013
// Design Name:
// Module Name: SinglePathAdderConversion
// Project Name:
// Target Devices:
// Tool versions:
 
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SinglePathAdderConversion #( parameter size_mantissa = 24, //calculate the size containing the hiden bit 1.M
parameter size_exponent = 8,
parameter size_exception_field = 2,
parameter size_counter = 5, //log2(size_mantissa) + 1 = 5)
parameter [size_exception_field - 1 : 0] zero = 0, //00
parameter [size_exception_field - 1 : 0] normal_number = 1, //01
parameter [size_exception_field - 1 : 0] infinity = 2, //10
parameter [size_exception_field - 1 : 0] NaN = 3, //11
parameter size_integer = 32,
parameter counter_integer = 6,//log2(size_integer) + 1 = 6)
parameter [1 : 0] FP_operation = 0, //00
parameter [1 : 0] FP_to_int = 1, //01
parameter [1 : 0] int_to_FP = 2, //10
parameter pipeline = 0,
parameter pipeline_pos = 0, // 8 bits
parameter size = size_mantissa + size_exponent + size_exception_field
)
( input [1:0] conversion,
input sub,
input [size - 1 : 0] a_number_i,
input [size - 1 : 0] b_number_i,
output[size - 1 : 0] resulted_number_o);
parameter double_size_mantissa = size_mantissa + size_mantissa;
parameter double_size_counter = size_counter + 1;
parameter max_size = (size_integer > size_mantissa)? size_integer : size_mantissa;
parameter max_counter = (counter_integer > size_counter)? counter_integer : size_counter;
parameter size_diff_i_m = (size_integer > size_mantissa)? (size_integer - size_mantissa) : (size_mantissa - size_integer);
parameter bias = {1'b0,{(size_exponent-1){1'b1}}};
parameter exp_biased = bias + size_mantissa;
parameter exponent = exp_biased - 1'b1;
parameter subtr = max_size -2'd2;
wire [size_exception_field - 1 : 0] sp_case_a_number, sp_case_b_number;
wire [size_mantissa - 1 : 0] m_a_number, m_b_number;
wire [size_exponent - 1 : 0] e_a_number, e_b_number;
wire s_a_number, s_b_number;
wire [size_exponent : 0] a_greater_exponent, b_greater_exponent;
wire [size_exponent - 1 : 0] exp_difference;
wire [size_exponent : 0] exp_inter;
wire [size_mantissa - 1 : 0] shifted_m_b, convert_neg_mantissa, mantissa_to_shift;
wire [size_mantissa - 1 : 0] initial_rounding_bits, inter_rounding_bits;
wire eff_op;
wire [size_mantissa + 1 : 0] adder_mantissa;
wire [size_mantissa : 0] unnormalized_mantissa;
wire [size_exception_field - 1 : 0] sp_case_o, resulted_exception_field;
wire [size_mantissa - 1 : 0] resulted_mantissa;
wire [size_exponent - 1 : 0] resulted_exponent;
wire resulted_sign;
wire zero_flag;
wire [size_exponent : 0] subtracter;
wire [max_size - size_mantissa : 0] dummy_bits;
wire [size_exponent : 0] shift_value_when_positive_exponent, shift_value_when_negative_exponent;
wire [size_exponent - 1 : 0] shift_value, shft_val;
wire lsb_shft_bit;
wire [size_exponent - 1 : 0] max_resulted_e_o;
wire [size_exponent - 1 : 0] max_unadjusted_exponent, max_adjust_exponent;
wire [size_exponent - 1 : 0] max_exp_selection;
wire [size_mantissa - 1 : 0] r_mantissa;
wire [size_mantissa : 0] max_rounded_mantissa;
wire [max_counter - 1 : 0] max_lzs;
wire [max_size - 1 : 0] max_entityINT_FP, max_entityFP_INT;
wire arith_shift;
wire max_ovf;
wire do_conversion;
assign do_conversion = |conversion; //let me know if there is a conversion
assign e_a_number = a_number_i[size_mantissa + size_exponent - 1 : size_mantissa - 1];
assign e_b_number = b_number_i[size_mantissa + size_exponent - 1 : size_mantissa - 1];
assign s_a_number = a_number_i[size - size_exception_field - 1];
assign s_b_number = b_number_i[size - size_exception_field - 1];
assign sp_case_a_number = a_number_i[size - 1 : size - size_exception_field];
assign sp_case_b_number = b_number_i[size - 1 : size - size_exception_field];
//find the greater exponent
assign a_greater_exponent = e_a_number - e_b_number;
assign b_greater_exponent = e_b_number - e_a_number;
//find the difference between exponents
assign exp_difference = (a_greater_exponent[size_exponent])? b_greater_exponent[size_exponent - 1 : 0] : a_greater_exponent[size_exponent - 1 : 0];
assign exp_inter = (b_greater_exponent[size_exponent])? {1'b0, e_a_number} : {1'b0, e_b_number};
//set shifter always on m_b_number
assign {m_a_number, m_b_number} = (b_greater_exponent[size_exponent])?
{{1'b1, a_number_i[size_mantissa - 2 :0]}, {1'b1, b_number_i[size_mantissa - 2 :0]}} :
{{1'b1, b_number_i[size_mantissa - 2 :0]}, {1'b1, a_number_i[size_mantissa - 2 :0]}};
assign subtracter = e_a_number - bias;
assign shift_value_when_positive_exponent = subtr - subtracter[size_exponent-1 : 0];
assign shift_value_when_negative_exponent = max_size + (~subtracter[size_exponent-1 : 0]);
assign shift_value = (subtracter[size_exponent])? shift_value_when_negative_exponent[size_exponent - 1 : 0] :
(shift_value_when_positive_exponent[size_exponent])? (~shift_value_when_positive_exponent[size_exponent - 1 : 0]):
shift_value_when_positive_exponent[size_exponent - 1 : 0];
assign shft_val = do_conversion? shift_value : exp_difference;
assign convert_neg_mantissa = {1'b0, ~a_number_i[size_mantissa-2 : 0]};
assign mantissa_to_shift = conversion[0]? (s_a_number? convert_neg_mantissa + 1'b1 : {1'b1, a_number_i[size_mantissa-2 : 0]}) : m_b_number;
assign arith_shift = conversion[0]? s_a_number : 1'b0;
//shift m_b_number
shifter #( .INPUT_SIZE(size_mantissa),
.SHIFT_SIZE(size_exponent),
.OUTPUT_SIZE(double_size_mantissa),
.DIRECTION(1'b0), //0=right, 1=left
.PIPELINE(pipeline),
.POSITION(pipeline_pos))
m_b_shifter_instance( .a(mantissa_to_shift),//mantissa
.arith(arith_shift),//logical shift
.shft(shft_val),
.shifted_a({shifted_m_b, initial_rounding_bits}));
assign max_entityFP_INT = {s_a_number, shifted_m_b[size_mantissa-1 : 0], initial_rounding_bits[size_mantissa-1 : size_mantissa - size_diff_i_m + 1]};
//istantiate effective_operation_component
effective_op effective_op_instance( .a_sign(s_a_number), .b_sign(s_b_number), .sub(sub), .eff_op(eff_op));
//compute unnormalized_mantissa
assign adder_mantissa = (eff_op)? ({1'b0, m_a_number} - {1'b0, shifted_m_b}) : ({1'b0, m_a_number} + {1'b0, shifted_m_b});
assign {unnormalized_mantissa, inter_rounding_bits} =
(adder_mantissa[size_mantissa + 1])? ({~adder_mantissa[size_mantissa : 0], ~initial_rounding_bits}) :
({adder_mantissa[size_mantissa : 0], initial_rounding_bits});
assign max_entityINT_FP = do_conversion? (s_a_number? (~a_number_i[max_size-1 : 0]) : a_number_i[max_size-1 : 0]) :
{{(max_size-size_mantissa-1){1'b0}}, unnormalized_mantissa[size_mantissa : 0]};
assign lsb_shft_bit = (do_conversion)? s_a_number : max_entityINT_FP[0];
assign max_ovf = do_conversion? 1'b0 : unnormalized_mantissa[size_mantissa];
//compute leading_zeros over unnormalized mantissa
leading_zeros #( .SIZE_INT(max_size), .SIZE_COUNTER(max_counter), .PIPELINE(pipeline))
leading_zeros_instance (.a(max_entityINT_FP),
.ovf(max_ovf),
.lz(max_lzs));
//compute shifting over unnormalized_mantissa
shifter #( .INPUT_SIZE(max_size),
.SHIFT_SIZE(max_counter),
.OUTPUT_SIZE(max_size + 1),
.DIRECTION(1'b1), //0=right, 1=left
.PIPELINE(pipeline),
.POSITION(pipeline_pos))
shifter_instance( .a(max_entityINT_FP),//mantissa
.arith(lsb_shft_bit),//logical shift
.shft(max_lzs),
.shifted_a({r_mantissa, dummy_bits}));
//instantiate rounding_component
rounding #( .SIZE_MOST_S_MANTISSA(size_mantissa + 1),
.SIZE_LEAST_S_MANTISSA(max_size - size_mantissa + 1))
rounding_instance( .unrounded_mantissa({1'b0,r_mantissa}),
.dummy_bits(dummy_bits),
.rounded_mantissa(max_rounded_mantissa));
assign max_exp_selection = do_conversion? exponent : exp_inter;
assign max_adjust_exponent = max_exp_selection - max_lzs;
assign max_unadjusted_exponent = max_adjust_exponent + size_diff_i_m;
assign max_resulted_e_o = (do_conversion & ~(|max_entityINT_FP))? bias : max_unadjusted_exponent + max_rounded_mantissa[size_mantissa];
assign resulted_exponent = conversion[0]? max_entityFP_INT[size_mantissa+size_exponent-2 : size_mantissa-1] : max_resulted_e_o;
assign resulted_mantissa = conversion[0]? max_entityFP_INT[size_mantissa-1 : 0] :
(max_rounded_mantissa[size_mantissa])? (max_rounded_mantissa[size_mantissa : 1]) :
(max_rounded_mantissa[size_mantissa-1 : 0]);
//compute exception_field
special_cases #( .size_exception_field(size_exception_field),
.zero(zero),
.normal_number(normal_number),
.infinity(infinity),
.NaN(NaN))
special_cases_instance( .sp_case_a_number(sp_case_a_number),
.sp_case_b_number(sp_case_b_number),
.sp_case_result_o(sp_case_o));
//compute special case
assign resulted_exception_field = do_conversion? sp_case_a_number : sp_case_o;
//set zero_flag in case of equal numbers
assign zero_flag = ~((|{resulted_mantissa,sp_case_o[1]}) & (|sp_case_o));
//compute resulted_sign
assign resulted_sign = do_conversion? s_a_number : ((eff_op)?
(!a_greater_exponent[size_exponent]? (!b_greater_exponent[size_exponent]? ~adder_mantissa[size_mantissa+1] : s_a_number) : ~s_b_number) :
s_a_number);
assign resulted_number_o = (zero_flag)? {size{1'b0}} :
{resulted_exception_field, resulted_sign, resulted_exponent, resulted_mantissa[size_mantissa - 2 : 0]};
endmodule
/xilinx_virtex_fp_library/trunk/SinglePathFPAdderMappedConversions/shifter.v
0,0 → 1,112
 
 
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:00:33 10/15/2013
// Design Name:
// Module Name: shifter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module shifter #( parameter INPUT_SIZE = 13,
parameter SHIFT_SIZE = 4,
parameter OUTPUT_SIZE = 24, //>INPUT_SIZE
parameter DIRECTION = 1,
parameter PIPELINE = 1,
parameter [7:0] POSITION = 8'b00000000)
(a, arith, shft, shifted_a);
input [INPUT_SIZE-1:0] a;
input arith;
input [SHIFT_SIZE-1:0] shft;
output [OUTPUT_SIZE-1:0] shifted_a;
wire [OUTPUT_SIZE-1:0] a_temp_d[SHIFT_SIZE:0];
wire [OUTPUT_SIZE-1:0] a_temp_q[SHIFT_SIZE:0];
assign a_temp_q[0][OUTPUT_SIZE-1 : OUTPUT_SIZE-INPUT_SIZE] = a;
assign a_temp_q[0][OUTPUT_SIZE-1-INPUT_SIZE : 0] = arith;
generate
begin : GENERATING
genvar i;
for (i = 0; i <= SHIFT_SIZE - 1; i = i + 1)
begin : BARREL_SHIFTER_GENERATION
if (DIRECTION == 1)
begin : LEFT
//begin : 1st_check
genvar j;
for (j = 0; j <= OUTPUT_SIZE - 1; j = j + 1)
begin : MUX_GEN_L
if (j < 2 ** i)
begin : ZERO_INS_L
assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : arith;
end
if (j >= 2 ** i)
begin : BIT_INS_L
assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : a_temp_q[i][j-2**i];
end
end
//end
end
if (DIRECTION == 0)
begin : RIGHT
//begin : 2nd_check
genvar j;
for (j = 0; j <= OUTPUT_SIZE - 1; j = j + 1)
begin : MUX_GEN_R
if (OUTPUT_SIZE - 1 < 2 ** i + j)
begin : ZERO_INS_R
assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : arith;
end
if (OUTPUT_SIZE - 1 >= 2 ** i + j)
begin : BIT_INS_R
assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : a_temp_q[i][j+2**i];
end
end
//end
end
if (PIPELINE != 0)
begin : PIPELINE_INSERTION
if (POSITION[i] == 1'b1)
begin : LATCH
d_ff #(OUTPUT_SIZE) D_INS(.clk(clk), .rst(rst), .d(a_temp_d[i]), .q(a_temp_q[i + 1]));
end
if (POSITION[i] == 1'b0)
begin : NO_LATCH
assign a_temp_q[i + 1] = a_temp_d[i];
end
end
if (PIPELINE == 0)
begin : NO_PIPELINE
assign a_temp_q[i + 1] = a_temp_d[i];
end
end
end
endgenerate
assign shifted_a = a_temp_q[SHIFT_SIZE];
endmodule
 
/xilinx_virtex_fp_library/trunk/SinglePathFPAdderMappedConversions/leading_zeros.v
0,0 → 1,139
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:50:09 10/17/2013
// Design Name:
// Module Name: leading_zeros
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module leading_zeros #( parameter SIZE_INT = 24, //mantissa bits
parameter SIZE_COUNTER = 5, //log2(size_mantissa) + 1 = 5)
parameter PIPELINE = 2)
(a, ovf, lz);
input [SIZE_INT-1:0] a;
input ovf;
output [SIZE_COUNTER-1:0] lz;
parameter nr_levels = SIZE_COUNTER - 1;
parameter max_pow_2 = 2 ** SIZE_COUNTER;
parameter size_lz = SIZE_COUNTER;
wire [max_pow_2-1:0] a_complete;
wire [max_pow_2-1:0] v_d[nr_levels-1:0];
wire [max_pow_2-1:0] v_q[nr_levels-1:0];
wire [max_pow_2-1:0] p_d[nr_levels-1:0];
wire [max_pow_2-1:0] p_q[nr_levels-1:0];
wire [size_lz-1:0] lzc;
assign a_complete[max_pow_2 - 1 : max_pow_2 - 1 - SIZE_INT + 1] = a;
generate
if (max_pow_2 != SIZE_INT)
begin : gen_if
assign a_complete[max_pow_2 - 1 - SIZE_INT : 0] = 0;
end
endgenerate
generate
begin : level_0
genvar i;
for (i = max_pow_2/4 - 1; i >= 0; i = i - 1)
begin : level_0
assign v_d[0][i] = (a_complete[4 * i + 3 : 4 * i] == 4'b0000) ? 1'b0 : 1'b1;
assign p_d[0][2*i+1:2*i] = (a_complete[4 * i + 3] == 1'b1) ? 2'b00 :
(a_complete[4 * i + 2] == 1'b1) ? 2'b01 :
(a_complete[4 * i + 1] == 1'b1) ? 2'b10 : 2'b11;
end
end
endgenerate
generate
begin : level_generation_begin
genvar i;
for (i = 1; i <= nr_levels - 1; i = i + 1)
begin : level_generation
//begin : v_levels_begin
genvar j;
for (j = 0; j <= max_pow_2/(2 ** (i + 2)) - 1; j = j + 1)
begin : v_levels
assign v_d[i][j] = v_q[i - 1][2*j+1] | v_q[i - 1][2*j];
end
//end
//begin : p_levels_begin
// genvar j;
for (j = 0; j <= max_pow_2/(2 ** (i + 2)) - 1; j = j + 1)
begin : p_levels
assign p_d[i][(i+2)*j+i+1] = (~(v_q[i - 1][2*j+1]));
assign p_d[i][(i+2)*j+i : (i+2)*j] = (v_q[i - 1][2*j+1] == 1'b1) ? p_q[i - 1][j*(2*i+2)+2*i+1 : j*(2*i+2) + i + 1] : p_q[i - 1][j*(2*i+2)+i : j*(2*i+2)];
end
//end
end
end
endgenerate
generate
if (PIPELINE != 0)
begin : pipeline_stages
//begin : INSERTION_begin
genvar i;
for (i = 0; i <= nr_levels - 2; i = i + 1)
begin : INSERTION
if ((i + 1) % nr_levels/(PIPELINE + 1) == 0)
begin : INS
d_ff #(max_pow_2) P_Di(.clk(clk), .rst(rst), .d(p_d[i]), .q(p_q[i]));
d_ff #(max_pow_2) V_Di(.clk(clk), .rst(rst), .d(v_d[i]), .q(v_q[i]));
end
if ((i + 1) % nr_levels/(PIPELINE + 1) != 0)
begin : NO_INS
assign p_q[i] = p_d[i];
assign v_q[i] = v_d[i];
end
end
//end
assign p_q[nr_levels - 1] = p_d[nr_levels - 1];
assign v_q[nr_levels - 1] = v_d[nr_levels - 1];
end
endgenerate
generate
if (PIPELINE == 0)
begin : no_pipeline
//begin : xhdl4
genvar i;
for (i = 0; i <= nr_levels - 1; i = i + 1)
begin : NO_INSERTION
assign p_q[i] = p_d[i];
assign v_q[i] = v_d[i];
end
//end
end
endgenerate
assign lzc[size_lz - 1:0] = p_q[nr_levels - 1][size_lz - 1:0];
generate
begin : lz_ovf_begin
genvar i;
for (i = 0; i <= size_lz - 1; i = i + 1)
begin : lz_ovf
assign lz[i] = lzc[i] & ((~ovf));
end
end
endgenerate
endmodule
/xilinx_virtex_fp_library/trunk/SinglePathFPAdderMappedConversions/rounding.v
0,0 → 1,35
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:09:49 11/04/2013
// Design Name:
// Module Name: rounding
// Project Name:
// Target Devices:
// Tool versions:
 
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
 
module rounding #( parameter SIZE_MOST_S_MANTISSA = 24,
parameter SIZE_LEAST_S_MANTISSA= 25)
( input [SIZE_MOST_S_MANTISSA - 1 : 0] unrounded_mantissa,
input [SIZE_LEAST_S_MANTISSA- 1 : 0] dummy_bits,
output[SIZE_MOST_S_MANTISSA - 1 : 0] rounded_mantissa);
wire g, sticky, round_dec;
assign g = dummy_bits[SIZE_LEAST_S_MANTISSA - 1];
assign sticky = |(dummy_bits[SIZE_LEAST_S_MANTISSA - 2 : 0]);
assign round_dec = g & (unrounded_mantissa[0] | sticky);
assign rounded_mantissa = unrounded_mantissa + round_dec;
endmodule

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