URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 1401 to Rev 1402
- ↔ Reverse comparison
Rev 1401 → Rev 1402
/trunk/or1ksim/cpu/or1k/sprs.c
35,6 → 35,7
#include "sim-config.h" |
#include "except.h" |
#include "execute.h" |
#include "dcache_model.h" |
|
extern int flag; |
|
58,6 → 59,31
case SPR_TTMR: |
spr_write_ttmr (value); |
break; |
/* Data cache simulateing stuff */ |
case SPR_DCBPR: |
if(value) { |
dc_simulate_read(value, 4); |
sprs[SPR_DCBPR] = 0; |
} |
break; |
case SPR_DCBFR: |
if(value != -1) { |
dc_inv(value); |
sprs[SPR_DCBFR] = -1; |
} |
break; |
case SPR_DCBIR: |
if(value != 0) { |
dc_inv(value); |
sprs[SPR_DCBIR] = 0; |
} |
break; |
case SPR_DCBWR: |
sprs[SPR_DCBWR] = 0; |
break; |
case SPR_DCBLR: |
sprs[SPR_DCBLR] = 0; |
break; |
case SPR_SR: |
/* Set internal flag also */ |
if(value & SPR_SR_F) flag = 1; |
/trunk/or1ksim/cache/dcache_model.c
322,30 → 322,6
} |
} |
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void dc_clock() |
{ |
oraddr_t addr; |
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if ((addr = mfspr(SPR_DCBPR))) { |
dc_simulate_read(addr, 4); |
mtspr(SPR_DCBPR, 0); |
} |
if ((addr = mfspr(SPR_DCBFR)) != -1) { |
dc_inv(addr); |
mtspr(SPR_DCBFR, -1); |
} |
if ((addr = mfspr(SPR_DCBIR))) { |
dc_inv(addr); |
mtspr(SPR_DCBIR, 0); |
} |
if ((addr = mfspr(SPR_DCBWR))) { |
mtspr(SPR_DCBWR, 0); |
} |
if ((addr = mfspr(SPR_DCBLR))) { |
mtspr(SPR_DCBLR, 0); |
} |
} |
|
/*-----------------------------------------------------[ DC configuration ]---*/ |
void dc_enabled(union param_val val, void *dat) |
{ |
/trunk/or1ksim/cache/dcache_model.h
24,4 → 24,4
uint32_t dc_simulate_read(oraddr_t dataaddr, int width); |
void dc_simulate_write(oraddr_t dataaddr, uint32_t data, int width); |
void dc_info(); |
void dc_clock(); |
void dc_inv(oraddr_t dataaddr); |
/trunk/or1ksim/toplevel.c
68,7 → 68,7
#include "cuc.h" |
|
/* CVS revision number. */ |
const char rcsrev[] = "$Revision: 1.118 $"; |
const char rcsrev[] = "$Revision: 1.119 $"; |
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inline void debug(int level, const char *format, ...) |
{ |
425,7 → 425,6
if (!config.pm.enabled || !testsprbits(SPR_PMR, SPR_PMR_DME | SPR_PMR_SME)) { |
if (runtime.sim.cont_run > 0) runtime.sim.cont_run--; |
if (cpu_clock ()) break; |
if (config.dc.enabled) dc_clock(); |
if (config.ic.enabled) ic_clock(); |
} |
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