URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 1403 to Rev 1404
- ↔ Reverse comparison
Rev 1403 → Rev 1404
/trunk/or1ksim/cpu/or1k/sprs.c
36,6 → 36,7
#include "except.h" |
#include "execute.h" |
#include "dcache_model.h" |
#include "icache_model.h" |
|
extern int flag; |
|
84,6 → 85,22
case SPR_DCBLR: |
sprs[SPR_DCBLR] = 0; |
break; |
/* Instruction cache simulateing stuff */ |
case SPR_ICBPR: |
if(value) { |
ic_simulate_fetch(value); |
sprs[SPR_ICBPR] = 0; |
} |
break; |
case SPR_ICBIR: |
if(value) { |
ic_inv(value); |
sprs[SPR_ICBIR] = 0; |
} |
break; |
case SPR_ICBLR: |
sprs[SPR_ICBLR] = 0; |
break; |
case SPR_SR: |
/* Set internal flag also */ |
if(value & SPR_SR_F) flag = 1; |
/trunk/or1ksim/cache/icache_model.h
22,5 → 22,5
#define MAX_IC_BLOCK_SIZE 4 /* In words */ |
|
uint32_t ic_simulate_fetch(oraddr_t fetchaddr); |
void ic_inv(oraddr_t dataaddr); |
void ic_info(); |
void ic_clock(); |
/trunk/or1ksim/cache/icache_model.c
196,23 → 196,6
} |
} |
|
void ic_clock() |
{ |
oraddr_t addr; |
|
if ((addr = mfspr(SPR_ICBPR))) { |
ic_simulate_fetch(addr); |
mtspr(SPR_ICBPR, 0); |
} |
if ((addr = mfspr(SPR_ICBIR))) { |
ic_inv(addr); |
mtspr(SPR_ICBIR, 0); |
} |
if ((addr = mfspr(SPR_ICBLR))) { |
mtspr(SPR_ICBLR, 0); |
} |
} |
|
/*-----------------------------------------------------[ IC configuration ]---*/ |
void ic_enabled(union param_val val, void *dat) |
{ |
/trunk/or1ksim/toplevel.c
68,7 → 68,7
#include "cuc.h" |
|
/* CVS revision number. */ |
const char rcsrev[] = "$Revision: 1.119 $"; |
const char rcsrev[] = "$Revision: 1.120 $"; |
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inline void debug(int level, const char *format, ...) |
{ |
425,7 → 425,6
if (!config.pm.enabled || !testsprbits(SPR_PMR, SPR_PMR_DME | SPR_PMR_SME)) { |
if (runtime.sim.cont_run > 0) runtime.sim.cont_run--; |
if (cpu_clock ()) break; |
if (config.ic.enabled) ic_clock(); |
} |
|
if (config.vapi.enabled && runtime.vapi.enabled) vapi_check(); |