OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 141 to Rev 142
    ↔ Reverse comparison
  •

Rev 141 → Rev 142

/openrisc/trunk/or1200/rtl/verilog/or1200_spram_1024x8.v
63,7 → 63,14
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: or1200_spram_1024x8.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Coding style changed.
//
// Revision 1.9 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
276,7 → 283,7
//
RAMB4_S4 ramb4_s4_0(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[3:0]),
.EN(ce),
289,7 → 296,7
//
RAMB4_S4 ramb4_s4_1(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[7:4]),
.EN(ce),
311,7 → 318,7
 
RAMB16_S9 ramb16_s9(
.CLK(clk),
.SSR(rst),
.SSR(1'b0),
.ADDR({1'b0,addr}),
.DI(di),
.DIP(1'b0),
/openrisc/trunk/or1200/rtl/verilog/or1200_spram.v
0,0 → 1,134
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dpram_32x32.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// New
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram
(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, ce, we, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 10;
parameter dw = 32;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input ce; // Chip enable input
input we; // Write enable input
//input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
 
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
`ifdef OR1200_ACTEL
reg [dw-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
`else
reg [dw-1:0] mem [(1<<aw)-1:0];
`endif
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
//assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
assign doq = mem[addr_reg];
//
// RAM read address register
//
always @(posedge clk)
if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (we && ce)
mem[addr] <= #1 di;
endmodule // or1200_spram
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
62,7 → 62,14
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: or1200_spram_2048x32_bw.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Coding style changed.
//
// Revision 1.5 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.4 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
334,7 → 341,7
//
RAMB4_S2 ramb4_s2_0(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[1:0]),
.EN(ce),
347,7 → 354,7
//
RAMB4_S2 ramb4_s2_1(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[3:2]),
.EN(ce),
360,7 → 367,7
//
RAMB4_S2 ramb4_s2_2(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[5:4]),
.EN(ce),
373,7 → 380,7
//
RAMB4_S2 ramb4_s2_3(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[7:6]),
.EN(ce),
385,7 → 392,7
//
RAMB4_S2 ramb4_s2_4(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[9:8]),
.EN(ce),
398,7 → 405,7
//
RAMB4_S2 ramb4_s2_5(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[11:10]),
.EN(ce),
411,7 → 418,7
//
RAMB4_S2 ramb4_s2_6(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[13:12]),
.EN(ce),
424,7 → 431,7
//
RAMB4_S2 ramb4_s2_7(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[15:14]),
.EN(ce),
436,7 → 443,7
//
RAMB4_S2 ramb4_s2_8(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[17:16]),
.EN(ce),
449,7 → 456,7
//
RAMB4_S2 ramb4_s2_9(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[19:18]),
.EN(ce),
462,7 → 469,7
//
RAMB4_S2 ramb4_s2_10(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[21:20]),
.EN(ce),
475,7 → 482,7
//
RAMB4_S2 ramb4_s2_11(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[23:22]),
.EN(ce),
487,7 → 494,7
//
RAMB4_S2 ramb4_s2_12(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[25:24]),
.EN(ce),
500,7 → 507,7
//
RAMB4_S2 ramb4_s2_13(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[27:26]),
.EN(ce),
513,7 → 520,7
//
RAMB4_S2 ramb4_s2_14(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[29:28]),
.EN(ce),
526,7 → 533,7
//
RAMB4_S2 ramb4_s2_15(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[31:30]),
.EN(ce),
551,7 → 558,7
//
RAMB16_S9 ramb16_s9_0(
.CLK(clk),
.SSR(rst),
.SSR(1'b0),
.ADDR(addr),
.DI(di[7:0]),
.DIP(1'b0),
566,7 → 573,7
//
RAMB16_S9 ramb16_s9_1(
.CLK(clk),
.SSR(rst),
.SSR(1'b0),
.ADDR(addr),
.DI(di[15:8]),
.DIP(1'b0),
581,7 → 588,7
//
RAMB16_S9 ramb16_s9_2(
.CLK(clk),
.SSR(rst),
.SSR(1'b0),
.ADDR(addr),
.DI(di[23:16]),
.DIP(1'b0),
596,7 → 603,7
//
RAMB16_S9 ramb16_s9_3(
.CLK(clk),
.SSR(rst),
.SSR(1'b0),
.ADDR(addr),
.DI(di[31:24]),
.DIP(1'b0),
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_32x24.v
63,7 → 63,14
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: or1200_spram_32x24.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Coding style changed.
//
// Revision 1.3 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.2 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
205,7 → 212,7
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR({3'h0, addr}),
.DI(di[15:0]),
.EN(ce),
218,7 → 225,7
//
RAMB4_S16 ramb4_s16_1(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR({3'h0, addr}),
.DI({8'h00, di[23:16]}),
.EN(ce),
240,7 → 247,7
 
RAMB16_S36 ramb16_s36(
.CLK(clk),
.SSR(rst),
.SSR(1'b0),
.ADDR({4'b0000, addr}),
.DI({8'h00, di}),
.DIP(4'h0),
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_1024x32.v
63,7 → 63,14
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: or1200_spram_1024x32.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Coding style changed.
//
// Revision 1.9 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
279,7 → 286,7
//
RAMB4_S4 ramb4_s4_0(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[3:0]),
.EN(ce),
292,7 → 299,7
//
RAMB4_S4 ramb4_s4_1(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[7:4]),
.EN(ce),
305,7 → 312,7
//
RAMB4_S4 ramb4_s4_2(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[11:8]),
.EN(ce),
318,7 → 325,7
//
RAMB4_S4 ramb4_s4_3(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[15:12]),
.EN(ce),
331,7 → 338,7
//
RAMB4_S4 ramb4_s4_4(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[19:16]),
.EN(ce),
344,7 → 351,7
//
RAMB4_S4 ramb4_s4_5(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[23:20]),
.EN(ce),
357,7 → 364,7
//
RAMB4_S4 ramb4_s4_6(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[27:24]),
.EN(ce),
370,7 → 377,7
//
RAMB4_S4 ramb4_s4_7(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[31:28]),
.EN(ce),
395,7 → 402,7
//
RAMB16_S9 ramb16_s9_0(
.CLK(clk),
.SSR(rst),
.SSR(1'b0),
.ADDR({1'b0,addr}),
.DI(di[7:0]),
.DIP(1'b0),
410,7 → 417,7
//
RAMB16_S9 ramb16_s9_1(
.CLK(clk),
.SSR(rst),
.SSR(1'b0),
.ADDR({1'b0,addr}),
.DI(di[15:8]),
.DIP(1'b0),
425,7 → 432,7
//
RAMB16_S9 ramb16_s9_2(
.CLK(clk),
.SSR(rst),
.SSR(1'b0),
.ADDR({1'b0,addr}),
.DI(di[23:16]),
.DIP(1'b0),
440,7 → 447,7
//
RAMB16_S9 ramb16_s9_3(
.CLK(clk),
.SSR(rst),
.SSR(1'b0),
.ADDR({1'b0,addr}),
.DI(di[31:24]),
.DIP(1'b0),
/openrisc/trunk/or1200/rtl/verilog/or1200_tt.v
43,7 → 43,13
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: or1200_tt.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// No update
//
// Revision 1.5 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.4 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
/openrisc/trunk/or1200/rtl/verilog/or1200_sprs.v
43,7 → 43,14
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: or1200_sprs.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Major update:
// Structure reordered and bugs fixed.
//
// Revision 1.11 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.9.4.1 2003/12/17 13:43:38 simons
// Exception prefix configuration changed.
//
114,10 → 121,11
 
// Internal CPU interface
flagforw, flag_we, flag, cyforw, cy_we, carry,
addrbase, addrofs, dat_i, alu_op, branch_op,
addrbase, addrofs, dat_i, branch_op, ex_spr_read, ex_spr_write,
epcr, eear, esr, except_started,
to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
boot_adr_sel_i,
 
// From/to other RISC units
spr_dat_pic, spr_dat_tt, spr_dat_pm,
149,7 → 157,8
input [width-1:0] addrbase; // SPR base address
input [15:0] addrofs; // SPR offset
input [width-1:0] dat_i; // SPR write data
input [`OR1200_ALUOP_WIDTH-1:0] alu_op; // ALU operation
input ex_spr_read; // l.mfspr in EX
input ex_spr_write; // l.mtspr in EX
input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch operation
input [width-1:0] epcr; // EPCR0
input [width-1:0] eear; // EEAR0
168,6 → 177,7
input [31:0] spr_dat_npc; // Data from NPC
input [31:0] spr_dat_ppc; // Data from PPC
input [31:0] spr_dat_mac; // Data from MAC
input boot_adr_sel_i;
 
//
// To/from other RISC units
195,9 → 205,11
//
// Internal regs & wires
//
reg [`OR1200_SR_WIDTH-1:0] sr; // SR
reg write_spr; // Write SPR
reg read_spr; // Read SPR
reg [`OR1200_SR_WIDTH-1:0] sr_reg; // SR
reg sr_reg_bit_eph; // SR_EPH bit
reg sr_reg_bit_eph_select; // SR_EPH select
wire sr_reg_bit_eph_muxed; // SR_EPH muxed bit
reg [`OR1200_SR_WIDTH-1:0] sr; // SR
reg [width-1:0] to_wbmux; // For l.mfspr
wire cfgr_sel; // Select for cfg regs
wire rf_sel; // Select for RF
209,9 → 221,9
wire esr_sel; // Select for ESR0
wire [31:0] sys_data; // Read data from system SPRs
wire du_access; // Debug unit access
wire [`OR1200_ALUOP_WIDTH-1:0] sprs_op; // ALU operation
reg [31:0] unqualified_cs; // Unqualified chip selects
 
wire ex_spr_write; // jb
//
// Decide if it is debug unit access
//
218,15 → 230,10
assign du_access = du_read | du_write;
 
//
// Generate sprs opcode
//
assign sprs_op = du_write ? `OR1200_ALUOP_MTSR : du_read ? `OR1200_ALUOP_MFSR : alu_op;
 
//
// Generate SPR address from base address and offset
// OR from debug unit address
//
assign spr_addr = du_access ? du_addr : addrbase | {16'h0000, addrofs};
assign spr_addr = du_access ? du_addr : (addrbase | {16'h0000, addrofs});
 
//
// SPR is written by debug unit or by l.mtspr
235,21 → 242,21
 
//
// debug unit data input:
// - read of SPRS by debug unit
// - write into debug unit SPRs by debug unit itself
// - read of SPRS by debug unit
// - write into debug unit SPRs by l.mtspr
//
assign du_dat_cpu = du_write ? du_dat_du : du_read ? to_wbmux : dat_i;
assign du_dat_cpu = du_read ? to_wbmux : du_write ? du_dat_du : dat_i;
 
//
// Write into SPRs when l.mtspr
// Write into SPRs when DU or l.mtspr
//
assign spr_we = du_write | write_spr;
assign spr_we = du_write | ex_spr_write;
 
//
// Qualify chip selects
//
assign spr_cs = unqualified_cs & {32{read_spr | write_spr}};
assign spr_cs = unqualified_cs & {32{du_read | du_write | ex_spr_read | (ex_spr_write & sr[`OR1200_SR_SM])}};
 
//
// Decoding of groups
298,22 → 305,31
// What to write into SR
//
assign to_sr[`OR1200_SR_FO:`OR1200_SR_OV] =
(except_started) ? sr[`OR1200_SR_FO:`OR1200_SR_OV] :
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_FO:`OR1200_SR_OV] :
(write_spr && sr_sel) ? {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OV]}:
(spr_we && sr_sel) ? {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OV]}:
sr[`OR1200_SR_FO:`OR1200_SR_OV];
assign to_sr[`OR1200_SR_TED] =
(except_started) ? 1'b1 :
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_TED] :
(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_TED]:
sr[`OR1200_SR_TED];
assign to_sr[`OR1200_SR_CY] =
(except_started) ? sr[`OR1200_SR_CY] :
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
cy_we ? cyforw :
(write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
sr[`OR1200_SR_CY];
assign to_sr[`OR1200_SR_F] =
(except_started) ? sr[`OR1200_SR_F] :
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_F] :
flag_we ? flagforw :
(write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_F] :
(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_F] :
sr[`OR1200_SR_F];
assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM] =
(except_started) ? {sr[`OR1200_SR_CE:`OR1200_SR_LEE], 2'b00, sr[`OR1200_SR_ICE:`OR1200_SR_DCE], 3'b001} :
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CE:`OR1200_SR_SM] :
(write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM]:
(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM]:
sr[`OR1200_SR_CE:`OR1200_SR_SM];
 
//
331,23 → 347,23
//
// Write enables for system SPRs
//
assign sr_we = (write_spr && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) | flag_we | cy_we;
assign pc_we = (write_spr && (npc_sel | ppc_sel));
assign epcr_we = (write_spr && epcr_sel);
assign eear_we = (write_spr && eear_sel);
assign esr_we = (write_spr && esr_sel);
assign sr_we = (spr_we && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) | flag_we | cy_we;
assign pc_we = (du_write && (npc_sel | ppc_sel));
assign epcr_we = (spr_we && epcr_sel);
assign eear_we = (spr_we && eear_sel);
assign esr_we = (spr_we && esr_sel);
 
//
// Output from system SPRs
//
assign sys_data = (spr_dat_cfgr & {32{read_spr & cfgr_sel}}) |
(spr_dat_rf & {32{read_spr & rf_sel}}) |
(spr_dat_npc & {32{read_spr & npc_sel}}) |
(spr_dat_ppc & {32{read_spr & ppc_sel}}) |
({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{read_spr & sr_sel}}) |
(epcr & {32{read_spr & epcr_sel}}) |
(eear & {32{read_spr & eear_sel}}) |
({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{read_spr & esr_sel}});
assign sys_data = (spr_dat_cfgr & {32{cfgr_sel}}) |
(spr_dat_rf & {32{rf_sel}}) |
(spr_dat_npc & {32{npc_sel}}) |
(spr_dat_ppc & {32{ppc_sel}}) |
({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{sr_sel}}) |
(epcr & {32{epcr_sel}}) |
(eear & {32{eear_sel}}) |
({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{esr_sel}});
 
//
// Flag alias
364,58 → 380,58
//
always @(posedge clk or posedge rst)
if (rst)
sr <= #1 {1'b1, `OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-3{1'b0}}, 1'b1};
else if (except_started) begin
sr[`OR1200_SR_SM] <= #1 1'b1;
sr[`OR1200_SR_TEE] <= #1 1'b0;
sr[`OR1200_SR_IEE] <= #1 1'b0;
sr[`OR1200_SR_DME] <= #1 1'b0;
sr[`OR1200_SR_IME] <= #1 1'b0;
end
sr_reg <= #1 {2'h1, `OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-4{1'b0}}, 1'b1};
else if (except_started)
sr_reg <= #1 to_sr[`OR1200_SR_WIDTH-1:0];
else if (sr_we)
sr <= #1 to_sr[`OR1200_SR_WIDTH-1:0];
sr_reg <= #1 to_sr[`OR1200_SR_WIDTH-1:0];
 
// EPH part of Supervision register
always @(posedge clk or posedge rst)
// default value
if (rst) begin
sr_reg_bit_eph <= #1 `OR1200_SR_EPH_DEF;
sr_reg_bit_eph_select <= #1 1'b1; // select async. value due to reset state
end
// selected value (different from default) is written into FF after reset state
else if (sr_reg_bit_eph_select) begin
sr_reg_bit_eph <= #1 boot_adr_sel_i; // dynamic value can only be assigned to FF out of reset!
sr_reg_bit_eph_select <= #1 1'b0; // select FF value
end
else if (sr_we) begin
sr_reg_bit_eph <= #1 to_sr[`OR1200_SR_EPH];
end
 
// select async. value of EPH bit after reset
assign sr_reg_bit_eph_muxed = (sr_reg_bit_eph_select) ? boot_adr_sel_i : sr_reg_bit_eph;
 
// EPH part joined together with rest of Supervision register
always @(sr_reg or sr_reg_bit_eph_muxed)
sr = {sr_reg[`OR1200_SR_WIDTH-1:`OR1200_SR_WIDTH-2], sr_reg_bit_eph_muxed, sr_reg[`OR1200_SR_WIDTH-4:0]};
 
//
// MTSPR/MFSPR interface
//
always @(sprs_op or spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
case (sprs_op) // synopsys parallel_case
`OR1200_ALUOP_MTSR : begin
write_spr = 1'b1;
read_spr = 1'b0;
to_wbmux = 32'b0;
end
`OR1200_ALUOP_MFSR : begin
casex (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
`OR1200_SPR_GROUP_TT:
to_wbmux = spr_dat_tt;
`OR1200_SPR_GROUP_PIC:
to_wbmux = spr_dat_pic;
`OR1200_SPR_GROUP_PM:
to_wbmux = spr_dat_pm;
`OR1200_SPR_GROUP_DMMU:
to_wbmux = spr_dat_dmmu;
`OR1200_SPR_GROUP_IMMU:
to_wbmux = spr_dat_immu;
`OR1200_SPR_GROUP_MAC:
to_wbmux = spr_dat_mac;
`OR1200_SPR_GROUP_DU:
to_wbmux = spr_dat_du;
`OR1200_SPR_GROUP_SYS:
to_wbmux = sys_data;
default:
to_wbmux = 32'b0;
endcase
write_spr = 1'b0;
read_spr = 1'b1;
end
default : begin
write_spr = 1'b0;
read_spr = 1'b0;
to_wbmux = 32'b0;
end
endcase
casex (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
`OR1200_SPR_GROUP_SYS:
to_wbmux = sys_data;
`OR1200_SPR_GROUP_TT:
to_wbmux = spr_dat_tt;
`OR1200_SPR_GROUP_PIC:
to_wbmux = spr_dat_pic;
`OR1200_SPR_GROUP_PM:
to_wbmux = spr_dat_pm;
`OR1200_SPR_GROUP_DMMU:
to_wbmux = spr_dat_dmmu;
`OR1200_SPR_GROUP_IMMU:
to_wbmux = spr_dat_immu;
`OR1200_SPR_GROUP_MAC:
to_wbmux = spr_dat_mac;
default: //`OR1200_SPR_GROUP_DU:
to_wbmux = spr_dat_du;
endcase
end
 
endmodule
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_64x22.v
63,7 → 63,14
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: or1200_spram_64x22.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Coding style changed.
//
// Revision 1.9 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
284,7 → 291,7
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR({2'b00, addr}),
.DI(di[15:0]),
.EN(ce),
297,7 → 304,7
//
RAMB4_S16 ramb4_s16_1(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR({2'b00, addr}),
.DI({10'b0000000000, di[21:16]}),
.EN(ce),
319,7 → 326,7
 
RAMB16_S36 ramb16_s36(
.CLK(clk),
.SSR(rst),
.SSR(1'b0),
.ADDR({3'b000, addr}),
.DI({10'b0000000000,di}),
.DIP(4'h0),
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_64x24.v
63,7 → 63,14
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: or1200_spram_64x24.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Coding style changed.
//
// Revision 1.9 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
286,7 → 293,7
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR({2'b00, addr}),
.DI(di[15:0]),
.EN(ce),
299,7 → 306,7
//
RAMB4_S16 ramb4_s16_1(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR({2'b00, addr}),
.DI({8'h00, di[23:16]}),
.EN(ce),
321,7 → 328,7
 
RAMB16_S36 ramb16_s36(
.CLK(clk),
.SSR(rst),
.SSR(1'b0),
.ADDR({3'b000, addr}),
.DI({8'h00,di}),
.DIP(4'h0),
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_2048x32.v
63,7 → 63,14
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: or1200_spram_2048x32.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Coding style changed.
//
// Revision 1.10 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.9 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
279,7 → 286,7
//
RAMB4_S2 ramb4_s2_0(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[1:0]),
.EN(ce),
292,7 → 299,7
//
RAMB4_S2 ramb4_s2_1(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[3:2]),
.EN(ce),
305,7 → 312,7
//
RAMB4_S2 ramb4_s2_2(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[5:4]),
.EN(ce),
318,7 → 325,7
//
RAMB4_S2 ramb4_s2_3(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[7:6]),
.EN(ce),
331,7 → 338,7
//
RAMB4_S2 ramb4_s2_4(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[9:8]),
.EN(ce),
344,7 → 351,7
//
RAMB4_S2 ramb4_s2_5(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[11:10]),
.EN(ce),
357,7 → 364,7
//
RAMB4_S2 ramb4_s2_6(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[13:12]),
.EN(ce),
370,7 → 377,7
//
RAMB4_S2 ramb4_s2_7(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[15:14]),
.EN(ce),
383,7 → 390,7
//
RAMB4_S2 ramb4_s2_8(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[17:16]),
.EN(ce),
396,7 → 403,7
//
RAMB4_S2 ramb4_s2_9(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[19:18]),
.EN(ce),
409,7 → 416,7
//
RAMB4_S2 ramb4_s2_10(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[21:20]),
.EN(ce),
422,7 → 429,7
//
RAMB4_S2 ramb4_s2_11(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[23:22]),
.EN(ce),
435,7 → 442,7
//
RAMB4_S2 ramb4_s2_12(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[25:24]),
.EN(ce),
448,7 → 455,7
//
RAMB4_S2 ramb4_s2_13(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[27:26]),
.EN(ce),
461,7 → 468,7
//
RAMB4_S2 ramb4_s2_14(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[29:28]),
.EN(ce),
474,7 → 481,7
//
RAMB4_S2 ramb4_s2_15(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[31:30]),
.EN(ce),
499,7 → 506,7
//
RAMB16_S9 ramb16_s9_0(
.CLK(clk),
.SSR(rst),
.SSR(1'b0),
.ADDR(addr),
.DI(di[7:0]),
.DIP(1'b0),
514,7 → 521,7
//
RAMB16_S9 ramb16_s9_1(
.CLK(clk),
.SSR(rst),
.SSR(1'b0),
.ADDR(addr),
.DI(di[15:8]),
.DIP(1'b0),
529,7 → 536,7
//
RAMB16_S9 ramb16_s9_2(
.CLK(clk),
.SSR(rst),
.SSR(1'b0),
.ADDR(addr),
.DI(di[23:16]),
.DIP(1'b0),
544,7 → 551,7
//
RAMB16_S9 ramb16_s9_3(
.CLK(clk),
.SSR(rst),
.SSR(1'b0),
.ADDR(addr),
.DI(di[31:24]),
.DIP(1'b0),
/openrisc/trunk/or1200/rtl/verilog/or1200_wbmux.v
43,7 → 43,13
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: or1200_wbmux.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// No update
//
// Revision 1.3 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.2 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_128x32.v
59,7 → 59,14
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: or1200_spram_128x32.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Coding style changed.
//
// Revision 1.3 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.2 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
192,7 → 199,7
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR({1'b0, addr}),
.DI(di[15:0]),
.EN(ce),
205,7 → 212,7
//
RAMB4_S16 ramb4_s16_1(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR({1'b0, addr}),
.DI(di[31:16]),
.EN(ce),
227,7 → 234,7
 
RAMB16_S36 ramb16_s36(
.CLK(clk),
.SSR(rst),
.SSR(1'b0),
.ADDR({2'b00, addr}),
.DI(di),
.DIP(4'h0),
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_256x21.v
63,7 → 63,14
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: or1200_spram_256x21.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Coding style changed.
//
// Revision 1.9 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
292,7 → 299,7
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[15:0]),
.EN(ce),
305,7 → 312,7
//
RAMB4_S16 ramb4_s16_1(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI({11'b00000000000, di[20:16]}),
.EN(ce),
327,7 → 334,7
 
RAMB16_S36 ramb16_s36(
.CLK(clk),
.SSR(rst),
.SSR(1'b0),
.ADDR({1'b0,addr}),
.DI({11'b00000000000,di[20:0]}),
.DIP(4'h0),
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
62,7 → 62,14
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: or1200_spram_1024x32_bw.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Coding style changed.
//
// Revision 1.4 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.3 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
331,7 → 338,7
//
RAMB4_S4 ramb4_s4_0(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[3:0]),
.EN(ce),
344,7 → 351,7
//
RAMB4_S4 ramb4_s4_1(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[7:4]),
.EN(ce),
357,7 → 364,7
//
RAMB4_S4 ramb4_s4_2(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[11:8]),
.EN(ce),
370,7 → 377,7
//
RAMB4_S4 ramb4_s4_3(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[15:12]),
.EN(ce),
383,7 → 390,7
//
RAMB4_S4 ramb4_s4_4(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[19:16]),
.EN(ce),
396,7 → 403,7
//
RAMB4_S4 ramb4_s4_5(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[23:20]),
.EN(ce),
409,7 → 416,7
//
RAMB4_S4 ramb4_s4_6(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[27:24]),
.EN(ce),
422,7 → 429,7
//
RAMB4_S4 ramb4_s4_7(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[31:28]),
.EN(ce),
447,7 → 454,7
//
RAMB16_S9 ramb16_s9_0(
.CLK(clk),
.SSR(rst),
.SSR(1'b0),
.ADDR({1'b0,addr}),
.DI(di[7:0]),
.DIP(1'b0),
462,7 → 469,7
//
RAMB16_S9 ramb16_s9_1(
.CLK(clk),
.SSR(rst),
.SSR(1'b0),
.ADDR({1'b0,addr}),
.DI(di[15:8]),
.DIP(1'b0),
477,7 → 484,7
//
RAMB16_S9 ramb16_s9_2(
.CLK(clk),
.SSR(rst),
.SSR(1'b0),
.ADDR({1'b0,addr}),
.DI(di[23:16]),
.DIP(1'b0),
492,7 → 499,7
//
RAMB16_S9 ramb16_s9_3(
.CLK(clk),
.SSR(rst),
.SSR(1'b0),
.ADDR({1'b0,addr}),
.DI(di[31:24]),
.DIP(1'b0),
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_32_bw.v
0,0 → 1,147
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM 32-bit Byte-Write ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// - Tadej Markovic, tadej.markovic@gmail.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dpram_32x32.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// New
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_32_bw
(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, ce, we, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 10;
parameter dw = 32;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input ce; // Chip enable input
input [3:0] we; // Write enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
 
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
`ifdef OR1200_ACTEL
reg [7:0] mem0 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
reg [7:0] mem1 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
reg [7:0] mem2 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
reg [7:0] mem3 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
`else
reg [7:0] mem0 [(1<<aw)-1:0];
reg [7:0] mem1 [(1<<aw)-1:0];
reg [7:0] mem2 [(1<<aw)-1:0];
reg [7:0] mem3 [(1<<aw)-1:0];
`endif
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = {mem0[addr_reg], mem1[addr_reg], mem2[addr_reg], mem3[addr_reg]};
//
// RAM read address register
//
always @(posedge clk)
if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce) begin
if (we[0])
mem0[addr] <= #1 di[31:24];
if (we[1])
mem1[addr] <= #1 di[23:16];
if (we[2])
mem2[addr] <= #1 di[15:08];
if (we[3])
mem3[addr] <= #1 di[07:00];
end
endmodule // or1200_spram
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_2048x8.v
63,7 → 63,14
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: or1200_spram_2048x8.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Coding style changed.
//
// Revision 1.9 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
276,7 → 283,7
//
RAMB4_S2 ramb4_s2_0(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[1:0]),
.EN(ce),
289,7 → 296,7
//
RAMB4_S2 ramb4_s2_1(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[3:2]),
.EN(ce),
302,7 → 309,7
//
RAMB4_S2 ramb4_s2_2(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[5:4]),
.EN(ce),
315,7 → 322,7
//
RAMB4_S2 ramb4_s2_3(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[7:6]),
.EN(ce),
337,7 → 344,7
 
RAMB16_S9 ramb16_s9(
.CLK(clk),
.SSR(rst),
.SSR(1'b0),
.ADDR(addr),
.DI(di),
.DIP(1'b0),
/openrisc/trunk/or1200/rtl/verilog/or1200_tpram_32x32.v
62,7 → 62,14
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: or1200_tpram_32x32.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Coding style changed.
//
// Revision 1.5 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.4 2004/06/08 18:15:48 lampret
// Changed behavior of the simulation generic models
//
229,7 → 236,7
//
RAMB4_S16_S16 ramb4_s16_s16_0(
.CLKA(clk_a),
.RSTA(rst_a),
.RSTA(1'b0),
.ADDRA(addr_a),
.DIA(di_a[15:0]),
.ENA(ce_a),
237,7 → 244,7
.DOA(do_a[15:0]),
 
.CLKB(clk_b),
.RSTB(rst_b),
.RSTB(1'b0),
.ADDRB(addr_b),
.DIB(di_b[15:0]),
.ENB(ce_b),
250,7 → 257,7
//
RAMB4_S16_S16 ramb4_s16_s16_1(
.CLKA(clk_a),
.RSTA(rst_a),
.RSTA(1'b0),
.ADDRA(addr_a),
.DIA(di_a[31:16]),
.ENA(ce_a),
258,7 → 265,7
.DOA(do_a[31:16]),
 
.CLKB(clk_b),
.RSTB(rst_b),
.RSTB(1'b0),
.ADDRB(addr_b),
.DIB(di_b[31:16]),
.ENB(ce_b),
280,7 → 287,7
 
RAMB16_S36_S36 ramb16_s36_s36(
.CLKA(clk_a),
.SSRA(rst_a),
.SSRA(1'b0),
.ADDRA({4'b0000,addr_a}),
.DIA(di_a),
.DIPA(4'h0),
290,7 → 297,7
.DOPA(),
 
.CLKB(clk_b),
.SSRB(rst_b),
.SSRB(1'b0),
.ADDRB({4'b0000,addr_b}),
.DIB(di_b),
.DIPB(4'h0),
318,8 → 325,8
.wren_a (we_a),
.inclocken_b (ce_b),
.wren_b (we_b),
.inaclr_a (rst_a),
.inaclr_b (rst_b),
.inaclr_a (1'b0),
.inaclr_b (1'b0),
.inclock_a (clk_a),
.inclock_b (clk_b),
.data_a (di_a),
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_64x14.v
63,7 → 63,14
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: or1200_spram_64x14.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Coding style changed.
//
// Revision 1.9 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
284,7 → 291,7
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR({2'b00, addr}),
.DI({2'b00, di[13:0]}),
.EN(ce),
304,7 → 311,7
 
RAMB16_S18 ramb16_s18(
.CLK(clk),
.SSR(rst),
.SSR(1'b0),
.ADDR({4'b0000, addr}),
.DI({2'b00, di[13:0]}),
.DIP(2'b00),
/openrisc/trunk/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
43,7 → 43,13
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: or1200_xcv_ram32x8d.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// No update
//
// Revision 1.2 2002/07/14 22:17:17 lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
/openrisc/trunk/or1200/rtl/verilog/or1200_top.v
43,7 → 43,14
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: or1200_top.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Major update:
// Structure reordered.
//
// Revision 1.13 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.12 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
177,6 → 184,8
pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o,
pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o
 
,sig_tick
 
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
318,6 → 327,7
//
wire [dw-1:0] icbiu_dat_ic;
wire [aw-1:0] icbiu_adr_ic;
wire [aw-1:0] icbiu_adr_ic_word;
wire icbiu_cyc_ic;
wire icbiu_stb_ic;
wire icbiu_we_ic;
330,6 → 340,11
wire [3:0] icbiu_tag_biu;
 
//
// SR Interface (this signal can be connected to the input pin)
//
wire boot_adr_sel = `OR1200_SR_EPH_DEF;
 
//
// CPU's SPR access to various RISC units (shared wires)
//
wire supv;
339,6 → 354,11
wire spr_we;
 
//
// SB
//
wire sb_en;
 
//
// DMMU and CPU
//
wire dmmu_en;
443,7 → 463,7
// CPU and TT
//
wire [dw-1:0] spr_dat_tt;
wire sig_tick;
output wire sig_tick; // jb
 
//
// Debug port and caches/MMUs
454,17 → 474,31
wire [dw-1:0] du_dat_du;
wire du_read;
wire du_write;
wire [12:0] du_except;
wire [12:0] du_except_trig;
wire [12:0] du_except_stop;
wire [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
wire [24:0] du_dmr1;
wire [dw-1:0] du_dat_cpu;
wire [dw-1:0] du_lsu_store_dat;
wire [dw-1:0] du_lsu_load_dat;
wire du_hwbkpt;
 
wire du_hwbkpt_ls_r = 1'b0;
wire flushpipe;
wire ex_freeze;
wire wb_freeze;
wire id_void;
wire ex_void;
wire [31:0] id_insn;
wire [31:0] ex_insn;
wire [31:0] wb_insn;
wire [31:0] id_pc;
wire [31:0] ex_pc;
wire [31:0] wb_pc;
wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
wire [31:0] spr_dat_npc;
wire [31:0] rf_dataw;
wire abort_ex;
wire abort_mvspr;
 
`ifdef OR1200_BIST
//
474,7 → 508,7
wire mbist_ic_so;
wire mbist_dmmu_so;
wire mbist_dc_so;
wire mbist_qmem_so;
wire mbist_qmem_so;
wire mbist_immu_si = mbist_si_i;
wire mbist_ic_si = mbist_immu_so;
wire mbist_qmem_si = mbist_ic_so;
490,7 → 524,7
//
// Instantiation of Instruction WISHBONE BIU
//
or1200_iwb_biu iwb_biu(
or1200_wb_biu iwb_biu(
// RISC clk, rst and clock control
.clk(clk_i),
.rst(rst_i),
519,7 → 553,7
 
// Internal RISC bus
.biu_dat_i(icbiu_dat_ic),
.biu_adr_i(icbiu_adr_ic),
.biu_adr_i(icbiu_adr_ic_word),
.biu_cyc_i(icbiu_cyc_ic),
.biu_stb_i(icbiu_stb_ic),
.biu_we_i(icbiu_we_ic),
529,6 → 563,7
.biu_ack_o(icbiu_ack_biu),
.biu_err_o(icbiu_err_biu)
);
assign icbiu_adr_ic_word = {icbiu_adr_ic[31:2], 2'h0};
 
//
// Instantiation of Data WISHBONE BIU
599,6 → 634,9
.icpu_rty_o(icpu_rty_immu),
.icpu_err_o(icpu_err_immu),
 
// SR Interface
.boot_adr_sel_i(boot_adr_sel),
 
// SPR access
.spr_cs(spr_cs[`OR1200_SPR_GROUP_IMMU]),
.spr_write(spr_we),
681,22 → 719,36
.icpu_tag_i(icpu_tag_immu),
 
// Connection CPU to external Debug port
.id_void(id_void),
.id_insn(id_insn),
.ex_void(ex_void),
.ex_insn(ex_insn),
.ex_freeze(ex_freeze),
.ex_insn(ex_insn),
.wb_insn(wb_insn),
.wb_freeze(wb_freeze),
.id_pc(id_pc),
.ex_pc(ex_pc),
.wb_pc(wb_pc),
.branch_op(branch_op),
.rf_dataw(rf_dataw),
.ex_flushpipe(flushpipe),
.du_stall(du_stall),
.du_addr(du_addr),
.du_dat_du(du_dat_du),
.du_read(du_read),
.du_write(du_write),
.du_except_trig(du_except_trig),
.du_except_stop(du_except_stop),
.du_dsr(du_dsr),
.du_except(du_except),
.du_dmr1(du_dmr1),
.du_hwbkpt(du_hwbkpt),
.du_hwbkpt_ls_r(du_hwbkpt_ls_r),
.du_dat_cpu(du_dat_cpu),
.du_hwbkpt(du_hwbkpt),
.rf_dataw(rf_dataw),
.du_lsu_store_dat(du_lsu_store_dat),
.du_lsu_load_dat(du_lsu_load_dat),
.abort_mvspr(abort_mvspr),
.abort_ex(abort_ex),
 
 
// Connection IMMU and CPU internally
.immu_en(immu_en),
 
717,6 → 769,12
// Connection DMMU and CPU internally
.dmmu_en(dmmu_en),
 
// SR Interface
.boot_adr_sel_i(boot_adr_sel),
 
// SB Enable
.sb_en(sb_en),
 
// Connection PIC and CPU's EXCEPT
.sig_int(sig_int),
.sig_tick(sig_tick),
898,6 → 956,9
.clk(clk_i),
.rst(rst_i),
 
// Internal RISC bus (SB)
.sb_en(sb_en),
 
// Internal RISC bus (DC<->SB)
.dcsb_dat_i(dcsb_dat_dc),
.dcsb_adr_i(dcsb_adr_dc),
941,6 → 1002,7
.ex_insn(ex_insn),
.id_pc(id_pc),
.du_dsr(du_dsr),
.du_dmr1(du_dmr1),
 
// For Trace buffer
.spr_dat_npc(spr_dat_npc),
953,7 → 1015,7
.du_dat_o(du_dat_du),
.du_read(du_read),
.du_write(du_write),
.du_except(du_except),
.du_except_stop(du_except_stop),
.du_hwbkpt(du_hwbkpt),
 
// Access to DU's SPRs
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_512x20.v
63,7 → 63,14
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: or1200_spram_512x20.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Coding style changed.
//
// Revision 1.9 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
289,7 → 296,7
//
RAMB4_S8 ramb4_s8_0(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[7:0]),
.EN(ce),
302,7 → 309,7
//
RAMB4_S8 ramb4_s8_1(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI(di[15:8]),
.EN(ce),
315,7 → 322,7
//
RAMB4_S8 ramb4_s8_2(
.CLK(clk),
.RST(rst),
.RST(1'b0),
.ADDR(addr),
.DI({4'b0000, di[19:16]}),
.EN(ce),
337,7 → 344,7
 
RAMB16_S36 ramb16_s36(
.CLK(clk),
.SSR(rst),
.SSR(1'b0),
.ADDR(addr),
.DI({12'h000,di}),
.DIP(4'h0),
/openrisc/trunk/or1200/rtl/verilog/or1200_dpram.v
0,0 → 1,147
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Double-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common double-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// double-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dpram_32x32.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// New
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_dpram
(
// Generic synchronous double-port RAM interface
clk_a, ce_a, addr_a, do_a,
clk_b, ce_b, we_b, addr_b, di_b
);
//
// Default address and data buses width
//
parameter aw = 5;
parameter dw = 32;
//
// Generic synchronous double-port RAM interface
//
input clk_a; // Clock
input ce_a; // Chip enable input
input [aw-1:0] addr_a; // address bus inputs
output [dw-1:0] do_a; // output data bus
input clk_b; // Clock
input ce_b; // Chip enable input
input we_b; // Write enable input
input [aw-1:0] addr_b; // address bus inputs
input [dw-1:0] di_b; // input data bus
//
// Internal wires and registers
//
//
// Generic double-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_a_reg; // RAM address registered
 
 
// Function to access GPRs (for use by Verilator). No need to hide this one
// from the simulator, since it has an input (as required by IEEE 1364-2001).
function [31:0] get_gpr;
// verilator public
input [aw-1:0] gpr_no;
 
get_gpr = { mem[gpr_no*32 + 31], mem[gpr_no*32 + 30],
mem[gpr_no*32 + 29], mem[gpr_no*32 + 28],
mem[gpr_no*32 + 27], mem[gpr_no*32 + 26],
mem[gpr_no*32 + 25], mem[gpr_no*32 + 24],
mem[gpr_no*32 + 23], mem[gpr_no*32 + 22],
mem[gpr_no*32 + 21], mem[gpr_no*32 + 20],
mem[gpr_no*32 + 19], mem[gpr_no*32 + 18],
mem[gpr_no*32 + 17], mem[gpr_no*32 + 16],
mem[gpr_no*32 + 15], mem[gpr_no*32 + 14],
mem[gpr_no*32 + 13], mem[gpr_no*32 + 12],
mem[gpr_no*32 + 11], mem[gpr_no*32 + 10],
mem[gpr_no*32 + 9], mem[gpr_no*32 + 8],
mem[gpr_no*32 + 7], mem[gpr_no*32 + 6],
mem[gpr_no*32 + 5], mem[gpr_no*32 + 4],
mem[gpr_no*32 + 3], mem[gpr_no*32 + 2],
mem[gpr_no*32 + 1], mem[gpr_no*32 + 0] };
endfunction // get_gpr
//
// Data output drivers
//
//assign do_a = (oe_a) ? mem[addr_a_reg] : {dw{1'b0}};
assign do_a = mem[addr_a_reg];
//
// RAM read
//
always @(posedge clk_a)
if (ce_a)
addr_a_reg <= #1 addr_a;
//
// RAM write
//
always @(posedge clk_b)
if (ce_b & we_b)
mem[addr_b] <= #1 di_b;
endmodule // or1200_dpram
/openrisc/trunk/or1200/rtl/verilog/or1200_wb_biu.v
48,7 → 48,14
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: or1200_wb_biu.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Major update:
// Structure reordered and bugs fixed.
//
// Revision 1.7 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.6.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
129,350 → 136,315
//
// RISC clock, reset and clock control
//
input clk; // RISC clock
input rst; // RISC reset
input [1:0] clmode; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
input clk; // RISC clock
input rst; // RISC reset
input [1:0] clmode; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
 
//
// WISHBONE interface
//
input wb_clk_i; // clock input
input wb_rst_i; // reset input
input wb_ack_i; // normal termination
input wb_err_i; // termination w/ error
input wb_rty_i; // termination w/ retry
input [dw-1:0] wb_dat_i; // input data bus
output wb_cyc_o; // cycle valid output
output [aw-1:0] wb_adr_o; // address bus outputs
output wb_stb_o; // strobe output
output wb_we_o; // indicates write transfer
output [3:0] wb_sel_o; // byte select outputs
output [dw-1:0] wb_dat_o; // output data bus
input wb_clk_i; // clock input
input wb_rst_i; // reset input
input wb_ack_i; // normal termination
input wb_err_i; // termination w/ error
input wb_rty_i; // termination w/ retry
input [dw-1:0] wb_dat_i; // input data bus
output wb_cyc_o; // cycle valid output
output [aw-1:0] wb_adr_o; // address bus outputs
output wb_stb_o; // strobe output
output wb_we_o; // indicates write transfer
output [3:0] wb_sel_o; // byte select outputs
output [dw-1:0] wb_dat_o; // output data bus
`ifdef OR1200_WB_CAB
output wb_cab_o; // consecutive address burst
output wb_cab_o; // consecutive address burst
`endif
`ifdef OR1200_WB_B3
output [2:0] wb_cti_o; // cycle type identifier
output [1:0] wb_bte_o; // burst type extension
output [2:0] wb_cti_o; // cycle type identifier
output [1:0] wb_bte_o; // burst type extension
`endif
 
//
// Internal RISC interface
//
input [dw-1:0] biu_dat_i; // input data bus
input [aw-1:0] biu_adr_i; // address bus
input biu_cyc_i; // WB cycle
input biu_stb_i; // WB strobe
input biu_we_i; // WB write enable
input biu_cab_i; // CAB input
input [3:0] biu_sel_i; // byte selects
output [31:0] biu_dat_o; // output data bus
output biu_ack_o; // ack output
output biu_err_o; // err output
input [dw-1:0] biu_dat_i; // input data bus
input [aw-1:0] biu_adr_i; // address bus
input biu_cyc_i; // WB cycle
input biu_stb_i; // WB strobe
input biu_we_i; // WB write enable
input biu_cab_i; // CAB input
input [3:0] biu_sel_i; // byte selects
output [31:0] biu_dat_o; // output data bus
output biu_ack_o; // ack output
output biu_err_o; // err output
 
//
// Registers
//
reg [1:0] valid_div; // Used for synchronization
`ifdef OR1200_REGISTERED_OUTPUTS
reg [aw-1:0] wb_adr_o; // address bus outputs
reg wb_cyc_o; // cycle output
reg wb_stb_o; // strobe output
reg wb_we_o; // indicates write transfer
reg [3:0] wb_sel_o; // byte select outputs
wire wb_ack; // normal termination
reg [aw-1:0] wb_adr_o; // address bus outputs
reg wb_cyc_o; // cycle output
reg wb_stb_o; // strobe output
reg wb_we_o; // indicates write transfer
reg [3:0] wb_sel_o; // byte select outputs
`ifdef OR1200_WB_CAB
reg wb_cab_o; // CAB output
reg wb_cab_o; // CAB output
`endif
`ifdef OR1200_WB_B3
reg [1:0] burst_len; // burst counter
reg [2:0] wb_cti_o; // cycle type identifier
reg [2:0] wb_cti_o; // cycle type identifier
reg [1:0] wb_bte_o; // burst type extension
`endif
reg [dw-1:0] wb_dat_o; // output data bus
`endif
`ifdef OR1200_REGISTERED_INPUTS
reg long_ack_o; // normal termination
reg long_err_o; // error termination
reg [dw-1:0] biu_dat_o; // output data bus
`else
wire long_ack_o; // normal termination
wire long_err_o; // error termination
`endif
wire aborted; // Graceful abort
reg aborted_r; // Graceful abort
wire retry; // Retry
reg [dw-1:0] wb_dat_o; // output data bus
 
`ifdef OR1200_WB_RETRY
reg [`OR1200_WB_RETRY-1:0] retry_cntr; // Retry counter
`endif
 
//
// WISHBONE I/F <-> Internal RISC I/F conversion
//
 
//
// Address bus
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_adr_o <= #1 {aw{1'b0}};
else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted & ~(wb_stb_o & ~wb_ack_i))
wb_adr_o <= #1 biu_adr_i;
reg [`OR1200_WB_RETRY-1:0] retry_cnt; // Retry counter
`else
assign wb_adr_o = biu_adr_i;
wire retry_cnt = 1'b0;
`endif
 
//
// Input data bus
//
`ifdef OR1200_REGISTERED_INPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
biu_dat_o <= #1 32'h0000_0000;
else if (wb_ack_i)
biu_dat_o <= #1 wb_dat_i;
`else
assign biu_dat_o = wb_dat_i;
`ifdef OR1200_WB_B3
reg [1:0] burst_len; // burst counter
`endif
 
//
// Output data bus
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_dat_o <= #1 {dw{1'b0}};
else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted)
wb_dat_o <= #1 biu_dat_i;
`else
assign wb_dat_o = biu_dat_i;
`endif
reg biu_stb_reg; // WB strobe
wire biu_stb; // WB strobe
reg wb_cyc_nxt; // next WB cycle value
reg wb_stb_nxt; // next WB strobe value
reg [2:0] wb_cti_nxt; // next cycle type identifier value
 
//
// Valid_div counts RISC clock cycles by modulo 4
// and is used to synchronize external WB i/f to
// RISC clock
//
always @(posedge clk or posedge rst)
if (rst)
valid_div <= #1 2'b0;
else
valid_div <= #1 valid_div + 1'd1;
reg wb_ack_cnt; // WB ack toggle counter
reg wb_err_cnt; // WB err toggle counter
reg wb_rty_cnt; // WB rty toggle counter
reg biu_ack_cnt; // BIU ack toggle counter
reg biu_err_cnt; // BIU err toggle counter
reg biu_rty_cnt; // BIU rty toggle counter
wire biu_rty; // BIU rty indicator
 
//
// biu_ack_o is one RISC clock cycle long long_ack_o.
// long_ack_o is one, two or four RISC clock cycles long because
// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.
//
assign biu_ack_o = long_ack_o
`ifdef OR1200_CLKDIV_2_SUPPORTED
& (valid_div[0] | ~clmode[0])
`ifdef OR1200_CLKDIV_4_SUPPORTED
& (valid_div[1] | ~clmode[1])
`endif
`endif
;
reg [1:0] wb_fsm_state_cur; // WB FSM - surrent state
reg [1:0] wb_fsm_state_nxt; // WB FSM - next state
wire [1:0] wb_fsm_idle = 2'h0; // WB FSM state - IDLE
wire [1:0] wb_fsm_trans = 2'h1; // WB FSM state - normal TRANSFER
wire [1:0] wb_fsm_last = 2'h2; // EB FSM state - LAST transfer
 
//
// Acknowledgment of the data to the RISC
// WISHBONE I/F <-> Internal RISC I/F conversion
//
// long_ack_o
//
`ifdef OR1200_REGISTERED_INPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
long_ack_o <= #1 1'b0;
else
long_ack_o <= #1 wb_ack_i & ~aborted;
`else
assign long_ack_o = wb_ack_i & ~aborted_r;
`endif
//assign wb_ack = wb_ack_i;
assign wb_ack = wb_ack_i && !wb_err_i && !wb_rty_i;
 
//
// biu_err_o is one RISC clock cycle long long_err_o.
// long_err_o is one, two or four RISC clock cycles long because
// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.
//
assign biu_err_o = long_err_o
`ifdef OR1200_CLKDIV_2_SUPPORTED
& (valid_div[0] | ~clmode[0])
`ifdef OR1200_CLKDIV_4_SUPPORTED
& (valid_div[1] | ~clmode[1])
`endif
`endif
;
// WB FSM - register part
//
always @(posedge wb_clk_i or posedge wb_rst_i) begin
if (wb_rst_i)
wb_fsm_state_cur <= #1 wb_fsm_idle;
else
wb_fsm_state_cur <= #1 wb_fsm_state_nxt;
end
 
//
// Error termination
//
// long_err_o
//
`ifdef OR1200_REGISTERED_INPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
long_err_o <= #1 1'b0;
else
long_err_o <= #1 wb_err_i & ~aborted;
`else
assign long_err_o = wb_err_i & ~aborted_r;
`endif
// WB burst tength counter
//
always @(posedge wb_clk_i or posedge wb_rst_i) begin
if (wb_rst_i) begin
burst_len <= #1 2'h0;
end
else begin
// burst counter
if (wb_fsm_state_cur == wb_fsm_idle)
burst_len <= #1 2'h2;
else if (wb_stb_o && wb_ack)
burst_len <= #1 burst_len - 1'b1;
end
end
 
//
// Retry counter
//
// Assert 'retry' when 'wb_rty_i' is sampled high and keep it high
// until retry counter doesn't expire
//
`ifdef OR1200_WB_RETRY
assign retry = wb_rty_i | (|retry_cntr);
`else
assign retry = 1'b0;
`endif
`ifdef OR1200_WB_RETRY
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
retry_cntr <= #1 1'b0;
else if (wb_rty_i)
retry_cntr <= #1 {`OR1200_WB_RETRY{1'b1}};
else if (retry_cntr)
retry_cntr <= #1 retry_cntr - 7'd1;
`endif
// WB FSM - combinatorial part
//
always @(wb_fsm_state_cur or burst_len or
wb_err_i or wb_rty_i or wb_ack or wb_cti_o or wb_sel_o or wb_stb_o or wb_we_o or
biu_cyc_i or biu_stb or biu_cab_i or biu_sel_i or biu_we_i) begin
// States of WISHBONE Finite State Machine
case(wb_fsm_state_cur)
// IDLE
wb_fsm_idle : begin
wb_cyc_nxt = biu_cyc_i && biu_stb;
wb_stb_nxt = biu_cyc_i && biu_stb;
wb_cti_nxt = {!biu_cab_i, 1'b1, !biu_cab_i};
if (biu_cyc_i && biu_stb)
wb_fsm_state_nxt = wb_fsm_trans;
else
wb_fsm_state_nxt = wb_fsm_idle;
end
// normal TRANSFER
wb_fsm_trans : begin
wb_cyc_nxt = !wb_stb_o || !wb_err_i && !wb_rty_i && !(wb_ack && wb_cti_o == 3'b111);
wb_stb_nxt = !wb_stb_o || !wb_err_i && !wb_rty_i && !wb_ack || !wb_err_i && !wb_rty_i && wb_cti_o == 3'b010 && !wb_we_o;
wb_cti_nxt[2] = wb_stb_o && wb_ack && burst_len == 'h0 || wb_cti_o[2];
wb_cti_nxt[1] = 1'b1 ;
wb_cti_nxt[0] = wb_stb_o && wb_ack && burst_len == 'h0 || wb_cti_o[0];
//if ((!biu_cyc_i || !biu_stb || !biu_cab_i) && wb_cti_o == 3'b010 || biu_sel_i != wb_sel_o || biu_we_i != wb_we_o)
if ((!biu_cyc_i || !biu_stb || !biu_cab_i || biu_sel_i != wb_sel_o || biu_we_i != wb_we_o) && wb_cti_o == 3'b010)
wb_fsm_state_nxt = wb_fsm_last;
else if ((wb_err_i || wb_rty_i || wb_ack && wb_cti_o == 3'b111) && wb_stb_o)
wb_fsm_state_nxt = wb_fsm_idle;
else
wb_fsm_state_nxt = wb_fsm_trans;
end
// LAST transfer
wb_fsm_last : begin
wb_cyc_nxt = !wb_stb_o || !wb_err_i && !wb_rty_i && !(wb_ack && wb_cti_o == 3'b111);
wb_stb_nxt = !wb_stb_o || !wb_err_i && !wb_rty_i && !(wb_ack && wb_cti_o == 3'b111);
wb_cti_nxt[2] = wb_ack && wb_stb_o || wb_cti_o[2];
wb_cti_nxt[1] = 1'b1 ;
wb_cti_nxt[0] = wb_ack && wb_stb_o || wb_cti_o[0];
if ((wb_err_i || wb_rty_i || wb_ack && wb_cti_o == 3'b111) && wb_stb_o)
wb_fsm_state_nxt = wb_fsm_idle;
else
wb_fsm_state_nxt = wb_fsm_last;
end
// default state
default:begin
wb_cyc_nxt = 1'bx;
wb_stb_nxt = 1'bx;
wb_cti_nxt = 3'bxxx;
wb_fsm_state_nxt = 2'bxx;
end
endcase
end
 
//
// Graceful completion of aborted transfers
//
// Assert 'aborted' when 1) current transfer is in progress (wb_stb_o; which
// we know is only asserted together with wb_cyc_o) 2) and in next WB clock cycle
// wb_stb_o would be deasserted (biu_cyc_i and biu_stb_i are low) 3) and
// there is no termination of current transfer in this WB clock cycle (wb_ack_i
// and wb_err_i are low).
// 'aborted_r' is registered 'aborted' and extended until this "aborted" transfer
// is properly terminated with wb_ack_i/wb_err_i.
// WB FSM - output signals
//
assign aborted = wb_stb_o & ~(biu_cyc_i & biu_stb_i) & ~(wb_ack_i | wb_err_i);
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
aborted_r <= #1 1'b0;
else if (wb_ack_i | wb_err_i)
aborted_r <= #1 1'b0;
else if (aborted)
aborted_r <= #1 1'b1;
 
//
// WB cyc_o
//
// Either 1) normal transfer initiated by biu_cyc_i (and biu_cab_i if
// bursts are enabled) and possibly suspended by 'retry'
// or 2) extended "aborted" transfer
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_cyc_o <= #1 1'b0;
else
`ifdef OR1200_NO_BURSTS
wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry | aborted & ~wb_ack_i;
`else
wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry | biu_cab_i | aborted & ~wb_ack_i;
always @(posedge wb_clk_i or posedge wb_rst_i) begin
if (wb_rst_i) begin
wb_cyc_o <= #1 1'b0;
wb_stb_o <= #1 1'b0;
wb_cti_o <= #1 3'b111;
wb_bte_o <= #1 2'b01; // 4-beat wrap burst = constant
`ifdef OR1200_WB_CAB
wb_cab_o <= #1 1'b0;
`endif
`else
`ifdef OR1200_NO_BURSTS
assign wb_cyc_o = biu_cyc_i & ~retry;
`else
assign wb_cyc_o = biu_cyc_i | biu_cab_i & ~retry;
wb_we_o <= #1 1'b0;
wb_sel_o <= #1 4'hf;
wb_adr_o <= #1 {aw{1'b0}};
wb_dat_o <= #1 {dw{1'b0}};
end
else begin
wb_cyc_o <= #1 wb_cyc_nxt;
// wb_stb_o <= #1 wb_stb_nxt;
if (wb_ack && wb_cti_o == 3'b111)
wb_stb_o <= #1 1'b0;
else
wb_stb_o <= #1 wb_stb_nxt;
wb_cti_o <= #1 wb_cti_nxt;
wb_bte_o <= #1 2'b01; // 4-beat wrap burst = constant
`ifdef OR1200_WB_CAB
wb_cab_o <= #1 biu_cab_i;
`endif
`endif
// we and sel - set at beginning of access
if (wb_fsm_state_cur == wb_fsm_idle) begin
wb_we_o <= #1 biu_we_i;
wb_sel_o <= #1 biu_sel_i;
end
// adr - set at beginning of access and changed at every termination
if (wb_fsm_state_cur == wb_fsm_idle) begin
wb_adr_o <= #1 biu_adr_i;
end
else if (wb_stb_o && wb_ack) begin
wb_adr_o[3:2] <= #1 wb_adr_o[3:2] + 1'b1;
end
// dat - write data changed after avery subsequent write access
if (!wb_stb_o) begin
wb_dat_o <= #1 biu_dat_i;
end
end
end
 
//
// WB stb_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_stb_o <= #1 1'b0;
else
wb_stb_o <= #1 (biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~retry | aborted & ~wb_ack_i;
`else
assign wb_stb_o = biu_cyc_i & biu_stb_i;
`endif
// WB & BIU termination toggle counters
//
always @(posedge wb_clk_i or posedge wb_rst_i) begin
if (wb_rst_i) begin
wb_ack_cnt <= #1 1'b0;
wb_err_cnt <= #1 1'b0;
wb_rty_cnt <= #1 1'b0;
end
else begin
// WB ack toggle counter
if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
wb_ack_cnt <= #1 1'b0;
else if (wb_stb_o && wb_ack)
wb_ack_cnt <= #1 !wb_ack_cnt;
// WB err toggle counter
if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
wb_err_cnt <= #1 1'b0;
else if (wb_stb_o && wb_err_i)
wb_err_cnt <= #1 !wb_err_cnt;
// WB rty toggle counter
if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
wb_rty_cnt <= #1 1'b0;
else if (wb_stb_o && wb_rty_i)
wb_rty_cnt <= #1 !wb_rty_cnt;
end
end
 
//
// WB we_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_we_o <= #1 1'b0;
else
wb_we_o <= #1 biu_cyc_i & biu_stb_i & biu_we_i | aborted & wb_we_o;
`else
assign wb_we_o = biu_cyc_i & biu_stb_i & biu_we_i;
always @(posedge clk or posedge rst) begin
if (rst) begin
biu_stb_reg <= #1 1'b0;
biu_ack_cnt <= #1 1'b0;
biu_err_cnt <= #1 1'b0;
biu_rty_cnt <= #1 1'b0;
`ifdef OR1200_WB_RETRY
retry_cnt <= {`OR1200_WB_RETRY{1'b0}};
`endif
 
//
// WB sel_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_sel_o <= #1 4'b0000;
else
wb_sel_o <= #1 biu_sel_i;
`else
assign wb_sel_o = biu_sel_i;
end
else begin
// BIU strobe
if (biu_stb_i && !biu_cab_i && biu_ack_o)
biu_stb_reg <= #1 1'b0;
else
biu_stb_reg <= #1 biu_stb_i;
// BIU ack toggle counter
if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
biu_ack_cnt <= #1 1'b0 ;
else if (biu_ack_o)
biu_ack_cnt <= #1 !biu_ack_cnt ;
// BIU err toggle counter
if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
biu_err_cnt <= #1 1'b0 ;
else if (wb_err_i && biu_err_o)
biu_err_cnt <= #1 !biu_err_cnt ;
// BIU rty toggle counter
if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
biu_rty_cnt <= #1 1'b0 ;
else if (biu_rty)
biu_rty_cnt <= #1 !biu_rty_cnt ;
`ifdef OR1200_WB_RETRY
if (biu_ack_o || biu_err_o)
retry_cnt <= #1 {`OR1200_WB_RETRY{1'b0}};
else if (biu_rty)
retry_cnt <= #1 retry_cnt + 1'b1;
`endif
end
end
 
`ifdef OR1200_WB_CAB
//
// WB cab_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_cab_o <= #1 1'b0;
else
wb_cab_o <= #1 biu_cab_i;
`else
assign wb_cab_o = biu_cab_i;
`endif
`endif
assign biu_stb = biu_stb_i && biu_stb_reg;
 
`ifdef OR1200_WB_B3
//
// Count burst beats
// Input BIU data bus
//
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
burst_len <= #1 2'b00;
else if (biu_cab_i && burst_len && wb_ack_i)
burst_len <= #1 burst_len - 1'b1;
else if (~biu_cab_i)
burst_len <= #1 2'b11;
assign biu_dat_o = wb_dat_i;
 
//
// WB cti_o
// Input BIU termination signals
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_cti_o <= #1 3'b000; // classic cycle
`ifdef OR1200_NO_BURSTS
else
wb_cti_o <= #1 3'b111; // end-of-burst
assign biu_rty = (wb_fsm_state_cur == wb_fsm_trans) && wb_rty_i && wb_stb_o && (wb_rty_cnt ~^ biu_rty_cnt);
assign biu_ack_o = (wb_fsm_state_cur == wb_fsm_trans) && wb_ack && wb_stb_o && (wb_ack_cnt ~^ biu_ack_cnt);
assign biu_err_o = (wb_fsm_state_cur == wb_fsm_trans) && wb_err_i && wb_stb_o && (wb_err_cnt ~^ biu_err_cnt)
`ifdef OR1200_WB_RETRY
|| biu_rty && retry_cnt[`OR1200_WB_RETRY-1];
`else
else if (biu_cab_i && burst_len[1])
wb_cti_o <= #1 3'b010; // incrementing burst cycle
else if (biu_cab_i && wb_ack_i)
wb_cti_o <= #1 3'b111; // end-of-burst
`endif // OR1200_NO_BURSTS
`else
Unsupported !!!;
;
`endif
 
//
// WB bte_o
//
assign wb_bte_o = 2'b01; // 4-beat wrap burst
 
`endif // OR1200_WB_B3
 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.