URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
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- This comparison shows the changes necessary to convert path
/
- from Rev 1411 to Rev 1412
- ↔ Reverse comparison
Rev 1411 → Rev 1412
/trunk/or1ksim/mmu/dmmu.c
36,6 → 36,8
#include "sim-config.h" |
#include "debug.h" |
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DEFAULT_DEBUG_CHANNEL(dmmu); |
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extern int cont_run; |
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/* Data MMU */ |
66,7 → 68,8
/* Did we find our tlb entry? */ |
if (way >= 0) { /* Yes, we did. */ |
dmmu_stats.loads_tlbhit++; |
debug(5, "DTLB hit (virtaddr=%"PRIxADDR").\n", virtaddr); |
TRACE("DTLB hit (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr, |
runtime.sim.cycles); |
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/* Test for page fault */ |
if (mfspr (SPR_SR) & SPR_SR_SM) { |
108,6 → 111,8
setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_V, 1); |
#endif |
except_handle(EXCEPT_DTLBMISS, virtaddr); |
TRACE("DTLB miss (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr, |
runtime.sim.cycles); |
/* if tlb refill implemented in HW */ |
/* return getsprbits(SPR_DTLBTR_BASE(minway) + set, SPR_DTLBTR_PPN) * config.dmmu.pagesize + (virtaddr % config.dmmu.pagesize); */ |
runtime.sim.mem_cycles += config.dmmu.missdelay; |
159,7 → 164,8
/* Did we find our tlb entry? */ |
if (way >= 0) { /* Yes, we did. */ |
dmmu_stats.loads_tlbhit++; |
debug(5, "DTLB hit (virtaddr=%"PRIxADDR").\n", virtaddr); |
TRACE("DTLB hit (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr, |
runtime.sim.cycles); |
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/* Test for page fault */ |
if (mfspr (SPR_SR) & SPR_SR_SM) { |
188,7 → 194,7
return(0); |
} |
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PRINTF("ERR, should never have happened\n"); |
ERR("ERR, should never have happened\n"); |
return(0); |
} |
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/trunk/or1ksim/support/dbchs.h
20,5 → 20,6
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/* Declatrations of all debug channels */ |
DECLARE_DEBUG_CHANNEL(sched) |
DECLARE_DEBUG_CHANNEL(dmmu) |
DECLARE_DEBUG_CHANNEL(tick) |
DECLARE_DEBUG_CHANNEL(uart) |