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URL https://opencores.org/ocsvn/or1k/or1k/trunk

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  • This comparison shows the changes necessary to convert path
    /
    from Rev 1417 to Rev 1418
    Reverse comparison

Rev 1417 → Rev 1418

/trunk/or1ksim/mmu/immu.c
72,15 → 72,6
immu_stats.fetch_tlbhit++;
TRACE("ITLB hit (virtaddr=%"PRIxADDR").\n", virtaddr);
/* Test for page fault */
if (mfspr (SPR_SR) & SPR_SR_SM) {
if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_SXE))
except_handle(EXCEPT_IPF, virtaddr);
} else {
if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_UXE))
except_handle(EXCEPT_IPF, virtaddr);
}
 
/* Set LRUs */
for (i = 0; i < config.immu.nways; i++)
if (testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU))
91,6 → 82,16
insn_ci = (mfspr(SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_CI) == SPR_ITLBTR_CI;
 
runtime.sim.mem_cycles += config.immu.hitdelay;
 
/* Test for page fault */
if (mfspr (SPR_SR) & SPR_SR_SM) {
if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_SXE))
except_handle(EXCEPT_IPF, virtaddr);
} else {
if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_UXE))
except_handle(EXCEPT_IPF, virtaddr);
}
 
ppn = mfspr(SPR_ITLBTR_BASE(way) + set) / config.immu.pagesize;
return (ppn * config.immu.pagesize) + (virtaddr % config.immu.pagesize);
}
109,10 → 110,12
setsprbits(SPR_ITLBTR_BASE(minway) + set, SPR_ITLBTR_PPN, vpn); /* 1 to 1 */
setsprbits(SPR_ITLBMR_BASE(minway) + set, SPR_ITLBMR_V, 1);
#endif
except_handle(EXCEPT_ITLBMISS, virtaddr);
 
/* if tlb refill implemented in HW */
/* return getsprbits(SPR_ITLBTR_BASE(minway) + set, SPR_ITLBTR_PPN) * config.immu.pagesize + (virtaddr % config.immu.pagesize); */
runtime.sim.mem_cycles += config.immu.missdelay;
 
except_handle(EXCEPT_ITLBMISS, virtaddr);
return 0;
}
}

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