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URL https://opencores.org/ocsvn/or1k/or1k/trunk

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  • This comparison shows the changes necessary to convert path
    /
    from Rev 1425 to Rev 1426
    Reverse comparison

Rev 1425 → Rev 1426

/trunk/or1ksim/pic/pic.c
38,10 → 38,11
#include "spr_defs.h"
#include "except.h"
#include "sprs.h"
#include "sched.h"
#include "debug.h"
#include "sched.h"
 
extern int cont_run;
DEFAULT_DEBUG_CHANNEL(pic);
 
/* Reset. It initializes PIC registers. */
void pic_reset()
52,14 → 53,14
mtspr(SPR_PICSR, 0);
}
 
/* Simulation hook. Called when interrupts are masked. */
void pic_clock(int i)
/* Handles the reporting of an interrupt if it had to be delayed */
void pic_clock(void *dat)
{
/* Don't do anything if interrupts not currently enabled */
if(testsprbits (SPR_SR, SPR_SR_IEE))
except_handle(EXCEPT_INT, mfspr(SPR_EEAR_BASE));
else
SCHED_ADD(pic_clock, 0, 1);
SCHED_ADD(pic_clock, NULL, 1);
}
 
/* WARNING: Don't eaven try and call this function *during* a simulated
71,15 → 72,16
setsprbits(SPR_PMR, SPR_PMR_DME, 0); /* Disable doze mode */
setsprbits(SPR_PMR, SPR_PMR_SME, 0); /* Disable sleep mode */
 
debug(4, "Asserting interrupt %d (%s).\n", line, getsprbit(SPR_PICMR, line) ? "Unmasked" : "Masked");
TRACE("Asserting interrupt %d (%s).\n", line, getsprbit(SPR_PICMR, line) ? "Unmasked" : "Masked");
 
if (getsprbit(SPR_PICMR, line) || line < 2) {
setsprbit(SPR_PICSR, line, 1);
/* Don't do anything if interrupts not currently enabled */
if (testsprbits (SPR_SR, SPR_SR_IEE))
if (testsprbits (SPR_SR, SPR_SR_IEE)) {
except_handle(EXCEPT_INT, mfspr(SPR_EEAR_BASE));
else
TRACE("Delivering interrupt on cycle %lli\n", runtime.sim.cycles);
} else
/* Interrupts not currently enabled, retry next clock cycle */
SCHED_ADD(pic_clock, 0, runtime.sim.cycles + 1);
SCHED_ADD(pic_clock, NULL, 1);
}
}
/trunk/or1ksim/support/dbchs.h
22,5 → 22,6
DECLARE_DEBUG_CHANNEL(sched)
DECLARE_DEBUG_CHANNEL(immu)
DECLARE_DEBUG_CHANNEL(dmmu)
DECLARE_DEBUG_CHANNEL(pic)
DECLARE_DEBUG_CHANNEL(tick)
DECLARE_DEBUG_CHANNEL(uart)

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