OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 143 to Rev 144
    ↔ Reverse comparison
  •

Rev 143 → Rev 144

/trunk/rtl/verilog/dbg_top.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.44 2004/03/28 20:27:02 igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.43 2004/03/22 16:35:46 igorm
// Temp version before changing dbg interface.
//
236,20 → 239,36
wb_bte_o
`endif
 
`ifdef DBG_CPU_SUPPORTED
`ifdef DBG_CPU0_SUPPORTED
// CPU signals
,
cpu_clk_i,
cpu_addr_o,
cpu_data_i,
cpu_data_o,
cpu_bp_i,
cpu_stall_o,
cpu_stb_o,
cpu_we_o,
cpu_ack_i,
cpu_rst_o
cpu0_clk_i,
cpu0_addr_o,
cpu0_data_i,
cpu0_data_o,
cpu0_bp_i,
cpu0_stall_o,
cpu0_stb_o,
cpu0_we_o,
cpu0_ack_i,
cpu0_rst_o
`endif
 
`ifdef DBG_CPU1_SUPPORTED
// CPU signals
,
cpu1_clk_i,
cpu1_addr_o,
cpu1_data_i,
cpu1_data_o,
cpu1_bp_i,
cpu1_stall_o,
cpu1_stb_o,
cpu1_we_o,
cpu1_ack_i,
cpu1_rst_o
`endif
 
);
 
 
293,31 → 312,54
wire shift_crc_wb = 1'b0;
`endif
 
`ifdef DBG_CPU_SUPPORTED
`ifdef DBG_CPU0_SUPPORTED
// CPU signals
input cpu_clk_i;
output [31:0] cpu_addr_o;
input [31:0] cpu_data_i;
output [31:0] cpu_data_o;
input cpu_bp_i;
output cpu_stall_o;
output cpu_stb_o;
output cpu_we_o;
input cpu_ack_i;
output cpu_rst_o;
input cpu0_clk_i;
output [31:0] cpu0_addr_o;
input [31:0] cpu0_data_i;
output [31:0] cpu0_data_o;
input cpu0_bp_i;
output cpu0_stall_o;
output cpu0_stb_o;
output cpu0_we_o;
input cpu0_ack_i;
output cpu0_rst_o;
 
reg cpu_debug_module;
reg cpu_ce;
wire tdi_cpu;
wire tdo_cpu;
wire crc_en_cpu;
wire shift_crc_cpu;
reg cpu0_debug_module;
reg cpu0_ce;
wire cpu0_tdi;
wire cpu0_tdo;
wire cpu0_crc_en;
wire cpu0_shift_crc;
`else
wire crc_en_cpu = 1'b0;
wire shift_crc_cpu = 1'b0;
wire cpu0_crc_en = 1'b0;
wire cpu0_shift_crc = 1'b0;
`endif
 
`ifdef DBG_CPU1_SUPPORTED
input cpu1_clk_i;
output [31:0] cpu1_addr_o;
input [31:0] cpu1_data_i;
output [31:0] cpu1_data_o;
input cpu1_bp_i;
output cpu1_stall_o;
output cpu1_stb_o;
output cpu1_we_o;
input cpu1_ack_i;
output cpu1_rst_o;
 
reg cpu1_debug_module;
reg cpu1_ce;
wire cpu1_tdi;
wire cpu1_tdo;
wire cpu1_crc_en;
wire cpu1_shift_crc;
`else
wire cpu1_crc_en = 1'b0;
wire cpu1_shift_crc = 1'b0;
`endif
 
 
reg [`DBG_TOP_DATA_CNT -1:0] data_cnt;
reg [`DBG_TOP_CRC_CNT -1:0] crc_cnt;
reg [`DBG_TOP_STATUS_CNT_WIDTH -1:0] status_cnt;
412,9 → 454,12
 
always @ (module_id)
begin
`ifdef DBG_CPU_SUPPORTED
cpu_debug_module <= #1 1'b0;
`ifdef DBG_CPU0_SUPPORTED
cpu0_debug_module <= #1 1'b0;
`endif
`ifdef DBG_CPU1_SUPPORTED
cpu1_debug_module <= #1 1'b0;
`endif
`ifdef DBG_WISHBONE_SUPPORTED
wishbone_module <= #1 1'b0;
`endif
421,13 → 466,16
module_select_error <= #1 1'b0;
case (module_id) /* synthesis parallel_case */
`ifdef DBG_CPU_SUPPORTED
`DBG_TOP_CPU_DEBUG_MODULE : cpu_debug_module <= #1 1'b1;
`ifdef DBG_CPU0_SUPPORTED
`DBG_TOP_CPU0_DEBUG_MODULE : cpu0_debug_module <= #1 1'b1;
`endif
`ifdef DBG_CPU1_SUPPORTED
`DBG_TOP_CPU1_DEBUG_MODULE : cpu1_debug_module <= #1 1'b1;
`endif
`ifdef DBG_WISHBONE_SUPPORTED
`DBG_TOP_WISHBONE_DEBUG_MODULE: wishbone_module <= #1 1'b1;
`DBG_TOP_WISHBONE_DEBUG_MODULE : wishbone_module <= #1 1'b1;
`endif
default : module_select_error <= #1 1'b1;
default : module_select_error <= #1 1'b1;
endcase
end
 
475,7 → 523,7
wire crc_en_dbg;
reg crc_started;
 
assign crc_en = crc_en_dbg | crc_en_wb | crc_en_cpu;
assign crc_en = crc_en_dbg | crc_en_wb | cpu1_crc_en | cpu0_crc_en;
 
assign crc_en_dbg = shift_dr_i & crc_cnt_end & (~status_cnt_end);
 
538,15 → 586,18
 
 
 
assign shift_crc = shift_crc_wb | shift_crc_cpu;
assign shift_crc = shift_crc_wb | cpu1_shift_crc | cpu0_shift_crc;
 
always @ (shift_crc or crc_out or tdo_module_select
`ifdef DBG_WISHBONE_SUPPORTED
or wishbone_ce or tdo_wb
`endif
`ifdef DBG_CPU_SUPPORTED
or cpu_ce or tdo_cpu
`ifdef DBG_CPU0_SUPPORTED
or cpu0_ce or cpu0_tdo
`endif
`ifdef DBG_CPU1_SUPPORTED
or cpu1_ce or cpu1_tdo
`endif
)
begin
if (shift_crc) // shifting crc
555,10 → 606,14
else if (wishbone_ce) // shifting data from wb
tdo_tmp = tdo_wb;
`endif
`ifdef DBG_CPU_SUPPORTED
else if (cpu_ce) // shifting data from cpu
tdo_tmp = tdo_cpu;
`ifdef DBG_CPU0_SUPPORTED
else if (cpu0_ce) // shifting data from cpu
tdo_tmp = cpu0_tdo;
`endif
`ifdef DBG_CPU1_SUPPORTED
else if (cpu1_ce) // shifting data from cpu
tdo_tmp = cpu1_tdo;
`endif
else
tdo_tmp = tdo_module_select;
end
582,9 → 637,12
`ifdef DBG_WISHBONE_SUPPORTED
wishbone_ce <= #1 1'b0;
`endif
`ifdef DBG_CPU_SUPPORTED
cpu_ce <= #1 1'b0;
`ifdef DBG_CPU0_SUPPORTED
cpu0_ce <= #1 1'b0;
`endif
`ifdef DBG_CPU1_SUPPORTED
cpu1_ce <= #1 1'b0;
`endif
end
else if(selecting_command & (~tdi_i))
begin
592,10 → 650,14
if (wishbone_module) // wishbone CE
wishbone_ce <= #1 1'b1;
`endif
`ifdef DBG_CPU_SUPPORTED
if (cpu_debug_module) // CPU CE
cpu_ce <= #1 1'b1;
`ifdef DBG_CPU0_SUPPORTED
if (cpu0_debug_module) // CPU CE
cpu0_ce <= #1 1'b1;
`endif
`ifdef DBG_CPU1_SUPPORTED
if (cpu1_debug_module) // CPU CE
cpu1_ce <= #1 1'b1;
`endif
end
else if (update_dr_i)
begin
602,9 → 664,12
`ifdef DBG_WISHBONE_SUPPORTED
wishbone_ce <= #1 1'b0;
`endif
`ifdef DBG_CPU_SUPPORTED
cpu_ce <= #1 1'b0;
`ifdef DBG_CPU0_SUPPORTED
cpu0_ce <= #1 1'b0;
`endif
`ifdef DBG_CPU1_SUPPORTED
cpu1_ce <= #1 1'b0;
`endif
end
end
 
613,9 → 678,12
assign tdi_wb = wishbone_ce & tdi_i;
`endif
 
`ifdef DBG_CPU_SUPPORTED
assign tdi_cpu = cpu_ce & tdi_i;
`ifdef DBG_CPU0_SUPPORTED
assign cpu0_tdi = cpu0_ce & tdi_i;
`endif
`ifdef DBG_CPU1_SUPPORTED
assign cpu1_tdi = cpu1_ce & tdi_i;
`endif
 
 
`ifdef DBG_WISHBONE_SUPPORTED
657,13 → 725,49
`endif
 
 
`ifdef DBG_CPU_SUPPORTED
 
`ifdef DBG_CPU0_SUPPORTED
dbg_cpu i_dbg_cpu_or1k (
// JTAG signals
.tck_i (tck_i),
.tdi_i (cpu0_tdi),
.tdo_o (cpu0_tdo),
 
// TAP states
.shift_dr_i (shift_dr_i),
.pause_dr_i (pause_dr_i),
.update_dr_i (update_dr_i),
 
.cpu_ce_i (cpu0_ce),
.crc_match_i (crc_match),
.crc_en_o (cpu0_crc_en),
.shift_crc_o (cpu0_shift_crc),
.rst_i (rst_i),
 
// CPU signals
.cpu_clk_i (cpu0_clk_i),
.cpu_addr_o (cpu0_addr_o),
.cpu_data_i (cpu0_data_i),
.cpu_data_o (cpu0_data_o),
.cpu_bp_i (cpu0_bp_i),
.cpu_stall_o (cpu0_stall_o),
.cpu_stb_o (cpu0_stb_o),
.cpu_we_o (cpu0_we_o),
.cpu_ack_i (cpu0_ack_i),
.cpu_rst_o (cpu0_rst_o)
);
 
`endif // DBG_CPU0_SUPPORTED
 
 
 
`ifdef DBG_CPU1_SUPPORTED
// Connecting cpu module
dbg_cpu i_dbg_cpu (
dbg_cpu i_dbg_cpu_8051 (
// JTAG signals
.tck_i (tck_i),
.tdi_i (tdi_cpu),
.tdo_o (tdo_cpu),
.tdi_i (cpu1_tdi),
.tdo_o (cpu1_tdo),
 
// TAP states
.shift_dr_i (shift_dr_i),
670,26 → 774,25
.pause_dr_i (pause_dr_i),
.update_dr_i (update_dr_i),
 
.cpu_ce_i (cpu_ce),
.cpu_ce_i (cpu1_ce),
.crc_match_i (crc_match),
.crc_en_o (crc_en_cpu),
.shift_crc_o (shift_crc_cpu),
.crc_en_o (cpu1_crc_en),
.shift_crc_o (cpu1_shift_crc),
.rst_i (rst_i),
 
// CPU signals
.cpu_clk_i (cpu_clk_i),
.cpu_addr_o (cpu_addr_o),
.cpu_data_i (cpu_data_i),
.cpu_data_o (cpu_data_o),
.cpu_bp_i (cpu_bp_i),
.cpu_stall_o (cpu_stall_o),
.cpu_stb_o (cpu_stb_o),
.cpu_we_o (cpu_we_o),
.cpu_ack_i (cpu_ack_i),
.cpu_rst_o (cpu_rst_o)
.cpu_clk_i (cpu1_clk_i),
.cpu_addr_o (cpu1_addr_o),
.cpu_data_i (cpu1_data_i),
.cpu_data_o (cpu1_data_o),
.cpu_bp_i (cpu1_bp_i),
.cpu_stall_o (cpu1_stall_o),
.cpu_stb_o (cpu1_stb_o),
.cpu_we_o (cpu1_we_o),
.cpu_ack_i (cpu1_ack_i),
.cpu_rst_o (cpu1_rst_o)
);
`endif // DBG_CPU_SUPPORTED
`endif
 
 
 
endmodule
/trunk/rtl/verilog/dbg_wb.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.21 2004/03/31 14:34:09 igorm
// data_cnt_lim length changed to reduce number of warnings.
//
// Revision 1.20 2004/03/28 20:27:02 igorm
// New release of the debug interface (3rd. release).
//
249,7 → 252,8
reg [2:0] fifo_cnt;
wire fifo_full;
wire fifo_empty;
reg [7:0] mem [0:3];
//reg [7:0] mem [0:3];
reg [7:0] mem0, mem1, mem2, mem3;
reg [2:0] mem_ptr_dsff;
reg wishbone_ce_csff;
reg mem_ptr_init;
295,7 → 299,6
end
 
reg [799:0] dr_text;
// Shift register for shifting in and out the data
always @ (posedge tck_i or posedge rst_i)
begin
303,18 → 306,15
begin
latch_data <= #1 1'b0;
dr <= #1 {`DBG_WB_DR_LEN{1'b0}};
dr_text = "reset";
end
else if (curr_cmd_rd_comm && crc_cnt_31) // Latching data (from iternal regs)
begin
dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1:0] <= #1 {acc_type, adr, len};
dr_text = "latch reg data";
end
else if (acc_type_read && curr_cmd_go && crc_cnt_31) // Latchind first data (from WB)
begin
dr[31:0] <= #1 input_data[31:0];
latch_data <= #1 1'b1;
dr_text = "latch first data";
end
else if (acc_type_read && curr_cmd_go && crc_cnt_end) // Latching data (from WB)
begin
329,13 → 329,11
2'b11 : dr[31:24] <= #1 input_data[7:0];
endcase
latch_data <= #1 1'b1;
dr_text = "latch_data byte";
end
else
begin
dr[31:24] <= #1 {dr[30:24], 1'b0};
latch_data <= #1 1'b0;
dr_text = "shift byte";
end
end
`DBG_WB_READ16: begin
346,13 → 344,11
else
dr[31:16] <= #1 input_data[31:16];
latch_data <= #1 1'b1;
dr_text = "latch_data_half";
end
else
begin
dr[31:16] <= #1 {dr[30:16], 1'b0};
latch_data <= #1 1'b0;
dr_text = "shift half";
end
end
`DBG_WB_READ32: begin
360,13 → 356,11
begin
dr[31:0] <= #1 input_data[31:0];
latch_data <= #1 1'b1;
dr_text = "latch_data word";
end
else
begin
dr[31:0] <= #1 {dr[30:0], 1'b0};
latch_data <= #1 1'b0;
dr_text = "shift word";
end
end
endcase
374,7 → 368,6
else if (enable && (!addr_len_cnt_end))
begin
dr <= #1 {dr[`DBG_WB_DR_LEN -2:0], tdi_i};
dr_text = "shift dr";
end
end
 
1025,7 → 1018,7
end
 
 
// Logic for latching data that is read from wishbone
/* Logic for latching data that is read from wishbone
always @ (posedge wb_clk_i)
begin
if (wb_ack_i)
1056,11 → 1049,93
endcase
end
end
*/
 
// Logic for latching data that is read from wishbone
always @ (posedge wb_clk_i)
begin
if (wb_ack_i)
begin
case (wb_sel_dsff) // synthesis parallel_case full_case
4'b1000 : begin
case (mem_ptr_dsff[1:0]) // synthesis parallel_case full_case
2'b00: mem0 <= #1 wb_dat_i[31:24];
2'b01: mem1 <= #1 wb_dat_i[31:24];
2'b10: mem2 <= #1 wb_dat_i[31:24];
2'b11: mem3 <= #1 wb_dat_i[31:24];
endcase
end
4'b0100 : begin
case (mem_ptr_dsff[1:0]) // synthesis parallel_case full_case
2'b00: mem0 <= #1 wb_dat_i[23:16];
2'b01: mem1 <= #1 wb_dat_i[23:16];
2'b10: mem2 <= #1 wb_dat_i[23:16];
2'b11: mem3 <= #1 wb_dat_i[23:16];
endcase
end
4'b0010 : begin
case (mem_ptr_dsff[1:0]) // synthesis parallel_case full_case
2'b00: mem0 <= #1 wb_dat_i[15:08];
2'b01: mem1 <= #1 wb_dat_i[15:08];
2'b10: mem2 <= #1 wb_dat_i[15:08];
2'b11: mem3 <= #1 wb_dat_i[15:08];
endcase
end
4'b0001 : begin
case (mem_ptr_dsff[1:0]) // synthesis parallel_case full_case
2'b00: mem0 <= #1 wb_dat_i[07:00];
2'b01: mem1 <= #1 wb_dat_i[07:00];
2'b10: mem2 <= #1 wb_dat_i[07:00];
2'b11: mem3 <= #1 wb_dat_i[07:00];
endcase
end
4'b1100 : // half
begin
case (mem_ptr_dsff[1:0]) // synthesis parallel_case full_case
2'b00: mem0 <= #1 wb_dat_i[31:24];
2'b01: mem1 <= #1 wb_dat_i[31:24];
2'b10: mem2 <= #1 wb_dat_i[31:24];
2'b11: mem3 <= #1 wb_dat_i[31:24];
endcase
case (mem_ptr_dsff[1:0]) // synthesis parallel_case full_case
2'b00: mem1 <= #1 wb_dat_i[23:16];
2'b01: mem2 <= #1 wb_dat_i[23:16];
2'b10: mem3 <= #1 wb_dat_i[23:16];
2'b11: mem0 <= #1 wb_dat_i[23:16];
endcase
end
4'b0011 : // half
begin
case (mem_ptr_dsff[1:0]) // synthesis parallel_case full_case
2'b00: mem0 <= #1 wb_dat_i[15:08];
2'b01: mem1 <= #1 wb_dat_i[15:08];
2'b10: mem2 <= #1 wb_dat_i[15:08];
2'b11: mem3 <= #1 wb_dat_i[15:08];
endcase
case (mem_ptr_dsff[1:0]) // synthesis parallel_case full_case
2'b00: mem1 <= #1 wb_dat_i[07:00];
2'b01: mem2 <= #1 wb_dat_i[07:00];
2'b10: mem3 <= #1 wb_dat_i[07:00];
2'b11: mem0 <= #1 wb_dat_i[07:00];
endcase
end
4'b1111 : // long
begin
mem0 <= #1 wb_dat_i[31:24];
mem1 <= #1 wb_dat_i[23:16];
mem2 <= #1 wb_dat_i[15:08];
mem3 <= #1 wb_dat_i[07:00];
end
endcase
end
end
 
assign input_data = {mem[0], mem[1], mem[2], mem[3]};
 
//assign input_data = {mem[0], mem[1], mem[2], mem[3]};
assign input_data = {mem0, mem1, mem2, mem3};
 
 
// Fifo counter and empty/full detection
always @ (posedge tck_i or posedge rst_i)
begin
1090,7 → 1165,6
assign fifo_full = fifo_cnt == 3'h4;
assign fifo_empty = fifo_cnt == 3'h0;
 
reg [799:0] tdo_text;
 
// TDO multiplexer
always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or curr_cmd_wr_comm or
1101,46 → 1175,37
if (pause_dr_i)
begin
tdo_o = busy_tck;
tdo_text = "busy_tck";
end
else if (crc_cnt_end && (!crc_cnt_end_q) && (curr_cmd_wr_comm || curr_cmd_go && acc_type_write ))
begin
tdo_o = ~crc_match_i;
tdo_text = "crc_match_i";
end
else if (curr_cmd_go && acc_type_read && crc_cnt_end && (!data_cnt_end))
begin
tdo_o = dr[31];
tdo_text = "dr[31]";
end
else if (curr_cmd_go && acc_type_read && data_cnt_end && (!data_cnt_end_q))
begin
tdo_o = ~crc_match_reg;
tdo_text = "crc_match_reg";
end
else if (curr_cmd_rd_comm && addr_len_cnt_end && (!addr_len_cnt_end_q))
begin
tdo_o = ~crc_match_reg;
tdo_text = "crc_match_reg_rd_comm";
end
else if (curr_cmd_rd_comm && crc_cnt_end && (!addr_len_cnt_end))
begin
tdo_o = dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1];
tdo_text = "rd_comm data";
end
else if (status_cnt_en)
begin
tdo_o = status[3];
tdo_text = "status";
end
else
begin
tdo_o = 1'b0;
tdo_text = "zero";
end
end
 
reg [799:0] status_text;
// Status register
always @ (posedge tck_i or posedge rst_i)
begin
1147,27 → 1212,22
if (rst_i)
begin
status <= #1 {`DBG_WB_STATUS_LEN{1'b0}};
status_text = "reset";
end
else if(crc_cnt_end && (!crc_cnt_end_q) && (!(curr_cmd_go && acc_type_read)))
begin
status <= #1 {1'b0, wb_error_tck, wb_overrun_tck, crc_match_i};
status_text = "latch ni read";
end
else if (data_cnt_end && (!data_cnt_end_q) && curr_cmd_go && acc_type_read)
begin
status <= #1 {1'b0, wb_error_tck, underrun_tck, crc_match_reg};
status_text = "latch read";
end
else if (addr_len_cnt_end && (!addr_len_cnt_end) && curr_cmd_rd_comm)
begin
status <= #1 {1'b0, 1'b0, 1'b0, crc_match_reg};
status_text = "rd_comm";
end
else if (shift_dr_i && (!status_cnt_end))
begin
status <= #1 {status[`DBG_WB_STATUS_LEN -2:0], status[`DBG_WB_STATUS_LEN -1]};
status_text = "shifting";
end
end
// Following status is shifted out (MSB first):
/trunk/rtl/verilog/dbg_defines.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.19 2004/03/28 20:27:02 igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.18 2004/03/22 16:35:46 igorm
// Temp version before changing dbg interface.
//
129,15 → 132,19
`define DBG_TOP_CRC_CNT 6
 
// Chains
`define DBG_TOP_CPU_DEBUG_MODULE 4'b0000
`define DBG_TOP_WISHBONE_DEBUG_MODULE 4'b0001
`define DBG_TOP_WISHBONE_DEBUG_MODULE 4'h0
`define DBG_TOP_CPU0_DEBUG_MODULE 4'h1
`define DBG_TOP_CPU1_DEBUG_MODULE 4'h2
 
// If WISHBONE debugging is supported uncomment the folowing line
// If WISHBONE sub-module is supported uncomment the folowing line
`define DBG_WISHBONE_SUPPORTED
 
// If CPU_DEBUG is supported uncomment the folowing line
`define DBG_CPU_SUPPORTED
// If CPU_0 sub-module is supported uncomment the folowing line
`define DBG_CPU0_SUPPORTED
 
// If CPU_1 sub-module is supported uncomment the folowing line
`define DBG_CPU1_SUPPORTED
 
// If more debug info is needed, uncomment the follofing line
//`define DBG_MORE_INFO
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.