OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /
    from Rev 1439 to Rev 1440
    Reverse comparison

Rev 1439 → Rev 1440

/trunk/or1ksim/cpu/or32/or32.c
20,6 → 20,9
 
/*
* $Log: not supported by cvs2svn $
* Revision 1.42 2005/03/16 12:25:56 nogj
* Fix the parameters to the l.ff1/l.maci instructions
*
* Revision 1.41 2005/02/09 17:41:03 nogj
* Mark a simulated cpu address as such, by introducing the new oraddr_t type
*
144,9 → 147,9
{ "l.macrc", "rD", "00 0x6 DDDDD ----1 0000 0000 0000 0000",
EF(l_macrc), 0, it_mac },
{ "l.sys", "K", "00 0x8 00000 00000 KKKK KKKK KKKK KKKK",
EF(l_sys), 0, it_unknown },
EF(l_sys), 0, it_exception },
{ "l.trap", "K", "00 0x8 01000 00000 KKKK KKKK KKKK KKKK",
EF(l_trap), 0, it_unknown },
EF(l_trap), 0, it_exception },
{ "l.msync", "", "00 0x8 10000 00000 0000 0000 0000 0000", EFN,
0, it_unknown },
{ "l.psync", "", "00 0x8 10100 00000 0000 0000 0000 0000", EFN,
/trunk/gen_or1k_isa/sources/or32.c
20,6 → 20,9
 
/*
* $Log: not supported by cvs2svn $
* Revision 1.42 2005/03/16 12:25:56 nogj
* Fix the parameters to the l.ff1/l.maci instructions
*
* Revision 1.41 2005/02/09 17:41:03 nogj
* Mark a simulated cpu address as such, by introducing the new oraddr_t type
*
144,9 → 147,9
{ "l.macrc", "rD", "00 0x6 DDDDD ----1 0000 0000 0000 0000",
EF(l_macrc), 0, it_mac },
{ "l.sys", "K", "00 0x8 00000 00000 KKKK KKKK KKKK KKKK",
EF(l_sys), 0, it_unknown },
EF(l_sys), 0, it_exception },
{ "l.trap", "K", "00 0x8 01000 00000 KKKK KKKK KKKK KKKK",
EF(l_trap), 0, it_unknown },
EF(l_trap), 0, it_exception },
{ "l.msync", "", "00 0x8 10000 00000 0000 0000 0000 0000", EFN,
0, it_unknown },
{ "l.psync", "", "00 0x8 10100 00000 0000 0000 0000 0000", EFN,
/trunk/gen_or1k_isa/sources/opcode/or32.c
20,6 → 20,9
 
/*
* $Log: not supported by cvs2svn $
* Revision 1.42 2005/03/16 12:25:56 nogj
* Fix the parameters to the l.ff1/l.maci instructions
*
* Revision 1.41 2005/02/09 17:41:03 nogj
* Mark a simulated cpu address as such, by introducing the new oraddr_t type
*
144,9 → 147,9
{ "l.macrc", "rD", "00 0x6 DDDDD ----1 0000 0000 0000 0000",
EF(l_macrc), 0, it_mac },
{ "l.sys", "K", "00 0x8 00000 00000 KKKK KKKK KKKK KKKK",
EF(l_sys), 0, it_unknown },
EF(l_sys), 0, it_exception },
{ "l.trap", "K", "00 0x8 01000 00000 KKKK KKKK KKKK KKKK",
EF(l_trap), 0, it_unknown },
EF(l_trap), 0, it_exception },
{ "l.msync", "", "00 0x8 10000 00000 0000 0000 0000 0000", EFN,
0, it_unknown },
{ "l.psync", "", "00 0x8 10100 00000 0000 0000 0000 0000", EFN,
/trunk/insight/opcodes/or32.c
20,6 → 20,9
 
/*
* $Log: not supported by cvs2svn $
* Revision 1.42 2005/03/16 12:25:56 nogj
* Fix the parameters to the l.ff1/l.maci instructions
*
* Revision 1.41 2005/02/09 17:41:03 nogj
* Mark a simulated cpu address as such, by introducing the new oraddr_t type
*
144,9 → 147,9
{ "l.macrc", "rD", "00 0x6 DDDDD ----1 0000 0000 0000 0000",
EF(l_macrc), 0, it_mac },
{ "l.sys", "K", "00 0x8 00000 00000 KKKK KKKK KKKK KKKK",
EF(l_sys), 0, it_unknown },
EF(l_sys), 0, it_exception },
{ "l.trap", "K", "00 0x8 01000 00000 KKKK KKKK KKKK KKKK",
EF(l_trap), 0, it_unknown },
EF(l_trap), 0, it_exception },
{ "l.msync", "", "00 0x8 10000 00000 0000 0000 0000 0000", EFN,
0, it_unknown },
{ "l.psync", "", "00 0x8 10100 00000 0000 0000 0000 0000", EFN,

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