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Change log for the T48 uController core |
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Version: $Date: 2004-10-26 21:41:38 $ |
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Release 0.5 BETA |
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* Bugfix for "P1 constantly in push-pull mode in t8048" |
Applied in t8048.vhd 1.3 |
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* Bugfix for "RD' and WR' not asserted for INS A, BUS and OUTL BUS, A" |
Applied in decoder.vhd 1.16 |
db_bus.vhd 1.3 |
Updated testcase black_box/ins. |
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* P1, P2 and BUS are written during the first instruction cycle of the |
OUTL instruction. This matches the descirption in the User Manual. |
The previous implementation updated these ports at the end of the |
second instruction cycle. |
Applied in decoder.vhd 1.16 |
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* Shifted deassertion of RD and WR to end of XTAL3 of machine state 2. |
The previous deassertion at the end of XTAL2 was not according to the |
User Manual. Their rising edge can now be used as a read/write strobe. |
On the other hand, PROG is still deasserted at the end of XTAL3. This |
is needed to for the rising edge of PROG within valid P2 expander data. |
Applied in clock_ctrl.vhd 1.6 |