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URL https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk

Subversion Repositories theia_gpu

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    from Rev 148 to Rev 149
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Rev 148 → Rev 149

/theia_gpu/trunk/rtl/GPU/CORES/MEM/Unit_MEM.v
113,7 → 113,7
wire [`DATA_ROW_WIDTH-1:0] wIOData_SMEM1,wIOData_SMEM2;//,wData_OMEM1,wData_OMEM2;
 
/*******************************************************
The memory is divided en several memory banks.
The Data memory is divided into several memory banks.
Each Bank has different characteristics:
 
* IO MEM: Input Registers, Written by IO, Read by EXE.
124,7 → 124,7
* OREG*: Output registers written by EXE, Read by IO.
 
Whenever an input address is received, this imput address
is divided up a bank selector and offset in the following way:
is divided in a bank selector and offset in the following way:
 
__________________________
| b6 b5 | b4 b3 b2 b1 b0 |
310,7 → 310,7
 
//The reason I put two ROMs is because I need to read 2 different Instruction
//addresses at the same time (branch-taken and branch-not-taken) and not sure
//hpw to write dual read channel ROM this way...
//how to write dual read channel ROM this way...
 
ROM IROM
(

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