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URL https://opencores.org/ocsvn/or1k/or1k/trunk

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  • This comparison shows the changes necessary to convert path
    /
    from Rev 1489 to Rev 1490
    Reverse comparison

Rev 1489 → Rev 1490

/trunk/or1ksim/peripheral/mc.c
43,6 → 43,8
#include "sim-config.h"
#include "debug.h"
 
DEFAULT_DEBUG_CHANNEL(mc);
 
struct mc_area {
struct dev_memarea *mem;
unsigned int cs;
108,7 → 110,7
struct mc *mc = dat;
int chipsel;
debug(5, "mc_write_word(%"PRIxADDR",%08"PRIx32")\n", addr, value);
TRACE("mc_write_word(%"PRIxADDR",%08"PRIx32")\n", addr, value);
 
switch (addr) {
case MC_CSR:
115,7 → 117,7
mc->csr = value;
break;
case MC_POC:
fprintf (stderr, "warning: write to MC's POC register!");
WARN("warning: write to MC's POC register!");
break;
case MC_BA_MASK:
mc->ba_mask = value & MC_BA_MASK_VALID;
133,7 → 135,7
set_csc_tms (addr >> 3, mc->csc[addr >> 3], mc->tms[addr >> 3], mc);
break;
} else
debug(1, "write out of range (addr %"PRIxADDR")\n", addr + mc->baseaddr);
TRACE("write out of range (addr %"PRIxADDR")\n", addr + mc->baseaddr);
}
}
 
143,7 → 145,7
struct mc *mc = dat;
uint32_t value = 0;
debug(5, "mc_read_word(%"PRIxADDR")", addr);
TRACE("mc_read_word(%"PRIxADDR")", addr);
 
switch (addr) {
case MC_CSR:
163,10 → 165,10
else
value = mc->csc[addr >> 3];
} else
debug(1, " read out of range (addr %"PRIxADDR")\n", addr + mc->baseaddr);
TRACE(" read out of range (addr %"PRIxADDR")\n", addr + mc->baseaddr);
break;
}
debug(5, " value(%"PRIx32")\n", value);
TRACE(" value(%"PRIx32")\n", value);
return value;
}
 
/trunk/or1ksim/support/dbchs.h
29,3 → 29,4
DECLARE_DEBUG_CHANNEL(config)
DECLARE_DEBUG_CHANNEL(ata)
DECLARE_DEBUG_CHANNEL(gpio)
DECLARE_DEBUG_CHANNEL(mc)

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