URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
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- This comparison shows the changes necessary to convert path
/
- from Rev 149 to Rev 150
- ↔ Reverse comparison
Rev 149 → Rev 150
/trunk/insight/gdb/remote-or1k.c
286,7 → 286,7
unsigned int data; |
{ |
or1k_set_chain (SC_RISC_DEBUG); |
or1k_write_reg (regno + REG_SPACE, data); |
or1k_write_reg (regno + REG_SPACE, (ULONGEST)data); |
} |
|
/* Reads register SPR from regno. */ |
625,9 → 625,11
else |
error ("The program is not being run."); |
|
|
/* Clear reason register for later. */ |
or1k_write_spr_reg (DRR_SPRNUM, 0); |
|
/* Else clause added by CZ 26/06/01 */ |
if (step) |
{ |
/* HW STEP. Set DMR1_ST. */ |
635,6 → 637,11
or1k_write_spr_reg (DMR1_SPRNUM, dmr1); |
dmr1 &= ~DMR1_ST; |
} |
else |
{ |
dmr1 &= ~DMR1_ST; |
or1k_write_spr_reg (DMR1_SPRNUM, dmr1); |
} |
|
or1k_commit_debug_registers (); |
/* Run the target. */ |
719,7 → 726,9
CORE_ADDR pc = read_pc (); |
int breakpoint = 0; |
int i; |
unsigned long value; /* CZ */ |
unsigned char break_bytes[4] = BRK_INSTR_STRUCT; |
unsigned long b_insn = ntohl(*((unsigned long*)break_bytes)); |
unsigned long value; |
|
for (i = 0; i < or1k_implementation.num_used_matchpoints; i++) |
if (dvr[i] == pc && dcr[i].dp && dcr[i].cc == CC_EQUAL |
733,8 → 742,14
/* Cause the trap/breakpoint exception to be ignored. This is |
the behavior of the simulator when the PC value is changed |
by a write command. All pending exceptions are cleared and |
the simulator continues at the PC value specified. */ |
or1k_write_spr_reg(PC_SPRNUM,value); |
the simulator continues at the PC value specified. We need |
to do this if the instruction at the current PC has the |
value BRK_INSTR_STRUCT */ |
|
if(b_insn == or1k_read_reg((pc >> 2) + MEM_SPACE)) |
{ |
or1k_write_spr_reg(PC_SPRNUM,value); |
} |
} |
else |
hit_watchpoint = 0; |
/trunk/gdb-5.0/gdb/remote-or1k.c
286,7 → 286,7
unsigned int data; |
{ |
or1k_set_chain (SC_RISC_DEBUG); |
or1k_write_reg (regno + REG_SPACE, data); |
or1k_write_reg (regno + REG_SPACE, (ULONGEST)data); |
} |
|
/* Reads register SPR from regno. */ |
625,9 → 625,11
else |
error ("The program is not being run."); |
|
|
/* Clear reason register for later. */ |
or1k_write_spr_reg (DRR_SPRNUM, 0); |
|
/* Else clause added by CZ 26/06/01 */ |
if (step) |
{ |
/* HW STEP. Set DMR1_ST. */ |
635,6 → 637,11
or1k_write_spr_reg (DMR1_SPRNUM, dmr1); |
dmr1 &= ~DMR1_ST; |
} |
else |
{ |
dmr1 &= ~DMR1_ST; |
or1k_write_spr_reg (DMR1_SPRNUM, dmr1); |
} |
|
or1k_commit_debug_registers (); |
/* Run the target. */ |
719,7 → 726,9
CORE_ADDR pc = read_pc (); |
int breakpoint = 0; |
int i; |
unsigned long value; /* CZ */ |
unsigned char break_bytes[4] = BRK_INSTR_STRUCT; |
unsigned long b_insn = ntohl(*((unsigned long*)break_bytes)); |
unsigned long value; |
|
for (i = 0; i < or1k_implementation.num_used_matchpoints; i++) |
if (dvr[i] == pc && dcr[i].dp && dcr[i].cc == CC_EQUAL |
733,8 → 742,14
/* Cause the trap/breakpoint exception to be ignored. This is |
the behavior of the simulator when the PC value is changed |
by a write command. All pending exceptions are cleared and |
the simulator continues at the PC value specified. */ |
or1k_write_spr_reg(PC_SPRNUM,value); |
the simulator continues at the PC value specified. We need |
to do this if the instruction at the current PC has the |
value BRK_INSTR_STRUCT */ |
|
if(b_insn == or1k_read_reg((pc >> 2) + MEM_SPACE)) |
{ |
or1k_write_spr_reg(PC_SPRNUM,value); |
} |
} |
else |
hit_watchpoint = 0; |